Hi,
This series converts atmel clocks bindings (PMC and slow clock
controller) to YAML. Along with it updated device trees to cope
with the dt-binding requirements.
Thank you,
Claudiu Beznea
Changes in v4:
- in patch 2/5: added "atmel,at91sam9x5-pmc", "syscon" to the list of
available compatibles
Changes in v4:
- changed the approach the compatibles are treated in patch 2/5 to avoid
having 2 enums on one items entry (thanks Conor for hint)
Changes in v3:
- in patch 2/5:
- get rid of 1st "items" section and embedd it in the last compatible
enum
- sort alphanumerically the compatibles in allOf
- collected tags
Changes in v2:
- in patch 2/5:
- dropped quotes from $id and $schema
- get rid of 1st "items" sections corresponding to "atmel,at91sam9260-pmc",
"syscon" compatible and move it to the proper enum
- ordered compatibles by name
- add description for #clock-cells
- remove blank lines
- keep order in required (same order that the properties were
defined)
- dropped required from allOf
- in patch 5/5:
- dropped quotes from $id and $schema
- drop first "items:" in compatible:oneOf section
- ordered compatibles by name
- moved additionalProperties after allOf
- dropped microchip,sama7g5-sckc from first allOf:if section
- moved "required" section from allOf to global "required" section
- dropped if:then from the last if:then:else in allOf
Claudiu Beznea (5):
ARM: dts: at91: use clock-controller name for PMC nodes
dt-bindings: clocks: atmel,at91rm9200-pmc: convert to yaml
ARM: dts: at91: at91sam9n12: witch sckc to new clock bindings
ARM: dts: at91: use clock-controller name for sckc nodes
dt-bindings: clocks: at91sam9x5-sckc: convert to yaml
.../devicetree/bindings/clock/at91-clock.txt | 58 -------
.../bindings/clock/atmel,at91rm9200-pmc.yaml | 154 ++++++++++++++++++
.../bindings/clock/atmel,at91sam9x5-sckc.yaml | 70 ++++++++
arch/arm/boot/dts/at91rm9200.dtsi | 2 +-
arch/arm/boot/dts/at91sam9260.dtsi | 2 +-
arch/arm/boot/dts/at91sam9261.dtsi | 2 +-
arch/arm/boot/dts/at91sam9263.dtsi | 2 +-
arch/arm/boot/dts/at91sam9g20.dtsi | 2 +-
arch/arm/boot/dts/at91sam9g25.dtsi | 2 +-
arch/arm/boot/dts/at91sam9g35.dtsi | 2 +-
arch/arm/boot/dts/at91sam9g45.dtsi | 4 +-
arch/arm/boot/dts/at91sam9n12.dtsi | 25 +--
arch/arm/boot/dts/at91sam9rl.dtsi | 4 +-
arch/arm/boot/dts/at91sam9x25.dtsi | 2 +-
arch/arm/boot/dts/at91sam9x35.dtsi | 2 +-
arch/arm/boot/dts/at91sam9x5.dtsi | 4 +-
arch/arm/boot/dts/sam9x60.dtsi | 4 +-
arch/arm/boot/dts/sama5d2.dtsi | 4 +-
arch/arm/boot/dts/sama5d3.dtsi | 4 +-
arch/arm/boot/dts/sama5d3_emac.dtsi | 2 +-
arch/arm/boot/dts/sama5d4.dtsi | 4 +-
arch/arm/boot/dts/sama7g5.dtsi | 2 +-
22 files changed, 253 insertions(+), 104 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/at91-clock.txt
create mode 100644 Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml
create mode 100644 Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
--
2.34.1
Convert Atmel slow clock controller documentation to yaml.
Signed-off-by: Claudiu Beznea <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
.../devicetree/bindings/clock/at91-clock.txt | 30 --------
.../bindings/clock/atmel,at91sam9x5-sckc.yaml | 70 +++++++++++++++++++
2 files changed, 70 insertions(+), 30 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/at91-clock.txt
create mode 100644 Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt
deleted file mode 100644
index 57394785d3b0..000000000000
--- a/Documentation/devicetree/bindings/clock/at91-clock.txt
+++ /dev/null
@@ -1,30 +0,0 @@
-Device Tree Clock bindings for arch-at91
-
-This binding uses the common clock binding[1].
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Slow Clock controller:
-
-Required properties:
-- compatible : shall be one of the following:
- "atmel,at91sam9x5-sckc",
- "atmel,sama5d3-sckc",
- "atmel,sama5d4-sckc" or
- "microchip,sam9x60-sckc":
- at91 SCKC (Slow Clock Controller)
-- #clock-cells : shall be 1 for "microchip,sam9x60-sckc" otherwise shall be 0.
-- clocks : shall be the input parent clock phandle for the clock.
-
-Optional properties:
-- atmel,osc-bypass : boolean property. Set this when a clock signal is directly
- provided on XIN.
-
-For example:
- sckc@fffffe50 {
- compatible = "atmel,at91sam9x5-sckc";
- reg = <0xfffffe50 0x4>;
- clocks = <&slow_xtal>;
- #clock-cells = <0>;
- };
-
diff --git a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
new file mode 100644
index 000000000000..7be29877e6d2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/atmel,at91sam9x5-sckc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Atmel Slow Clock Controller (SCKC)
+
+maintainers:
+ - Claudiu Beznea <[email protected]>
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - atmel,at91sam9x5-sckc
+ - atmel,sama5d3-sckc
+ - atmel,sama5d4-sckc
+ - microchip,sam9x60-sckc
+ - items:
+ - const: microchip,sama7g5-sckc
+ - const: microchip,sam9x60-sckc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ "#clock-cells":
+ enum: [0, 1]
+
+ atmel,osc-bypass:
+ type: boolean
+ description: set when a clock signal is directly provided on XIN
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - "#clock-cells"
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - microchip,sam9x60-sckc
+ then:
+ properties:
+ "#clock-cells":
+ const: 1
+ else:
+ properties:
+ "#clock-cells":
+ const: 0
+
+additionalProperties: false
+
+examples:
+ - |
+ clk32k: clock-controller@fffffe50 {
+ compatible = "microchip,sam9x60-sckc";
+ reg = <0xfffffe50 0x4>;
+ clocks = <&slow_xtal>;
+ #clock-cells = <1>;
+ };
+
+...
--
2.34.1
Use clock-controller generic name for slow clock controller nodes.
Signed-off-by: Claudiu Beznea <[email protected]>
---
arch/arm/boot/dts/at91sam9g45.dtsi | 2 +-
arch/arm/boot/dts/at91sam9rl.dtsi | 2 +-
arch/arm/boot/dts/at91sam9x5.dtsi | 2 +-
arch/arm/boot/dts/sam9x60.dtsi | 2 +-
arch/arm/boot/dts/sama5d2.dtsi | 2 +-
arch/arm/boot/dts/sama5d3.dtsi | 2 +-
arch/arm/boot/dts/sama5d4.dtsi | 2 +-
7 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 76afeb31b7f5..498cb92b29f9 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -923,7 +923,7 @@ usb2: gadget@fff78000 {
status = "disabled";
};
- clk32k: sckc@fffffd50 {
+ clk32k: clock-controller@fffffd50 {
compatible = "atmel,at91sam9x5-sckc";
reg = <0xfffffd50 0x4>;
clocks = <&slow_xtal>;
diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
index a12e6c419fe3..d7e8a115c916 100644
--- a/arch/arm/boot/dts/at91sam9rl.dtsi
+++ b/arch/arm/boot/dts/at91sam9rl.dtsi
@@ -799,7 +799,7 @@ watchdog@fffffd40 {
status = "disabled";
};
- clk32k: sckc@fffffd50 {
+ clk32k: clock-controller@fffffd50 {
compatible = "atmel,at91sam9x5-sckc";
reg = <0xfffffd50 0x4>;
clocks = <&slow_xtal>;
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index af19ef2a875c..0123ee47151c 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -154,7 +154,7 @@ pit: timer@fffffe30 {
clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
};
- clk32k: sckc@fffffe50 {
+ clk32k: clock-controller@fffffe50 {
compatible = "atmel,at91sam9x5-sckc";
reg = <0xfffffe50 0x4>;
clocks = <&slow_xtal>;
diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi
index 6f5177df01bc..933d73505a8b 100644
--- a/arch/arm/boot/dts/sam9x60.dtsi
+++ b/arch/arm/boot/dts/sam9x60.dtsi
@@ -700,7 +700,7 @@ pit: timer@fffffe40 {
clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
};
- clk32k: sckc@fffffe50 {
+ clk32k: clock-controller@fffffe50 {
compatible = "microchip,sam9x60-sckc";
reg = <0xfffffe50 0x4>;
clocks = <&slow_xtal>;
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index 86009dd28e62..5f632e3f039e 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -704,7 +704,7 @@ watchdog: watchdog@f8048040 {
status = "disabled";
};
- clk32k: sckc@f8048050 {
+ clk32k: clock-controller@f8048050 {
compatible = "atmel,sama5d4-sckc";
reg = <0xf8048050 0x4>;
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 4524a16322d1..0eebf6c760b3 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -1040,7 +1040,7 @@ watchdog: watchdog@fffffe40 {
status = "disabled";
};
- clk32k: sckc@fffffe50 {
+ clk32k: clock-controller@fffffe50 {
compatible = "atmel,sama5d3-sckc";
reg = <0xfffffe50 0x4>;
clocks = <&slow_xtal>;
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index e94f3a661f4b..de6c82969232 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -761,7 +761,7 @@ watchdog: watchdog@fc068640 {
status = "disabled";
};
- clk32k: sckc@fc068650 {
+ clk32k: clock-controller@fc068650 {
compatible = "atmel,sama5d4-sckc";
reg = <0xfc068650 0x4>;
#clock-cells = <0>;
--
2.34.1
Use clock-controller generic name for PMC nodes.
Signed-off-by: Claudiu Beznea <[email protected]>
---
arch/arm/boot/dts/at91rm9200.dtsi | 2 +-
arch/arm/boot/dts/at91sam9260.dtsi | 2 +-
arch/arm/boot/dts/at91sam9261.dtsi | 2 +-
arch/arm/boot/dts/at91sam9263.dtsi | 2 +-
arch/arm/boot/dts/at91sam9g20.dtsi | 2 +-
arch/arm/boot/dts/at91sam9g25.dtsi | 2 +-
arch/arm/boot/dts/at91sam9g35.dtsi | 2 +-
arch/arm/boot/dts/at91sam9g45.dtsi | 2 +-
arch/arm/boot/dts/at91sam9n12.dtsi | 2 +-
arch/arm/boot/dts/at91sam9rl.dtsi | 2 +-
arch/arm/boot/dts/at91sam9x25.dtsi | 2 +-
arch/arm/boot/dts/at91sam9x35.dtsi | 2 +-
arch/arm/boot/dts/at91sam9x5.dtsi | 2 +-
arch/arm/boot/dts/sam9x60.dtsi | 2 +-
arch/arm/boot/dts/sama5d2.dtsi | 2 +-
arch/arm/boot/dts/sama5d3.dtsi | 2 +-
arch/arm/boot/dts/sama5d3_emac.dtsi | 2 +-
arch/arm/boot/dts/sama5d4.dtsi | 2 +-
arch/arm/boot/dts/sama7g5.dtsi | 2 +-
19 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 6f9004ebf424..37b500f6f395 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -102,7 +102,7 @@ ramc0: ramc@ffffff00 {
reg = <0xffffff00 0x100>;
};
- pmc: pmc@fffffc00 {
+ pmc: clock-controller@fffffc00 {
compatible = "atmel,at91rm9200-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 789fe356dbf6..16e3b24b4ddd 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -115,7 +115,7 @@ matrix: matrix@ffffee00 {
reg = <0xffffee00 0x200>;
};
- pmc: pmc@fffffc00 {
+ pmc: clock-controller@fffffc00 {
compatible = "atmel,at91sam9260-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
index ee0bd1aceb3f..fe9ead867e2a 100644
--- a/arch/arm/boot/dts/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -599,7 +599,7 @@ pioC: gpio@fffff800 {
};
};
- pmc: pmc@fffffc00 {
+ pmc: clock-controller@fffffc00 {
compatible = "atmel,at91sam9261-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 3ce9ea987312..ee5e6ed44dd4 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -101,7 +101,7 @@ aic: interrupt-controller@fffff000 {
atmel,external-irqs = <30 31>;
};
- pmc: pmc@fffffc00 {
+ pmc: clock-controller@fffffc00 {
compatible = "atmel,at91sam9263-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 708e1646b7f4..738a43ffd228 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -41,7 +41,7 @@ adc0: adc@fffe0000 {
atmel,adc-startup-time = <40>;
};
- pmc: pmc@fffffc00 {
+ pmc: clock-controller@fffffc00 {
compatible = "atmel,at91sam9g20-pmc", "atmel,at91sam9260-pmc", "syscon";
};
};
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi
index d2f13afb35ea..ec3c77221881 100644
--- a/arch/arm/boot/dts/at91sam9g25.dtsi
+++ b/arch/arm/boot/dts/at91sam9g25.dtsi
@@ -26,7 +26,7 @@ pinctrl@fffff400 {
>;
};
- pmc: pmc@fffffc00 {
+ pmc: clock-controller@fffffc00 {
compatible = "atmel,at91sam9g25-pmc", "atmel,at91sam9x5-pmc", "syscon";
};
};
diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi
index 48c2bc4a7753..c9cfb93092ee 100644
--- a/arch/arm/boot/dts/at91sam9g35.dtsi
+++ b/arch/arm/boot/dts/at91sam9g35.dtsi
@@ -25,7 +25,7 @@ pinctrl@fffff400 {
>;
};
- pmc: pmc@fffffc00 {
+ pmc: clock-controller@fffffc00 {
compatible = "atmel,at91sam9g35-pmc", "atmel,at91sam9x5-pmc", "syscon";
};
};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 95f5d76234db..76afeb31b7f5 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -129,7 +129,7 @@ matrix: matrix@ffffea00 {
reg = <0xffffea00 0x200>;
};
- pmc: pmc@fffffc00 {
+ pmc: clock-controller@fffffc00 {
compatible = "atmel,at91sam9g45-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 83114d26f10d..c2e7460fb7ff 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -118,7 +118,7 @@ smc: smc@ffffea00 {
reg = <0xffffea00 0x200>;
};
- pmc: pmc@fffffc00 {
+ pmc: clock-controller@fffffc00 {
compatible = "atmel,at91sam9n12-pmc", "syscon";
reg = <0xfffffc00 0x200>;
#clock-cells = <2>;
diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
index 364a2ff0a763..a12e6c419fe3 100644
--- a/arch/arm/boot/dts/at91sam9rl.dtsi
+++ b/arch/arm/boot/dts/at91sam9rl.dtsi
@@ -763,7 +763,7 @@ pioD: gpio@fffffa00 {
};
};
- pmc: pmc@fffffc00 {
+ pmc: clock-controller@fffffc00 {
compatible = "atmel,at91sam9rl-pmc", "syscon";
reg = <0xfffffc00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi
index 0fe8802e1242..7036f5f04571 100644
--- a/arch/arm/boot/dts/at91sam9x25.dtsi
+++ b/arch/arm/boot/dts/at91sam9x25.dtsi
@@ -27,7 +27,7 @@ pinctrl@fffff400 {
>;
};
- pmc: pmc@fffffc00 {
+ pmc: clock-controller@fffffc00 {
compatible = "atmel,at91sam9x25-pmc", "atmel,at91sam9x5-pmc", "syscon";
};
};
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi
index 0bfa21f18f87..eb03b0497e37 100644
--- a/arch/arm/boot/dts/at91sam9x35.dtsi
+++ b/arch/arm/boot/dts/at91sam9x35.dtsi
@@ -26,7 +26,7 @@ pinctrl@fffff400 {
>;
};
- pmc: pmc@fffffc00 {
+ pmc: clock-controller@fffffc00 {
compatible = "atmel,at91sam9x35-pmc", "atmel,at91sam9x5-pmc", "syscon";
};
};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 0c26c925761b..af19ef2a875c 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -126,7 +126,7 @@ smc: smc@ffffea00 {
reg = <0xffffea00 0x200>;
};
- pmc: pmc@fffffc00 {
+ pmc: clock-controller@fffffc00 {
compatible = "atmel,at91sam9x5-pmc", "syscon";
reg = <0xfffffc00 0x200>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi
index 8f5477e307dd..6f5177df01bc 100644
--- a/arch/arm/boot/dts/sam9x60.dtsi
+++ b/arch/arm/boot/dts/sam9x60.dtsi
@@ -660,7 +660,7 @@ pioD: gpio@fffffa00 {
};
};
- pmc: pmc@fffffc00 {
+ pmc: clock-controller@fffffc00 {
compatible = "microchip,sam9x60-pmc", "syscon";
reg = <0xfffffc00 0x200>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index 14c35c12a115..86009dd28e62 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -284,7 +284,7 @@ dma1: dma-controller@f0004000 {
clock-names = "dma_clk";
};
- pmc: pmc@f0014000 {
+ pmc: clock-controller@f0014000 {
compatible = "atmel,sama5d2-pmc", "syscon";
reg = <0xf0014000 0x160>;
interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index bde8e92d60bb..4524a16322d1 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -1001,7 +1001,7 @@ pioE: gpio@fffffa00 {
};
};
- pmc: pmc@fffffc00 {
+ pmc: clock-controller@fffffc00 {
compatible = "atmel,sama5d3-pmc", "syscon";
reg = <0xfffffc00 0x120>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
diff --git a/arch/arm/boot/dts/sama5d3_emac.dtsi b/arch/arm/boot/dts/sama5d3_emac.dtsi
index 45226108850d..5d7ce13de8cc 100644
--- a/arch/arm/boot/dts/sama5d3_emac.dtsi
+++ b/arch/arm/boot/dts/sama5d3_emac.dtsi
@@ -30,7 +30,7 @@ AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A EMDC, conflicts with
};
};
- pmc: pmc@fffffc00 {
+ pmc: clock-controller@fffffc00 {
};
macb1: ethernet@f802c000 {
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index af62157ae214..e94f3a661f4b 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -250,7 +250,7 @@ dma0: dma-controller@f0014000 {
clock-names = "dma_clk";
};
- pmc: pmc@f0018000 {
+ pmc: clock-controller@f0018000 {
compatible = "atmel,sama5d4-pmc", "syscon";
reg = <0xf0018000 0x120>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
index ab131762ecb5..f0478a43edc2 100644
--- a/arch/arm/boot/dts/sama7g5.dtsi
+++ b/arch/arm/boot/dts/sama7g5.dtsi
@@ -241,7 +241,7 @@ pioA: pinctrl@e0014000 {
clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
};
- pmc: pmc@e0018000 {
+ pmc: clock-controller@e0018000 {
compatible = "microchip,sama7g5-pmc", "syscon";
reg = <0xe0018000 0x200>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
--
2.34.1
Switch slow clock controller to new clock bindings.
Signed-off-by: Claudiu Beznea <[email protected]>
---
arch/arm/boot/dts/at91sam9n12.dtsi | 23 +++--------------------
1 file changed, 3 insertions(+), 20 deletions(-)
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index c2e7460fb7ff..0e28101b26bf 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -146,28 +146,11 @@ shdwc@fffffe10 {
clocks = <&clk32k>;
};
- sckc@fffffe50 {
+ clk32k: clock-controller@fffffe50 {
compatible = "atmel,at91sam9x5-sckc";
reg = <0xfffffe50 0x4>;
-
- slow_osc: slow_osc {
- compatible = "atmel,at91sam9x5-clk-slow-osc";
- #clock-cells = <0>;
- clocks = <&slow_xtal>;
- };
-
- slow_rc_osc: slow_rc_osc {
- compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-accuracy = <50000000>;
- };
-
- clk32k: slck {
- compatible = "atmel,at91sam9x5-clk-slow";
- #clock-cells = <0>;
- clocks = <&slow_rc_osc>, <&slow_osc>;
- };
+ clocks = <&slow_xtal>;
+ #clock-cells = <0>;
};
mmc0: mmc@f0008000 {
--
2.34.1
Convert Atmel PMC documentation to yaml. Along with it clock names
were adapted according to the current available device trees as
different controller versions accept different clock (some of them
have 3 clocks as input, some has 2 clocks as inputs and some with 2
input clocks uses different clock names).
Signed-off-by: Claudiu Beznea <[email protected]>
---
.../devicetree/bindings/clock/at91-clock.txt | 28 ----
.../bindings/clock/atmel,at91rm9200-pmc.yaml | 154 ++++++++++++++++++
2 files changed, 154 insertions(+), 28 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml
diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt
index 13f45db3b66d..57394785d3b0 100644
--- a/Documentation/devicetree/bindings/clock/at91-clock.txt
+++ b/Documentation/devicetree/bindings/clock/at91-clock.txt
@@ -28,31 +28,3 @@ For example:
#clock-cells = <0>;
};
-Power Management Controller (PMC):
-
-Required properties:
-- compatible : shall be "atmel,<chip>-pmc", "syscon" or
- "microchip,sam9x60-pmc"
- <chip> can be: at91rm9200, at91sam9260, at91sam9261,
- at91sam9263, at91sam9g45, at91sam9n12, at91sam9rl, at91sam9g15,
- at91sam9g25, at91sam9g35, at91sam9x25, at91sam9x35, at91sam9x5,
- sama5d2, sama5d3 or sama5d4.
-- #clock-cells : from common clock binding; shall be set to 2. The first entry
- is the type of the clock (core, system, peripheral or generated) and the
- second entry its index as provided by the datasheet
-- clocks : Must contain an entry for each entry in clock-names.
-- clock-names: Must include the following entries: "slow_clk", "main_xtal"
-
-Optional properties:
-- atmel,osc-bypass : boolean property. Set this when a clock signal is directly
- provided on XIN.
-
-For example:
- pmc: pmc@f0018000 {
- compatible = "atmel,sama5d4-pmc", "syscon";
- reg = <0xf0018000 0x120>;
- interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
- #clock-cells = <2>;
- clocks = <&clk32k>, <&main_xtal>;
- clock-names = "slow_clk", "main_xtal";
- };
diff --git a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml
new file mode 100644
index 000000000000..c1bdcd9058ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml
@@ -0,0 +1,154 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/atmel,at91rm9200-pmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Atmel Power Management Controller (PMC)
+
+maintainers:
+ - Claudiu Beznea <[email protected]>
+
+description:
+ The power management controller optimizes power consumption by controlling all
+ system and user peripheral clocks. The PMC enables/disables the clock inputs
+ to many of the peripherals and to the processor.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: atmel,at91sam9g20-pmc
+ - const: atmel,at91sam9260-pmc
+ - const: syscon
+ - items:
+ - enum:
+ - atmel,at91sam9g15-pmc
+ - atmel,at91sam9g25-pmc
+ - atmel,at91sam9g35-pmc
+ - atmel,at91sam9x25-pmc
+ - atmel,at91sam9x35-pmc
+ - const: atmel,at91sam9x5-pmc
+ - const: syscon
+ - items:
+ - enum:
+ - atmel,at91rm9200-pmc
+ - atmel,at91sam9260-pmc
+ - atmel,at91sam9g45-pmc
+ - atmel,at91sam9n12-pmc
+ - atmel,at91sam9rl-pmc
+ - atmel,at91sam9x5-pmc
+ - atmel,sama5d2-pmc
+ - atmel,sama5d3-pmc
+ - atmel,sama5d4-pmc
+ - microchip,sam9x60-pmc
+ - microchip,sama7g5-pmc
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ "#clock-cells":
+ description: |
+ - 1st cell is the clock type, one of PMC_TYPE_CORE, PMC_TYPE_SYSTEM,
+ PMC_TYPE_PERIPHERAL, PMC_TYPE_GCK, PMC_TYPE_PROGRAMMABLE (as defined
+ in <dt-bindings/clock/at91.h>)
+ - 2nd cell is the clock identifier as defined in <dt-bindings/clock/at91.h
+ (for core clocks) or as defined in datasheet (for system, peripheral,
+ gck and programmable clocks).
+ const: 2
+
+ clocks:
+ minItems: 2
+ maxItems: 3
+
+ clock-names:
+ minItems: 2
+ maxItems: 3
+
+ atmel,osc-bypass:
+ description: set when a clock signal is directly provided on XIN
+ type: boolean
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#clock-cells"
+ - clocks
+ - clock-names
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - microchip,sam9x60-pmc
+ - microchip,sama7g5-pmc
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ items:
+ - const: td_slck
+ - const: md_slck
+ - const: main_xtal
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - atmel,at91rm9200-pmc
+ - atmel,at91sam9260-pmc
+ - atmel,at91sam9g20-pmc
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: slow_xtal
+ - const: main_xtal
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - atmel,sama5d2-pmc
+ - atmel,sama5d3-pmc
+ - atmel,sama5d4-pmc
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: slow_clk
+ - const: main_xtal
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ pmc: clock-controller@f0018000 {
+ compatible = "atmel,sama5d4-pmc", "syscon";
+ reg = <0xf0018000 0x120>;
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ #clock-cells = <2>;
+ clocks = <&clk32k>, <&main_xtal>;
+ clock-names = "slow_clk", "main_xtal";
+ };
+
+...
--
2.34.1
On Wed, May 17, 2023 at 12:41:16PM +0300, Claudiu Beznea wrote:
> Convert Atmel PMC documentation to yaml. Along with it clock names
> were adapted according to the current available device trees as
> different controller versions accept different clock (some of them
> have 3 clocks as input, some has 2 clocks as inputs and some with 2
> input clocks uses different clock names).
>
> Signed-off-by: Claudiu Beznea <[email protected]>
Looks good to me now Claudiu, thanks!
Reviewed-by: Conor Dooley <[email protected]>
Cheers,
Conor.
On Wed, 17 May 2023 12:41:19 +0300, Claudiu Beznea wrote:
> Convert Atmel slow clock controller documentation to yaml.
>
> Signed-off-by: Claudiu Beznea <[email protected]>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> ---
> .../devicetree/bindings/clock/at91-clock.txt | 30 --------
> .../bindings/clock/atmel,at91sam9x5-sckc.yaml | 70 +++++++++++++++++++
> 2 files changed, 70 insertions(+), 30 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/at91-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
>
Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.
Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.
Full log is available here: https://patchwork.ozlabs.org/patch/1782586
sckc@fffffe50: '#clock-cells' is a required property
arch/arm/boot/dts/at91sam9n12ek.dtb
sckc@fffffe50: 'clocks' is a required property
arch/arm/boot/dts/at91sam9n12ek.dtb
sckc@fffffe50: 'slck', 'slow_osc', 'slow_rc_osc' do not match any of the regexes: 'pinctrl-[0-9]+'
arch/arm/boot/dts/at91sam9n12ek.dtb
On 17/05/2023 11:41, Claudiu Beznea wrote:
> Convert Atmel PMC documentation to yaml. Along with it clock names
> were adapted according to the current available device trees as
> different controller versions accept different clock (some of them
> have 3 clocks as input, some has 2 clocks as inputs and some with 2
> input clocks uses different clock names).
Thank you for your patch. There is something to discuss/improve.
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - atmel,at91rm9200-pmc
> + - atmel,at91sam9260-pmc
> + - atmel,at91sam9g20-pmc
> + then:
> + properties:
> + clocks:
> + minItems: 2
> + maxItems: 2
> + clock-names:
> + items:
> + - const: slow_xtal
> + - const: main_xtal
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - atmel,sama5d2-pmc
> + - atmel,sama5d3-pmc
> + - atmel,sama5d4-pmc
> + then:
> + properties:
> + clocks:
> + minItems: 2
> + maxItems: 2
> + clock-names:
> + items:
> + - const: slow_clk
> + - const: main_xtal
This and previous if, should be squashed. You have exactly the same then:.
Best regards,
Krzysztof
On 17.05.2023 17:21, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 17/05/2023 11:41, Claudiu Beznea wrote:
>> Convert Atmel PMC documentation to yaml. Along with it clock names
>> were adapted according to the current available device trees as
>> different controller versions accept different clock (some of them
>> have 3 clocks as input, some has 2 clocks as inputs and some with 2
>> input clocks uses different clock names).
>
> Thank you for your patch. There is something to discuss/improve.
>
>
>> +
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - atmel,at91rm9200-pmc
>> + - atmel,at91sam9260-pmc
>> + - atmel,at91sam9g20-pmc
>> + then:
>> + properties:
>> + clocks:
>> + minItems: 2
>> + maxItems: 2
>> + clock-names:
>> + items:
>> + - const: slow_xtal
>> + - const: main_xtal
>> +
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - atmel,sama5d2-pmc
>> + - atmel,sama5d3-pmc
>> + - atmel,sama5d4-pmc
>> + then:
>> + properties:
>> + clocks:
>> + minItems: 2
>> + maxItems: 2
>> + clock-names:
>> + items:
>> + - const: slow_clk
>> + - const: main_xtal
>
> This and previous if, should be squashed. You have exactly the same then:.
Clock names are different. Or do you propose to have a if for
clocks:
minItems: 2
maxItems: 2
and 2 ifs for clock names?
>
>
>
> Best regards,
> Krzysztof
>
On 18/05/2023 08:03, [email protected] wrote:
> On 17.05.2023 17:21, Krzysztof Kozlowski wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On 17/05/2023 11:41, Claudiu Beznea wrote:
>>> Convert Atmel PMC documentation to yaml. Along with it clock names
>>> were adapted according to the current available device trees as
>>> different controller versions accept different clock (some of them
>>> have 3 clocks as input, some has 2 clocks as inputs and some with 2
>>> input clocks uses different clock names).
>>
>> Thank you for your patch. There is something to discuss/improve.
>>
>>
>>> +
>>> + - if:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + enum:
>>> + - atmel,at91rm9200-pmc
>>> + - atmel,at91sam9260-pmc
>>> + - atmel,at91sam9g20-pmc
>>> + then:
>>> + properties:
>>> + clocks:
>>> + minItems: 2
>>> + maxItems: 2
>>> + clock-names:
>>> + items:
>>> + - const: slow_xtal
>>> + - const: main_xtal
>>> +
>>> + - if:
>>> + properties:
>>> + compatible:
>>> + contains:
>>> + enum:
>>> + - atmel,sama5d2-pmc
>>> + - atmel,sama5d3-pmc
>>> + - atmel,sama5d4-pmc
>>> + then:
>>> + properties:
>>> + clocks:
>>> + minItems: 2
>>> + maxItems: 2
>>> + clock-names:
>>> + items:
>>> + - const: slow_clk
>>> + - const: main_xtal
>>
>> This and previous if, should be squashed. You have exactly the same then:.
>
> Clock names are different. Or do you propose to have a if for
> clocks:
> minItems: 2
> maxItems: 2
>
> and 2 ifs for clock names?
Ah, I see, they have different names - xtal -> clk.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 17.05.2023 17:15, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Wed, 17 May 2023 12:41:19 +0300, Claudiu Beznea wrote:
>> Convert Atmel slow clock controller documentation to yaml.
>>
>> Signed-off-by: Claudiu Beznea <[email protected]>
>> Reviewed-by: Krzysztof Kozlowski <[email protected]>
>> ---
>> .../devicetree/bindings/clock/at91-clock.txt | 30 --------
>> .../bindings/clock/atmel,at91sam9x5-sckc.yaml | 70 +++++++++++++++++++
>> 2 files changed, 70 insertions(+), 30 deletions(-)
>> delete mode 100644 Documentation/devicetree/bindings/clock/at91-clock.txt
>> create mode 100644 Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
>>
>
> Running 'make dtbs_check' with the schema in this patch gives the
> following warnings. Consider if they are expected or the schema is
> incorrect. These may not be new warnings.
>
> Note that it is not yet a requirement to have 0 warnings for dtbs_check.
> This will change in the future.
>
> Full log is available here: https://patchwork.ozlabs.org/patch/1782586
>
>
> sckc@fffffe50: '#clock-cells' is a required property
> arch/arm/boot/dts/at91sam9n12ek.dtb
>
> sckc@fffffe50: 'clocks' is a required property
> arch/arm/boot/dts/at91sam9n12ek.dtb
>
> sckc@fffffe50: 'slck', 'slow_osc', 'slow_rc_osc' do not match any of the regexes: 'pinctrl-[0-9]+'
> arch/arm/boot/dts/at91sam9n12ek.dtb
Is it possible that this has been checked on a wrong base? I'm asking this
because:
- patch 3/5 in this series uses proper bindings for slow clock controller
on at91sam9n12.dtsi (which includes #clock-cells and clocks bindings and
removes slck, slow_osc, slow_rc_osc)
- patch 4/5 in this series does s/sckc@/clock-controller@/ in all AT91
device trees.
Moreover, I've re-checked all the individual dtsi files that describes a
slow clock controller and all descriptions has the "#clock-cells", "clocks"
property available and no slck, slow_osc, slow_rc_osc as childs of
sckc@fffffe50.
If not, could you please let me know your checker command?
Thank you,
Claudiu
On 18/05/2023 10:31, [email protected] wrote:
> On 17.05.2023 17:15, Krzysztof Kozlowski wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On Wed, 17 May 2023 12:41:19 +0300, Claudiu Beznea wrote:
>>> Convert Atmel slow clock controller documentation to yaml.
>>>
>>> Signed-off-by: Claudiu Beznea <[email protected]>
>>> Reviewed-by: Krzysztof Kozlowski <[email protected]>
>>> ---
>>> .../devicetree/bindings/clock/at91-clock.txt | 30 --------
>>> .../bindings/clock/atmel,at91sam9x5-sckc.yaml | 70 +++++++++++++++++++
>>> 2 files changed, 70 insertions(+), 30 deletions(-)
>>> delete mode 100644 Documentation/devicetree/bindings/clock/at91-clock.txt
>>> create mode 100644 Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
>>>
>>
>> Running 'make dtbs_check' with the schema in this patch gives the
>> following warnings. Consider if they are expected or the schema is
>> incorrect. These may not be new warnings.
>>
>> Note that it is not yet a requirement to have 0 warnings for dtbs_check.
>> This will change in the future.
>>
>> Full log is available here: https://patchwork.ozlabs.org/patch/1782586
>>
>>
>> sckc@fffffe50: '#clock-cells' is a required property
>> arch/arm/boot/dts/at91sam9n12ek.dtb
>>
>> sckc@fffffe50: 'clocks' is a required property
>> arch/arm/boot/dts/at91sam9n12ek.dtb
>>
>> sckc@fffffe50: 'slck', 'slow_osc', 'slow_rc_osc' do not match any of the regexes: 'pinctrl-[0-9]+'
>> arch/arm/boot/dts/at91sam9n12ek.dtb
>
> Is it possible that this has been checked on a wrong base? I'm asking this
> because:
> - patch 3/5 in this series uses proper bindings for slow clock controller
> on at91sam9n12.dtsi (which includes #clock-cells and clocks bindings and
> removes slck, slow_osc, slow_rc_osc)
> - patch 4/5 in this series does s/sckc@/clock-controller@/ in all AT91
> device trees.
Yes, it is quite likely. It's up to you to investigate it or ignore if
you are sure report is a false positive.
>
> Moreover, I've re-checked all the individual dtsi files that describes a
> slow clock controller and all descriptions has the "#clock-cells", "clocks"
> property available and no slck, slow_osc, slow_rc_osc as childs of
> sckc@fffffe50.
>
> If not, could you please let me know your checker command?
make dbts_check
Best regards,
Krzysztof
On 17.05.2023 12:41, Claudiu Beznea wrote:
[ ... ]
>
> Claudiu Beznea (5):
> ARM: dts: at91: use clock-controller name for PMC nodes
> ARM: dts: at91: at91sam9n12: witch sckc to new clock bindings
> ARM: dts: at91: use clock-controller name for sckc nodes
Applied to at91-dt, thanks!
> dt-bindings: clocks: atmel,at91rm9200-pmc: convert to yaml
> dt-bindings: clocks: at91sam9x5-sckc: convert to yaml
Applied to clk-microchip, thanks!