Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core
module which is powered by T-HEAD's TH1520 SoC. Add minimal device
tree files for the core module and the development board.
Support basic uart/gpio/dmac drivers, so supports booting to a basic
shell.
FWICT, one issue I'm not sure is the cpu reset dt-binding: IIUC, the
secondary CPUs in T-HEAD SMP capable platforms need some special
handling. The first one is to write the warm reset entry to entry
register. The second one is write a SoC specific control value to
a SoC specific control reg. The last one is to clone some CSRs for
secondary CPUs to ensure these CSRs' values are the same as the
main boot CPU. This DT node is mainly used by opensbi firmware.
Any suggestion about this reset dt-binding is appreciated!
Thanks
Since v1:
- add missing plic, clint, th1520 itself dt-bindings
- use c900-plic
- s/light/th1520
- add dt-binding for T-HEAD CPU reset
- enable ARCH_THEAD in defconfig
- fix all dtbs_check error/warning except the CPU RESET, see above.
Jisheng Zhang (9):
dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC
dt-bindings: timer: Add T-HEAD TH1520 clint
dt-bindings: riscv: Add T-HEAD TH1520 board compatibles
dt-binding: riscv: add T-HEAD CPU reset
riscv: Add the T-HEAD SoC family Kconfig option
riscv: dts: add initial T-HEAD TH1520 SoC device tree
riscv: dts: thead: add sipeed Lichee Pi 4A board device tree
MAINTAINERS: add entry for T-HEAD RISC-V SoC
riscv: defconfig: enable T-HEAD SoC
.../sifive,plic-1.0.0.yaml | 1 +
.../bindings/riscv/thead,cpu-reset.yaml | 69 +++
.../devicetree/bindings/riscv/thead.yaml | 29 ++
.../bindings/timer/sifive,clint.yaml | 1 +
MAINTAINERS | 6 +
arch/riscv/Kconfig.socs | 6 +
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/thead/Makefile | 2 +
.../dts/thead/th1520-lichee-module-4a.dtsi | 38 ++
.../boot/dts/thead/th1520-lichee-pi-4a.dts | 32 ++
arch/riscv/boot/dts/thead/th1520.dtsi | 451 ++++++++++++++++++
arch/riscv/configs/defconfig | 1 +
12 files changed, 637 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
create mode 100644 Documentation/devicetree/bindings/riscv/thead.yaml
create mode 100644 arch/riscv/boot/dts/thead/Makefile
create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
create mode 100644 arch/riscv/boot/dts/thead/th1520.dtsi
--
2.40.0
Add compatible string for T-HEAD TH1520 plic.
Signed-off-by: Jisheng Zhang <[email protected]>
---
.../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index f75736a061af..0fa9b862e4a5 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -65,6 +65,7 @@ properties:
- items:
- enum:
- allwinner,sun20i-d1-plic
+ - thead,th1520-plic
- const: thead,c900-plic
- items:
- const: sifive,plic-1.0.0
--
2.40.0
The secondary CPUs in T-HEAD SMP capable platforms need some special
handling. The first one is to write the warm reset entry to entry
register. The second one is write a SoC specific control value to
a SoC specific control reg. The last one is to clone some CSRs for
secondary CPUs to ensure these CSRs' values are the same as the
main boot CPU. This DT node is mainly used by opensbi firmware.
Signed-off-by: Jisheng Zhang <[email protected]>
---
.../bindings/riscv/thead,cpu-reset.yaml | 69 +++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
diff --git a/Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml b/Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
new file mode 100644
index 000000000000..ba8c87583b6b
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/thead,cpu-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: T-HEAD cpu reset controller
+
+maintainers:
+ - Jisheng Zhang <[email protected]>
+
+description: |
+ The secondary CPUs in T-HEAD SMP capable platforms need some special
+ handling. The first one is to write the warm reset entry to entry
+ register. The second one is write a SoC specific control value to
+ a SoC specific control reg. The last one is to clone some CSRs for
+ secondary CPUs to ensure these CSRs' values are the same as the
+ main boot CPU.
+
+properties:
+ $nodename:
+ pattern: "^cpurst"
+
+ compatible:
+ oneOf:
+ - description: CPU reset on T-HEAD TH1520 SoC
+ items:
+ - const: thead,reset-th1520
+
+ entry-reg:
+ $ref: /schemas/types.yaml#/definitions/uint64
+ description: |
+ The entry reg address.
+
+ entry-cnt:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ The entry reg count.
+
+ control-reg:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ The control reg address.
+
+ control-val:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ The value to be set into the control reg.
+
+ csr-copy:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ The CSR registers to be cloned during CPU warm reset.
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ cpurst: cpurst@ffff019050 {
+ compatible = "thead,reset-th1520";
+ entry-reg = <0xff 0xff019050>;
+ entry-cnt = <4>;
+ control-reg = <0xff 0xff015004>;
+ control-val = <0x1c>;
+ csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
+ };
--
2.40.0
Enable T-HEAD SoC config in defconfig to allow the default
upstream kernel to boot on Sipeed Lichee Pi 4A board.
Signed-off-by: Jisheng Zhang <[email protected]>
---
arch/riscv/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index d98d6e90b2b8..109e4b5b003c 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -27,6 +27,7 @@ CONFIG_EXPERT=y
CONFIG_PROFILING=y
CONFIG_SOC_MICROCHIP_POLARFIRE=y
CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_THEAD=y
CONFIG_SOC_SIFIVE=y
CONFIG_SOC_STARFIVE=y
CONFIG_ARCH_SUNXI=y
--
2.40.0
Several SoMs and boards are available that feature the T-HEAD TH1520
SoC. Document the compatible strings.
Signed-off-by: Jisheng Zhang <[email protected]>
---
.../devicetree/bindings/riscv/thead.yaml | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/thead.yaml
diff --git a/Documentation/devicetree/bindings/riscv/thead.yaml b/Documentation/devicetree/bindings/riscv/thead.yaml
new file mode 100644
index 000000000000..e62f6821372e
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/thead.yaml
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/thead.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: T-HEAD SoC-based boards
+
+maintainers:
+ - Jisheng Zhang <[email protected]>
+
+description:
+ T-HEAD SoC-based boards
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: Sipeed Lichee Pi 4A board for the Sipeed Lichee Module 4A
+ items:
+ - enum:
+ - sipeed,lichee-pi-4a
+ - const: sipeed,lichee-module-4a
+ - const: thead,th1520
+
+additionalProperties: true
+
+...
--
2.40.0
Add compatible string for the T-HEAD TH1520 clint.
Signed-off-by: Jisheng Zhang <[email protected]>
---
Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index 94bef9424df1..388d3385d7eb 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -37,6 +37,7 @@ properties:
- items:
- enum:
- allwinner,sun20i-d1-clint
+ - thead,th1520-clint
- const: thead,c900-clint
- items:
- const: sifive,clint0
--
2.40.0
Currently, I would like to maintain the T-HEAD RISC-V SoC support.
Signed-off-by: Jisheng Zhang <[email protected]>
---
MAINTAINERS | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index e0ad886d3163..6df20c65798a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -18162,6 +18162,12 @@ F: drivers/perf/riscv_pmu.c
F: drivers/perf/riscv_pmu_legacy.c
F: drivers/perf/riscv_pmu_sbi.c
+RISC-V THEAD SoC SUPPORT
+M: Jisheng Zhang <[email protected]>
+L: [email protected]
+S: Maintained
+F: arch/riscv/boot/dts/thead/
+
RNBD BLOCK DRIVERS
M: Md. Haris Iqbal <[email protected]>
M: Jack Wang <[email protected]>
--
2.40.0
Add initial device tree for the TH1520 RISC-V SoC by T-HEAD.
Signed-off-by: Jisheng Zhang <[email protected]>
---
arch/riscv/boot/dts/thead/th1520.dtsi | 451 ++++++++++++++++++++++++++
1 file changed, 451 insertions(+)
create mode 100644 arch/riscv/boot/dts/thead/th1520.dtsi
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
new file mode 100644
index 000000000000..60754d7c6319
--- /dev/null
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -0,0 +1,451 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Alibaba Group Holding Limited.
+ * Copyright (C) 2023 Jisheng Zhang <[email protected]>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "thead,th1520";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <3000000>;
+
+ c910_0: cpu@0 {
+ compatible = "thead,c910", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ reg = <0>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache>;
+ mmu-type = "riscv,sv39";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ c910_1: cpu@1 {
+ compatible = "thead,c910", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ reg = <1>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache>;
+ mmu-type = "riscv,sv39";
+
+ cpu1_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ c910_2: cpu@2 {
+ compatible = "thead,c910", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ reg = <2>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache>;
+ mmu-type = "riscv,sv39";
+
+ cpu2_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ c910_3: cpu@3 {
+ compatible = "thead,c910", "riscv";
+ device_type = "cpu";
+ riscv,isa = "rv64imafdc";
+ reg = <3>;
+ i-cache-block-size = <64>;
+ i-cache-size = <65536>;
+ i-cache-sets = <512>;
+ d-cache-block-size = <64>;
+ d-cache-size = <65536>;
+ d-cache-sets = <512>;
+ next-level-cache = <&l2_cache>;
+ mmu-type = "riscv,sv39";
+
+ cpu3_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&c910_0>;
+ };
+
+ core1 {
+ cpu = <&c910_1>;
+ };
+
+ core2 {
+ cpu = <&c910_2>;
+ };
+
+ core3 {
+ cpu = <&c910_3>;
+ };
+ };
+ };
+
+ l2_cache: l2-cache {
+ compatible = "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-size = <1048576>;
+ cache-sets = <1024>;
+ cache-unified;
+ };
+ };
+
+ osc: oscillator {
+ compatible = "fixed-clock";
+ clock-output-names = "osc_24m";
+ #clock-cells = <0>;
+ };
+
+ osc_32k: 32k-oscillator {
+ compatible = "fixed-clock";
+ clock-output-names = "osc_32k";
+ #clock-cells = <0>;
+ };
+
+ apb_clk: apb-clk-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "apb_clk";
+ #clock-cells = <0>;
+ };
+
+ uart_sclk: uart-sclk-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "uart_sclk";
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&plic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cpurst: cpurst {
+ compatible = "thead,reset-th1520";
+ entry-reg = <0xff 0xff019050>;
+ entry-cnt = <4>;
+ control-reg = <0xff 0xff015004>;
+ control-val = <0x1c>;
+ csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
+ };
+
+ plic: interrupt-controller@ffd8000000 {
+ compatible = "thead,th1520-plic", "thead,c900-plic";
+ reg = <0xff 0xd8000000 0x0 0x01000000>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>,
+ <&cpu2_intc 11>, <&cpu2_intc 9>,
+ <&cpu3_intc 11>, <&cpu3_intc 9>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ riscv,ndev = <240>;
+ };
+
+ clint: timer@ffdc000000 {
+ compatible = "thead,th1520-clint", "thead,c900-clint";
+ reg = <0xff 0xdc000000 0x0 0x00010000>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+ <&cpu1_intc 3>, <&cpu1_intc 7>,
+ <&cpu2_intc 3>, <&cpu2_intc 7>,
+ <&cpu3_intc 3>, <&cpu3_intc 7>;
+ };
+
+ uart0: serial@ffe7014000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xff 0xe7014000 0x0 0x4000>;
+ interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_sclk>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart1: serial@ffe7f00000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xff 0xe7f00000 0x0 0x4000>;
+ interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_sclk>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart3: serial@ffe7f04000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xff 0xe7f04000 0x0 0x4000>;
+ interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_sclk>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ gpio2: gpio@ffe7f34000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xe7f34000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ portc: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpio3: gpio@ffe7f38000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xe7f38000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ portd: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpio0: gpio@ffec005000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xec005000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpio1: gpio@ffec006000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xec006000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ portb: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ uart2: serial@ffec010000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xff 0xec010000 0x0 0x4000>;
+ interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_sclk>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ dmac0: dma-controller@ffefc00000 {
+ compatible = "snps,axi-dma-1.01a";
+ reg = <0xff 0xefc00000 0x0 0x1000>;
+ interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb_clk>, <&apb_clk>;
+ clock-names = "core-clk", "cfgr-clk";
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ snps,block-size = <65536 65536 65536 65536>;
+ snps,priority = <0 1 2 3>;
+ snps,dma-masters = <1>;
+ snps,data-width = <4>;
+ snps,axi-max-burst-len = <16>;
+ status = "disabled";
+ };
+
+ timer0: timer@ffefc32000 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0xff 0xefc32000 0x0 0x14>;
+ clocks = <&apb_clk>;
+ clock-names = "timer";
+ interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ timer1: timer@ffefc32014 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0xff 0xefc32014 0x0 0x14>;
+ clocks = <&apb_clk>;
+ clock-names = "timer";
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ timer2: timer@ffefc32028 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0xff 0xefc32028 0x0 0x14>;
+ clocks = <&apb_clk>;
+ clock-names = "timer";
+ interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ timer3: timer@ffefc3203c {
+ compatible = "snps,dw-apb-timer";
+ reg = <0xff 0xefc3203c 0x0 0x14>;
+ clocks = <&apb_clk>;
+ clock-names = "timer";
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ uart4: serial@fff7f08000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xff 0xf7f08000 0x0 0x4000>;
+ interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_sclk>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart5: serial@fff7f0c000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xff 0xf7f0c000 0x0 0x4000>;
+ interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_sclk>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ timer4: timer@ffffc33000 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0xff 0xffc33000 0x0 0x14>;
+ clocks = <&apb_clk>;
+ clock-names = "timer";
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ timer5: timer@ffffc33014 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0xff 0xffc33014 0x0 0x14>;
+ clocks = <&apb_clk>;
+ clock-names = "timer";
+ interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ timer6: timer@ffffc33028 {
+ compatible = "snps,dw-apb-timer";
+ reg = <0xff 0xffc33028 0x0 0x14>;
+ clocks = <&apb_clk>;
+ clock-names = "timer";
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ timer7: timer@ffffc3303c {
+ compatible = "snps,dw-apb-timer";
+ reg = <0xff 0xffc3303c 0x0 0x14>;
+ clocks = <&apb_clk>;
+ clock-names = "timer";
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ ao_gpio0: gpio@fffff41000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xfff41000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ porte: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ ao_gpio1: gpio@fffff52000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff 0xfff52000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ portf: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+ };
+};
--
2.40.0
Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core
module which is powered by T-HEAD's TH1520 SoC. Add minimal device
tree files for the core module and the development board.
Support basic uart/gpio/dmac drivers, so supports booting to a basic
shell.
Signed-off-by: Jisheng Zhang <[email protected]>
---
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/thead/Makefile | 2 +
.../dts/thead/th1520-lichee-module-4a.dtsi | 38 +++++++++++++++++++
.../boot/dts/thead/th1520-lichee-pi-4a.dts | 32 ++++++++++++++++
4 files changed, 73 insertions(+)
create mode 100644 arch/riscv/boot/dts/thead/Makefile
create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index f0d9f89054f8..1e884868ccba 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -2,6 +2,7 @@
subdir-y += allwinner
subdir-y += sifive
subdir-y += starfive
+subdir-y += thead
subdir-y += canaan
subdir-y += microchip
subdir-y += renesas
diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile
new file mode 100644
index 000000000000..e311fc9a5939
--- /dev/null
+++ b/arch/riscv/boot/dts/thead/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb
diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
new file mode 100644
index 000000000000..4b0249ac710f
--- /dev/null
+++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Jisheng Zhang <[email protected]>
+ */
+
+/dts-v1/;
+
+#include "th1520.dtsi"
+
+/ {
+ model = "Sipeed Lichee Module 4A";
+ compatible = "sipeed,lichee-module-4a", "thead,th1520";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x00000000 0x2 0x00000000>;
+ };
+};
+
+&osc {
+ clock-frequency = <24000000>;
+};
+
+&osc_32k {
+ clock-frequency = <32768>;
+};
+
+&apb_clk {
+ clock-frequency = <62500000>;
+};
+
+&uart_sclk {
+ clock-frequency = <100000000>;
+};
+
+&dmac0 {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
new file mode 100644
index 000000000000..a1248b2ee3a3
--- /dev/null
+++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Jisheng Zhang <[email protected]>
+ */
+
+#include "th1520-lichee-module-4a.dtsi"
+
+/ {
+ model = "Sipeed Lichee Pi 4A";
+ compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520";
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
--
2.40.0
The first SoC in the T-HEAD series is TH1520, containing quad T-HEAD
C910 cores.
Signed-off-by: Jisheng Zhang <[email protected]>
---
arch/riscv/Kconfig.socs | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 1cf69f958f10..ce10a38dff37 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -41,6 +41,12 @@ config ARCH_SUNXI
This enables support for Allwinner sun20i platform hardware,
including boards based on the D1 and D1s SoCs.
+config ARCH_THEAD
+ bool "T-HEAD RISC-V SoCs"
+ select ERRATA_THEAD
+ help
+ This enables support for the RISC-V based T-HEAD SoCs.
+
config ARCH_VIRT
def_bool SOC_VIRT
--
2.40.0
On Fri, May 19, 2023 at 02:45:34AM +0800, Jisheng Zhang wrote:
> Add compatible string for the T-HEAD TH1520 clint.
>
> Signed-off-by: Jisheng Zhang <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Thanks,
Conor.
On Fri, 19 May 2023 02:45:36 +0800, Jisheng Zhang wrote:
> The secondary CPUs in T-HEAD SMP capable platforms need some special
> handling. The first one is to write the warm reset entry to entry
> register. The second one is write a SoC specific control value to
> a SoC specific control reg. The last one is to clone some CSRs for
> secondary CPUs to ensure these CSRs' values are the same as the
> main boot CPU. This DT node is mainly used by opensbi firmware.
>
> Signed-off-by: Jisheng Zhang <[email protected]>
> ---
> .../bindings/riscv/thead,cpu-reset.yaml | 69 +++++++++++++++++++
> 1 file changed, 69 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/riscv/thead,cpu-reset.example.dts:18.35-25.11: Warning (unit_address_vs_reg): /example-0/cpurst@ffff019050: node has a unit name, but no reg or ranges property
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/riscv/thead,cpu-reset.example.dtb: cpurst@ffff019050: control-reg:0: [255, 4278276100] is too long
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
On Fri, May 19, 2023 at 02:45:33AM +0800, Jisheng Zhang wrote:
> Add compatible string for T-HEAD TH1520 plic.
>
> Signed-off-by: Jisheng Zhang <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Thanks,
Conor.
Hey Jisheng,
On Fri, May 19, 2023 at 02:45:36AM +0800, Jisheng Zhang wrote:
> The secondary CPUs in T-HEAD SMP capable platforms need some special
> handling. The first one is to write the warm reset entry to entry
> register. The second one is write a SoC specific control value to
> a SoC specific control reg. The last one is to clone some CSRs for
> secondary CPUs to ensure these CSRs' values are the same as the
> main boot CPU. This DT node is mainly used by opensbi firmware.
>
> Signed-off-by: Jisheng Zhang <[email protected]>
> ---
> .../bindings/riscv/thead,cpu-reset.yaml | 69 +++++++++++++++++++
> 1 file changed, 69 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
>
> diff --git a/Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml b/Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
> new file mode 100644
> index 000000000000..ba8c87583b6b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
> @@ -0,0 +1,69 @@
> +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/riscv/thead,cpu-reset.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: T-HEAD cpu reset controller
> +
> +maintainers:
> + - Jisheng Zhang <[email protected]>
> +
> +description: |
> + The secondary CPUs in T-HEAD SMP capable platforms need some special
> + handling. The first one is to write the warm reset entry to entry
> + register. The second one is write a SoC specific control value to
> + a SoC specific control reg. The last one is to clone some CSRs for
> + secondary CPUs to ensure these CSRs' values are the same as the
> + main boot CPU.
Okay..
> +
> +properties:
> + $nodename:
> + pattern: "^cpurst"
Firstly, why the nodename enforcement? We have a compatible, so we
should be okay, no?
> +
> + compatible:
> + oneOf:
> + - description: CPU reset on T-HEAD TH1520 SoC
> + items:
> + - const: thead,reset-th1520
You've only got one thing here, you don't need the oneOf.
Also, s/reset-th1520/th1520-reset/ please - although I do not know if
"reset" is the right word here. Do we know what the IP block is called
in the TRM/T-Head docs? Perhaps Guo Ren does if not.
> + entry-reg:
> + $ref: /schemas/types.yaml#/definitions/uint64
> + description: |
> + The entry reg address.
> +
> + entry-cnt:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + The entry reg count.
> +
> + control-reg:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + The control reg address.
> +
> + control-val:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + The value to be set into the control reg.
> +
> + csr-copy:
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + description: |
> + The CSR registers to be cloned during CPU warm reset.
All of these values set on a per-soc basis, right?
If so, I don't think they should be in here at all since you should be
able to figure out the offsets from the base & the values to write based
on the compatible string alone, no?
Putting register values into the DT is always "suspect"!
> +required:
> + - compatible
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + cpurst: cpurst@ffff019050 {
^^^^^^^^^^^^^^^^^
This is also "suspect" and implies that "entry reg" should just be a
normal "reg" property.
> + compatible = "thead,reset-th1520";
> + entry-reg = <0xff 0xff019050>;
> + entry-cnt = <4>;
> + control-reg = <0xff 0xff015004>;
> + control-val = <0x1c>;
> + csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
> + };
> --
> 2.40.0
>
On Fri, May 19, 2023 at 02:45:37AM +0800, Jisheng Zhang wrote:
> The first SoC in the T-HEAD series is TH1520, containing quad T-HEAD
> C910 cores.
>
Reviewed-by: Conor Dooley <[email protected]>
Thanks,
Conor.
On Fri, May 19, 2023 at 02:45:35AM +0800, Jisheng Zhang wrote:
> Several SoMs and boards are available that feature the T-HEAD TH1520
> SoC. Document the compatible strings.
>
> Signed-off-by: Jisheng Zhang <[email protected]>
> ---
> .../devicetree/bindings/riscv/thead.yaml | 29 +++++++++++++++++++
> 1 file changed, 29 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/riscv/thead.yaml
>
> diff --git a/Documentation/devicetree/bindings/riscv/thead.yaml b/Documentation/devicetree/bindings/riscv/thead.yaml
> new file mode 100644
> index 000000000000..e62f6821372e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/riscv/thead.yaml
> @@ -0,0 +1,29 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/riscv/thead.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: T-HEAD SoC-based boards
> +
> +maintainers:
> + - Jisheng Zhang <[email protected]>
> +
> +description:
> + T-HEAD SoC-based boards
> +
> +properties:
> + $nodename:
> + const: '/'
> + compatible:
> + oneOf:
> + - description: Sipeed Lichee Pi 4A board for the Sipeed Lichee Module 4A
> + items:
> + - enum:
> + - sipeed,lichee-pi-4a
> + - const: sipeed,lichee-module-4a
> + - const: thead,th1520
Same here re: other SoMs I guess. Probably more interest in creating
them here though!
I heard on the grapevine that the boards people have now are perhaps not
the same as the design that they're going to ship in the main production
run?
Do you know if there is a more detailed part number for the boards, just
in case there are some software-visible changes?
Thanks,
Conor.
On Fri, May 19, 2023 at 02:45:40AM +0800, Jisheng Zhang wrote:
> Currently, I would like to maintain the T-HEAD RISC-V SoC support.
>
> Signed-off-by: Jisheng Zhang <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Thanks,
Conor.
> ---
> MAINTAINERS | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index e0ad886d3163..6df20c65798a 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -18162,6 +18162,12 @@ F: drivers/perf/riscv_pmu.c
> F: drivers/perf/riscv_pmu_legacy.c
> F: drivers/perf/riscv_pmu_sbi.c
>
> +RISC-V THEAD SoC SUPPORT
> +M: Jisheng Zhang <[email protected]>
> +L: [email protected]
> +S: Maintained
> +F: arch/riscv/boot/dts/thead/
> +
> RNBD BLOCK DRIVERS
> M: Md. Haris Iqbal <[email protected]>
> M: Jack Wang <[email protected]>
> --
> 2.40.0
>
On Fri, May 19, 2023 at 02:45:41AM +0800, Jisheng Zhang wrote:
> Enable T-HEAD SoC config in defconfig to allow the default
> upstream kernel to boot on Sipeed Lichee Pi 4A board.
Reviewed-by: Conor Dooley <[email protected]>
Thanks,
Conor.
>
> Signed-off-by: Jisheng Zhang <[email protected]>
> ---
> arch/riscv/configs/defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index d98d6e90b2b8..109e4b5b003c 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -27,6 +27,7 @@ CONFIG_EXPERT=y
> CONFIG_PROFILING=y
> CONFIG_SOC_MICROCHIP_POLARFIRE=y
> CONFIG_ARCH_RENESAS=y
> +CONFIG_ARCH_THEAD=y
> CONFIG_SOC_SIFIVE=y
> CONFIG_SOC_STARFIVE=y
> CONFIG_ARCH_SUNXI=y
> --
> 2.40.0
>
On Fri, May 19, 2023 at 02:45:39AM +0800, Jisheng Zhang wrote:
> Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core
> module which is powered by T-HEAD's TH1520 SoC. Add minimal device
> tree files for the core module and the development board.
>
> Support basic uart/gpio/dmac drivers, so supports booting to a basic
> shell.
>
> Signed-off-by: Jisheng Zhang <[email protected]>
> + compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520";
This patch, modulo my comments elsewhere about the compatibles, seems
fine.
On Fri, May 19, 2023 at 02:45:38AM +0800, Jisheng Zhang wrote:
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&c910_0>;
> + };
> +
> + core1 {
> + cpu = <&c910_1>;
> + };
> +
> + core2 {
> + cpu = <&c910_2>;
> + };
> +
> + core3 {
> + cpu = <&c910_3>;
> + };
> + };
> + };
We actually don't need to add these anymore, I fixed our topology
detection :) No harm to keep it though!
> + cpurst: cpurst {
> + compatible = "thead,reset-th1520";
> + entry-reg = <0xff 0xff019050>;
> + entry-cnt = <4>;
> + control-reg = <0xff 0xff015004>;
> + control-val = <0x1c>;
> + csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
> + };
I figure this will be no surprise to you:
arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dtb: soc: cpurst: {'compatible': ['thead,reset-th1520'], 'entry-reg': [[1099494953040]], 'entry-cnt': [[4]], 'control-reg': [[255, 4278276100]], 'control-val': [[28]], 'csr-copy': [[2035, 1984, 1985, 1986, 1987, 1989, 1996]]} should not be valid under {'type': 'object'}
arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dtb: cpurst: control-reg:0: [255, 4278276100] is too long
> + dmac0: dma-controller@ffefc00000 {
> + compatible = "snps,axi-dma-1.01a";
> + reg = <0xff 0xefc00000 0x0 0x1000>;
> + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&apb_clk>, <&apb_clk>;
> + clock-names = "core-clk", "cfgr-clk";
> + #dma-cells = <1>;
> + dma-channels = <4>;
> + snps,block-size = <65536 65536 65536 65536>;
> + snps,priority = <0 1 2 3>;
> + snps,dma-masters = <1>;
> + snps,data-width = <4>;
> + snps,axi-max-burst-len = <16>;
> + status = "disabled";
^^^^^^^^^^^^^^^^^^^^^^^
These are spaces :(
> + };
Cheers,
Conor.
在 2023-05-18星期四的 20:40 +0100，Conor Dooley写道：
> On Fri, May 19, 2023 at 02:45:35AM +0800, Jisheng Zhang wrote:
> > Several SoMs and boards are available that feature the T-HEAD
> > TH1520
> > SoC. Document the compatible strings.
> >
> > Signed-off-by: Jisheng Zhang <[email protected]>
> > ---
> > .../devicetree/bindings/riscv/thead.yaml | 29
> > +++++++++++++++++++
> > 1 file changed, 29 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/riscv/thead.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/thead.yaml
> > b/Documentation/devicetree/bindings/riscv/thead.yaml
> > new file mode 100644
> > index 000000000000..e62f6821372e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/riscv/thead.yaml
> > @@ -0,0 +1,29 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/riscv/thead.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: T-HEAD SoC-based boards
> > +
> > +maintainers:
> > + - Jisheng Zhang <[email protected]>
> > +
> > +description:
> > + T-HEAD SoC-based boards
> > +
> > +properties:
> > + $nodename:
> > + const: '/'
> > + compatible:
> > + oneOf:
> > + - description: Sipeed Lichee Pi 4A board for the Sipeed
> > Lichee Module 4A
> > + items:
> > + - enum:
> > + - sipeed,lichee-pi-4a
> > + - const: sipeed,lichee-module-4a
> > + - const: thead,th1520
>
> Same here re: other SoMs I guess. Probably more interest in creating
> them here though!
>
> I heard on the grapevine that the boards people have now are perhaps
> not
> the same as the design that they're going to ship in the main
> production
> run?
There really was an early EVB that is not public, but the EVB is called
LM4A EVB instead of LP4A.
The Lichee Pi 4A board here is the production run one.
> Do you know if there is a more detailed part number for the boards,
> just
> in case there are some software-visible changes?
>
> Thanks,
> Conor.
On Thu, 18 May 2023 11:45:41 PDT (-0700), [email protected] wrote:
> Enable T-HEAD SoC config in defconfig to allow the default
> upstream kernel to boot on Sipeed Lichee Pi 4A board.
>
> Signed-off-by: Jisheng Zhang <[email protected]>
> ---
> arch/riscv/configs/defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index d98d6e90b2b8..109e4b5b003c 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -27,6 +27,7 @@ CONFIG_EXPERT=y
> CONFIG_PROFILING=y
> CONFIG_SOC_MICROCHIP_POLARFIRE=y
> CONFIG_ARCH_RENESAS=y
> +CONFIG_ARCH_THEAD=y
> CONFIG_SOC_SIFIVE=y
> CONFIG_SOC_STARFIVE=y
> CONFIG_ARCH_SUNXI=y
Acked-by: Palmer Dabbelt <[email protected]>
Acked-by: Guo Ren <[email protected]>
On Sat, May 20, 2023 at 4:56 AM Palmer Dabbelt <[email protected]> wrote:
>
> On Thu, 18 May 2023 11:45:41 PDT (-0700), [email protected] wrote:
> > Enable T-HEAD SoC config in defconfig to allow the default
> > upstream kernel to boot on Sipeed Lichee Pi 4A board.
> >
> > Signed-off-by: Jisheng Zhang <[email protected]>
> > ---
> > arch/riscv/configs/defconfig | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> > index d98d6e90b2b8..109e4b5b003c 100644
> > --- a/arch/riscv/configs/defconfig
> > +++ b/arch/riscv/configs/defconfig
> > @@ -27,6 +27,7 @@ CONFIG_EXPERT=y
> > CONFIG_PROFILING=y
> > CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > CONFIG_ARCH_RENESAS=y
> > +CONFIG_ARCH_THEAD=y
> > CONFIG_SOC_SIFIVE=y
> > CONFIG_SOC_STARFIVE=y
> > CONFIG_ARCH_SUNXI=y
>
> Acked-by: Palmer Dabbelt <[email protected]>
--
Best Regards
Guo Ren
Reviewed-by: Guo Ren <[email protected]>
On Fri, May 19, 2023 at 2:56 AM Jisheng Zhang <[email protected]> wrote:
>
> Add compatible string for T-HEAD TH1520 plic.
>
> Signed-off-by: Jisheng Zhang <[email protected]>
> ---
> .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> index f75736a061af..0fa9b862e4a5 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> @@ -65,6 +65,7 @@ properties:
> - items:
> - enum:
> - allwinner,sun20i-d1-plic
> + - thead,th1520-plic
> - const: thead,c900-plic
> - items:
> - const: sifive,plic-1.0.0
> --
> 2.40.0
>
--
Best Regards
Guo Ren
On Fri, May 19, 2023 at 3:53 AM Conor Dooley <[email protected]> wrote:
>
> Hey Jisheng,
>
> On Fri, May 19, 2023 at 02:45:36AM +0800, Jisheng Zhang wrote:
> > The secondary CPUs in T-HEAD SMP capable platforms need some special
> > handling. The first one is to write the warm reset entry to entry
> > register. The second one is write a SoC specific control value to
> > a SoC specific control reg. The last one is to clone some CSRs for
> > secondary CPUs to ensure these CSRs' values are the same as the
> > main boot CPU. This DT node is mainly used by opensbi firmware.
> >
> > Signed-off-by: Jisheng Zhang <[email protected]>
> > ---
> > .../bindings/riscv/thead,cpu-reset.yaml | 69 +++++++++++++++++++
> > 1 file changed, 69 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml b/Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
> > new file mode 100644
> > index 000000000000..ba8c87583b6b
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
> > @@ -0,0 +1,69 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/riscv/thead,cpu-reset.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: T-HEAD cpu reset controller
> > +
> > +maintainers:
> > + - Jisheng Zhang <[email protected]>
> > +
> > +description: |
> > + The secondary CPUs in T-HEAD SMP capable platforms need some special
> > + handling. The first one is to write the warm reset entry to entry
> > + register. The second one is write a SoC specific control value to
> > + a SoC specific control reg. The last one is to clone some CSRs for
> > + secondary CPUs to ensure these CSRs' values are the same as the
> > + main boot CPU.
>
> Okay..
>
> > +
> > +properties:
> > + $nodename:
> > + pattern: "^cpurst"
>
> Firstly, why the nodename enforcement? We have a compatible, so we
> should be okay, no?
Yes, it needn't.
>
> > +
> > + compatible:
> > + oneOf:
> > + - description: CPU reset on T-HEAD TH1520 SoC
> > + items:
> > + - const: thead,reset-th1520
>
> You've only got one thing here, you don't need the oneOf.
> Also, s/reset-th1520/th1520-reset/ please - although I do not know if
> "reset" is the right word here. Do we know what the IP block is called
> in the TRM/T-Head docs? Perhaps Guo Ren does if not.
It's called CPU reset controller; every core has reset_ctrl &
reset_entry signals; Soc just gathers them into some regs.
For th1520, we have 4 reset_entries registers and 1 reset_ctrl
register. Fu Wei would give out more details about it.
>
> > + entry-reg:
> > + $ref: /schemas/types.yaml#/definitions/uint64
> > + description: |
> > + The entry reg address.
> > +
> > + entry-cn
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description: |
> > + The entry reg count.
> > +
> > + control-reg:
> > + $ref: /schemas/types.yaml#/definitions/uint32
It should be uint64.
> > + description: |
> > + The control reg address.
> > +
> > + control-val:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description: |
> > + The value to be set into the control reg.
> > +
> > + csr-copy:
> > + $ref: /schemas/types.yaml#/definitions/uint32-array
> > + description: |
> > + The CSR registers to be cloned during CPU warm reset.
>
> All of these values set on a per-soc basis, right?
Yes
> If so, I don't think they should be in here at all since you should be
> able to figure out the offsets from the base & the values to write based
> on the compatible string alone, no?
The driver works with all T-HEAD CPUs, not only for th1520. Some
vendors may have their own custom CSRs, so the csr-copy feature is
flexible enough to adjust in dts. As far as I can tell, hardware teams
typically prefer to focus on the firmware binary rather than setting
up the software compiling environment.
>
> Putting register values into the DT is always "suspect"!
It's not register values, it's register offset/ CSR number.
>
> > +required:
> > + - compatible
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + cpurst: cpurst@ffff019050 {
> ^^^^^^^^^^^^^^^^^
> This is also "suspect" and implies that "entry reg" should just be a
> normal "reg" property.
Yes, but we needn't reg, here. It should be:
cpurst {
Thx for debugging.
>
>
> > + compatible = "thead,reset-th1520";
> > + entry-reg = <0xff 0xff019050>;
> > + entry-cnt = <4>;
> > + control-reg = <0xff 0xff015004>;
> > + control-val = <0x1c>;
> > + csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
> > + };
> > --
> > 2.40.0
> >
--
Best Regards
Guo Ren
Hey,
On Mon, May 22, 2023 at 10:16:19AM +0800, Guo Ren wrote:
> On Fri, May 19, 2023 at 3:53 AM Conor Dooley <[email protected]> wrote:
> > On Fri, May 19, 2023 at 02:45:36AM +0800, Jisheng Zhang wrote:
> > > The secondary CPUs in T-HEAD SMP capable platforms need some special
> > > handling. The first one is to write the warm reset entry to entry
> > > register. The second one is write a SoC specific control value to
> > > a SoC specific control reg. The last one is to clone some CSRs for
> > > secondary CPUs to ensure these CSRs' values are the same as the
> > > main boot CPU. This DT node is mainly used by opensbi firmware.
> > >
> > > Signed-off-by: Jisheng Zhang <[email protected]>
> > > ---
> > > .../bindings/riscv/thead,cpu-reset.yaml | 69 +++++++++++++++++++
> > > 1 file changed, 69 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml b/Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
> > > new file mode 100644
> > > index 000000000000..ba8c87583b6b
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
> > > @@ -0,0 +1,69 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/riscv/thead,cpu-reset.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: T-HEAD cpu reset controller
> > > +
> > > +maintainers:
> > > + - Jisheng Zhang <[email protected]>
> > > +
> > > +description: |
> > > + The secondary CPUs in T-HEAD SMP capable platforms need some special
> > > + handling. The first one is to write the warm reset entry to entry
> > > + register. The second one is write a SoC specific control value to
> > > + a SoC specific control reg. The last one is to clone some CSRs for
> > > + secondary CPUs to ensure these CSRs' values are the same as the
> > > + main boot CPU.
> > > +
> > > + compatible:
> > > + oneOf:
> > > + - description: CPU reset on T-HEAD TH1520 SoC
> > > + items:
> > > + - const: thead,reset-th1520
> >
> > You've only got one thing here, you don't need the oneOf.
> > Also, s/reset-th1520/th1520-reset/ please - although I do not know if
> > "reset" is the right word here. Do we know what the IP block is called
> > in the TRM/T-Head docs? Perhaps Guo Ren does if not.
> It's called CPU reset controller; every core has reset_ctrl &
> reset_entry signals; Soc just gathers them into some regs.
> For th1520, we have 4 reset_entries registers and 1 reset_ctrl
> register. Fu Wei would give out more details about it.
Okay, thanks. Sounds like this SoC will have multiple reset controllers
then, since there is likely one for the peripherals too?
thead,th1520-cpu-reset seems like a good idea to me?
> > > + entry-reg:
> > > + $ref: /schemas/types.yaml#/definitions/uint64
> > > + description: |
> > > + The entry reg address.
> > > +
> > > + entry-cn
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + description: |
> > > + The entry reg count.
> > > +
> > > + control-reg:
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> It should be uint64.
>
> > > + description: |
> > > + The control reg address.
> > > +
> > > + control-val:
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + description: |
> > > + The value to be set into the control reg.
> > > +
> > > + csr-copy:
> > > + $ref: /schemas/types.yaml#/definitions/uint32-array
> > > + description: |
> > > + The CSR registers to be cloned during CPU warm reset.
> >
> > All of these values set on a per-soc basis, right?
> Yes
> > If so, I don't think they should be in here at all since you should be
> > able to figure out the offsets from the base & the values to write based
> > on the compatible string alone, no?
> The driver works with all T-HEAD CPUs, not only for th1520. Some
> vendors may have their own custom CSRs, so the csr-copy feature is
> flexible enough to adjust in dts. As far as I can tell, hardware teams
> typically prefer to focus on the firmware binary rather than setting
> up the software compiling environment.
In this case "firmware" means opensbi, since that's where Jisheng
mentioned in their cover that they intended using this.
> > Putting register values into the DT is always "suspect"!
> It's not register values, it's register offset/ CSR number.
So "control-val" is not a value? "The value to be set into the control
reg" makes it sound oddly like one!!
My point I guess is that this entry could be written like
reset-controller@ffff019050 {
compatible = "thead,th1520-cpu-reset";
reg = <0xff 0xff019050 0xfoo 0xbar>, <0xff 0xff015004 0xfoo 0xbar>;
};
or even:
reset-controller@ffff019050 {
compatible = "thead,th1520-cpu-reset";
reg = <0xff 0xff019050 0xfoo 0xbar>, <0xff 0xff015004 0xfoo 0xbar>;
reg-names = "entry", "control";
};
And csr-copy, entry-cn and control-val can be derived from the
compatible string given you've said they are set on a per-soc basis.
> > > +required:
> > > + - compatible
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > + - |
> > > + cpurst: cpurst@ffff019050 {
> > ^^^^^^^^^^^^^^^^^
> > This is also "suspect" and implies that "entry reg" should just be a
> > normal "reg" property.
> Yes, but we needn't reg, here. It should be:
>
> cpurst {
I don't think it should! Firstly, "cpurst" is not a generic node name,
but I also don't agree that "control-reg" and "entry-reg" should not
just be 2 reg entries.
Cheers,
Conor.
On Mon, May 22, 2023 at 3:09 PM Conor Dooley <[email protected]> wrote:
>
> Hey,
>
> On Mon, May 22, 2023 at 10:16:19AM +0800, Guo Ren wrote:
> > On Fri, May 19, 2023 at 3:53 AM Conor Dooley <[email protected]> wrote:
> > > On Fri, May 19, 2023 at 02:45:36AM +0800, Jisheng Zhang wrote:
> > > > The secondary CPUs in T-HEAD SMP capable platforms need some special
> > > > handling. The first one is to write the warm reset entry to entry
> > > > register. The second one is write a SoC specific control value to
> > > > a SoC specific control reg. The last one is to clone some CSRs for
> > > > secondary CPUs to ensure these CSRs' values are the same as the
> > > > main boot CPU. This DT node is mainly used by opensbi firmware.
> > > >
> > > > Signed-off-by: Jisheng Zhang <[email protected]>
> > > > ---
> > > > .../bindings/riscv/thead,cpu-reset.yaml | 69 +++++++++++++++++++
> > > > 1 file changed, 69 insertions(+)
> > > > create mode 100644 Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml b/Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
> > > > new file mode 100644
> > > > index 000000000000..ba8c87583b6b
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
> > > > @@ -0,0 +1,69 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
> > > > +%YAML 1.2
> > > > +---
> > > > +$id: http://devicetree.org/schemas/riscv/thead,cpu-reset.yaml#
> > > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > +
> > > > +title: T-HEAD cpu reset controller
> > > > +
> > > > +maintainers:
> > > > + - Jisheng Zhang <[email protected]>
> > > > +
> > > > +description: |
> > > > + The secondary CPUs in T-HEAD SMP capable platforms need some special
> > > > + handling. The first one is to write the warm reset entry to entry
> > > > + register. The second one is write a SoC specific control value to
> > > > + a SoC specific control reg. The last one is to clone some CSRs for
> > > > + secondary CPUs to ensure these CSRs' values are the same as the
> > > > + main boot CPU.
>
> > > > +
> > > > + compatible:
> > > > + oneOf:
> > > > + - description: CPU reset on T-HEAD TH1520 SoC
> > > > + items:
> > > > + - const: thead,reset-th1520
> > >
> > > You've only got one thing here, you don't need the oneOf.
> > > Also, s/reset-th1520/th1520-reset/ please - although I do not know if
> > > "reset" is the right word here. Do we know what the IP block is called
> > > in the TRM/T-Head docs? Perhaps Guo Ren does if not.
> > It's called CPU reset controller; every core has reset_ctrl &
> > reset_entry signals; Soc just gathers them into some regs.
> > For th1520, we have 4 reset_entries registers and 1 reset_ctrl
> > register. Fu Wei would give out more details about it.
>
> Okay, thanks. Sounds like this SoC will have multiple reset controllers
> then, since there is likely one for the peripherals too?
> thead,th1520-cpu-reset seems like a good idea to me?
>
> > > > + entry-reg:
> > > > + $ref: /schemas/types.yaml#/definitions/uint64
> > > > + description: |
> > > > + The entry reg address.
> > > > +
> > > > + entry-cn
> > > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > > + description: |
> > > > + The entry reg count.
> > > > +
> > > > + control-reg:
> > > > + $ref: /schemas/types.yaml#/definitions/uint32
> > It should be uint64.
> >
> > > > + description: |
> > > > + The control reg address.
> > > > +
> > > > + control-val:
> > > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > > + description: |
> > > > + The value to be set into the control reg.
> > > > +
> > > > + csr-copy:
> > > > + $ref: /schemas/types.yaml#/definitions/uint32-array
> > > > + description: |
> > > > + The CSR registers to be cloned during CPU warm reset.
> > >
> > > All of these values set on a per-soc basis, right?
> > Yes
> > > If so, I don't think they should be in here at all since you should be
> > > able to figure out the offsets from the base & the values to write based
> > > on the compatible string alone, no?
> > The driver works with all T-HEAD CPUs, not only for th1520. Some
> > vendors may have their own custom CSRs, so the csr-copy feature is
> > flexible enough to adjust in dts. As far as I can tell, hardware teams
> > typically prefer to focus on the firmware binary rather than setting
> > up the software compiling environment.
>
> In this case "firmware" means opensbi, since that's where Jisheng
> mentioned in their cover that they intended using this.
Yes, firmware -> opensbi. The hardware guys just modify dtb without
recompiling the opensbi.
>
> > > Putting register values into the DT is always "suspect"!
> > It's not register values, it's register offset/ CSR number.
>
> So "control-val" is not a value? "The value to be set into the control
> reg" makes it sound oddly like one!!
>
> My point I guess is that this entry could be written like
>
> reset-controller@ffff019050 {
> compatible = "thead,th1520-cpu-reset";
> reg = <0xff 0xff019050 0xfoo 0xbar>, <0xff 0xff015004 0xfoo 0xbar>;
> };
>
> or even:
>
> reset-controller@ffff019050 {
> compatible = "thead,th1520-cpu-reset";
> reg = <0xff 0xff019050 0xfoo 0xbar>, <0xff 0xff015004 0xfoo 0xbar>;
> reg-names = "entry", "control";
> };
Better naming, I agree with you at this point.
But, we have to make changes to the current opensbi implementation to
match your advice.
>
> And csr-copy, entry-cn and control-val can be derived from the
> compatible string given you've said they are set on a per-soc basis.
>
> > > > +required:
> > > > + - compatible
> > > > +
> > > > +additionalProperties: false
> > > > +
> > > > +examples:
> > > > + - |
> > > > + cpurst: cpurst@ffff019050 {
> > > ^^^^^^^^^^^^^^^^^
> > > This is also "suspect" and implies that "entry reg" should just be a
> > > normal "reg" property.
> > Yes, but we needn't reg, here. It should be:
> >
> > cpurst {
>
> I don't think it should! Firstly, "cpurst" is not a generic node name,
Yes, reset-controller is better.
> but I also don't agree that "control-reg" and "entry-reg" should not
> just be 2 reg entries.
Yes, Yes. You've said.
>
> Cheers,
> Conor.
--
Best Regards
Guo Ren
Hi Jisheng
On 02:45 Fri 19 May , Jisheng Zhang wrote:
> Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core
> module which is powered by T-HEAD's TH1520 SoC. Add minimal device
> tree files for the core module and the development board.
>
> Support basic uart/gpio/dmac drivers, so supports booting to a basic
> shell.
>
> FWICT, one issue I'm not sure is the cpu reset dt-binding: IIUC, the
> secondary CPUs in T-HEAD SMP capable platforms need some special
> handling. The first one is to write the warm reset entry to entry
> register. The second one is write a SoC specific control value to
> a SoC specific control reg. The last one is to clone some CSRs for
> secondary CPUs to ensure these CSRs' values are the same as the
> main boot CPU. This DT node is mainly used by opensbi firmware.
> Any suggestion about this reset dt-binding is appreciated!
>
> Thanks
>
> Since v1:
> - add missing plic, clint, th1520 itself dt-bindings
> - use c900-plic
> - s/light/th1520
> - add dt-binding for T-HEAD CPU reset
> - enable ARCH_THEAD in defconfig
> - fix all dtbs_check error/warning except the CPU RESET, see above.
it would be nice to have a URL reference to v0
https://lore.kernel.org/all/[email protected]/
>
> Jisheng Zhang (9):
> dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC
> dt-bindings: timer: Add T-HEAD TH1520 clint
> dt-bindings: riscv: Add T-HEAD TH1520 board compatibles
> dt-binding: riscv: add T-HEAD CPU reset
> riscv: Add the T-HEAD SoC family Kconfig option
> riscv: dts: add initial T-HEAD TH1520 SoC device tree
> riscv: dts: thead: add sipeed Lichee Pi 4A board device tree
> MAINTAINERS: add entry for T-HEAD RISC-V SoC
> riscv: defconfig: enable T-HEAD SoC
>
> .../sifive,plic-1.0.0.yaml | 1 +
> .../bindings/riscv/thead,cpu-reset.yaml | 69 +++
> .../devicetree/bindings/riscv/thead.yaml | 29 ++
> .../bindings/timer/sifive,clint.yaml | 1 +
> MAINTAINERS | 6 +
> arch/riscv/Kconfig.socs | 6 +
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/thead/Makefile | 2 +
> .../dts/thead/th1520-lichee-module-4a.dtsi | 38 ++
> .../boot/dts/thead/th1520-lichee-pi-4a.dts | 32 ++
> arch/riscv/boot/dts/thead/th1520.dtsi | 451 ++++++++++++++++++
> arch/riscv/configs/defconfig | 1 +
> 12 files changed, 637 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
> create mode 100644 Documentation/devicetree/bindings/riscv/thead.yaml
> create mode 100644 arch/riscv/boot/dts/thead/Makefile
> create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
> create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
> create mode 100644 arch/riscv/boot/dts/thead/th1520.dtsi
>
> --
> 2.40.0
>
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv
--
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55
Hi Jisheng:
On 02:45 Fri 19 May , Jisheng Zhang wrote:
> Add initial device tree for the TH1520 RISC-V SoC by T-HEAD.
>
> Signed-off-by: Jisheng Zhang <[email protected]>
> ---
> arch/riscv/boot/dts/thead/th1520.dtsi | 451 ++++++++++++++++++++++++++
> 1 file changed, 451 insertions(+)
> create mode 100644 arch/riscv/boot/dts/thead/th1520.dtsi
>
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> new file mode 100644
> index 000000000000..60754d7c6319
> --- /dev/null
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -0,0 +1,451 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2021 Alibaba Group Holding Limited.
I think you are trying to copy this from vendor's kernel?
would it be more proper/accurate to set as
T-HEAD Semiconductor Co., LTD
> + * Copyright (C) 2023 Jisheng Zhang <[email protected]>
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + compatible = "thead,th1520";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus: cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <3000000>;
> +
> + c910_0: cpu@0 {
> + compatible = "thead,c910", "riscv";
> + device_type = "cpu";
> + riscv,isa = "rv64imafdc";
> + reg = <0>;
> + i-cache-block-size = <64>;
> + i-cache-size = <65536>;
> + i-cache-sets = <512>;
> + d-cache-block-size = <64>;
> + d-cache-size = <65536>;
> + d-cache-sets = <512>;
> + next-level-cache = <&l2_cache>;
> + mmu-type = "riscv,sv39";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + c910_1: cpu@1 {
> + compatible = "thead,c910", "riscv";
> + device_type = "cpu";
> + riscv,isa = "rv64imafdc";
> + reg = <1>;
> + i-cache-block-size = <64>;
> + i-cache-size = <65536>;
> + i-cache-sets = <512>;
> + d-cache-block-size = <64>;
> + d-cache-size = <65536>;
> + d-cache-sets = <512>;
> + next-level-cache = <&l2_cache>;
> + mmu-type = "riscv,sv39";
> +
> + cpu1_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + c910_2: cpu@2 {
> + compatible = "thead,c910", "riscv";
> + device_type = "cpu";
> + riscv,isa = "rv64imafdc";
> + reg = <2>;
> + i-cache-block-size = <64>;
> + i-cache-size = <65536>;
> + i-cache-sets = <512>;
> + d-cache-block-size = <64>;
> + d-cache-size = <65536>;
> + d-cache-sets = <512>;
> + next-level-cache = <&l2_cache>;
> + mmu-type = "riscv,sv39";
> +
> + cpu2_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + c910_3: cpu@3 {
> + compatible = "thead,c910", "riscv";
> + device_type = "cpu";
> + riscv,isa = "rv64imafdc";
> + reg = <3>;
> + i-cache-block-size = <64>;
> + i-cache-size = <65536>;
> + i-cache-sets = <512>;
> + d-cache-block-size = <64>;
> + d-cache-size = <65536>;
> + d-cache-sets = <512>;
> + next-level-cache = <&l2_cache>;
> + mmu-type = "riscv,sv39";
> +
> + cpu3_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&c910_0>;
> + };
> +
> + core1 {
> + cpu = <&c910_1>;
> + };
> +
> + core2 {
> + cpu = <&c910_2>;
> + };
> +
> + core3 {
> + cpu = <&c910_3>;
> + };
> + };
> + };
> +
> + l2_cache: l2-cache {
> + compatible = "cache";
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-size = <1048576>;
> + cache-sets = <1024>;
> + cache-unified;
> + };
> + };
> +
> + osc: oscillator {
> + compatible = "fixed-clock";
> + clock-output-names = "osc_24m";
> + #clock-cells = <0>;
> + };
> +
> + osc_32k: 32k-oscillator {
> + compatible = "fixed-clock";
> + clock-output-names = "osc_32k";
> + #clock-cells = <0>;
> + };
> +
> + apb_clk: apb-clk-clock {
> + compatible = "fixed-clock";
> + clock-output-names = "apb_clk";
> + #clock-cells = <0>;
> + };
> +
> + uart_sclk: uart-sclk-clock {
> + compatible = "fixed-clock";
> + clock-output-names = "uart_sclk";
> + #clock-cells = <0>;
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + interrupt-parent = <&plic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + cpurst: cpurst {
> + compatible = "thead,reset-th1520";
> + entry-reg = <0xff 0xff019050>;
> + entry-cnt = <4>;
> + control-reg = <0xff 0xff015004>;
> + control-val = <0x1c>;
> + csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3 0x7c5 0x7cc>;
> + };
> +
> + plic: interrupt-controller@ffd8000000 {
> + compatible = "thead,th1520-plic", "thead,c900-plic";
> + reg = <0xff 0xd8000000 0x0 0x01000000>;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
> + <&cpu1_intc 11>, <&cpu1_intc 9>,
> + <&cpu2_intc 11>, <&cpu2_intc 9>,
> + <&cpu3_intc 11>, <&cpu3_intc 9>;
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + riscv,ndev = <240>;
> + };
> +
> + clint: timer@ffdc000000 {
> + compatible = "thead,th1520-clint", "thead,c900-clint";
> + reg = <0xff 0xdc000000 0x0 0x00010000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> + <&cpu1_intc 3>, <&cpu1_intc 7>,
> + <&cpu2_intc 3>, <&cpu2_intc 7>,
> + <&cpu3_intc 3>, <&cpu3_intc 7>;
> + };
> +
> + uart0: serial@ffe7014000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0xff 0xe7014000 0x0 0x4000>;
~~~~~
probably you are writing this according to the address map?
from UART controller's perspective, it's valid reg range from 0x00 - 0xFF
so I think limiting the address space to 0x100 would be more proper?
less io space consumed, less page table needed?
> + interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&uart_sclk>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart1: serial@ffe7f00000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0xff 0xe7f00000 0x0 0x4000>;
> + interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&uart_sclk>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart3: serial@ffe7f04000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0xff 0xe7f04000 0x0 0x4000>;
> + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&uart_sclk>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + gpio2: gpio@ffe7f34000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0xff 0xe7f34000 0x0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + portc: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + gpio3: gpio@ffe7f38000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0xff 0xe7f38000 0x0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + portd: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + gpio0: gpio@ffec005000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0xff 0xec005000 0x0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + porta: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + gpio1: gpio@ffec006000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0xff 0xec006000 0x0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + portb: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + uart2: serial@ffec010000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0xff 0xec010000 0x0 0x4000>;
> + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&uart_sclk>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + dmac0: dma-controller@ffefc00000 {
> + compatible = "snps,axi-dma-1.01a";
> + reg = <0xff 0xefc00000 0x0 0x1000>;
> + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&apb_clk>, <&apb_clk>;
> + clock-names = "core-clk", "cfgr-clk";
> + #dma-cells = <1>;
> + dma-channels = <4>;
> + snps,block-size = <65536 65536 65536 65536>;
> + snps,priority = <0 1 2 3>;
> + snps,dma-masters = <1>;
> + snps,data-width = <4>;
> + snps,axi-max-burst-len = <16>;
> + status = "disabled";
> + };
> +
> + timer0: timer@ffefc32000 {
> + compatible = "snps,dw-apb-timer";
> + reg = <0xff 0xefc32000 0x0 0x14>;
> + clocks = <&apb_clk>;
> + clock-names = "timer";
> + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + timer1: timer@ffefc32014 {
> + compatible = "snps,dw-apb-timer";
> + reg = <0xff 0xefc32014 0x0 0x14>;
> + clocks = <&apb_clk>;
> + clock-names = "timer";
> + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + timer2: timer@ffefc32028 {
> + compatible = "snps,dw-apb-timer";
> + reg = <0xff 0xefc32028 0x0 0x14>;
> + clocks = <&apb_clk>;
> + clock-names = "timer";
> + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + timer3: timer@ffefc3203c {
> + compatible = "snps,dw-apb-timer";
> + reg = <0xff 0xefc3203c 0x0 0x14>;
> + clocks = <&apb_clk>;
> + clock-names = "timer";
> + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + uart4: serial@fff7f08000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0xff 0xf7f08000 0x0 0x4000>;
> + interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&uart_sclk>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart5: serial@fff7f0c000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0xff 0xf7f0c000 0x0 0x4000>;
> + interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&uart_sclk>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + timer4: timer@ffffc33000 {
> + compatible = "snps,dw-apb-timer";
> + reg = <0xff 0xffc33000 0x0 0x14>;
> + clocks = <&apb_clk>;
> + clock-names = "timer";
> + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + timer5: timer@ffffc33014 {
> + compatible = "snps,dw-apb-timer";
> + reg = <0xff 0xffc33014 0x0 0x14>;
> + clocks = <&apb_clk>;
> + clock-names = "timer";
> + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + timer6: timer@ffffc33028 {
> + compatible = "snps,dw-apb-timer";
> + reg = <0xff 0xffc33028 0x0 0x14>;
> + clocks = <&apb_clk>;
> + clock-names = "timer";
> + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + timer7: timer@ffffc3303c {
> + compatible = "snps,dw-apb-timer";
> + reg = <0xff 0xffc3303c 0x0 0x14>;
> + clocks = <&apb_clk>;
> + clock-names = "timer";
> + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + ao_gpio0: gpio@fffff41000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0xff 0xfff41000 0x0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + porte: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + ao_gpio1: gpio@fffff52000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0xff 0xfff52000 0x0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + portf: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> + };
> +};
> --
> 2.40.0
>
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv
--
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55
On Fri, 19 May 2023 02:45:36 +0800, Jisheng Zhang wrote:
> The secondary CPUs in T-HEAD SMP capable platforms need some special
> handling. The first one is to write the warm reset entry to entry
> register. The second one is write a SoC specific control value to
> a SoC specific control reg. The last one is to clone some CSRs for
> secondary CPUs to ensure these CSRs' values are the same as the
> main boot CPU. This DT node is mainly used by opensbi firmware.
>
> Signed-off-by: Jisheng Zhang <[email protected]>
> ---
> .../bindings/riscv/thead,cpu-reset.yaml | 69 +++++++++++++++++++
> 1 file changed, 69 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/riscv/thead,cpu-reset.example.dts:18.35-25.11: Warning (unit_address_vs_reg): /example-0/cpurst@ffff019050: node has a unit name, but no reg or ranges property
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/riscv/thead,cpu-reset.example.dtb: cpurst@ffff019050: control-reg:0: [255, 4278276100] is too long
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/riscv/thead,cpu-reset.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1783487
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.