From: Bartosz Golaszewski <[email protected]>
Add the GPU and PCIe IOMMUs for sa8775p platforms as well as the required
GPU clock controller driver.
NOTE: I didn't pick up Krzysztof's tag for patch 4/5 as the patch changed
significantly.
v3 -> v4:
- fix the adreno smmu compatibles
- drop patches that are already in next
v2 -> v3:
- select QCOM_GDSC in Kconfig for the GPUCC module
- the GPU SMMU is actually an adreno SMMU so describe it as such and
fix the DT
- fix the mapped memory size for the PCIe SMMU
v1 -> v2:
- remove unused include in the GPUCC driver
- remove unused clock from the GPUCC driver and make it compatible
with the generic QCom GPUCC bindings
- put the new defconfig option in the right place (as per savedefconfig)
and make the GPUCC driver a module rather than built-in
- describe the smmu clocks for sa8775p in dt-bindings
Bartosz Golaszewski (5):
arm64: defconfig: enable the SA8775P GPUCC driver
arm64: dts: qcom: sa8775p: add the pcie smmu node
arm64: dts: qcom: sa8775p: add the GPU clock controller node
dt-bindings: iommu: arm,smmu: enable clocks for sa8775p Adreno SMMU
arm64: dts: qcom: sa8775p: add the GPU IOMMU node
.../devicetree/bindings/iommu/arm,smmu.yaml | 6 +-
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 125 ++++++++++++++++++
arch/arm64/configs/defconfig | 1 +
3 files changed, 130 insertions(+), 2 deletions(-)
--
2.37.2
From: Bartosz Golaszewski <[email protected]>
The GPU SMMU will require the clocks property to be set so put the
relevant compatible into the adreno if-then block.
Signed-off-by: Bartosz Golaszewski <[email protected]>
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index ba677d401e24..53bed0160be8 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -79,6 +79,7 @@ properties:
- description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
items:
- enum:
+ - qcom,sa8775p-smmu-500
- qcom,sc7280-smmu-500
- qcom,sm6115-smmu-500
- qcom,sm6125-smmu-500
@@ -331,7 +332,9 @@ allOf:
properties:
compatible:
contains:
- const: qcom,sc7280-smmu-500
+ enum:
+ - qcom,sa8775p-smmu-500
+ - qcom,sc7280-smmu-500
then:
properties:
clock-names:
@@ -413,7 +416,6 @@ allOf:
- nvidia,smmu-500
- qcom,qcm2290-smmu-500
- qcom,qdu1000-smmu-500
- - qcom,sa8775p-smmu-500
- qcom,sc7180-smmu-500
- qcom,sc8180x-smmu-500
- qcom,sc8280xp-smmu-500
--
2.37.2
From: Bartosz Golaszewski <[email protected]>
Add the GPUCC node for sa8775p platforms.
Signed-off-by: Bartosz Golaszewski <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index a23175352a20..191b510b5a1a 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -591,6 +591,20 @@ tcsr_mutex: hwlock@1f40000 {
#hwlock-cells = <1>;
};
+ gpucc: clock-controller@3d90000 {
+ compatible = "qcom,sa8775p-gpucc";
+ reg = <0x0 0x03d90000 0x0 0xa000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+ clock-names = "bi_tcxo",
+ "gcc_gpu_gpll0_clk_src",
+ "gcc_gpu_gpll0_div_clk_src";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sa8775p-pdc", "qcom,pdc";
reg = <0x0 0x0b220000 0x0 0x30000>,
--
2.37.2
From: Bartosz Golaszewski <[email protected]>
Add the Adreno GPU IOMMU for sa8775p-based platforms.
Signed-off-by: Bartosz Golaszewski <[email protected]>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 37 +++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 191b510b5a1a..92712d0c4100 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
+#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -605,6 +606,42 @@ gpucc: clock-controller@3d90000 {
#power-domain-cells = <1>;
};
+ adreno_smmu: iommu@3da0000 {
+ compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu",
+ "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x0 0x03da0000 0x0 0x20000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <2>;
+ dma-coherent;
+ power-domains = <&gpucc GPU_CC_CX_GDSC>;
+ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_HUB_AON_CLK>;
+ clock-names = "gcc_gpu_memnoc_gfx_clk",
+ "gcc_gpu_snoc_dvm_gfx_clk",
+ "gpu_cc_ahb_clk",
+ "gpu_cc_hlos1_vote_gpu_smmu_clk",
+ "gpu_cc_cx_gmu_clk",
+ "gpu_cc_hub_cx_int_clk",
+ "gpu_cc_hub_aon_clk";
+ interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sa8775p-pdc", "qcom,pdc";
reg = <0x0 0x0b220000 0x0 0x30000>,
--
2.37.2
From: Bartosz Golaszewski <[email protected]>
Add the PCIe SMMU node for sa8775p platforms.
Signed-off-by: Bartosz Golaszewski <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 74 +++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 2343df7e0ea4..a23175352a20 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -809,6 +809,80 @@ apps_smmu: iommu@15000000 {
<GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
};
+ pcie_smmu: iommu@15200000 {
+ compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x0 0x15200000 0x0 0x80000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <2>;
+
+ interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
--
2.37.2
From: Bartosz Golaszewski <[email protected]>
Enable the GPUCC module for SA8775P platforms in the arm64 defconfig.
Signed-off-by: Bartosz Golaszewski <[email protected]>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index b6342b40c600..e1063ab32658 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1164,6 +1164,7 @@ CONFIG_MSM_GCC_8998=y
CONFIG_QCS_GCC_404=y
CONFIG_SA_GCC_8775P=y
CONFIG_SC_DISPCC_8280XP=m
+CONFIG_SA_GPUCC_8775P=m
CONFIG_SC_GCC_7180=y
CONFIG_SC_GCC_7280=y
CONFIG_SC_GCC_8180X=y
--
2.37.2
On 17/04/2023 14:58, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <[email protected]>
>
> Add the PCIe SMMU node for sa8775p platforms.
>
> Signed-off-by: Bartosz Golaszewski <[email protected]>
> Reviewed-by: Konrad Dybcio <[email protected]>
> ---
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Mon, Apr 17, 2023 at 02:58:41PM +0200, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <[email protected]>
>
> Add the PCIe SMMU node for sa8775p platforms.
>
> Signed-off-by: Bartosz Golaszewski <[email protected]>
> Reviewed-by: Konrad Dybcio <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 74 +++++++++++++++++++++++++++
> 1 file changed, 74 insertions(+)
Hi Bartosz,
Adding Shazad.
I upgraded to the meta Shazad mentioned in v2[1], but I still get a
synchronous external abort on reboot:
[ 8.285500] arm-smmu 15200000.iommu: disabling translation
4 12.145913 Injecting instruction/data abort to VM 3, original ESR_EL2 = 0x93800047, fault VA = 0xffff80000a080000, fault IPA = 0x15200000, ELR_EL2 = 0xffffae99a42c96e4
[ 8.310145] Internal error: synchronous external abort: 0000000096000010 [#1] PREEMPT SMP
[ 8.316561] Modules linked in: qcom_pon crct10dif_ce gpucc_sa8775p i2c_qcom_geni spi_geni_qcom ufs_qcom phy_qcom_qmp_ufs socinfo fuse ipv6
[ 8.331284] CPU: 4 PID: 1 Comm: systemd-shutdow Not tainted 6.3.0-rc7-next-20230417-00014-g93340f644112 #136
[ 8.341365] Hardware name: Qualcomm SA8775P Ride (DT)
[ 8.346555] pstate: 00400005 (nzcv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[ 8.353705] pc : arm_smmu_device_shutdown+0x64/0x154
[ 8.358815] lr : arm_smmu_device_shutdown+0x3c/0x154
[ 8.363915] sp : ffff80000805bc00
[ 8.367322] x29: ffff80000805bc00 x28: ffff69c250ca0000 x27: 0000000000000000
[ 8.374643] x26: ffffae99a53357f8 x25: 0000000000000001 x24: ffffae99a60d5028
[ 8.381963] x23: ffff69c2516ab890 x22: ffffae99a614e218 x21: ffff69c251668c10
[ 8.389283] x20: ffff69c2516ab810 x19: ffff69c251479a80 x18: 0000000000000006
[ 8.396603] x17: 0000000000000014 x16: 0000000000000030 x15: ffff80000805b5d0
[ 8.403923] x14: 0000000000000000 x13: ffffae99a5ce1a28 x12: 00000000000005eb
[ 8.411243] x11: 00000000000001f9 x10: ffffae99a5d39a28 x9 : ffffae99a5ce1a28
[ 8.418563] x8 : 00000000ffffefff x7 : ffffae99a5d39a28 x6 : 80000000fffff000
[ 8.425884] x5 : 000000000000bff4 x4 : 0000000000000000 x3 : 0000000000000000
[ 8.433204] x2 : 0000000000000000 x1 : ffff80000a080000 x0 : 0000000000000001
[ 8.440524] Call trace:
[ 8.443039] arm_smmu_device_shutdown+0x64/0x154
[ 8.447784] platform_shutdown+0x24/0x34
[ 8.451821] device_shutdown+0x150/0x258
[ 8.455857] kernel_restart+0x40/0xc0
[ 8.459623] __do_sys_reboot+0x1f0/0x274
[ 8.463656] __arm64_sys_reboot+0x24/0x30
[ 8.467778] invoke_syscall+0x48/0x114
[ 8.471633] el0_svc_common+0x40/0xf4
[ 8.475397] do_el0_svc+0x3c/0x9c
[ 8.478806] el0_svc+0x2c/0x84
[ 8.481947] el0t_64_sync_handler+0xf4/0x120
[ 8.486334] el0t_64_sync+0x190/0x194
[ 8.490100] Code: f9400404 b50005e4 f9400661 52800020 (b9000020)
[ 8.496361] ---[ end trace 0000000000000000 ]---
[1] https://lore.kernel.org/linux-arm-kernel/[email protected]/
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index 2343df7e0ea4..a23175352a20 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -809,6 +809,80 @@ apps_smmu: iommu@15000000 {
> <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> + pcie_smmu: iommu@15200000 {
> + compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
> + reg = <0x0 0x15200000 0x0 0x80000>;
> + #iommu-cells = <2>;
> + #global-interrupts = <2>;
> +
> + interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> intc: interrupt-controller@17a00000 {
> compatible = "arm,gic-v3";
> reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
> --
> 2.37.2
>
--
Eric Chanudet
On 18.04.2023 18:52, Eric Chanudet wrote:
> On Mon, Apr 17, 2023 at 02:58:41PM +0200, Bartosz Golaszewski wrote:
>> From: Bartosz Golaszewski <[email protected]>
>>
>> Add the PCIe SMMU node for sa8775p platforms.
>>
>> Signed-off-by: Bartosz Golaszewski <[email protected]>
>> Reviewed-by: Konrad Dybcio <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 74 +++++++++++++++++++++++++++
>> 1 file changed, 74 insertions(+)
>
> Hi Bartosz,
>
> Adding Shazad.
>
> I upgraded to the meta Shazad mentioned in v2[1], but I still get a
> synchronous external abort on reboot:
Taking a look at downstream, looks like:
- it's marked as dma-coherent
- it expects interconnects (MAS_PCIE[01]<->SLV_EBI1)
Perhaps that's worth looking into
Konrad
>
> [ 8.285500] arm-smmu 15200000.iommu: disabling translation
> 4 12.145913 Injecting instruction/data abort to VM 3, original ESR_EL2 = 0x93800047, fault VA = 0xffff80000a080000, fault IPA = 0x15200000, ELR_EL2 = 0xffffae99a42c96e4
> [ 8.310145] Internal error: synchronous external abort: 0000000096000010 [#1] PREEMPT SMP
> [ 8.316561] Modules linked in: qcom_pon crct10dif_ce gpucc_sa8775p i2c_qcom_geni spi_geni_qcom ufs_qcom phy_qcom_qmp_ufs socinfo fuse ipv6
> [ 8.331284] CPU: 4 PID: 1 Comm: systemd-shutdow Not tainted 6.3.0-rc7-next-20230417-00014-g93340f644112 #136
> [ 8.341365] Hardware name: Qualcomm SA8775P Ride (DT)
> [ 8.346555] pstate: 00400005 (nzcv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> [ 8.353705] pc : arm_smmu_device_shutdown+0x64/0x154
> [ 8.358815] lr : arm_smmu_device_shutdown+0x3c/0x154
> [ 8.363915] sp : ffff80000805bc00
> [ 8.367322] x29: ffff80000805bc00 x28: ffff69c250ca0000 x27: 0000000000000000
> [ 8.374643] x26: ffffae99a53357f8 x25: 0000000000000001 x24: ffffae99a60d5028
> [ 8.381963] x23: ffff69c2516ab890 x22: ffffae99a614e218 x21: ffff69c251668c10
> [ 8.389283] x20: ffff69c2516ab810 x19: ffff69c251479a80 x18: 0000000000000006
> [ 8.396603] x17: 0000000000000014 x16: 0000000000000030 x15: ffff80000805b5d0
> [ 8.403923] x14: 0000000000000000 x13: ffffae99a5ce1a28 x12: 00000000000005eb
> [ 8.411243] x11: 00000000000001f9 x10: ffffae99a5d39a28 x9 : ffffae99a5ce1a28
> [ 8.418563] x8 : 00000000ffffefff x7 : ffffae99a5d39a28 x6 : 80000000fffff000
> [ 8.425884] x5 : 000000000000bff4 x4 : 0000000000000000 x3 : 0000000000000000
> [ 8.433204] x2 : 0000000000000000 x1 : ffff80000a080000 x0 : 0000000000000001
> [ 8.440524] Call trace:
> [ 8.443039] arm_smmu_device_shutdown+0x64/0x154
> [ 8.447784] platform_shutdown+0x24/0x34
> [ 8.451821] device_shutdown+0x150/0x258
> [ 8.455857] kernel_restart+0x40/0xc0
> [ 8.459623] __do_sys_reboot+0x1f0/0x274
> [ 8.463656] __arm64_sys_reboot+0x24/0x30
> [ 8.467778] invoke_syscall+0x48/0x114
> [ 8.471633] el0_svc_common+0x40/0xf4
> [ 8.475397] do_el0_svc+0x3c/0x9c
> [ 8.478806] el0_svc+0x2c/0x84
> [ 8.481947] el0t_64_sync_handler+0xf4/0x120
> [ 8.486334] el0t_64_sync+0x190/0x194
> [ 8.490100] Code: f9400404 b50005e4 f9400661 52800020 (b9000020)
> [ 8.496361] ---[ end trace 0000000000000000 ]---
>
> [1] https://lore.kernel.org/linux-arm-kernel/[email protected]/
>
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> index 2343df7e0ea4..a23175352a20 100644
>> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> @@ -809,6 +809,80 @@ apps_smmu: iommu@15000000 {
>> <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
>> };
>>
>> + pcie_smmu: iommu@15200000 {
>> + compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
>> + reg = <0x0 0x15200000 0x0 0x80000>;
>> + #iommu-cells = <2>;
>> + #global-interrupts = <2>;
>> +
>> + interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> intc: interrupt-controller@17a00000 {
>> compatible = "arm,gic-v3";
>> reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
>> --
>> 2.37.2
>>
>
On 4/18/2023 10:22 PM, Eric Chanudet wrote:
> On Mon, Apr 17, 2023 at 02:58:41PM +0200, Bartosz Golaszewski wrote:
>> From: Bartosz Golaszewski <[email protected]>
>>
>> Add the PCIe SMMU node for sa8775p platforms.
>>
>> Signed-off-by: Bartosz Golaszewski <[email protected]>
>> Reviewed-by: Konrad Dybcio <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 74 +++++++++++++++++++++++++++
>> 1 file changed, 74 insertions(+)
>
> Hi Bartosz,
>
> Adding Shazad.
>
> I upgraded to the meta Shazad mentioned in v2[1], but I still get a
> synchronous external abort on reboot:
>
> [ 8.285500] arm-smmu 15200000.iommu: disabling translation
> 4 12.145913 Injecting instruction/data abort to VM 3, original ESR_EL2 = 0x93800047, fault VA = 0xffff80000a080000, fault IPA = 0x15200000, ELR_EL2 = 0xffffae99a42c96e4
> [ 8.310145] Internal error: synchronous external abort: 0000000096000010 [#1] PREEMPT SMP
> [ 8.316561] Modules linked in: qcom_pon crct10dif_ce gpucc_sa8775p i2c_qcom_geni spi_geni_qcom ufs_qcom phy_qcom_qmp_ufs socinfo fuse ipv6
> [ 8.331284] CPU: 4 PID: 1 Comm: systemd-shutdow Not tainted 6.3.0-rc7-next-20230417-00014-g93340f644112 #136
> [ 8.341365] Hardware name: Qualcomm SA8775P Ride (DT)
> [ 8.346555] pstate: 00400005 (nzcv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
> [ 8.353705] pc : arm_smmu_device_shutdown+0x64/0x154
> [ 8.358815] lr : arm_smmu_device_shutdown+0x3c/0x154
> [ 8.363915] sp : ffff80000805bc00
> [ 8.367322] x29: ffff80000805bc00 x28: ffff69c250ca0000 x27: 0000000000000000
> [ 8.374643] x26: ffffae99a53357f8 x25: 0000000000000001 x24: ffffae99a60d5028
> [ 8.381963] x23: ffff69c2516ab890 x22: ffffae99a614e218 x21: ffff69c251668c10
> [ 8.389283] x20: ffff69c2516ab810 x19: ffff69c251479a80 x18: 0000000000000006
> [ 8.396603] x17: 0000000000000014 x16: 0000000000000030 x15: ffff80000805b5d0
> [ 8.403923] x14: 0000000000000000 x13: ffffae99a5ce1a28 x12: 00000000000005eb
> [ 8.411243] x11: 00000000000001f9 x10: ffffae99a5d39a28 x9 : ffffae99a5ce1a28
> [ 8.418563] x8 : 00000000ffffefff x7 : ffffae99a5d39a28 x6 : 80000000fffff000
> [ 8.425884] x5 : 000000000000bff4 x4 : 0000000000000000 x3 : 0000000000000000
> [ 8.433204] x2 : 0000000000000000 x1 : ffff80000a080000 x0 : 0000000000000001
> [ 8.440524] Call trace:
> [ 8.443039] arm_smmu_device_shutdown+0x64/0x154
> [ 8.447784] platform_shutdown+0x24/0x34
> [ 8.451821] device_shutdown+0x150/0x258
> [ 8.455857] kernel_restart+0x40/0xc0
> [ 8.459623] __do_sys_reboot+0x1f0/0x274
> [ 8.463656] __arm64_sys_reboot+0x24/0x30
> [ 8.467778] invoke_syscall+0x48/0x114
> [ 8.471633] el0_svc_common+0x40/0xf4
> [ 8.475397] do_el0_svc+0x3c/0x9c
> [ 8.478806] el0_svc+0x2c/0x84
> [ 8.481947] el0t_64_sync_handler+0xf4/0x120
> [ 8.486334] el0t_64_sync+0x190/0x194
> [ 8.490100] Code: f9400404 b50005e4 f9400661 52800020 (b9000020)
> [ 8.496361] ---[ end trace 0000000000000000 ]---
>
> [1] https://lore.kernel.org/linux-arm-kernel/[email protected]/
>
Adding Parikshit to comment.
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> index 2343df7e0ea4..a23175352a20 100644
>> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> @@ -809,6 +809,80 @@ apps_smmu: iommu@15000000 {
>> <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
>> };
>>
>> + pcie_smmu: iommu@15200000 {
>> + compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
>> + reg = <0x0 0x15200000 0x0 0x80000>;
>> + #iommu-cells = <2>;
>> + #global-interrupts = <2>;
>> +
>> + interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> intc: interrupt-controller@17a00000 {
>> compatible = "arm,gic-v3";
>> reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
>> --
>> 2.37.2
>>
>
-Shazad
On Mon, 17 Apr 2023 14:58:39 +0200, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <[email protected]>
>
> Add the GPU and PCIe IOMMUs for sa8775p platforms as well as the required
> GPU clock controller driver.
>
> NOTE: I didn't pick up Krzysztof's tag for patch 4/5 as the patch changed
> significantly.
>
> [...]
Applied, thanks!
[1/5] arm64: defconfig: enable the SA8775P GPUCC driver
commit: 8125a56125114d91843918cc6ef95367c4c39fc7
Best regards,
--
Bjorn Andersson <[email protected]>
On Mon, Apr 17, 2023 at 2:58 PM Bartosz Golaszewski <[email protected]> wrote:
>
> From: Bartosz Golaszewski <[email protected]>
>
> The GPU SMMU will require the clocks property to be set so put the
> relevant compatible into the adreno if-then block.
>
> Signed-off-by: Bartosz Golaszewski <[email protected]>
> ---
> Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> index ba677d401e24..53bed0160be8 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> @@ -79,6 +79,7 @@ properties:
> - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
> items:
> - enum:
> + - qcom,sa8775p-smmu-500
> - qcom,sc7280-smmu-500
> - qcom,sm6115-smmu-500
> - qcom,sm6125-smmu-500
> @@ -331,7 +332,9 @@ allOf:
> properties:
> compatible:
> contains:
> - const: qcom,sc7280-smmu-500
> + enum:
> + - qcom,sa8775p-smmu-500
> + - qcom,sc7280-smmu-500
> then:
> properties:
> clock-names:
> @@ -413,7 +416,6 @@ allOf:
> - nvidia,smmu-500
> - qcom,qcm2290-smmu-500
> - qcom,qdu1000-smmu-500
> - - qcom,sa8775p-smmu-500
> - qcom,sc7180-smmu-500
> - qcom,sc8180x-smmu-500
> - qcom,sc8280xp-smmu-500
> --
> 2.37.2
>
Gentle ping for a review and a pick up. The DT patches that use this
schema are in next now so check_dtbs will now fail.
Bart
On 16/05/2023 12:07, Bartosz Golaszewski wrote:
> On Mon, Apr 17, 2023 at 2:58 PM Bartosz Golaszewski <[email protected]> wrote:
>>
>> From: Bartosz Golaszewski <[email protected]>
>>
>> The GPU SMMU will require the clocks property to be set so put the
>> relevant compatible into the adreno if-then block.
>>
>> Signed-off-by: Bartosz Golaszewski <[email protected]>
>> ---
>> Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 6 ++++--
>> 1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
>> index ba677d401e24..53bed0160be8 100644
>> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
>> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
>> @@ -79,6 +79,7 @@ properties:
>> - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
>> items:
>> - enum:
>> + - qcom,sa8775p-smmu-500
>> - qcom,sc7280-smmu-500
>> - qcom,sm6115-smmu-500
>> - qcom,sm6125-smmu-500
>> @@ -331,7 +332,9 @@ allOf:
>> properties:
>> compatible:
>> contains:
>> - const: qcom,sc7280-smmu-500
>> + enum:
>> + - qcom,sa8775p-smmu-500
>> + - qcom,sc7280-smmu-500
>> then:
>> properties:
>> clock-names:
>> @@ -413,7 +416,6 @@ allOf:
>> - nvidia,smmu-500
>> - qcom,qcm2290-smmu-500
>> - qcom,qdu1000-smmu-500
>> - - qcom,sa8775p-smmu-500
>> - qcom,sc7180-smmu-500
>> - qcom,sc8180x-smmu-500
>> - qcom,sc8280xp-smmu-500
>> --
>> 2.37.2
>>
>
> Gentle ping for a review and a pick up. The DT patches that use this
> schema are in next now so check_dtbs will now fail.
I assume this is not for me, as you got my tag in v2, which I repeated
in v3.
Best regards,
Krzysztof
On Tue, May 16, 2023 at 12:33 PM Krzysztof Kozlowski
<[email protected]> wrote:
>
> On 16/05/2023 12:07, Bartosz Golaszewski wrote:
> > On Mon, Apr 17, 2023 at 2:58 PM Bartosz Golaszewski <[email protected]> wrote:
> >>
> >> From: Bartosz Golaszewski <[email protected]>
> >>
> >> The GPU SMMU will require the clocks property to be set so put the
> >> relevant compatible into the adreno if-then block.
> >>
> >> Signed-off-by: Bartosz Golaszewski <[email protected]>
> >> ---
> >> Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 6 ++++--
> >> 1 file changed, 4 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> >> index ba677d401e24..53bed0160be8 100644
> >> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> >> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> >> @@ -79,6 +79,7 @@ properties:
> >> - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
> >> items:
> >> - enum:
> >> + - qcom,sa8775p-smmu-500
> >> - qcom,sc7280-smmu-500
> >> - qcom,sm6115-smmu-500
> >> - qcom,sm6125-smmu-500
> >> @@ -331,7 +332,9 @@ allOf:
> >> properties:
> >> compatible:
> >> contains:
> >> - const: qcom,sc7280-smmu-500
> >> + enum:
> >> + - qcom,sa8775p-smmu-500
> >> + - qcom,sc7280-smmu-500
> >> then:
> >> properties:
> >> clock-names:
> >> @@ -413,7 +416,6 @@ allOf:
> >> - nvidia,smmu-500
> >> - qcom,qcm2290-smmu-500
> >> - qcom,qdu1000-smmu-500
> >> - - qcom,sa8775p-smmu-500
> >> - qcom,sc7180-smmu-500
> >> - qcom,sc8180x-smmu-500
> >> - qcom,sc8280xp-smmu-500
> >> --
> >> 2.37.2
> >>
> >
> > Gentle ping for a review and a pick up. The DT patches that use this
> > schema are in next now so check_dtbs will now fail.
>
> I assume this is not for me, as you got my tag in v2, which I repeated
> in v3.
>
> Best regards,
> Krzysztof
>
The patch changed significantly between v2 and v3 which is why I
dropped your ack as explained in the cover letter for v3. The response
I got for v3 looked like an automated email so I didn't re-collect the
tag. If this looks good to you - could you still Ack it officially
with the adreno compatible changes?
Bart
On 17/04/2023 14:58, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <[email protected]>
>
> The GPU SMMU will require the clocks property to be set so put the
> relevant compatible into the adreno if-then block.
>
> Signed-off-by: Bartosz Golaszewski <[email protected]>
> ---
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Tue, May 16, 2023 at 1:42 PM Krzysztof Kozlowski
<[email protected]> wrote:
>
> On 17/04/2023 14:58, Bartosz Golaszewski wrote:
> > From: Bartosz Golaszewski <[email protected]>
> >
> > The GPU SMMU will require the clocks property to be set so put the
> > relevant compatible into the adreno if-then block.
> >
> > Signed-off-by: Bartosz Golaszewski <[email protected]>
> > ---
>
>
> Acked-by: Krzysztof Kozlowski <[email protected]>
>
> Best regards,
> Krzysztof
>
Hey IOMMU maintainers, could you please pick this one up for the next
merge window?
Thanks in advance
Bartosz
On 30/05/2023 11:47, Bartosz Golaszewski wrote:
> On Tue, May 16, 2023 at 1:42 PM Krzysztof Kozlowski
> <[email protected]> wrote:
>>
>> On 17/04/2023 14:58, Bartosz Golaszewski wrote:
>>> From: Bartosz Golaszewski <[email protected]>
>>>
>>> The GPU SMMU will require the clocks property to be set so put the
>>> relevant compatible into the adreno if-then block.
>>>
>>> Signed-off-by: Bartosz Golaszewski <[email protected]>
>>> ---
>>
>>
>> Acked-by: Krzysztof Kozlowski <[email protected]>
>>
>> Best regards,
>> Krzysztof
>>
>
> Hey IOMMU maintainers, could you please pick this one up for the next
> merge window?
I think you missed to Cc them (except Will).
Best regards,
Krzysztof
On Tue, May 30, 2023 at 03:17:43PM +0200, Krzysztof Kozlowski wrote:
> On 30/05/2023 11:47, Bartosz Golaszewski wrote:
> > On Tue, May 16, 2023 at 1:42 PM Krzysztof Kozlowski
> > <[email protected]> wrote:
> >>
> >> On 17/04/2023 14:58, Bartosz Golaszewski wrote:
> >>> From: Bartosz Golaszewski <[email protected]>
> >>>
> >>> The GPU SMMU will require the clocks property to be set so put the
> >>> relevant compatible into the adreno if-then block.
> >>>
> >>> Signed-off-by: Bartosz Golaszewski <[email protected]>
> >>> ---
> >>
> >>
> >> Acked-by: Krzysztof Kozlowski <[email protected]>
> >>
> >> Best regards,
> >> Krzysztof
> >>
> >
> > Hey IOMMU maintainers, could you please pick this one up for the next
> > merge window?
>
> I think you missed to Cc them (except Will).
Sorry for the delay, I'll grab this one now.
Will
On Mon, 17 Apr 2023 14:58:39 +0200, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <[email protected]>
>
> Add the GPU and PCIe IOMMUs for sa8775p platforms as well as the required
> GPU clock controller driver.
>
> NOTE: I didn't pick up Krzysztof's tag for patch 4/5 as the patch changed
> significantly.
>
> [...]
Applied bindings patch to will (for-joerg/arm-smmu/bindings), thanks!
[4/5] dt-bindings: iommu: arm,smmu: enable clocks for sa8775p Adreno SMMU
https://git.kernel.org/will/c/387a80a74125
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev