Hello,
This patch series adds dma support for the StarFive JH7110 RISC-V
SoC. The first patch adds device tree binding. The second patch includes
dma driver. The last patch adds device node of dma to JH7110 dts.
The series has been tested on the VisionFive 2 board which equip with
JH7110 SoC and works normally.
The last patch should be applied after the following patchset:
https://lore.kernel.org/all/[email protected]/
Changes since v5:
- Modified polling time to DMA transmission completion status. Submit a
separate patch for this change.
Changes since v4:
- Rebased on Linux 6.3-rc1.
- Added description for reset items in the dt-binding.
- Simplified the usage of match data.
Changes since v3:
- Constrain the minItems of resets to 2 for jh7110 dma in the
dt-binding.
- Replaced all uses of of_device_is_compatible with of_device_get_match_data.
- Moved the definition of struct axi_dma_chip_config to dw-axi-dmac-platform.c
Changes since v2:
- Added minItems with value 1 and changed the maxItems' value to 2 about
resets properties in the dt-binding.
- Added match data for jh7110-axi-dma and executed reset call to match
data.
- Dropped reset-names from dma node of device tree.
Changes since v1:
- Rebased on Linux 6.2.
- Changed the compatible string to SoC specific and dropped '-rst' from
reset-names in the dt-binding.
- Dropped 'snps,num-hs-if' in the dt-binding.
- Use different configuration on CH_CFG registers according to the compatible string.
---
v5: https://lore.kernel.org/all/[email protected]/
v4: https://lore.kernel.org/all/[email protected]/
v3: https://lore.kernel.org/all/[email protected]/
v2: https://lore.kernel.org/all/[email protected]/
v1: https://lore.kernel.org/all/[email protected]/
Walker Chen (4):
dt-bindings: dma: snps,dw-axi-dmac: constrain the items of resets for
JH7110 dma
dmaengine: dw-axi-dmac: Add support for StarFive JH7110 DMA
dmaengine: dw-axi-dmac: Increase polling time to DMA transmission
completion status
riscv: dts: starfive: add dma controller node
.../bindings/dma/snps,dw-axi-dmac.yaml | 23 ++++++++++-
arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 +++++++++
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 40 ++++++++++++++++---
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
4 files changed, 75 insertions(+), 7 deletions(-)
base-commit: fe15c26ee26efa11741a7b632e9f23b01aca4cc6
prerequisite-patch-id: c3a6b87df79b338fc97766406d010fedb79ab428
prerequisite-patch-id: b49509523cf7c098f684647bdc4fdaece48b61bc
prerequisite-patch-id: 46cc850aa0e9e03ccf5ed23d8458babfca3d71af
prerequisite-patch-id: a6975e61ee5803fbd74b1c21ab925fd81c3c0eab
prerequisite-patch-id: ac150a8c622e858e088df8121093d448df49c245
prerequisite-patch-id: 044263ef2fb9f1e5a586edbf85d5f67814a28430
prerequisite-patch-id: 89f049f951e5acf75aab92541992f816fd0acc0d
prerequisite-patch-id: 9f3dbc9073eee89134e68977e941e457593c2757
prerequisite-patch-id: 8600b156a235be2b3db53be3f834e7a370e2cfb9
prerequisite-patch-id: 1b2d0982b18da060c82134f05bf3ce16425bac8d
prerequisite-patch-id: 090ba4b78d47bc19204916e76fdbc70021785388
prerequisite-patch-id: a5d9e0f7d4f8163f566678894cf693015119f2d9
prerequisite-patch-id: 4c12d958e3a3d629d86dddb1e4f099d8909393e0
prerequisite-patch-id: bb939c0c7c26b08addfccd890f9d3974b6eaec53
prerequisite-patch-id: 8f5c66dfb14403424044192f6fa05b347ad356a7
prerequisite-patch-id: fd93763b95469912bde9bdfa4cd827c8d5dba9c6
prerequisite-patch-id: 6987950c2eb4b3773b2df8f7934eff434244aeab
prerequisite-patch-id: 258ea5f9b8bf41b6981345dcc81795f25865d38f
prerequisite-patch-id: 8b6f2c9660c0ac0ee4e73e4c21aca8e6b75e81b9
prerequisite-patch-id: dbb0c0151b8bdf093e6ce79fd2fe3f60791a6e0b
prerequisite-patch-id: e7773c977a7b37692e9792b21cc4f17fa58f9215
prerequisite-patch-id: d57e95d31686772abc4c4d5aa1cadc344dc293cd
prerequisite-patch-id: 9f911969d0a550648493952c99096d26e05d4d83
prerequisite-patch-id: 2ddada18ab6ea5cd1da14212aaf59632f5203d40
prerequisite-patch-id: 398744c61913c76a35754de867c4f820ca7a8d99
prerequisite-patch-id: be3d7a6a13098884ec26cd5e543cc95c39045e35
prerequisite-patch-id: b3ce7955a80d90d992b7d1bca3409f465810b2bb
prerequisite-patch-id: db2f66860cc5b2fd2f71747c4428287b6e3153fb
prerequisite-patch-id: 9da71dcd3af4c68da9d855b43aab6927103e7525
prerequisite-patch-id: 2d9e4f185631549094b6136cf8717a507b68c5bb
prerequisite-patch-id: bb8e071ed43998874b9d98292c0dcdeedc0760ca
prerequisite-patch-id: cd0b464336aabfbfad96c1a3595c0f9ce9401638
prerequisite-patch-id: 24eab3d30274700c2be4727bece743c76d2618bd
prerequisite-patch-id: 584c256c9acb52ee2773d0c81c3f4977fc18155a
prerequisite-patch-id: 2bc43b375b470f7e8bbe937b78678ba3856e3b8f
--
2.17.1
Add the dma controller node for the Starfive JH7110 SoC.
Reviewed-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Walker Chen <[email protected]>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 17220576b21c..b503b6137743 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -510,6 +510,24 @@
#gpio-cells = <2>;
};
+ dma: dma-controller@16050000 {
+ compatible = "starfive,jh7110-axi-dma";
+ reg = <0x0 0x16050000 0x0 0x10000>;
+ clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
+ <&stgcrg JH7110_STGCLK_DMA1P_AHB>;
+ clock-names = "core-clk", "cfgr-clk";
+ resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
+ <&stgcrg JH7110_STGRST_DMA1P_AHB>;
+ interrupts = <73>;
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ snps,dma-masters = <1>;
+ snps,data-width = <3>;
+ snps,block-size = <65536 65536 65536 65536>;
+ snps,priority = <0 1 2 3>;
+ snps,axi-max-burst-len = <16>;
+ };
+
aoncrg: clock-controller@17000000 {
compatible = "starfive,jh7110-aoncrg";
reg = <0x0 0x17000000 0x0 0x10000>;
--
2.17.1
Add DMA reset operation in device probe and use different configuration
on CH_CFG registers according to match data. Update all uses of
of_device_is_compatible with of_device_get_match_data.
Signed-off-by: Walker Chen <[email protected]>
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 38 ++++++++++++++++---
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 34 insertions(+), 5 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 4169e1d7d5ca..6cfcb541d8c3 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -21,10 +21,12 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_device.h>
#include <linux/of_dma.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/property.h>
+#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/types.h>
@@ -46,6 +48,10 @@
DMA_SLAVE_BUSWIDTH_32_BYTES | \
DMA_SLAVE_BUSWIDTH_64_BYTES)
+#define AXI_DMA_FLAG_HAS_APB_REGS BIT(0)
+#define AXI_DMA_FLAG_HAS_RESETS BIT(1)
+#define AXI_DMA_FLAG_USE_CFG2 BIT(2)
+
static inline void
axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val)
{
@@ -86,7 +92,8 @@ static inline void axi_chan_config_write(struct axi_dma_chan *chan,
cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS |
config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
- if (chan->chip->dw->hdata->reg_map_8_channels) {
+ if (chan->chip->dw->hdata->reg_map_8_channels &&
+ !chan->chip->dw->hdata->use_cfg2) {
cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS |
config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS |
config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS |
@@ -1367,10 +1374,11 @@ static int parse_device_properties(struct axi_dma_chip *chip)
static int dw_probe(struct platform_device *pdev)
{
- struct device_node *node = pdev->dev.of_node;
struct axi_dma_chip *chip;
struct dw_axi_dma *dw;
struct dw_axi_dma_hcfg *hdata;
+ struct reset_control *resets;
+ unsigned int flags;
u32 i;
int ret;
@@ -1398,12 +1406,25 @@ static int dw_probe(struct platform_device *pdev)
if (IS_ERR(chip->regs))
return PTR_ERR(chip->regs);
- if (of_device_is_compatible(node, "intel,kmb-axi-dma")) {
+ flags = (uintptr_t)of_device_get_match_data(&pdev->dev);
+ if (flags & AXI_DMA_FLAG_HAS_APB_REGS) {
chip->apb_regs = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(chip->apb_regs))
return PTR_ERR(chip->apb_regs);
}
+ if (flags & AXI_DMA_FLAG_HAS_RESETS) {
+ resets = devm_reset_control_array_get_exclusive(&pdev->dev);
+ if (IS_ERR(resets))
+ return PTR_ERR(resets);
+
+ ret = reset_control_deassert(resets);
+ if (ret)
+ return ret;
+ }
+
+ chip->dw->hdata->use_cfg2 = !!(flags & AXI_DMA_FLAG_USE_CFG2);
+
chip->core_clk = devm_clk_get(chip->dev, "core-clk");
if (IS_ERR(chip->core_clk))
return PTR_ERR(chip->core_clk);
@@ -1554,8 +1575,15 @@ static const struct dev_pm_ops dw_axi_dma_pm_ops = {
};
static const struct of_device_id dw_dma_of_id_table[] = {
- { .compatible = "snps,axi-dma-1.01a" },
- { .compatible = "intel,kmb-axi-dma" },
+ {
+ .compatible = "snps,axi-dma-1.01a"
+ }, {
+ .compatible = "intel,kmb-axi-dma",
+ .data = (void *)AXI_DMA_FLAG_HAS_APB_REGS,
+ }, {
+ .compatible = "starfive,jh7110-axi-dma",
+ .data = (void *)(AXI_DMA_FLAG_HAS_RESETS | AXI_DMA_FLAG_USE_CFG2),
+ },
{}
};
MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index e9d5eb0fd594..eb267cb24f67 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -33,6 +33,7 @@ struct dw_axi_dma_hcfg {
/* Register map for DMAX_NUM_CHANNELS <= 8 */
bool reg_map_8_channels;
bool restrict_axi_burst_len;
+ bool use_cfg2;
};
struct axi_dma_chan {
--
2.17.1
The DMA controller needs two reset items to work properly on JH7110 SoC,
so there is need to constrain the items' value to 2, other platforms
have 1 reset item at most.
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Walker Chen <[email protected]>
---
.../bindings/dma/snps,dw-axi-dmac.yaml | 23 ++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
index 5c81194e2300..363cf8bd150d 100644
--- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
@@ -20,6 +20,7 @@ properties:
enum:
- snps,axi-dma-1.01a
- intel,kmb-axi-dma
+ - starfive,jh7110-axi-dma
reg:
minItems: 1
@@ -58,7 +59,8 @@ properties:
maximum: 8
resets:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
snps,dma-masters:
description: |
@@ -109,6 +111,25 @@ required:
- snps,priority
- snps,block-size
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - starfive,jh7110-axi-dma
+then:
+ properties:
+ resets:
+ minItems: 2
+ items:
+ - description: AXI reset line
+ - description: AHB reset line
+ - description: module reset
+else:
+ properties:
+ resets:
+ maxItems: 1
+
additionalProperties: false
examples:
--
2.17.1
On Wed, 22 Mar 2023 at 10:48, Walker Chen <[email protected]> wrote:
>
> Add DMA reset operation in device probe and use different configuration
> on CH_CFG registers according to match data. Update all uses of
> of_device_is_compatible with of_device_get_match_data.
>
> Signed-off-by: Walker Chen <[email protected]>
Thanks!
Reviewed-by: Emil Renner Berthing <[email protected]>
> ---
> .../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 38 ++++++++++++++++---
> drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
> 2 files changed, 34 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> index 4169e1d7d5ca..6cfcb541d8c3 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> @@ -21,10 +21,12 @@
> #include <linux/kernel.h>
> #include <linux/module.h>
> #include <linux/of.h>
> +#include <linux/of_device.h>
> #include <linux/of_dma.h>
> #include <linux/platform_device.h>
> #include <linux/pm_runtime.h>
> #include <linux/property.h>
> +#include <linux/reset.h>
> #include <linux/slab.h>
> #include <linux/types.h>
>
> @@ -46,6 +48,10 @@
> DMA_SLAVE_BUSWIDTH_32_BYTES | \
> DMA_SLAVE_BUSWIDTH_64_BYTES)
>
> +#define AXI_DMA_FLAG_HAS_APB_REGS BIT(0)
> +#define AXI_DMA_FLAG_HAS_RESETS BIT(1)
> +#define AXI_DMA_FLAG_USE_CFG2 BIT(2)
> +
> static inline void
> axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val)
> {
> @@ -86,7 +92,8 @@ static inline void axi_chan_config_write(struct axi_dma_chan *chan,
>
> cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS |
> config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
> - if (chan->chip->dw->hdata->reg_map_8_channels) {
> + if (chan->chip->dw->hdata->reg_map_8_channels &&
> + !chan->chip->dw->hdata->use_cfg2) {
> cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS |
> config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS |
> config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS |
> @@ -1367,10 +1374,11 @@ static int parse_device_properties(struct axi_dma_chip *chip)
>
> static int dw_probe(struct platform_device *pdev)
> {
> - struct device_node *node = pdev->dev.of_node;
> struct axi_dma_chip *chip;
> struct dw_axi_dma *dw;
> struct dw_axi_dma_hcfg *hdata;
> + struct reset_control *resets;
> + unsigned int flags;
> u32 i;
> int ret;
>
> @@ -1398,12 +1406,25 @@ static int dw_probe(struct platform_device *pdev)
> if (IS_ERR(chip->regs))
> return PTR_ERR(chip->regs);
>
> - if (of_device_is_compatible(node, "intel,kmb-axi-dma")) {
> + flags = (uintptr_t)of_device_get_match_data(&pdev->dev);
> + if (flags & AXI_DMA_FLAG_HAS_APB_REGS) {
> chip->apb_regs = devm_platform_ioremap_resource(pdev, 1);
> if (IS_ERR(chip->apb_regs))
> return PTR_ERR(chip->apb_regs);
> }
>
> + if (flags & AXI_DMA_FLAG_HAS_RESETS) {
> + resets = devm_reset_control_array_get_exclusive(&pdev->dev);
> + if (IS_ERR(resets))
> + return PTR_ERR(resets);
> +
> + ret = reset_control_deassert(resets);
> + if (ret)
> + return ret;
> + }
> +
> + chip->dw->hdata->use_cfg2 = !!(flags & AXI_DMA_FLAG_USE_CFG2);
> +
> chip->core_clk = devm_clk_get(chip->dev, "core-clk");
> if (IS_ERR(chip->core_clk))
> return PTR_ERR(chip->core_clk);
> @@ -1554,8 +1575,15 @@ static const struct dev_pm_ops dw_axi_dma_pm_ops = {
> };
>
> static const struct of_device_id dw_dma_of_id_table[] = {
> - { .compatible = "snps,axi-dma-1.01a" },
> - { .compatible = "intel,kmb-axi-dma" },
> + {
> + .compatible = "snps,axi-dma-1.01a"
> + }, {
> + .compatible = "intel,kmb-axi-dma",
> + .data = (void *)AXI_DMA_FLAG_HAS_APB_REGS,
> + }, {
> + .compatible = "starfive,jh7110-axi-dma",
> + .data = (void *)(AXI_DMA_FLAG_HAS_RESETS | AXI_DMA_FLAG_USE_CFG2),
> + },
> {}
> };
> MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> index e9d5eb0fd594..eb267cb24f67 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> @@ -33,6 +33,7 @@ struct dw_axi_dma_hcfg {
> /* Register map for DMAX_NUM_CHANNELS <= 8 */
> bool reg_map_8_channels;
> bool restrict_axi_burst_len;
> + bool use_cfg2;
> };
>
> struct axi_dma_chan {
> --
> 2.17.1
>
On 22-03-23, 17:48, Walker Chen wrote:
> Add DMA reset operation in device probe and use different configuration
> on CH_CFG registers according to match data. Update all uses of
> of_device_is_compatible with of_device_get_match_data.
>
> Signed-off-by: Walker Chen <[email protected]>
> ---
> .../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 38 ++++++++++++++++---
> drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
> 2 files changed, 34 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> index 4169e1d7d5ca..6cfcb541d8c3 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> @@ -21,10 +21,12 @@
> #include <linux/kernel.h>
> #include <linux/module.h>
> #include <linux/of.h>
> +#include <linux/of_device.h>
> #include <linux/of_dma.h>
> #include <linux/platform_device.h>
> #include <linux/pm_runtime.h>
> #include <linux/property.h>
> +#include <linux/reset.h>
> #include <linux/slab.h>
> #include <linux/types.h>
>
> @@ -46,6 +48,10 @@
> DMA_SLAVE_BUSWIDTH_32_BYTES | \
> DMA_SLAVE_BUSWIDTH_64_BYTES)
>
> +#define AXI_DMA_FLAG_HAS_APB_REGS BIT(0)
> +#define AXI_DMA_FLAG_HAS_RESETS BIT(1)
> +#define AXI_DMA_FLAG_USE_CFG2 BIT(2)
> +
> static inline void
> axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val)
> {
> @@ -86,7 +92,8 @@ static inline void axi_chan_config_write(struct axi_dma_chan *chan,
>
> cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS |
> config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
> - if (chan->chip->dw->hdata->reg_map_8_channels) {
> + if (chan->chip->dw->hdata->reg_map_8_channels &&
> + !chan->chip->dw->hdata->use_cfg2) {
I think this will break existing users..
This is set for reg_map_8_channels && use_cfg2, latter being set only
for new controller, so what about existing users of these bits?
> cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS |
> config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS |
> config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS |
> @@ -1367,10 +1374,11 @@ static int parse_device_properties(struct axi_dma_chip *chip)
>
> static int dw_probe(struct platform_device *pdev)
> {
> - struct device_node *node = pdev->dev.of_node;
> struct axi_dma_chip *chip;
> struct dw_axi_dma *dw;
> struct dw_axi_dma_hcfg *hdata;
> + struct reset_control *resets;
> + unsigned int flags;
> u32 i;
> int ret;
>
> @@ -1398,12 +1406,25 @@ static int dw_probe(struct platform_device *pdev)
> if (IS_ERR(chip->regs))
> return PTR_ERR(chip->regs);
>
> - if (of_device_is_compatible(node, "intel,kmb-axi-dma")) {
> + flags = (uintptr_t)of_device_get_match_data(&pdev->dev);
> + if (flags & AXI_DMA_FLAG_HAS_APB_REGS) {
> chip->apb_regs = devm_platform_ioremap_resource(pdev, 1);
> if (IS_ERR(chip->apb_regs))
> return PTR_ERR(chip->apb_regs);
> }
>
> + if (flags & AXI_DMA_FLAG_HAS_RESETS) {
> + resets = devm_reset_control_array_get_exclusive(&pdev->dev);
> + if (IS_ERR(resets))
> + return PTR_ERR(resets);
> +
> + ret = reset_control_deassert(resets);
> + if (ret)
> + return ret;
> + }
> +
> + chip->dw->hdata->use_cfg2 = !!(flags & AXI_DMA_FLAG_USE_CFG2);
> +
> chip->core_clk = devm_clk_get(chip->dev, "core-clk");
> if (IS_ERR(chip->core_clk))
> return PTR_ERR(chip->core_clk);
> @@ -1554,8 +1575,15 @@ static const struct dev_pm_ops dw_axi_dma_pm_ops = {
> };
>
> static const struct of_device_id dw_dma_of_id_table[] = {
> - { .compatible = "snps,axi-dma-1.01a" },
> - { .compatible = "intel,kmb-axi-dma" },
> + {
> + .compatible = "snps,axi-dma-1.01a"
> + }, {
> + .compatible = "intel,kmb-axi-dma",
> + .data = (void *)AXI_DMA_FLAG_HAS_APB_REGS,
> + }, {
> + .compatible = "starfive,jh7110-axi-dma",
> + .data = (void *)(AXI_DMA_FLAG_HAS_RESETS | AXI_DMA_FLAG_USE_CFG2),
> + },
> {}
> };
> MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> index e9d5eb0fd594..eb267cb24f67 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> @@ -33,6 +33,7 @@ struct dw_axi_dma_hcfg {
> /* Register map for DMAX_NUM_CHANNELS <= 8 */
> bool reg_map_8_channels;
> bool restrict_axi_burst_len;
> + bool use_cfg2;
> };
>
> struct axi_dma_chan {
> --
> 2.17.1
--
~Vinod
On 2023/3/31 20:04, Vinod Koul wrote:
> On 22-03-23, 17:48, Walker Chen wrote:
>> Add DMA reset operation in device probe and use different configuration
>> on CH_CFG registers according to match data. Update all uses of
>> of_device_is_compatible with of_device_get_match_data.
>>
>> Signed-off-by: Walker Chen <[email protected]>
>> ---
>> .../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 38 ++++++++++++++++---
>> drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
>> 2 files changed, 34 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
>> index 4169e1d7d5ca..6cfcb541d8c3 100644
>> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
>> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
>> @@ -21,10 +21,12 @@
>> #include <linux/kernel.h>
>> #include <linux/module.h>
>> #include <linux/of.h>
>> +#include <linux/of_device.h>
>> #include <linux/of_dma.h>
>> #include <linux/platform_device.h>
>> #include <linux/pm_runtime.h>
>> #include <linux/property.h>
>> +#include <linux/reset.h>
>> #include <linux/slab.h>
>> #include <linux/types.h>
>>
>> @@ -46,6 +48,10 @@
>> DMA_SLAVE_BUSWIDTH_32_BYTES | \
>> DMA_SLAVE_BUSWIDTH_64_BYTES)
>>
>> +#define AXI_DMA_FLAG_HAS_APB_REGS BIT(0)
>> +#define AXI_DMA_FLAG_HAS_RESETS BIT(1)
>> +#define AXI_DMA_FLAG_USE_CFG2 BIT(2)
>> +
>> static inline void
>> axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val)
>> {
>> @@ -86,7 +92,8 @@ static inline void axi_chan_config_write(struct axi_dma_chan *chan,
>>
>> cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS |
>> config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS);
>> - if (chan->chip->dw->hdata->reg_map_8_channels) {
>> + if (chan->chip->dw->hdata->reg_map_8_channels &&
>> + !chan->chip->dw->hdata->use_cfg2) {
>
> I think this will break existing users..
>
> This is set for reg_map_8_channels && use_cfg2, latter being set only
> for new controller, so what about existing users of these bits?
Firstly thank you for your comments!
There is a statement 'use_cfg2 = !!(flags & AXI_DMA_FLAG_USE_CFG2);' to be added in dw_probe function.
Assuming older/existing platform run this code block, e.g. when compatible is "snps,axi-dma-1.01a",
the value of variable 'use_cfg2' is still false, the original logic will not be broken. So other existing
users are not affected by this.
Looking forward to your more comments. Thanks!
Best regards,
Walker
On 22-03-23, 17:48, Walker Chen wrote:
> Hello,
>
> This patch series adds dma support for the StarFive JH7110 RISC-V
> SoC. The first patch adds device tree binding. The second patch includes
> dma driver. The last patch adds device node of dma to JH7110 dts.
>
> The series has been tested on the VisionFive 2 board which equip with
> JH7110 SoC and works normally.
Applied 1-3, thanks
--
~Vinod
On 2023/4/13 1:27, Vinod Koul wrote:
> On 22-03-23, 17:48, Walker Chen wrote:
>> Hello,
>>
>> This patch series adds dma support for the StarFive JH7110 RISC-V
>> SoC. The first patch adds device tree binding. The second patch includes
>> dma driver. The last patch adds device node of dma to JH7110 dts.
>>
>> The series has been tested on the VisionFive 2 board which equip with
>> JH7110 SoC and works normally.
>
> Applied 1-3, thanks
>
Vinod, thank you very much!
Best regards,
Walker
On 2023-03-22 17:48, Walker Chen wrote:
> Add the dma controller node for the Starfive JH7110 SoC.
>
> Reviewed-by: Emil Renner Berthing <[email protected]>
> Signed-off-by: Walker Chen <[email protected]>
> ---
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index 17220576b21c..b503b6137743 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -510,6 +510,24 @@
> #gpio-cells = <2>;
> };
>
> + dma: dma-controller@16050000 {
> + compatible = "starfive,jh7110-axi-dma";
> + reg = <0x0 0x16050000 0x0 0x10000>;
> + clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
> + <&stgcrg JH7110_STGCLK_DMA1P_AHB>;
> + clock-names = "core-clk", "cfgr-clk";
> + resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
> + <&stgcrg JH7110_STGRST_DMA1P_AHB>;
> + interrupts = <73>;
> + #dma-cells = <1>;
> + dma-channels = <4>;
> + snps,dma-masters = <1>;
> + snps,data-width = <3>;
> + snps,block-size = <65536 65536 65536 65536>;
> + snps,priority = <0 1 2 3>;
> + snps,axi-max-burst-len = <16>;
> + };
> +
> aoncrg: clock-controller@17000000 {
> compatible = "starfive,jh7110-aoncrg";
> reg = <0x0 0x17000000 0x0 0x10000>;
It appears that this patch has never been applied, although the rest of
the series has already been merged. Unfortunately it doesn't apply
anymore due to other changes to that file.
Could you please rebase and repost it?
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
[email protected] http://aurel32.net
On Sun, Jul 02, 2023 at 12:01:29AM +0200, Aurelien Jarno wrote:
> On 2023-03-22 17:48, Walker Chen wrote:
> > Add the dma controller node for the Starfive JH7110 SoC.
> >
> > Reviewed-by: Emil Renner Berthing <[email protected]>
> > Signed-off-by: Walker Chen <[email protected]>
> > ---
> > arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 ++++++++++++++++++
> > 1 file changed, 18 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > index 17220576b21c..b503b6137743 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > @@ -510,6 +510,24 @@
> > #gpio-cells = <2>;
> > };
> >
> > + dma: dma-controller@16050000 {
> > + compatible = "starfive,jh7110-axi-dma";
> > + reg = <0x0 0x16050000 0x0 0x10000>;
> > + clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
> > + <&stgcrg JH7110_STGCLK_DMA1P_AHB>;
> > + clock-names = "core-clk", "cfgr-clk";
> > + resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
> > + <&stgcrg JH7110_STGRST_DMA1P_AHB>;
> > + interrupts = <73>;
> > + #dma-cells = <1>;
> > + dma-channels = <4>;
> > + snps,dma-masters = <1>;
> > + snps,data-width = <3>;
> > + snps,block-size = <65536 65536 65536 65536>;
> > + snps,priority = <0 1 2 3>;
> > + snps,axi-max-burst-len = <16>;
> > + };
> > +
> > aoncrg: clock-controller@17000000 {
> > compatible = "starfive,jh7110-aoncrg";
> > reg = <0x0 0x17000000 0x0 0x10000>;
>
> It appears that this patch has never been applied, although the rest of
> the series has already been merged.
Correct. I can't apply it because the stgcrg it depends on is still
pending.
> Unfortunately it doesn't apply
> anymore due to other changes to that file.
>
> Could you please rebase and repost it?
On 2023/7/2 6:01, Aurelien Jarno wrote:
> On 2023-03-22 17:48, Walker Chen wrote:
>> Add the dma controller node for the Starfive JH7110 SoC.
>>
>> Reviewed-by: Emil Renner Berthing <[email protected]>
>> Signed-off-by: Walker Chen <[email protected]>
>> ---
>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 ++++++++++++++++++
>> 1 file changed, 18 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> index 17220576b21c..b503b6137743 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> @@ -510,6 +510,24 @@
>> #gpio-cells = <2>;
>> };
>>
>> + dma: dma-controller@16050000 {
>> + compatible = "starfive,jh7110-axi-dma";
>> + reg = <0x0 0x16050000 0x0 0x10000>;
>> + clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
>> + <&stgcrg JH7110_STGCLK_DMA1P_AHB>;
>> + clock-names = "core-clk", "cfgr-clk";
>> + resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
>> + <&stgcrg JH7110_STGRST_DMA1P_AHB>;
>> + interrupts = <73>;
>> + #dma-cells = <1>;
>> + dma-channels = <4>;
>> + snps,dma-masters = <1>;
>> + snps,data-width = <3>;
>> + snps,block-size = <65536 65536 65536 65536>;
>> + snps,priority = <0 1 2 3>;
>> + snps,axi-max-burst-len = <16>;
>> + };
>> +
>> aoncrg: clock-controller@17000000 {
>> compatible = "starfive,jh7110-aoncrg";
>> reg = <0x0 0x17000000 0x0 0x10000>;
>
> It appears that this patch has never been applied, although the rest of
> the series has already been merged. Unfortunately it doesn't apply
> anymore due to other changes to that file.
>
> Could you please rebase and repost it?
>
Of course I will repost it, but this depends on whether the stg clock is merged.
Regards,
Walker