Hi,
The qcom,pcie.yaml containing all devices results in huge allOf: section
with a lot of if:then: clauses making review and changes quite
difficult.
Split common parts into common schema and then move few devices to
dedicated files, so that each file will be easier to review.
I did not split/move all devices yet, so if this gets accepted I plan to
send more patches.
Best regards,
Krzysztof
---
Krzysztof Kozlowski (6):
dt-bindings: PCI: qcom,pcie-sm8550: move SM8550 to dedicated schema
dt-bindings: PCI: qcom,pcie-sm8450: move SM8450 to dedicated schema
dt-bindings: PCI: qcom,pcie-sm8250: move SM8250 to dedicated schema
dt-bindings: PCI: qcom,pcie-sm8150: move SM8150 to dedicated schema
dt-bindings: PCI: qcom,pcie-sm8350: move SM8350 to dedicated schema
dt-bindings: PCI: qcom,pcie-sc8280xp: move SC8280XP to dedicated schema
.../devicetree/bindings/pci/qcom,pcie-common.yaml | 98 ++++++++
.../bindings/pci/qcom,pcie-sc8280xp.yaml | 180 ++++++++++++++
.../devicetree/bindings/pci/qcom,pcie-sm8150.yaml | 157 ++++++++++++
.../devicetree/bindings/pci/qcom,pcie-sm8250.yaml | 180 ++++++++++++++
.../devicetree/bindings/pci/qcom,pcie-sm8350.yaml | 169 +++++++++++++
.../devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 215 +++++++++++++++++
.../devicetree/bindings/pci/qcom,pcie-sm8550.yaml | 171 +++++++++++++
.../devicetree/bindings/pci/qcom,pcie.yaml | 268 ---------------------
8 files changed, 1170 insertions(+), 268 deletions(-)
---
base-commit: a0bf076e449e022944b440174491f5c583753d84
change-id: 20240108-dt-bindings-pci-qcom-split-624737f7ba67
Best regards,
--
Krzysztof Kozlowski <[email protected]>
The qcom,pcie.yaml binding file containing all possible Qualcomm SoC
PCIe root complexes gets quite complicated with numerous if:then:
conditions customizing clocks, interrupts, regs and resets. Adding and
reviewing new devices is difficult, so simplify it by having shared
common binding and file with only one group of compatible devices:
1. Copy all common qcom,pcie.yaml properties (so everything except
supplies) to a new shared qcom,pcie-common.yaml schema.
2. Move SM8550 PCIe compatible devices to dedicated binding file.
This creates equivalent SM8550 schema file, except missing required
compatible which is actually redundant.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../devicetree/bindings/pci/qcom,pcie-common.yaml | 98 ++++++++++++
.../devicetree/bindings/pci/qcom,pcie-sm8550.yaml | 171 +++++++++++++++++++++
.../devicetree/bindings/pci/qcom,pcie.yaml | 38 -----
3 files changed, 269 insertions(+), 38 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml
new file mode 100644
index 000000000000..125136176f93
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm PCI Express Root Complex Common Properties
+
+maintainers:
+ - Bjorn Andersson <[email protected]>
+ - Manivannan Sadhasivam <[email protected]>
+
+properties:
+ reg:
+ minItems: 4
+ maxItems: 6
+
+ reg-names:
+ minItems: 4
+ maxItems: 6
+
+ interrupts:
+ minItems: 1
+ maxItems: 8
+
+ interrupt-names:
+ minItems: 1
+ maxItems: 8
+
+ iommu-map:
+ minItems: 1
+ maxItems: 16
+
+ clocks:
+ minItems: 3
+ maxItems: 13
+
+ clock-names:
+ minItems: 3
+ maxItems: 13
+
+ dma-coherent: true
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: pcie-mem
+ - const: cpu-pcie
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ items:
+ - const: pciephy
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ minItems: 1
+ maxItems: 12
+
+ reset-names:
+ minItems: 1
+ maxItems: 12
+
+ perst-gpios:
+ description: GPIO controlled connection to PERST# signal
+ maxItems: 1
+
+ wake-gpios:
+ description: GPIO controlled connection to WAKE# signal
+ maxItems: 1
+
+required:
+ - reg
+ - reg-names
+ - interrupt-map-mask
+ - interrupt-map
+ - clocks
+ - clock-names
+
+anyOf:
+ - required:
+ - interrupts
+ - interrupt-names
+ - "#interrupt-cells"
+ - required:
+ - msi-map
+ - msi-map-mask
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+
+additionalProperties: true
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml
new file mode 100644
index 000000000000..b6d025f153bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml
@@ -0,0 +1,171 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8550.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8550 PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <[email protected]>
+ - Manivannan Sadhasivam <[email protected]>
+
+description:
+ Qualcomm SM8550 SoC (and compatible) PCIe root complex controller is based on
+ the Synopsys DesignWare PCIe IP.
+
+properties:
+ compatible:
+ oneOf:
+ - const: qcom,pcie-sm8550
+ - items:
+ - enum:
+ - qcom,pcie-sm8650
+ - const: qcom,pcie-sm8550
+
+ reg:
+ minItems: 5
+ maxItems: 6
+
+ reg-names:
+ minItems: 5
+ items:
+ - const: parf # Qualcomm specific registers
+ - const: dbi # DesignWare PCIe registers
+ - const: elbi # External local bus interface registers
+ - const: atu # ATU address space
+ - const: config # PCIe configuration space
+ - const: mhi # MHI registers
+
+ clocks:
+ minItems: 7
+ maxItems: 8
+
+ clock-names:
+ minItems: 7
+ items:
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: ddrss_sf_tbu # PCIe SF TBU clock
+ - const: noc_aggr # Aggre NoC PCIe AXI clock
+ - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
+
+ resets:
+ minItems: 1
+ maxItems: 2
+
+ reset-names:
+ minItems: 1
+ items:
+ - const: pci # PCIe core reset
+ - const: link_down # PCIe link down reset
+
+oneOf:
+ - properties:
+ interrupts:
+ maxItems: 1
+ interrupt-names:
+ items:
+ - const: msi
+
+ - properties:
+ interrupts:
+ minItems: 8
+ interrupt-names:
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,sm8550-gcc.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@1c00000 {
+ compatible = "qcom,pcie-sm8550";
+ reg = <0 0x01c00000 0 0x3000>,
+ <0 0x60000000 0 0xf1d>,
+ <0 0x60000f20 0 0xa8>,
+ <0 0x60001000 0 0x1000>,
+ <0 0x60100000 0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
+
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ num-lanes = <2>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ddrss_sf_tbu",
+ "noc_aggr";
+
+ dma-coherent;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
+ <0x100 &apps_smmu 0x1401 0x1>;
+
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ power-domains = <&gcc PCIE_0_GDSC>;
+
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "pci";
+
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index a93ab3b54066..3b7dd9a4ef60 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -40,11 +40,6 @@ properties:
- qcom,pcie-sm8350
- qcom,pcie-sm8450-pcie0
- qcom,pcie-sm8450-pcie1
- - qcom,pcie-sm8550
- - items:
- - enum:
- - qcom,pcie-sm8650
- - const: qcom,pcie-sm8550
- items:
- const: qcom,pcie-msm8998
- const: qcom,pcie-msm8996
@@ -226,7 +221,6 @@ allOf:
- qcom,pcie-sm8350
- qcom,pcie-sm8450-pcie0
- qcom,pcie-sm8450-pcie1
- - qcom,pcie-sm8550
then:
properties:
reg:
@@ -715,37 +709,6 @@ allOf:
items:
- const: pci # PCIe core reset
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-sm8550
- then:
- properties:
- clocks:
- minItems: 7
- maxItems: 8
- clock-names:
- minItems: 7
- items:
- - const: aux # Auxiliary clock
- - const: cfg # Configuration clock
- - const: bus_master # Master AXI clock
- - const: bus_slave # Slave AXI clock
- - const: slave_q2a # Slave Q2A clock
- - const: ddrss_sf_tbu # PCIe SF TBU clock
- - const: noc_aggr # Aggre NoC PCIe AXI clock
- - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
- resets:
- minItems: 1
- maxItems: 2
- reset-names:
- minItems: 1
- items:
- - const: pci # PCIe core reset
- - const: link_down # PCIe link down reset
-
- if:
properties:
compatible:
@@ -883,7 +846,6 @@ allOf:
- qcom,pcie-sm8350
- qcom,pcie-sm8450-pcie0
- qcom,pcie-sm8450-pcie1
- - qcom,pcie-sm8550
then:
oneOf:
- properties:
--
2.34.1
Move SM8450 PCIe devices from qcom,pcie.yaml binding to a dedicated file
to make reviewing easier.
This creates equivalent schema file, except missing required compatible
which is actually redundant.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 215 +++++++++++++++++++++
.../devicetree/bindings/pci/qcom,pcie.yaml | 67 -------
2 files changed, 215 insertions(+), 67 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml
new file mode 100644
index 000000000000..59ba809b6204
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml
@@ -0,0 +1,215 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8450.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8450 PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <[email protected]>
+ - Manivannan Sadhasivam <[email protected]>
+
+description:
+ Qualcomm SM8450 SoC PCIe root complex controller is based on the Synopsys
+ DesignWare PCIe IP.
+
+properties:
+ compatible:
+ enum:
+ - qcom,pcie-sm8450-pcie0
+ - qcom,pcie-sm8450-pcie1
+
+ reg:
+ minItems: 5
+ maxItems: 6
+
+ reg-names:
+ minItems: 5
+ items:
+ - const: parf # Qualcomm specific registers
+ - const: dbi # DesignWare PCIe registers
+ - const: elbi # External local bus interface registers
+ - const: atu # ATU address space
+ - const: config # PCIe configuration space
+ - const: mhi # MHI registers
+
+ clocks:
+ minItems: 11
+ maxItems: 12
+
+ clock-names:
+ minItems: 11
+ maxItems: 12
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: pci
+
+oneOf:
+ - properties:
+ interrupts:
+ maxItems: 1
+ interrupt-names:
+ items:
+ - const: msi
+
+ - properties:
+ interrupts:
+ minItems: 8
+ interrupt-names:
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-sm8450-pcie0
+ then:
+ properties:
+ clocks:
+ minItems: 12
+ maxItems: 12
+ clock-names:
+ items:
+ - const: pipe # PIPE clock
+ - const: pipe_mux # PIPE MUX
+ - const: phy_pipe # PIPE output clock
+ - const: ref # REFERENCE clock
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: ddrss_sf_tbu # PCIe SF TBU clock
+ - const: aggre0 # Aggre NoC PCIe0 AXI clock
+ - const: aggre1 # Aggre NoC PCIe1 AXI clock
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-sm8450-pcie1
+ then:
+ properties:
+ clocks:
+ minItems: 11
+ maxItems: 11
+ clock-names:
+ items:
+ - const: pipe # PIPE clock
+ - const: pipe_mux # PIPE MUX
+ - const: phy_pipe # PIPE output clock
+ - const: ref # REFERENCE clock
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: ddrss_sf_tbu # PCIe SF TBU clock
+ - const: aggre1 # Aggre NoC PCIe1 AXI clock
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sm8450.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interconnect/qcom,sm8450.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@1c00000 {
+ compatible = "qcom,pcie-sm8450-pcie0";
+ reg = <0 0x01c00000 0 0x3000>,
+ <0 0x60000000 0 0xf1d>,
+ <0 0x60000f20 0 0xa8>,
+ <0 0x60001000 0 0x1000>,
+ <0 0x60100000 0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
+
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ max-link-speed = <2>;
+ num-lanes = <1>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+ <&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
+ <&pcie0_phy>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
+ clock-names = "pipe",
+ "pipe_mux",
+ "phy_pipe",
+ "ref",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ddrss_sf_tbu",
+ "aggre0",
+ "aggre1";
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ msi-map = <0x0 &gic_its 0x5981 0x1>,
+ <0x100 &gic_its 0x5980 0x1>;
+ msi-map-mask = <0xff00>;
+
+ iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
+ <0x100 &apps_smmu 0x1c01 0x1>;
+
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ power-domains = <&gcc PCIE_0_GDSC>;
+
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "pci";
+
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 3b7dd9a4ef60..791ddab8ddc7 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -38,8 +38,6 @@ properties:
- qcom,pcie-sm8150
- qcom,pcie-sm8250
- qcom,pcie-sm8350
- - qcom,pcie-sm8450-pcie0
- - qcom,pcie-sm8450-pcie1
- items:
- const: qcom,pcie-msm8998
- const: qcom,pcie-msm8996
@@ -219,8 +217,6 @@ allOf:
- qcom,pcie-sdx55
- qcom,pcie-sm8250
- qcom,pcie-sm8350
- - qcom,pcie-sm8450-pcie0
- - qcom,pcie-sm8450-pcie1
then:
properties:
reg:
@@ -648,67 +644,6 @@ allOf:
items:
- const: pci # PCIe core reset
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-sm8450-pcie0
- then:
- properties:
- clocks:
- minItems: 12
- maxItems: 12
- clock-names:
- items:
- - const: pipe # PIPE clock
- - const: pipe_mux # PIPE MUX
- - const: phy_pipe # PIPE output clock
- - const: ref # REFERENCE clock
- - const: aux # Auxiliary clock
- - const: cfg # Configuration clock
- - const: bus_master # Master AXI clock
- - const: bus_slave # Slave AXI clock
- - const: slave_q2a # Slave Q2A clock
- - const: ddrss_sf_tbu # PCIe SF TBU clock
- - const: aggre0 # Aggre NoC PCIe0 AXI clock
- - const: aggre1 # Aggre NoC PCIe1 AXI clock
- resets:
- maxItems: 1
- reset-names:
- items:
- - const: pci # PCIe core reset
-
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-sm8450-pcie1
- then:
- properties:
- clocks:
- minItems: 11
- maxItems: 11
- clock-names:
- items:
- - const: pipe # PIPE clock
- - const: pipe_mux # PIPE MUX
- - const: phy_pipe # PIPE output clock
- - const: ref # REFERENCE clock
- - const: aux # Auxiliary clock
- - const: cfg # Configuration clock
- - const: bus_master # Master AXI clock
- - const: bus_slave # Slave AXI clock
- - const: slave_q2a # Slave Q2A clock
- - const: ddrss_sf_tbu # PCIe SF TBU clock
- - const: aggre1 # Aggre NoC PCIe1 AXI clock
- resets:
- maxItems: 1
- reset-names:
- items:
- - const: pci # PCIe core reset
-
- if:
properties:
compatible:
@@ -844,8 +779,6 @@ allOf:
- qcom,pcie-sm8150
- qcom,pcie-sm8250
- qcom,pcie-sm8350
- - qcom,pcie-sm8450-pcie0
- - qcom,pcie-sm8450-pcie1
then:
oneOf:
- properties:
--
2.34.1
Move SM8250 PCIe devices from qcom,pcie.yaml binding to a dedicated file
to make reviewing easier.
This creates equivalent schema file, except missing required compatible
which is actually redundant.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../devicetree/bindings/pci/qcom,pcie-sm8250.yaml | 180 +++++++++++++++++++++
.../devicetree/bindings/pci/qcom,pcie.yaml | 48 ------
2 files changed, 180 insertions(+), 48 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml
new file mode 100644
index 000000000000..f668f0f2e497
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml
@@ -0,0 +1,180 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8250.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8250 PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <[email protected]>
+ - Manivannan Sadhasivam <[email protected]>
+
+description:
+ Qualcomm SM8250 SoC PCIe root complex controller is based on the Synopsys
+ DesignWare PCIe IP.
+
+properties:
+ compatible:
+ const: qcom,pcie-sm8250
+
+ reg:
+ minItems: 5
+ maxItems: 6
+
+ reg-names:
+ minItems: 5
+ items:
+ - const: parf # Qualcomm specific registers
+ - const: dbi # DesignWare PCIe registers
+ - const: elbi # External local bus interface registers
+ - const: atu # ATU address space
+ - const: config # PCIe configuration space
+ - const: mhi # MHI registers
+
+ clocks:
+ minItems: 8
+ maxItems: 9
+
+ clock-names:
+ # Unfortunately the "optional" ref clock is used in the middle of the list
+ oneOf:
+ - items:
+ - const: pipe # PIPE clock
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: ref # REFERENCE clock
+ - const: tbu # PCIe TBU clock
+ - const: ddrss_sf_tbu # PCIe SF TBU clock
+ - items:
+ - const: pipe # PIPE clock
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: tbu # PCIe TBU clock
+ - const: ddrss_sf_tbu # PCIe SF TBU clock
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: pci
+
+oneOf:
+ - properties:
+ interrupts:
+ maxItems: 1
+ interrupt-names:
+ items:
+ - const: msi
+
+ - properties:
+ interrupts:
+ minItems: 8
+ interrupt-names:
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sm8250.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interconnect/qcom,sm8250.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@1c00000 {
+ compatible = "qcom,pcie-sm8250";
+ reg = <0 0x01c00000 0 0x3000>,
+ <0 0x60000000 0 0xf1d>,
+ <0 0x60000f20 0 0xa8>,
+ <0 0x60001000 0 0x1000>,
+ <0 0x60100000 0 0x100000>,
+ <0 0x01c03000 0 0x1000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
+
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ num-lanes = <1>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+ <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
+ clock-names = "pipe",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "tbu",
+ "ddrss_sf_tbu";
+
+ dma-coherent;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
+ <0x100 &apps_smmu 0x1c01 0x1>;
+
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ power-domains = <&gcc PCIE_0_GDSC>;
+
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "pci";
+
+ perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 791ddab8ddc7..14341d210063 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -36,7 +36,6 @@ properties:
- qcom,pcie-sdm845
- qcom,pcie-sdx55
- qcom,pcie-sm8150
- - qcom,pcie-sm8250
- qcom,pcie-sm8350
- items:
- const: qcom,pcie-msm8998
@@ -215,7 +214,6 @@ allOf:
- qcom,pcie-sc8180x
- qcom,pcie-sc8280xp
- qcom,pcie-sdx55
- - qcom,pcie-sm8250
- qcom,pcie-sm8350
then:
properties:
@@ -570,51 +568,6 @@ allOf:
items:
- const: pci # PCIe core reset
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-sm8250
- then:
- oneOf:
- # Unfortunately the "optional" ref clock is used in the middle of the list
- - properties:
- clocks:
- minItems: 9
- maxItems: 9
- clock-names:
- items:
- - const: pipe # PIPE clock
- - const: aux # Auxiliary clock
- - const: cfg # Configuration clock
- - const: bus_master # Master AXI clock
- - const: bus_slave # Slave AXI clock
- - const: slave_q2a # Slave Q2A clock
- - const: ref # REFERENCE clock
- - const: tbu # PCIe TBU clock
- - const: ddrss_sf_tbu # PCIe SF TBU clock
- - properties:
- clocks:
- minItems: 8
- maxItems: 8
- clock-names:
- items:
- - const: pipe # PIPE clock
- - const: aux # Auxiliary clock
- - const: cfg # Configuration clock
- - const: bus_master # Master AXI clock
- - const: bus_slave # Slave AXI clock
- - const: slave_q2a # Slave Q2A clock
- - const: tbu # PCIe TBU clock
- - const: ddrss_sf_tbu # PCIe SF TBU clock
- properties:
- resets:
- maxItems: 1
- reset-names:
- items:
- - const: pci # PCIe core reset
-
- if:
properties:
compatible:
@@ -777,7 +730,6 @@ allOf:
- qcom,pcie-sc8180x
- qcom,pcie-sdm845
- qcom,pcie-sm8150
- - qcom,pcie-sm8250
- qcom,pcie-sm8350
then:
oneOf:
--
2.34.1
Move SM8150 PCIe devices from qcom,pcie.yaml binding to a dedicated file
to make reviewing easier.
This creates equivalent schema file, except missing required compatible
which is actually redundant.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../devicetree/bindings/pci/qcom,pcie-sm8150.yaml | 157 +++++++++++++++++++++
.../devicetree/bindings/pci/qcom,pcie.yaml | 29 ----
2 files changed, 157 insertions(+), 29 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml
new file mode 100644
index 000000000000..acb69501e81c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml
@@ -0,0 +1,157 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8150.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8150 PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <[email protected]>
+ - Manivannan Sadhasivam <[email protected]>
+
+description:
+ Qualcomm SM8150 SoC PCIe root complex controller is based on the Synopsys
+ DesignWare PCIe IP.
+
+properties:
+ compatible:
+ const: qcom,pcie-sm8150
+
+ reg:
+ minItems: 5
+ maxItems: 6
+
+ reg-names:
+ minItems: 5
+ items:
+ - const: parf # Qualcomm specific registers
+ - const: dbi # DesignWare PCIe registers
+ - const: elbi # External local bus interface registers
+ - const: atu # ATU address space
+ - const: config # PCIe configuration space
+ - const: mhi # MHI registers
+
+ clocks:
+ minItems: 8
+ maxItems: 8
+
+ clock-names:
+ items:
+ - const: pipe # PIPE clock
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: tbu # PCIe TBU clock
+ - const: ref # REFERENCE clock
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: pci
+
+oneOf:
+ - properties:
+ interrupts:
+ maxItems: 1
+ interrupt-names:
+ items:
+ - const: msi
+
+ - properties:
+ interrupts:
+ minItems: 8
+ interrupt-names:
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sm8150.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interconnect/qcom,sm8150.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ pcie@1c00000 {
+ compatible = "qcom,pcie-sm8150";
+ reg = <0 0x01c00000 0 0x3000>,
+ <0 0x60000000 0 0xf1d>,
+ <0 0x60000f20 0 0xa8>,
+ <0 0x60001000 0 0x1000>,
+ <0 0x60100000 0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
+
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ num-lanes = <1>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+ <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "pipe",
+ "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "tbu",
+ "ref";
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
+ <0x100 &apps_smmu 0x1d81 0x1>;
+
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ power-domains = <&gcc PCIE_0_GDSC>;
+
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "pci";
+
+ perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 14341d210063..47888b5b1a13 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -35,7 +35,6 @@ properties:
- qcom,pcie-sc8280xp
- qcom,pcie-sdm845
- qcom,pcie-sdx55
- - qcom,pcie-sm8150
- qcom,pcie-sm8350
- items:
- const: qcom,pcie-msm8998
@@ -541,33 +540,6 @@ allOf:
items:
- const: pci # PCIe core reset
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-sm8150
- then:
- properties:
- clocks:
- minItems: 8
- maxItems: 8
- clock-names:
- items:
- - const: pipe # PIPE clock
- - const: aux # Auxiliary clock
- - const: cfg # Configuration clock
- - const: bus_master # Master AXI clock
- - const: bus_slave # Slave AXI clock
- - const: slave_q2a # Slave Q2A clock
- - const: tbu # PCIe TBU clock
- - const: ref # REFERENCE clock
- resets:
- maxItems: 1
- reset-names:
- items:
- - const: pci # PCIe core reset
-
- if:
properties:
compatible:
@@ -729,7 +701,6 @@ allOf:
- qcom,pcie-sc7280
- qcom,pcie-sc8180x
- qcom,pcie-sdm845
- - qcom,pcie-sm8150
- qcom,pcie-sm8350
then:
oneOf:
--
2.34.1
Move SM8350 PCIe devices from qcom,pcie.yaml binding to a dedicated file
to make reviewing easier.
This creates equivalent schema file, except missing required compatible
which is actually redundant.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../devicetree/bindings/pci/qcom,pcie-sm8350.yaml | 169 +++++++++++++++++++++
.../devicetree/bindings/pci/qcom,pcie.yaml | 32 ----
2 files changed, 169 insertions(+), 32 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml
new file mode 100644
index 000000000000..fea41340b2c3
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8350.yaml
@@ -0,0 +1,169 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8350.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8350 PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <[email protected]>
+ - Manivannan Sadhasivam <[email protected]>
+
+description:
+ Qualcomm SM8350 SoC PCIe root complex controller is based on the Synopsys
+ DesignWare PCIe IP.
+
+properties:
+ compatible:
+ const: qcom,pcie-sm8350
+
+ reg:
+ minItems: 5
+ maxItems: 6
+
+ reg-names:
+ minItems: 5
+ items:
+ - const: parf # Qualcomm specific registers
+ - const: dbi # DesignWare PCIe registers
+ - const: elbi # External local bus interface registers
+ - const: atu # ATU address space
+ - const: config # PCIe configuration space
+ - const: mhi # MHI registers
+
+ clocks:
+ minItems: 8
+ maxItems: 9
+
+ clock-names:
+ minItems: 8
+ items:
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: tbu # PCIe TBU clock
+ - const: ddrss_sf_tbu # PCIe SF TBU clock
+ - const: aggre1 # Aggre NoC PCIe1 AXI clock
+ - const: aggre0 # Aggre NoC PCIe0 AXI clock
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: pci
+
+oneOf:
+ - properties:
+ interrupts:
+ maxItems: 1
+ interrupt-names:
+ items:
+ - const: msi
+
+ - properties:
+ interrupts:
+ minItems: 8
+ interrupt-names:
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sm8350.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interconnect/qcom,sm8350.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@1c00000 {
+ compatible = "qcom,pcie-sm8350";
+ reg = <0 0x01c00000 0 0x3000>,
+ <0 0x60000000 0 0xf1d>,
+ <0 0x60000f20 0 0xa8>,
+ <0 0x60001000 0 0x1000>,
+ <0 0x60100000 0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
+
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ num-lanes = <1>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "tbu",
+ "ddrss_sf_tbu",
+ "aggre1",
+ "aggre0";
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
+ <0x100 &apps_smmu 0x1c01 0x1>;
+
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+
+ pinctrl-0 = <&pcie0_default_state>;
+ pinctrl-names = "default";
+
+ power-domains = <&gcc PCIE_0_GDSC>;
+
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "pci";
+
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 47888b5b1a13..6e03a1bce5d4 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -35,7 +35,6 @@ properties:
- qcom,pcie-sc8280xp
- qcom,pcie-sdm845
- qcom,pcie-sdx55
- - qcom,pcie-sm8350
- items:
- const: qcom,pcie-msm8998
- const: qcom,pcie-msm8996
@@ -213,7 +212,6 @@ allOf:
- qcom,pcie-sc8180x
- qcom,pcie-sc8280xp
- qcom,pcie-sdx55
- - qcom,pcie-sm8350
then:
properties:
reg:
@@ -540,35 +538,6 @@ allOf:
items:
- const: pci # PCIe core reset
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-sm8350
- then:
- properties:
- clocks:
- minItems: 8
- maxItems: 9
- clock-names:
- minItems: 8
- items:
- - const: aux # Auxiliary clock
- - const: cfg # Configuration clock
- - const: bus_master # Master AXI clock
- - const: bus_slave # Slave AXI clock
- - const: slave_q2a # Slave Q2A clock
- - const: tbu # PCIe TBU clock
- - const: ddrss_sf_tbu # PCIe SF TBU clock
- - const: aggre1 # Aggre NoC PCIe1 AXI clock
- - const: aggre0 # Aggre NoC PCIe0 AXI clock
- resets:
- maxItems: 1
- reset-names:
- items:
- - const: pci # PCIe core reset
-
- if:
properties:
compatible:
@@ -701,7 +670,6 @@ allOf:
- qcom,pcie-sc7280
- qcom,pcie-sc8180x
- qcom,pcie-sdm845
- - qcom,pcie-sm8350
then:
oneOf:
- properties:
--
2.34.1
Move SC8280XP compatible PCIe devices from qcom,pcie.yaml binding to a
dedicated file to make reviewing easier.
This creates equivalent schema file, except missing required compatible
which is actually redundant.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../bindings/pci/qcom,pcie-sc8280xp.yaml | 180 +++++++++++++++++++++
.../devicetree/bindings/pci/qcom,pcie.yaml | 54 -------
2 files changed, 180 insertions(+), 54 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml
new file mode 100644
index 000000000000..25c9f13ae977
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sc8280xp.yaml
@@ -0,0 +1,180 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,pcie-sc8280xp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SC8280XP PCI Express Root Complex
+
+maintainers:
+ - Bjorn Andersson <[email protected]>
+ - Manivannan Sadhasivam <[email protected]>
+
+description:
+ Qualcomm SC8280XP SoC PCIe root complex controller is based on the Synopsys
+ DesignWare PCIe IP.
+
+properties:
+ compatible:
+ enum:
+ - qcom,pcie-sa8540p
+ - qcom,pcie-sc8280xp
+
+ reg:
+ minItems: 5
+ maxItems: 6
+
+ reg-names:
+ minItems: 5
+ items:
+ - const: parf # Qualcomm specific registers
+ - const: dbi # DesignWare PCIe registers
+ - const: elbi # External local bus interface registers
+ - const: atu # ATU address space
+ - const: config # PCIe configuration space
+ - const: mhi # MHI registers
+
+ clocks:
+ minItems: 8
+ maxItems: 9
+
+ clock-names:
+ minItems: 8
+ items:
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: ddrss_sf_tbu # PCIe SF TBU clock
+ - const: noc_aggr_4 # NoC aggregate 4 clock
+ - const: noc_aggr_south_sf # NoC aggregate South SF clock
+ - const: cnoc_qx # Configuration NoC QX clock
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: pci
+
+ vddpe-3v3-supply:
+ description: A phandle to the PCIe endpoint power supply
+
+required:
+ - interconnects
+ - interconnect-names
+
+allOf:
+ - $ref: qcom,pcie-common.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-sc8280xp
+ then:
+ properties:
+ interrupts:
+ minItems: 4
+ maxItems: 4
+ interrupt-names:
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ else:
+ properties:
+ interrupts:
+ maxItems: 1
+ interrupt-names:
+ items:
+ - const: msi
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interconnect/qcom,sc8280xp.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie@1c20000 {
+ compatible = "qcom,pcie-sc8280xp";
+ reg = <0x0 0x01c20000 0x0 0x3000>,
+ <0x0 0x3c000000 0x0 0xf1d>,
+ <0x0 0x3c000f20 0x0 0xa8>,
+ <0x0 0x3c001000 0x0 0x1000>,
+ <0x0 0x3c100000 0x0 0x100000>,
+ <0x0 0x01c23000 0x0 0x1000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
+ ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>,
+ <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
+
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ linux,pci-domain = <2>;
+ num-lanes = <4>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+ clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
+ <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ddrss_sf_tbu",
+ "noc_aggr_4",
+ "noc_aggr_south_sf";
+
+ dma-coherent;
+
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ phys = <&pcie2a_phy>;
+ phy-names = "pciephy";
+
+ pinctrl-0 = <&pcie2a_default>;
+ pinctrl-names = "default";
+
+ power-domains = <&gcc PCIE_2A_GDSC>;
+
+ resets = <&gcc GCC_PCIE_2A_BCR>;
+ reset-names = "pci";
+
+ perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+ vddpe-3v3-supply = <&vreg_nvme>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 6e03a1bce5d4..c8f36978a94c 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -28,11 +28,9 @@ properties:
- qcom,pcie-ipq8074-gen3
- qcom,pcie-msm8996
- qcom,pcie-qcs404
- - qcom,pcie-sa8540p
- qcom,pcie-sa8775p
- qcom,pcie-sc7280
- qcom,pcie-sc8180x
- - qcom,pcie-sc8280xp
- qcom,pcie-sdm845
- qcom,pcie-sdx55
- items:
@@ -210,7 +208,6 @@ allOf:
- qcom,pcie-sa8775p
- qcom,pcie-sc7280
- qcom,pcie-sc8180x
- - qcom,pcie-sc8280xp
- qcom,pcie-sdx55
then:
properties:
@@ -538,36 +535,6 @@ allOf:
items:
- const: pci # PCIe core reset
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-sa8540p
- - qcom,pcie-sc8280xp
- then:
- properties:
- clocks:
- minItems: 8
- maxItems: 9
- clock-names:
- minItems: 8
- items:
- - const: aux # Auxiliary clock
- - const: cfg # Configuration clock
- - const: bus_master # Master AXI clock
- - const: bus_slave # Slave AXI clock
- - const: slave_q2a # Slave Q2A clock
- - const: ddrss_sf_tbu # PCIe SF TBU clock
- - const: noc_aggr_4 # NoC aggregate 4 clock
- - const: noc_aggr_south_sf # NoC aggregate South SF clock
- - const: cnoc_qx # Configuration NoC QX clock
- resets:
- maxItems: 1
- reset-names:
- items:
- - const: pci # PCIe core reset
-
- if:
properties:
compatible:
@@ -623,9 +590,7 @@ allOf:
compatible:
contains:
enum:
- - qcom,pcie-sa8540p
- qcom,pcie-sa8775p
- - qcom,pcie-sc8280xp
then:
required:
- interconnects
@@ -692,24 +657,6 @@ allOf:
- const: msi6
- const: msi7
- - if:
- properties:
- compatible:
- contains:
- enum:
- - qcom,pcie-sc8280xp
- then:
- properties:
- interrupts:
- minItems: 4
- maxItems: 4
- interrupt-names:
- items:
- - const: msi0
- - const: msi1
- - const: msi2
- - const: msi3
-
- if:
properties:
compatible:
@@ -724,7 +671,6 @@ allOf:
- qcom,pcie-ipq8074
- qcom,pcie-ipq8074-gen3
- qcom,pcie-qcs404
- - qcom,pcie-sa8540p
then:
properties:
interrupts:
--
2.34.1
On Mon, Jan 08, 2024 at 03:19:14PM +0100, Krzysztof Kozlowski wrote:
> The qcom,pcie.yaml binding file containing all possible Qualcomm SoC
> PCIe root complexes gets quite complicated with numerous if:then:
> conditions customizing clocks, interrupts, regs and resets. Adding and
> reviewing new devices is difficult, so simplify it by having shared
> common binding and file with only one group of compatible devices:
>
> 1. Copy all common qcom,pcie.yaml properties (so everything except
> supplies) to a new shared qcom,pcie-common.yaml schema.
> 2. Move SM8550 PCIe compatible devices to dedicated binding file.
>
> This creates equivalent SM8550 schema file, except missing required
> compatible which is actually redundant.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> .../devicetree/bindings/pci/qcom,pcie-common.yaml | 98 ++++++++++++
> .../devicetree/bindings/pci/qcom,pcie-sm8550.yaml | 171 +++++++++++++++++++++
> .../devicetree/bindings/pci/qcom,pcie.yaml | 38 -----
> 3 files changed, 269 insertions(+), 38 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml
> new file mode 100644
> index 000000000000..125136176f93
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml
> @@ -0,0 +1,98 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/qcom,pcie-common.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm PCI Express Root Complex Common Properties
> +
> +maintainers:
> + - Bjorn Andersson <[email protected]>
> + - Manivannan Sadhasivam <[email protected]>
> +
> +properties:
> + reg:
> + minItems: 4
> + maxItems: 6
> +
> + reg-names:
> + minItems: 4
> + maxItems: 6
> +
> + interrupts:
> + minItems: 1
> + maxItems: 8
> +
> + interrupt-names:
> + minItems: 1
> + maxItems: 8
> +
> + iommu-map:
> + minItems: 1
> + maxItems: 16
> +
> + clocks:
> + minItems: 3
> + maxItems: 13
> +
> + clock-names:
> + minItems: 3
> + maxItems: 13
> +
> + dma-coherent: true
> +
> + interconnects:
> + maxItems: 2
> +
> + interconnect-names:
> + items:
> + - const: pcie-mem
> + - const: cpu-pcie
> +
> + phys:
> + maxItems: 1
> +
> + phy-names:
> + items:
> + - const: pciephy
> +
> + power-domains:
> + maxItems: 1
> +
> + resets:
> + minItems: 1
> + maxItems: 12
> +
> + reset-names:
> + minItems: 1
> + maxItems: 12
> +
> + perst-gpios:
> + description: GPIO controlled connection to PERST# signal
> + maxItems: 1
> +
> + wake-gpios:
> + description: GPIO controlled connection to WAKE# signal
> + maxItems: 1
> +
> +required:
> + - reg
> + - reg-names
> + - interrupt-map-mask
> + - interrupt-map
> + - clocks
> + - clock-names
> +
> +anyOf:
> + - required:
> + - interrupts
> + - interrupt-names
> + - "#interrupt-cells"
> + - required:
> + - msi-map
> + - msi-map-mask
> +
> +allOf:
> + - $ref: /schemas/pci/pci-bus.yaml#
> +
> +additionalProperties: true
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml
> new file mode 100644
> index 000000000000..b6d025f153bc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml
> @@ -0,0 +1,171 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8550.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SM8550 PCI Express Root Complex
> +
> +maintainers:
> + - Bjorn Andersson <[email protected]>
> + - Manivannan Sadhasivam <[email protected]>
> +
> +description:
> + Qualcomm SM8550 SoC (and compatible) PCIe root complex controller is based on
> + the Synopsys DesignWare PCIe IP.
> +
> +properties:
> + compatible:
> + oneOf:
> + - const: qcom,pcie-sm8550
> + - items:
> + - enum:
> + - qcom,pcie-sm8650
> + - const: qcom,pcie-sm8550
> +
> + reg:
> + minItems: 5
> + maxItems: 6
> +
> + reg-names:
> + minItems: 5
> + items:
> + - const: parf # Qualcomm specific registers
> + - const: dbi # DesignWare PCIe registers
> + - const: elbi # External local bus interface registers
> + - const: atu # ATU address space
> + - const: config # PCIe configuration space
> + - const: mhi # MHI registers
> +
> + clocks:
> + minItems: 7
> + maxItems: 8
> +
> + clock-names:
> + minItems: 7
> + items:
> + - const: aux # Auxiliary clock
> + - const: cfg # Configuration clock
> + - const: bus_master # Master AXI clock
> + - const: bus_slave # Slave AXI clock
> + - const: slave_q2a # Slave Q2A clock
> + - const: ddrss_sf_tbu # PCIe SF TBU clock
> + - const: noc_aggr # Aggre NoC PCIe AXI clock
> + - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
> +
> + resets:
> + minItems: 1
> + maxItems: 2
> +
> + reset-names:
> + minItems: 1
> + items:
> + - const: pci # PCIe core reset
> + - const: link_down # PCIe link down reset
> +
> +oneOf:
> + - properties:
> + interrupts:
> + maxItems: 1
> + interrupt-names:
> + items:
> + - const: msi
> +
> + - properties:
> + interrupts:
> + minItems: 8
> + interrupt-names:
> + items:
> + - const: msi0
> + - const: msi1
> + - const: msi2
> + - const: msi3
> + - const: msi4
> + - const: msi5
> + - const: msi6
> + - const: msi7
How does a given SoC have 1 or 8 interrupts? I guess it is possible. A
comment here would be helpful.
Reviewed-by: Rob Herring <[email protected]>
On Mon, Jan 08, 2024 at 03:19:15PM +0100, Krzysztof Kozlowski wrote:
> Move SM8450 PCIe devices from qcom,pcie.yaml binding to a dedicated file
> to make reviewing easier.
>
> This creates equivalent schema file, except missing required compatible
> which is actually redundant.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> .../devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 215 +++++++++++++++++++++
> .../devicetree/bindings/pci/qcom,pcie.yaml | 67 -------
> 2 files changed, 215 insertions(+), 67 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml
> new file mode 100644
> index 000000000000..59ba809b6204
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml
> @@ -0,0 +1,215 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8450.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SM8450 PCI Express Root Complex
> +
> +maintainers:
> + - Bjorn Andersson <[email protected]>
> + - Manivannan Sadhasivam <[email protected]>
> +
> +description:
> + Qualcomm SM8450 SoC PCIe root complex controller is based on the Synopsys
> + DesignWare PCIe IP.
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,pcie-sm8450-pcie0
> + - qcom,pcie-sm8450-pcie1
> +
> + reg:
> + minItems: 5
> + maxItems: 6
> +
> + reg-names:
> + minItems: 5
> + items:
> + - const: parf # Qualcomm specific registers
> + - const: dbi # DesignWare PCIe registers
> + - const: elbi # External local bus interface registers
> + - const: atu # ATU address space
> + - const: config # PCIe configuration space
> + - const: mhi # MHI registers
> +
> + clocks:
> + minItems: 11
> + maxItems: 12
> +
> + clock-names:
> + minItems: 11
> + maxItems: 12
> +
> + resets:
> + maxItems: 1
> +
> + reset-names:
> + items:
> + - const: pci
> +
> +oneOf:
> + - properties:
> + interrupts:
> + maxItems: 1
> + interrupt-names:
> + items:
> + - const: msi
> +
> + - properties:
> + interrupts:
> + minItems: 8
> + interrupt-names:
> + items:
> + - const: msi0
> + - const: msi1
> + - const: msi2
> + - const: msi3
> + - const: msi4
> + - const: msi5
> + - const: msi6
> + - const: msi7
> +
> +allOf:
> + - $ref: qcom,pcie-common.yaml#
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,pcie-sm8450-pcie0
> + then:
> + properties:
> + clocks:
> + minItems: 12
> + maxItems: 12
> + clock-names:
> + items:
> + - const: pipe # PIPE clock
> + - const: pipe_mux # PIPE MUX
> + - const: phy_pipe # PIPE output clock
> + - const: ref # REFERENCE clock
> + - const: aux # Auxiliary clock
> + - const: cfg # Configuration clock
> + - const: bus_master # Master AXI clock
> + - const: bus_slave # Slave AXI clock
> + - const: slave_q2a # Slave Q2A clock
> + - const: ddrss_sf_tbu # PCIe SF TBU clock
> + - const: aggre0 # Aggre NoC PCIe0 AXI clock
> + - const: aggre1 # Aggre NoC PCIe1 AXI clock
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,pcie-sm8450-pcie1
> + then:
> + properties:
> + clocks:
> + minItems: 11
> + maxItems: 11
> + clock-names:
> + items:
> + - const: pipe # PIPE clock
> + - const: pipe_mux # PIPE MUX
> + - const: phy_pipe # PIPE output clock
> + - const: ref # REFERENCE clock
> + - const: aux # Auxiliary clock
> + - const: cfg # Configuration clock
> + - const: bus_master # Master AXI clock
> + - const: bus_slave # Slave AXI clock
> + - const: slave_q2a # Slave Q2A clock
> + - const: ddrss_sf_tbu # PCIe SF TBU clock
> + - const: aggre1 # Aggre NoC PCIe1 AXI clock
Almost the same list. Combine them and just make the 11th entry "enum:
[aggre0, aggre1]".
Rob
On Mon, 08 Jan 2024 15:19:16 +0100, Krzysztof Kozlowski wrote:
> Move SM8250 PCIe devices from qcom,pcie.yaml binding to a dedicated file
> to make reviewing easier.
>
> This creates equivalent schema file, except missing required compatible
> which is actually redundant.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> .../devicetree/bindings/pci/qcom,pcie-sm8250.yaml | 180 +++++++++++++++++++++
> .../devicetree/bindings/pci/qcom,pcie.yaml | 48 ------
> 2 files changed, 180 insertions(+), 48 deletions(-)
>
Reviewed-by: Rob Herring <[email protected]>
On Mon, 08 Jan 2024 15:19:17 +0100, Krzysztof Kozlowski wrote:
> Move SM8150 PCIe devices from qcom,pcie.yaml binding to a dedicated file
> to make reviewing easier.
>
> This creates equivalent schema file, except missing required compatible
> which is actually redundant.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> .../devicetree/bindings/pci/qcom,pcie-sm8150.yaml | 157 +++++++++++++++++++++
> .../devicetree/bindings/pci/qcom,pcie.yaml | 29 ----
> 2 files changed, 157 insertions(+), 29 deletions(-)
>
Reviewed-by: Rob Herring <[email protected]>
On Mon, 08 Jan 2024 15:19:18 +0100, Krzysztof Kozlowski wrote:
> Move SM8350 PCIe devices from qcom,pcie.yaml binding to a dedicated file
> to make reviewing easier.
>
> This creates equivalent schema file, except missing required compatible
> which is actually redundant.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> .../devicetree/bindings/pci/qcom,pcie-sm8350.yaml | 169 +++++++++++++++++++++
> .../devicetree/bindings/pci/qcom,pcie.yaml | 32 ----
> 2 files changed, 169 insertions(+), 32 deletions(-)
>
Reviewed-by: Rob Herring <[email protected]>
On Mon, 08 Jan 2024 15:19:19 +0100, Krzysztof Kozlowski wrote:
> Move SC8280XP compatible PCIe devices from qcom,pcie.yaml binding to a
> dedicated file to make reviewing easier.
>
> This creates equivalent schema file, except missing required compatible
> which is actually redundant.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> .../bindings/pci/qcom,pcie-sc8280xp.yaml | 180 +++++++++++++++++++++
> .../devicetree/bindings/pci/qcom,pcie.yaml | 54 -------
> 2 files changed, 180 insertions(+), 54 deletions(-)
>
Reviewed-by: Rob Herring <[email protected]>
On Tue, Jan 16, 2024 at 08:44:19AM -0600, Rob Herring wrote:
> On Mon, Jan 08, 2024 at 03:19:14PM +0100, Krzysztof Kozlowski wrote:
> > The qcom,pcie.yaml binding file containing all possible Qualcomm SoC
> > PCIe root complexes gets quite complicated with numerous if:then:
> > conditions customizing clocks, interrupts, regs and resets. Adding and
> > reviewing new devices is difficult, so simplify it by having shared
> > common binding and file with only one group of compatible devices:
> >
> > 1. Copy all common qcom,pcie.yaml properties (so everything except
> > supplies) to a new shared qcom,pcie-common.yaml schema.
> > 2. Move SM8550 PCIe compatible devices to dedicated binding file.
> >
> > This creates equivalent SM8550 schema file, except missing required
> > compatible which is actually redundant.
> >
> > Signed-off-by: Krzysztof Kozlowski <[email protected]>
> > ---
> > .../devicetree/bindings/pci/qcom,pcie-common.yaml | 98 ++++++++++++
> > .../devicetree/bindings/pci/qcom,pcie-sm8550.yaml | 171 +++++++++++++++++++++
> > .../devicetree/bindings/pci/qcom,pcie.yaml | 38 -----
> > 3 files changed, 269 insertions(+), 38 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml
> > new file mode 100644
> > index 000000000000..125136176f93
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml
> > @@ -0,0 +1,98 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/qcom,pcie-common.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm PCI Express Root Complex Common Properties
> > +
> > +maintainers:
> > + - Bjorn Andersson <[email protected]>
> > + - Manivannan Sadhasivam <[email protected]>
> > +
> > +properties:
> > + reg:
> > + minItems: 4
> > + maxItems: 6
> > +
> > + reg-names:
> > + minItems: 4
> > + maxItems: 6
> > +
> > + interrupts:
> > + minItems: 1
> > + maxItems: 8
> > +
> > + interrupt-names:
> > + minItems: 1
> > + maxItems: 8
> > +
> > + iommu-map:
> > + minItems: 1
> > + maxItems: 16
> > +
> > + clocks:
> > + minItems: 3
> > + maxItems: 13
> > +
> > + clock-names:
> > + minItems: 3
> > + maxItems: 13
> > +
> > + dma-coherent: true
> > +
> > + interconnects:
> > + maxItems: 2
> > +
> > + interconnect-names:
> > + items:
> > + - const: pcie-mem
> > + - const: cpu-pcie
> > +
> > + phys:
> > + maxItems: 1
> > +
> > + phy-names:
> > + items:
> > + - const: pciephy
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + resets:
> > + minItems: 1
> > + maxItems: 12
> > +
> > + reset-names:
> > + minItems: 1
> > + maxItems: 12
> > +
> > + perst-gpios:
> > + description: GPIO controlled connection to PERST# signal
> > + maxItems: 1
> > +
> > + wake-gpios:
> > + description: GPIO controlled connection to WAKE# signal
> > + maxItems: 1
> > +
> > +required:
> > + - reg
> > + - reg-names
> > + - interrupt-map-mask
> > + - interrupt-map
> > + - clocks
> > + - clock-names
> > +
> > +anyOf:
> > + - required:
> > + - interrupts
> > + - interrupt-names
> > + - "#interrupt-cells"
> > + - required:
> > + - msi-map
> > + - msi-map-mask
> > +
> > +allOf:
> > + - $ref: /schemas/pci/pci-bus.yaml#
> > +
> > +additionalProperties: true
> > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml
> > new file mode 100644
> > index 000000000000..b6d025f153bc
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml
> > @@ -0,0 +1,171 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8550.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm SM8550 PCI Express Root Complex
> > +
> > +maintainers:
> > + - Bjorn Andersson <[email protected]>
> > + - Manivannan Sadhasivam <[email protected]>
> > +
> > +description:
> > + Qualcomm SM8550 SoC (and compatible) PCIe root complex controller is based on
> > + the Synopsys DesignWare PCIe IP.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - const: qcom,pcie-sm8550
> > + - items:
> > + - enum:
> > + - qcom,pcie-sm8650
> > + - const: qcom,pcie-sm8550
> > +
> > + reg:
> > + minItems: 5
> > + maxItems: 6
> > +
> > + reg-names:
> > + minItems: 5
> > + items:
> > + - const: parf # Qualcomm specific registers
> > + - const: dbi # DesignWare PCIe registers
> > + - const: elbi # External local bus interface registers
> > + - const: atu # ATU address space
> > + - const: config # PCIe configuration space
> > + - const: mhi # MHI registers
> > +
> > + clocks:
> > + minItems: 7
> > + maxItems: 8
> > +
> > + clock-names:
> > + minItems: 7
> > + items:
> > + - const: aux # Auxiliary clock
> > + - const: cfg # Configuration clock
> > + - const: bus_master # Master AXI clock
> > + - const: bus_slave # Slave AXI clock
> > + - const: slave_q2a # Slave Q2A clock
> > + - const: ddrss_sf_tbu # PCIe SF TBU clock
> > + - const: noc_aggr # Aggre NoC PCIe AXI clock
> > + - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock
> > +
> > + resets:
> > + minItems: 1
> > + maxItems: 2
> > +
> > + reset-names:
> > + minItems: 1
> > + items:
> > + - const: pci # PCIe core reset
> > + - const: link_down # PCIe link down reset
> > +
> > +oneOf:
> > + - properties:
> > + interrupts:
> > + maxItems: 1
> > + interrupt-names:
> > + items:
> > + - const: msi
> > +
> > + - properties:
> > + interrupts:
> > + minItems: 8
> > + interrupt-names:
> > + items:
> > + - const: msi0
> > + - const: msi1
> > + - const: msi2
> > + - const: msi3
> > + - const: msi4
> > + - const: msi5
> > + - const: msi6
> > + - const: msi7
>
> How does a given SoC have 1 or 8 interrupts? I guess it is possible. A
> comment here would be helpful.
>
No, this is due to kernel developers not able to find out the max MSI numbers
for each platforms out of the Qcom internal documentation.
Let it be for now, I will try to fetch these numbers to make it accurate later.
- Mani
> Reviewed-by: Rob Herring <[email protected]>
>
--
மணிவண்ணன் சதாசிவம்
On 16/01/2024 15:48, Rob Herring wrote:
>> + clock-names:
>> + items:
>> + - const: pipe # PIPE clock
>> + - const: pipe_mux # PIPE MUX
>> + - const: phy_pipe # PIPE output clock
>> + - const: ref # REFERENCE clock
>> + - const: aux # Auxiliary clock
>> + - const: cfg # Configuration clock
>> + - const: bus_master # Master AXI clock
>> + - const: bus_slave # Slave AXI clock
>> + - const: slave_q2a # Slave Q2A clock
>> + - const: ddrss_sf_tbu # PCIe SF TBU clock
>> + - const: aggre1 # Aggre NoC PCIe1 AXI clock
>
> Almost the same list. Combine them and just make the 11th entry "enum:
> [aggre0, aggre1]".
Sure.
Best regards,
Krzysztof
On Mon, Jan 08, 2024 at 03:19:13PM +0100, Krzysztof Kozlowski wrote:
> Hi,
>
> The qcom,pcie.yaml containing all devices results in huge allOf: section
> with a lot of if:then: clauses making review and changes quite
> difficult.
>
> Split common parts into common schema and then move few devices to
> dedicated files, so that each file will be easier to review.
>
> I did not split/move all devices yet, so if this gets accepted I plan to
> send more patches.
>
Acked-by: Manivannan Sadhasivam <[email protected]>
- Mani
> Best regards,
> Krzysztof
>
> ---
> Krzysztof Kozlowski (6):
> dt-bindings: PCI: qcom,pcie-sm8550: move SM8550 to dedicated schema
> dt-bindings: PCI: qcom,pcie-sm8450: move SM8450 to dedicated schema
> dt-bindings: PCI: qcom,pcie-sm8250: move SM8250 to dedicated schema
> dt-bindings: PCI: qcom,pcie-sm8150: move SM8150 to dedicated schema
> dt-bindings: PCI: qcom,pcie-sm8350: move SM8350 to dedicated schema
> dt-bindings: PCI: qcom,pcie-sc8280xp: move SC8280XP to dedicated schema
>
> .../devicetree/bindings/pci/qcom,pcie-common.yaml | 98 ++++++++
> .../bindings/pci/qcom,pcie-sc8280xp.yaml | 180 ++++++++++++++
> .../devicetree/bindings/pci/qcom,pcie-sm8150.yaml | 157 ++++++++++++
> .../devicetree/bindings/pci/qcom,pcie-sm8250.yaml | 180 ++++++++++++++
> .../devicetree/bindings/pci/qcom,pcie-sm8350.yaml | 169 +++++++++++++
> .../devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 215 +++++++++++++++++
> .../devicetree/bindings/pci/qcom,pcie-sm8550.yaml | 171 +++++++++++++
> .../devicetree/bindings/pci/qcom,pcie.yaml | 268 ---------------------
> 8 files changed, 1170 insertions(+), 268 deletions(-)
> ---
> base-commit: a0bf076e449e022944b440174491f5c583753d84
> change-id: 20240108-dt-bindings-pci-qcom-split-624737f7ba67
>
> Best regards,
> --
> Krzysztof Kozlowski <[email protected]>
>
--
மணிவண்ணன் சதாசிவம்
On 17/01/2024 07:30, Manivannan Sadhasivam wrote:
>>
>> How does a given SoC have 1 or 8 interrupts? I guess it is possible. A
>> comment here would be helpful.
>>
>
> No, this is due to kernel developers not able to find out the max MSI numbers
> for each platforms out of the Qcom internal documentation.
>
> Let it be for now, I will try to fetch these numbers to make it accurate later.
I'll complete the interrupts the binding and the DTS.
Best regards,
Krzysztof