Just a couple of minor fixes in preparation for PCIe shutdown (and by
extension CX, AOSD and DDR power collapse - anybody here a fan of
suspend?).
If you want to test this on your machine, you're gonna need:
- https://lore.kernel.org/all/20231227-topic-pmdomain_sync_cleanup-v1-1-5f36769d538b@linaro.org/
- https://lore.kernel.org/all/[email protected]/
- https://lore.kernel.org/all/[email protected]/
- All PCIe devices that require fw must be fully booted (so that they can be suspended)
- You must not have any dangling resource votes (not the case on 8280-crd)
Signed-off-by: Konrad Dybcio <[email protected]>
---
Konrad Dybcio (3):
arm64: dts: qcom: sc8280xp: Fix PCIe PHY power-domains
arm64: dts: qcom: sc8280xp: Correct USB PHY power domains
arm64: dts: qcom: sc8280xp-crd: Add PCIe CLKREQ# sleep state
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 78 ++++++++++++++++++++-----------
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 18 +++----
2 files changed, 60 insertions(+), 36 deletions(-)
---
base-commit: 39676dfe52331dba909c617f213fdb21015c8d10
change-id: 20231227-topic-8280_pcie_dts-4d3a94efe6e7
Best regards,
--
Konrad Dybcio <[email protected]>
The PCIe GDSCs are only related to the RCs. The PCIe PHYs on the other
hand, are powered by VDD_MX and their specific VDDA_PHY/PLL regulators.
Fix the power-domains assignment to stop potentially toggling the GDSC
unnecessarily.
Fixes: 813e83157001 ("arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes")
Signed-off-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index febf28356ff8..72c5818b67f2 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -1797,7 +1797,7 @@ pcie4_phy: phy@1c06000 {
assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
assigned-clock-rates = <100000000>;
- power-domains = <&gcc PCIE_4_GDSC>;
+ power-domains = <&rpmhpd SC8280XP_MX>;
resets = <&gcc GCC_PCIE_4_PHY_BCR>;
reset-names = "phy";
@@ -1895,7 +1895,7 @@ pcie3b_phy: phy@1c0e000 {
assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
assigned-clock-rates = <100000000>;
- power-domains = <&gcc PCIE_3B_GDSC>;
+ power-domains = <&rpmhpd SC8280XP_MX>;
resets = <&gcc GCC_PCIE_3B_PHY_BCR>;
reset-names = "phy";
@@ -1994,7 +1994,7 @@ pcie3a_phy: phy@1c14000 {
assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
assigned-clock-rates = <100000000>;
- power-domains = <&gcc PCIE_3A_GDSC>;
+ power-domains = <&rpmhpd SC8280XP_MX>;
resets = <&gcc GCC_PCIE_3A_PHY_BCR>;
reset-names = "phy";
@@ -2094,7 +2094,7 @@ pcie2b_phy: phy@1c1e000 {
assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
assigned-clock-rates = <100000000>;
- power-domains = <&gcc PCIE_2B_GDSC>;
+ power-domains = <&rpmhpd SC8280XP_MX>;
resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
reset-names = "phy";
@@ -2193,7 +2193,7 @@ pcie2a_phy: phy@1c24000 {
assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;
assigned-clock-rates = <100000000>;
- power-domains = <&gcc PCIE_2A_GDSC>;
+ power-domains = <&rpmhpd SC8280XP_MX>;
resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
reset-names = "phy";
--
2.43.0
The USB GDSCs are only related to the controllers. The PHYs on the other
hand, are powered by VDD_MX and their specific VDDA_PHY/PLL regulators.
Fix the power-domains assignment to stop potentially toggling the GDSC
unnecessarily.
Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
Signed-off-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 72c5818b67f2..4b18a0762ca7 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -2597,7 +2597,7 @@ usb_2_qmpphy0: phy@88ef000 {
<&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
reset-names = "phy", "phy_phy";
- power-domains = <&gcc USB30_MP_GDSC>;
+ power-domains = <&rpmhpd SC8280XP_MX>;
#clock-cells = <0>;
clock-output-names = "usb2_phy0_pipe_clk";
@@ -2621,7 +2621,7 @@ usb_2_qmpphy1: phy@88f1000 {
<&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
reset-names = "phy", "phy_phy";
- power-domains = <&gcc USB30_MP_GDSC>;
+ power-domains = <&rpmhpd SC8280XP_MX>;
#clock-cells = <0>;
clock-output-names = "usb2_phy1_pipe_clk";
@@ -3109,7 +3109,7 @@ usb_0_qmpphy: phy@88eb000 {
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "aux", "ref", "com_aux", "usb3_pipe";
- power-domains = <&gcc USB30_PRIM_GDSC>;
+ power-domains = <&rpmhpd SC8280XP_MX>;
resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
<&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
@@ -3162,7 +3162,7 @@ usb_1_qmpphy: phy@8903000 {
<&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
clock-names = "aux", "ref", "com_aux", "usb3_pipe";
- power-domains = <&gcc USB30_SEC_GDSC>;
+ power-domains = <&rpmhpd SC8280XP_MX>;
resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
<&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>;
--
2.43.0
The CLKREQ pin should not be muxed to its active function when the RC
is asleep. Add the missing pin sleep states to resolve that.
Fixes: d907fe5acbf1 ("arm64: dts: qcom: sc8280xp-crd: enable WiFi controller")
Fixes: 17e2ccaf65d1 ("arm64: dts: qcom: sc8280xp-crd: enable SDX55 modem")
Fixes: 6a1ec5eca73c ("arm64: dts: qcom: sc8280xp-crd: enable NVMe SSD")
Signed-off-by: Konrad Dybcio <[email protected]>
---
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 78 ++++++++++++++++++++-----------
1 file changed, 51 insertions(+), 27 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
index ffc4406422ae..58c0c2d10cb3 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
@@ -530,8 +530,9 @@ &pcie2a {
vddpe-3v3-supply = <&vreg_nvme>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie2a_default>;
+ pinctrl-0 = <&pcie2a_default>, <&pcie2a_clkreq_default>;
+ pinctrl-1 = <&pcie2a_default>, <&pcie2a_clkreq_sleep>;
+ pinctrl-names = "default", "sleep";
status = "okay";
};
@@ -549,8 +550,9 @@ &pcie3a {
vddpe-3v3-supply = <&vreg_wwan>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie3a_default>;
+ pinctrl-0 = <&pcie3a_default>, <&pcie3a_clkreq_default>;
+ pinctrl-1 = <&pcie3a_default>, <&pcie3a_clkreq_sleep>;
+ pinctrl-names = "default", "sleep";
status = "okay";
};
@@ -568,8 +570,9 @@ &pcie4 {
vddpe-3v3-supply = <&vreg_wlan>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie4_default>;
+ pinctrl-0 = <&pcie4_default>, <&pcie4_clkreq_default>;
+ pinctrl-1 = <&pcie4_default>, <&pcie4_clkreq_sleep>;
+ pinctrl-names = "default", "sleep";
status = "okay";
};
@@ -835,13 +838,6 @@ nvme_reg_en: nvme-reg-en-state {
};
pcie2a_default: pcie2a-default-state {
- clkreq-n-pins {
- pins = "gpio142";
- function = "pcie2a_clkreq";
- drive-strength = <2>;
- bias-pull-up;
- };
-
perst-n-pins {
pins = "gpio143";
function = "gpio";
@@ -857,14 +853,21 @@ wake-n-pins {
};
};
- pcie3a_default: pcie3a-default-state {
- clkreq-n-pins {
- pins = "gpio150";
- function = "pcie3a_clkreq";
- drive-strength = <2>;
- bias-pull-up;
- };
+ pcie2a_clkreq_default: pcie2a-clkreq-default-state {
+ pins = "gpio142";
+ function = "pcie2a_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ pcie2a_clkreq_sleep: pcie2a-clkreq-sleep-state {
+ pins = "gpio142";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ pcie3a_default: pcie3a-default-state {
perst-n-pins {
pins = "gpio151";
function = "gpio";
@@ -880,14 +883,21 @@ wake-n-pins {
};
};
- pcie4_default: pcie4-default-state {
- clkreq-n-pins {
- pins = "gpio140";
- function = "pcie4_clkreq";
- drive-strength = <2>;
- bias-pull-up;
- };
+ pcie3a_clkreq_default: pcie3a-clkreq-default-state {
+ pins = "gpio150";
+ function = "pcie3a_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ pcie3a_clkreq_sleep: pcie3a-clkreq-sleep-state {
+ pins = "gpio150";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ pcie4_default: pcie4-default-state {
perst-n-pins {
pins = "gpio141";
function = "gpio";
@@ -903,6 +913,20 @@ wake-n-pins {
};
};
+ pcie4_clkreq_default: pcie4-clkreq-default-state {
+ pins = "gpio140";
+ function = "pcie4_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ pcie4_clkreq_sleep: pcie4-clkreq-sleep-state {
+ pins = "gpio140";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
sdc2_default_state: sdc2-default-state {
clk-pins {
pins = "sdc2_clk";
--
2.43.0
On Wed, Dec 27, 2023 at 11:28:26PM +0100, Konrad Dybcio wrote:
> The PCIe GDSCs are only related to the RCs. The PCIe PHYs on the other
> hand, are powered by VDD_MX and their specific VDDA_PHY/PLL regulators.
No, that does not seem to be entirely correct. I added the power-domains
here precisely because they were needed to enable the PHYs.
This is something I stumbled over when trying to figure out how to
add support for the second lane pair (i.e. four-lane mode), and I just
went back and confirmed that this is still the case.
If you try to enable one of these PHYs without the corresponding GDSC
being enabled, you end up with:
[ 37.709324] ------------[ cut here ]------------
[ 37.718196] gcc_pcie_3b_aux_clk status stuck at 'off'
[ 37.718205] WARNING: CPU: 4 PID: 482 at drivers/clk/qcom/clk-branch.c:86 clk_branch_wait+0x144/0x15c
Now, you may or may not want to describe the above in the devicetree,
but this makes it sound like you're trying to work around an issue with
the current Linux implementation.
> Fix the power-domains assignment to stop potentially toggling the GDSC
> unnecessarily.
Nothing is being toggled unnecessarily, and generally this is just
another use count increment.
> Fixes: 813e83157001 ("arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes")
So not sure a Fixes tag is warranted either.
> @@ -1895,7 +1895,7 @@ pcie3b_phy: phy@1c0e000 {
> assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
> assigned-clock-rates = <100000000>;
>
> - power-domains = <&gcc PCIE_3B_GDSC>;
> + power-domains = <&rpmhpd SC8280XP_MX>;
>
> resets = <&gcc GCC_PCIE_3B_PHY_BCR>;
> reset-names = "phy";
Johan
On Wed, Dec 27, 2023 at 11:28:27PM +0100, Konrad Dybcio wrote:
> The USB GDSCs are only related to the controllers.
Are you sure?
> The PHYs on the other
> hand, are powered by VDD_MX and their specific VDDA_PHY/PLL regulators.
>
> Fix the power-domains assignment to stop potentially toggling the GDSC
> unnecessarily.
Again, there's no additional toggling being done here, but yes, this may
keep the domains enabled during suspend depending on how the driver is
implemented.
If that's the concern, then please spell that out too.
> Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
May not be needed either.
> @@ -2597,7 +2597,7 @@ usb_2_qmpphy0: phy@88ef000 {
> <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
> reset-names = "phy", "phy_phy";
>
> - power-domains = <&gcc USB30_MP_GDSC>;
> + power-domains = <&rpmhpd SC8280XP_MX>;
Johan
On Wed, Dec 27, 2023 at 11:28:28PM +0100, Konrad Dybcio wrote:
> The CLKREQ pin should not be muxed to its active function when the RC
> is asleep.
You forgot to explain *why* you think this is needed.
Note that this is only appears to be done for one upstream Qualcomm SoC
(msm8996) currently, and that, notably, there is no driver support for
actually changing the pin state.
> Add the missing pin sleep states to resolve that.
> Fixes: d907fe5acbf1 ("arm64: dts: qcom: sc8280xp-crd: enable WiFi controller")
> Fixes: 17e2ccaf65d1 ("arm64: dts: qcom: sc8280xp-crd: enable SDX55 modem")
> Fixes: 6a1ec5eca73c ("arm64: dts: qcom: sc8280xp-crd: enable NVMe SSD")
So not sure these Fixes tags are warranted either.
> Signed-off-by: Konrad Dybcio <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 78 ++++++++++++++++++++-----------
> 1 file changed, 51 insertions(+), 27 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> index ffc4406422ae..58c0c2d10cb3 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> @@ -530,8 +530,9 @@ &pcie2a {
>
> vddpe-3v3-supply = <&vreg_nvme>;
>
> - pinctrl-names = "default";
> - pinctrl-0 = <&pcie2a_default>;
> + pinctrl-0 = <&pcie2a_default>, <&pcie2a_clkreq_default>;
> + pinctrl-1 = <&pcie2a_default>, <&pcie2a_clkreq_sleep>;
> + pinctrl-names = "default", "sleep";
Johan
On 29.12.2023 14:01, Johan Hovold wrote:
> On Wed, Dec 27, 2023 at 11:28:27PM +0100, Konrad Dybcio wrote:
>> The USB GDSCs are only related to the controllers.
>
> Are you sure?
That's what I've been told from rather reliable sources.
>
>> The PHYs on the other
>> hand, are powered by VDD_MX and their specific VDDA_PHY/PLL regulators.
>>
>> Fix the power-domains assignment to stop potentially toggling the GDSC
>> unnecessarily.
>
> Again, there's no additional toggling being done here, but yes, this may
> keep the domains enabled during suspend depending on how the driver is
> implemented.
No, it can actually happen. (Some) QMP PHYs are referenced by the
DP hardware. If USB is disabled (or suspended), the DP being active
will hold these GDSCs enabled.
Konrad
> If that's the concern, then please spell that out too.
>
>> Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
>
> May not be needed either.
>
>> @@ -2597,7 +2597,7 @@ usb_2_qmpphy0: phy@88ef000 {
>> <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
>> reset-names = "phy", "phy_phy";
>>
>> - power-domains = <&gcc USB30_MP_GDSC>;
>> + power-domains = <&rpmhpd SC8280XP_MX>;
>
> Johan
On 29.12.2023 12:24, Johan Hovold wrote:
> On Wed, Dec 27, 2023 at 11:28:26PM +0100, Konrad Dybcio wrote:
>> The PCIe GDSCs are only related to the RCs. The PCIe PHYs on the other
>> hand, are powered by VDD_MX and their specific VDDA_PHY/PLL regulators.
>
> No, that does not seem to be entirely correct. I added the power-domains
> here precisely because they were needed to enable the PHYs.
>
> This is something I stumbled over when trying to figure out how to
> add support for the second lane pair (i.e. four-lane mode), and I just
> went back and confirmed that this is still the case.
>
> If you try to enable one of these PHYs without the corresponding GDSC
> being enabled, you end up with:
>
> [ 37.709324] ------------[ cut here ]------------
> [ 37.718196] gcc_pcie_3b_aux_clk status stuck at 'off'
> [ 37.718205] WARNING: CPU: 4 PID: 482 at drivers/clk/qcom/clk-branch.c:86 clk_branch_wait+0x144/0x15c
>
> Now, you may or may not want to describe the above in the devicetree,
> but this makes it sound like you're trying to work around an issue with
> the current Linux implementation.
Could you please recheck this with patch 1 from [1] applied?
Konrad
[1] https://lore.kernel.org/linux-arm-msm/[email protected]/T/#u
On Fri, Dec 29, 2023 at 02:08:25PM +0100, Konrad Dybcio wrote:
> On 29.12.2023 12:24, Johan Hovold wrote:
> > On Wed, Dec 27, 2023 at 11:28:26PM +0100, Konrad Dybcio wrote:
> >> The PCIe GDSCs are only related to the RCs. The PCIe PHYs on the other
> >> hand, are powered by VDD_MX and their specific VDDA_PHY/PLL regulators.
> >
> > No, that does not seem to be entirely correct. I added the power-domains
> > here precisely because they were needed to enable the PHYs.
> > If you try to enable one of these PHYs without the corresponding GDSC
> > being enabled, you end up with:
> >
> > [ 37.709324] ------------[ cut here ]------------
> > [ 37.718196] gcc_pcie_3b_aux_clk status stuck at 'off'
> > [ 37.718205] WARNING: CPU: 4 PID: 482 at drivers/clk/qcom/clk-branch.c:86 clk_branch_wait+0x144/0x15c
> >
> > Now, you may or may not want to describe the above in the devicetree,
> > but this makes it sound like you're trying to work around an issue with
> > the current Linux implementation.
> Could you please recheck this with patch 1 from [1] applied?
As expected that makes no difference as I'm powering on the PHY without
the corresponding controller being enabled (which otherwise guarantees
the GDSC to be on).
> [1] https://lore.kernel.org/linux-arm-msm/[email protected]/T/#u
Johan
[ Please remember to trim your replies and add a newline before your
inline comments to make them readable. ]
On Fri, Dec 29, 2023 at 02:06:26PM +0100, Konrad Dybcio wrote:
> On 29.12.2023 14:01, Johan Hovold wrote:
> > On Wed, Dec 27, 2023 at 11:28:27PM +0100, Konrad Dybcio wrote:
> >> Fix the power-domains assignment to stop potentially toggling the GDSC
> >> unnecessarily.
> >
> > Again, there's no additional toggling being done here, but yes, this may
> > keep the domains enabled during suspend depending on how the driver is
> > implemented.
> No, it can actually happen. (Some) QMP PHYs are referenced by the
> DP hardware. If USB is disabled (or suspended), the DP being active
> will hold these GDSCs enabled.
That's not a "toggling", is it? Also if the DP controller is a consumer of
these PHY's why should it not prevent the PHYs from suspending?
Johan
On 29.12.2023 14:25, Johan Hovold wrote:
> [ Please remember to trim your replies and add a newline before your
> inline comments to make them readable. ]
>
> On Fri, Dec 29, 2023 at 02:06:26PM +0100, Konrad Dybcio wrote:
>> On 29.12.2023 14:01, Johan Hovold wrote:
>>> On Wed, Dec 27, 2023 at 11:28:27PM +0100, Konrad Dybcio wrote:
>
>>>> Fix the power-domains assignment to stop potentially toggling the GDSC
>>>> unnecessarily.
>>>
>>> Again, there's no additional toggling being done here, but yes, this may
>>> keep the domains enabled during suspend depending on how the driver is
>>> implemented.
>
>> No, it can actually happen. (Some) QMP PHYs are referenced by the
>> DP hardware. If USB is disabled (or suspended), the DP being active
>> will hold these GDSCs enabled.
>
> That's not a "toggling", is it? Also if the DP controller is a consumer of
> these PHY's why should it not prevent the PHYs from suspending?
As far as I'm concerned, "toggling" is the correct word for "switching it
on".. While the PHYs are indeed useful for getting displayport to work,
the USB controller itself may not be necessary there, so enabling its
power line would be a bit of a waste..
Konrad
On Fri, Dec 29, 2023 at 04:05:18PM +0100, Konrad Dybcio wrote:
> On 29.12.2023 14:25, Johan Hovold wrote:
> > On Fri, Dec 29, 2023 at 02:06:26PM +0100, Konrad Dybcio wrote:
> >> On 29.12.2023 14:01, Johan Hovold wrote:
> >>> On Wed, Dec 27, 2023 at 11:28:27PM +0100, Konrad Dybcio wrote:
> >
> >>>> Fix the power-domains assignment to stop potentially toggling the GDSC
> >>>> unnecessarily.
> >>>
> >>> Again, there's no additional toggling being done here, but yes, this may
> >>> keep the domains enabled during suspend depending on how the driver is
> >>> implemented.
> >
> >> No, it can actually happen. (Some) QMP PHYs are referenced by the
> >> DP hardware. If USB is disabled (or suspended), the DP being active
> >> will hold these GDSCs enabled.
> >
> > That's not a "toggling", is it? Also if the DP controller is a consumer of
> > these PHY's why should it not prevent the PHYs from suspending?
>
> As far as I'm concerned, "toggling" is the correct word for "switching it
> on"..
Hmm, this doesn't make sense. The PHY power domain will be disabled when
the PHY is suspended, regardless of the DP controller. But sure, a
system with USB disabled, would end up with the USB GDSC on.
> While the PHYs are indeed useful for getting displayport to work,
> the USB controller itself may not be necessary there, so enabling its
> power line would be a bit of a waste..
Sure, if the PHYs truly don't need the USB PD then fine, this just
doesn't seem to be case for PCIe, or at least the picture isn't as clear
as your previous commit message suggested.
Johan
On Fri, Dec 29, 2023 at 12:24:55PM +0100, Johan Hovold wrote:
> On Wed, Dec 27, 2023 at 11:28:26PM +0100, Konrad Dybcio wrote:
> > The PCIe GDSCs are only related to the RCs. The PCIe PHYs on the other
> > hand, are powered by VDD_MX and their specific VDDA_PHY/PLL regulators.
>
> No, that does not seem to be entirely correct. I added the power-domains
> here precisely because they were needed to enable the PHYs.
>
> This is something I stumbled over when trying to figure out how to
> add support for the second lane pair (i.e. four-lane mode), and I just
> went back and confirmed that this is still the case.
>
> If you try to enable one of these PHYs without the corresponding GDSC
> being enabled, you end up with:
>
> [ 37.709324] ------------[ cut here ]------------
> [ 37.718196] gcc_pcie_3b_aux_clk status stuck at 'off'
> [ 37.718205] WARNING: CPU: 4 PID: 482 at drivers/clk/qcom/clk-branch.c:86 clk_branch_wait+0x144/0x15c
>
Technically this patch is correct. PHYs are backed by MX domain only and not
GDSCs. Only the controllers (PCIe, UFS, USB) are backed by GDSCs. The fact that
you are seeing issue with PCIe Aux clock suggests me that this clock may not be
applicable to the PHY but it needs to be enabled for working of the PHY somehow.
I'll try to find the details on how exactly it is needed.
But if I get the answer like, "This clock is also sourced to PHY directly", then
we may need to add dual power domain for PHY (both GDSC and MX).
> Now, you may or may not want to describe the above in the devicetree,
> but this makes it sound like you're trying to work around an issue with
> the current Linux implementation.
>
Adding MX domain to PHY in devicetree is definitely not a workaround. It is the
actual hardware representation. MX is the always on domain, and when CX collapse
happens during suspend state, it will ensure that all the analog components
(like PHY) are kept powered on. Otherwise, we will see link down issues.
But, I heard from Qcom that _only_ on this platform, MX is not backing the PCIe
PHY. I can correlate that with my encounter with PCIe issues after forcing CX
power collapse.
I haven't looked in detail on how this series fixes that issue though.
- Mani
> > Fix the power-domains assignment to stop potentially toggling the GDSC
> > unnecessarily.
>
> Nothing is being toggled unnecessarily, and generally this is just
> another use count increment.
>
> > Fixes: 813e83157001 ("arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes")
>
> So not sure a Fixes tag is warranted either.
>
> > @@ -1895,7 +1895,7 @@ pcie3b_phy: phy@1c0e000 {
> > assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
> > assigned-clock-rates = <100000000>;
> >
> > - power-domains = <&gcc PCIE_3B_GDSC>;
> > + power-domains = <&rpmhpd SC8280XP_MX>;
> >
> > resets = <&gcc GCC_PCIE_3B_PHY_BCR>;
> > reset-names = "phy";
>
> Johan
>
--
மணிவண்ணன் சதாசிவம்
On Fri, Dec 29, 2023 at 02:01:06PM +0100, Johan Hovold wrote:
> On Wed, Dec 27, 2023 at 11:28:27PM +0100, Konrad Dybcio wrote:
> > The USB GDSCs are only related to the controllers.
>
> Are you sure?
>
Yes, that's what I was told by UFS and PCIe teams and some of the internal
documentation also confirms the same.
> > The PHYs on the other
> > hand, are powered by VDD_MX and their specific VDDA_PHY/PLL regulators.
> >
> > Fix the power-domains assignment to stop potentially toggling the GDSC
> > unnecessarily.
>
> Again, there's no additional toggling being done here, but yes, this may
> keep the domains enabled during suspend depending on how the driver is
> implemented.
>
> If that's the concern, then please spell that out too.
>
> > Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
>
> May not be needed either.
>
Fixes tag is indeed needed on this platform and all other platforms too.
- Mani
> > @@ -2597,7 +2597,7 @@ usb_2_qmpphy0: phy@88ef000 {
> > <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
> > reset-names = "phy", "phy_phy";
> >
> > - power-domains = <&gcc USB30_MP_GDSC>;
> > + power-domains = <&rpmhpd SC8280XP_MX>;
>
> Johan
>
--
மணிவண்ணன் சதாசிவம்
On Wed, Dec 27, 2023 at 11:28:28PM +0100, Konrad Dybcio wrote:
> The CLKREQ pin should not be muxed to its active function when the RC
> is asleep. Add the missing pin sleep states to resolve that.
>
I don't understand why it should not be muxed and wondering what is the actual
issue you are seeing that lead to this conclusion.
- Mani
> Fixes: d907fe5acbf1 ("arm64: dts: qcom: sc8280xp-crd: enable WiFi controller")
> Fixes: 17e2ccaf65d1 ("arm64: dts: qcom: sc8280xp-crd: enable SDX55 modem")
> Fixes: 6a1ec5eca73c ("arm64: dts: qcom: sc8280xp-crd: enable NVMe SSD")
> Signed-off-by: Konrad Dybcio <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 78 ++++++++++++++++++++-----------
> 1 file changed, 51 insertions(+), 27 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> index ffc4406422ae..58c0c2d10cb3 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> @@ -530,8 +530,9 @@ &pcie2a {
>
> vddpe-3v3-supply = <&vreg_nvme>;
>
> - pinctrl-names = "default";
> - pinctrl-0 = <&pcie2a_default>;
> + pinctrl-0 = <&pcie2a_default>, <&pcie2a_clkreq_default>;
> + pinctrl-1 = <&pcie2a_default>, <&pcie2a_clkreq_sleep>;
> + pinctrl-names = "default", "sleep";
>
> status = "okay";
> };
> @@ -549,8 +550,9 @@ &pcie3a {
>
> vddpe-3v3-supply = <&vreg_wwan>;
>
> - pinctrl-names = "default";
> - pinctrl-0 = <&pcie3a_default>;
> + pinctrl-0 = <&pcie3a_default>, <&pcie3a_clkreq_default>;
> + pinctrl-1 = <&pcie3a_default>, <&pcie3a_clkreq_sleep>;
> + pinctrl-names = "default", "sleep";
>
> status = "okay";
> };
> @@ -568,8 +570,9 @@ &pcie4 {
>
> vddpe-3v3-supply = <&vreg_wlan>;
>
> - pinctrl-names = "default";
> - pinctrl-0 = <&pcie4_default>;
> + pinctrl-0 = <&pcie4_default>, <&pcie4_clkreq_default>;
> + pinctrl-1 = <&pcie4_default>, <&pcie4_clkreq_sleep>;
> + pinctrl-names = "default", "sleep";
>
> status = "okay";
> };
> @@ -835,13 +838,6 @@ nvme_reg_en: nvme-reg-en-state {
> };
>
> pcie2a_default: pcie2a-default-state {
> - clkreq-n-pins {
> - pins = "gpio142";
> - function = "pcie2a_clkreq";
> - drive-strength = <2>;
> - bias-pull-up;
> - };
> -
> perst-n-pins {
> pins = "gpio143";
> function = "gpio";
> @@ -857,14 +853,21 @@ wake-n-pins {
> };
> };
>
> - pcie3a_default: pcie3a-default-state {
> - clkreq-n-pins {
> - pins = "gpio150";
> - function = "pcie3a_clkreq";
> - drive-strength = <2>;
> - bias-pull-up;
> - };
> + pcie2a_clkreq_default: pcie2a-clkreq-default-state {
> + pins = "gpio142";
> + function = "pcie2a_clkreq";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + pcie2a_clkreq_sleep: pcie2a-clkreq-sleep-state {
> + pins = "gpio142";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
>
> + pcie3a_default: pcie3a-default-state {
> perst-n-pins {
> pins = "gpio151";
> function = "gpio";
> @@ -880,14 +883,21 @@ wake-n-pins {
> };
> };
>
> - pcie4_default: pcie4-default-state {
> - clkreq-n-pins {
> - pins = "gpio140";
> - function = "pcie4_clkreq";
> - drive-strength = <2>;
> - bias-pull-up;
> - };
> + pcie3a_clkreq_default: pcie3a-clkreq-default-state {
> + pins = "gpio150";
> + function = "pcie3a_clkreq";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
>
> + pcie3a_clkreq_sleep: pcie3a-clkreq-sleep-state {
> + pins = "gpio150";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + pcie4_default: pcie4-default-state {
> perst-n-pins {
> pins = "gpio141";
> function = "gpio";
> @@ -903,6 +913,20 @@ wake-n-pins {
> };
> };
>
> + pcie4_clkreq_default: pcie4-clkreq-default-state {
> + pins = "gpio140";
> + function = "pcie4_clkreq";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + pcie4_clkreq_sleep: pcie4-clkreq-sleep-state {
> + pins = "gpio140";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> sdc2_default_state: sdc2-default-state {
> clk-pins {
> pins = "sdc2_clk";
>
> --
> 2.43.0
>
>
--
மணிவண்ணன் சதாசிவம்
On 29.12.2023 18:03, Manivannan Sadhasivam wrote:
> On Fri, Dec 29, 2023 at 12:24:55PM +0100, Johan Hovold wrote:
>> On Wed, Dec 27, 2023 at 11:28:26PM +0100, Konrad Dybcio wrote:
>>> The PCIe GDSCs are only related to the RCs. The PCIe PHYs on the other
>>> hand, are powered by VDD_MX and their specific VDDA_PHY/PLL regulators.
>>
>> No, that does not seem to be entirely correct. I added the power-domains
>> here precisely because they were needed to enable the PHYs.
>>
>> This is something I stumbled over when trying to figure out how to
>> add support for the second lane pair (i.e. four-lane mode), and I just
>> went back and confirmed that this is still the case.
>>
>> If you try to enable one of these PHYs without the corresponding GDSC
>> being enabled, you end up with:
>>
>> [ 37.709324] ------------[ cut here ]------------
>> [ 37.718196] gcc_pcie_3b_aux_clk status stuck at 'off'
>> [ 37.718205] WARNING: CPU: 4 PID: 482 at drivers/clk/qcom/clk-branch.c:86 clk_branch_wait+0x144/0x15c
>>
>
> Technically this patch is correct. PHYs are backed by MX domain only and not
> GDSCs. Only the controllers (PCIe, UFS, USB) are backed by GDSCs. The fact that
> you are seeing issue with PCIe Aux clock suggests me that this clock may not be
> applicable to the PHY but it needs to be enabled for working of the PHY somehow.
> I'll try to find the details on how exactly it is needed.
>
> But if I get the answer like, "This clock is also sourced to PHY directly", then
> we may need to add dual power domain for PHY (both GDSC and MX).
>
>> Now, you may or may not want to describe the above in the devicetree,
>> but this makes it sound like you're trying to work around an issue with
>> the current Linux implementation.
I did a bit of experimentation, and.. I think that the PHY itself doesn't
need the GDSC to be enabled.
However.
The AUX clock requires the GDSC to be enabled and the PHY will fail to
power on if this clock is disabled.
That makes me wonder if representing the PCIe PHY as a wholly separate
device (instead of e.g. it being a subdev of PCIe RC) is even correct..
>>
>
> Adding MX domain to PHY in devicetree is definitely not a workaround. It is the
> actual hardware representation. MX is the always on domain, and when CX collapse
> happens during suspend state, it will ensure that all the analog components
> (like PHY) are kept powered on. Otherwise, we will see link down issues.
>
> But, I heard from Qcom that _only_ on this platform, MX is not backing the PCIe
> PHY. I can correlate that with my encounter with PCIe issues after forcing CX
> power collapse.
I've heard otherwise, the PHY itself is powered by MX, but CX needs
to be (should be?) enabled for communication with the RC (which itself
needs CX to be up to function).
Konrad
On 29.12.2023 18:14, Manivannan Sadhasivam wrote:
> On Wed, Dec 27, 2023 at 11:28:28PM +0100, Konrad Dybcio wrote:
>> The CLKREQ pin should not be muxed to its active function when the RC
>> is asleep. Add the missing pin sleep states to resolve that.
>>
>
> I don't understand why it should not be muxed and wondering what is the actual
> issue you are seeing that lead to this conclusion.
According to my knowledge, demuxing this pin prevents the RC from
getting (possibly erronous) reference clock request signals when
running the RC shutdown sequence. Reading this again, the fixes
tags don't really fit this commit.
What's perhaps more interesting is that on msm8996, Qualcomm vendor
kernels used to remove the pull-up on the CLKREQ pin in its sleep
state, while on msm8998 through sm8550 they keep it there, always..
Perhaps an oversight?
Konrad
On 29.12.2023 13:55, Johan Hovold wrote:
> On Wed, Dec 27, 2023 at 11:28:28PM +0100, Konrad Dybcio wrote:
>> The CLKREQ pin should not be muxed to its active function when the RC
>> is asleep.
>
> You forgot to explain *why* you think this is needed.
You're right, I was in a flurry of patchsending..
>
> Note that this is only appears to be done for one upstream Qualcomm SoC
> (msm8996) currently, and that, notably, there is no driver support for
> actually changing the pin state.
Please see my reply to Mani.
>
>> Add the missing pin sleep states to resolve that.
>
>> Fixes: d907fe5acbf1 ("arm64: dts: qcom: sc8280xp-crd: enable WiFi controller")
>> Fixes: 17e2ccaf65d1 ("arm64: dts: qcom: sc8280xp-crd: enable SDX55 modem")
>> Fixes: 6a1ec5eca73c ("arm64: dts: qcom: sc8280xp-crd: enable NVMe SSD")
>
> So not sure these Fixes tags are warranted either.
Agreed!
Konrad
On Fri, Dec 29, 2023 at 10:40:08PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Dec 29, 2023 at 02:01:06PM +0100, Johan Hovold wrote:
> > On Wed, Dec 27, 2023 at 11:28:27PM +0100, Konrad Dybcio wrote:
> > > The USB GDSCs are only related to the controllers.
> >
> > Are you sure?
>
> Yes, that's what I was told by UFS and PCIe teams and some of the internal
> documentation also confirms the same.
Ok, good. I'm not sure I did a corresponding test of powering on a USB
PHY without the corresponding USB GDSC enabled, so perhaps the issue I
noted only applies to PCIe.
Johan
On Fri, Dec 29, 2023 at 10:33:34PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Dec 29, 2023 at 12:24:55PM +0100, Johan Hovold wrote:
> > On Wed, Dec 27, 2023 at 11:28:26PM +0100, Konrad Dybcio wrote:
> > > The PCIe GDSCs are only related to the RCs. The PCIe PHYs on the other
> > > hand, are powered by VDD_MX and their specific VDDA_PHY/PLL regulators.
> >
> > No, that does not seem to be entirely correct. I added the power-domains
> > here precisely because they were needed to enable the PHYs.
> >
> > This is something I stumbled over when trying to figure out how to
> > add support for the second lane pair (i.e. four-lane mode), and I just
> > went back and confirmed that this is still the case.
> >
> > If you try to enable one of these PHYs without the corresponding GDSC
> > being enabled, you end up with:
> >
> > [ 37.709324] ------------[ cut here ]------------
> > [ 37.718196] gcc_pcie_3b_aux_clk status stuck at 'off'
> > [ 37.718205] WARNING: CPU: 4 PID: 482 at drivers/clk/qcom/clk-branch.c:86 clk_branch_wait+0x144/0x15c
> >
>
> Technically this patch is correct. PHYs are backed by MX domain only and not
> GDSCs. Only the controllers (PCIe, UFS, USB) are backed by GDSCs. The fact that
> you are seeing issue with PCIe Aux clock suggests me that this clock may not be
> applicable to the PHY but it needs to be enabled for working of the PHY somehow.
> I'll try to find the details on how exactly it is needed.
Sounds good, thanks.
> But if I get the answer like, "This clock is also sourced to PHY directly", then
> we may need to add dual power domain for PHY (both GDSC and MX).
Right.
> > Now, you may or may not want to describe the above in the devicetree,
> > but this makes it sound like you're trying to work around an issue with
> > the current Linux implementation.
> >
>
> Adding MX domain to PHY in devicetree is definitely not a workaround.
I was referring to the fact that the GDSC domain also appears to be
needed even if that may possible get in the way when trying to implement
suspend.
> It is the
> actual hardware representation. MX is the always on domain, and when CX collapse
> happens during suspend state, it will ensure that all the analog components
> (like PHY) are kept powered on. Otherwise, we will see link down issues.
But if it's an always-on domain as you say, it should not be shut down,
right? Perhaps you still want it described in DT for some other reason.
> But, I heard from Qcom that _only_ on this platform, MX is not backing the PCIe
> PHY. I can correlate that with my encounter with PCIe issues after forcing CX
> power collapse.
Ok, but that seems to imply that this patch is definitely *not* correct
(for sc8280xp)?
Johan
On Mon, Jan 22, 2024 at 10:55:28PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Dec 29, 2023 at 10:33:34PM +0530, Manivannan Sadhasivam wrote:
> > On Fri, Dec 29, 2023 at 12:24:55PM +0100, Johan Hovold wrote:
> > > On Wed, Dec 27, 2023 at 11:28:26PM +0100, Konrad Dybcio wrote:
> > > > The PCIe GDSCs are only related to the RCs. The PCIe PHYs on the other
> > > > hand, are powered by VDD_MX and their specific VDDA_PHY/PLL regulators.
> > >
> > > No, that does not seem to be entirely correct. I added the power-domains
> > > here precisely because they were needed to enable the PHYs.
> > >
> > > This is something I stumbled over when trying to figure out how to
> > > add support for the second lane pair (i.e. four-lane mode), and I just
> > > went back and confirmed that this is still the case.
> > >
> > > If you try to enable one of these PHYs without the corresponding GDSC
> > > being enabled, you end up with:
> > >
> > > [ 37.709324] ------------[ cut here ]------------
> > > [ 37.718196] gcc_pcie_3b_aux_clk status stuck at 'off'
> > > [ 37.718205] WARNING: CPU: 4 PID: 482 at drivers/clk/qcom/clk-branch.c:86 clk_branch_wait+0x144/0x15c
> > >
> >
> > Technically this patch is correct. PHYs are backed by MX domain only and not
> > GDSCs. Only the controllers (PCIe, UFS, USB) are backed by GDSCs. The fact that
> > you are seeing issue with PCIe Aux clock suggests me that this clock may not be
> > applicable to the PHY but it needs to be enabled for working of the PHY somehow.
> > I'll try to find the details on how exactly it is needed.
> >
> > But if I get the answer like, "This clock is also sourced to PHY directly", then
> > we may need to add dual power domain for PHY (both GDSC and MX).
> >
>
> So I answer I got from Qcom is that this clock is only applicable to the PCIe
> controller and not PHYs. On some platforms, there is a separate PCIE_PHY_AUX_CLK
> coming from GCC that is used during L1SS state. I think that caused confusion
> while adding PHY support for followup platforms and folks just used PCIE_AUX_CLK
> since they couldn't find the actual PCIE_PHY_AUX_CLK.
Thanks for sorting that out.
> I've prepared a series to fix this mess, but I want to know how you end up
> seeing the above "clk status stuck at off" issue. Is there an actual usecase for
> powering up PHY without controller or you just experimented with it?
As I mentioned, I ran into this when experimenting with how to enable
the "companion" PHY for four-lane support. There shouldn't be any use
case for it (apart from using it to determine that the current
description of the PHY resources is incomplete or incorrect).
Johan
On Fri, Dec 29, 2023 at 10:33:34PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Dec 29, 2023 at 12:24:55PM +0100, Johan Hovold wrote:
> > On Wed, Dec 27, 2023 at 11:28:26PM +0100, Konrad Dybcio wrote:
> > > The PCIe GDSCs are only related to the RCs. The PCIe PHYs on the other
> > > hand, are powered by VDD_MX and their specific VDDA_PHY/PLL regulators.
> >
> > No, that does not seem to be entirely correct. I added the power-domains
> > here precisely because they were needed to enable the PHYs.
> >
> > This is something I stumbled over when trying to figure out how to
> > add support for the second lane pair (i.e. four-lane mode), and I just
> > went back and confirmed that this is still the case.
> >
> > If you try to enable one of these PHYs without the corresponding GDSC
> > being enabled, you end up with:
> >
> > [ 37.709324] ------------[ cut here ]------------
> > [ 37.718196] gcc_pcie_3b_aux_clk status stuck at 'off'
> > [ 37.718205] WARNING: CPU: 4 PID: 482 at drivers/clk/qcom/clk-branch.c:86 clk_branch_wait+0x144/0x15c
> >
>
> Technically this patch is correct. PHYs are backed by MX domain only and not
> GDSCs. Only the controllers (PCIe, UFS, USB) are backed by GDSCs. The fact that
> you are seeing issue with PCIe Aux clock suggests me that this clock may not be
> applicable to the PHY but it needs to be enabled for working of the PHY somehow.
> I'll try to find the details on how exactly it is needed.
>
> But if I get the answer like, "This clock is also sourced to PHY directly", then
> we may need to add dual power domain for PHY (both GDSC and MX).
>
So I answer I got from Qcom is that this clock is only applicable to the PCIe
controller and not PHYs. On some platforms, there is a separate PCIE_PHY_AUX_CLK
coming from GCC that is used during L1SS state. I think that caused confusion
while adding PHY support for followup platforms and folks just used PCIE_AUX_CLK
since they couldn't find the actual PCIE_PHY_AUX_CLK.
I've prepared a series to fix this mess, but I want to know how you end up
seeing the above "clk status stuck at off" issue. Is there an actual usecase for
powering up PHY without controller or you just experimented with it?
- Mani
--
மணிவண்ணன் சதாசிவம்
On Mon, Jan 22, 2024 at 06:36:51PM +0100, Johan Hovold wrote:
> On Mon, Jan 22, 2024 at 10:55:28PM +0530, Manivannan Sadhasivam wrote:
> > On Fri, Dec 29, 2023 at 10:33:34PM +0530, Manivannan Sadhasivam wrote:
> > > On Fri, Dec 29, 2023 at 12:24:55PM +0100, Johan Hovold wrote:
> > > > On Wed, Dec 27, 2023 at 11:28:26PM +0100, Konrad Dybcio wrote:
> > > > > The PCIe GDSCs are only related to the RCs. The PCIe PHYs on the other
> > > > > hand, are powered by VDD_MX and their specific VDDA_PHY/PLL regulators.
> > > >
> > > > No, that does not seem to be entirely correct. I added the power-domains
> > > > here precisely because they were needed to enable the PHYs.
> > > >
> > > > This is something I stumbled over when trying to figure out how to
> > > > add support for the second lane pair (i.e. four-lane mode), and I just
> > > > went back and confirmed that this is still the case.
> > > >
> > > > If you try to enable one of these PHYs without the corresponding GDSC
> > > > being enabled, you end up with:
> > > >
> > > > [ 37.709324] ------------[ cut here ]------------
> > > > [ 37.718196] gcc_pcie_3b_aux_clk status stuck at 'off'
> > > > [ 37.718205] WARNING: CPU: 4 PID: 482 at drivers/clk/qcom/clk-branch.c:86 clk_branch_wait+0x144/0x15c
> > > >
> > >
> > > Technically this patch is correct. PHYs are backed by MX domain only and not
> > > GDSCs. Only the controllers (PCIe, UFS, USB) are backed by GDSCs. The fact that
> > > you are seeing issue with PCIe Aux clock suggests me that this clock may not be
> > > applicable to the PHY but it needs to be enabled for working of the PHY somehow.
> > > I'll try to find the details on how exactly it is needed.
> > >
> > > But if I get the answer like, "This clock is also sourced to PHY directly", then
> > > we may need to add dual power domain for PHY (both GDSC and MX).
> > >
> >
> > So I answer I got from Qcom is that this clock is only applicable to the PCIe
> > controller and not PHYs. On some platforms, there is a separate PCIE_PHY_AUX_CLK
> > coming from GCC that is used during L1SS state. I think that caused confusion
> > while adding PHY support for followup platforms and folks just used PCIE_AUX_CLK
> > since they couldn't find the actual PCIE_PHY_AUX_CLK.
>
> Thanks for sorting that out.
>
> > I've prepared a series to fix this mess, but I want to know how you end up
> > seeing the above "clk status stuck at off" issue. Is there an actual usecase for
> > powering up PHY without controller or you just experimented with it?
>
> As I mentioned, I ran into this when experimenting with how to enable
> the "companion" PHY for four-lane support. There shouldn't be any use
> case for it (apart from using it to determine that the current
> description of the PHY resources is incomplete or incorrect).
>
Ok. I tested by enabling the PHY clocks during qmp_pcie_clk_init() without
PCIE_GDSC. It worked for one instance of the PHY which doesn't have
PCIE_PHY_AUX_CLK, but for the PHY instance with this clock, I saw the same "clk
stuck" issue. Then checking the internal documentation revealed that this clock
needs PCIE_GDSC to become functional >.<
So to conclude, PCIE_AUX_CLK belongs to the controller and it needs GDSC. And
PCIE_PHY_AUX_CLK belongs to the PHY and it also needs GDSC.
I will just submit a series to remove the PCIE_AUX_CLK from PHY nodes. Then
in another series, I'll remove the GDSC for PHY instances that do not require
PCIE_PHY_AUX_CLK.
Hope this makes sense.
- Mani
--
மணிவண்ணன் சதாசிவம்
On 1/23/24 18:06, Manivannan Sadhasivam wrote:
> On Mon, Jan 22, 2024 at 06:36:51PM +0100, Johan Hovold wrote:
>> On Mon, Jan 22, 2024 at 10:55:28PM +0530, Manivannan Sadhasivam wrote:
>>> On Fri, Dec 29, 2023 at 10:33:34PM +0530, Manivannan Sadhasivam wrote:
>>>> On Fri, Dec 29, 2023 at 12:24:55PM +0100, Johan Hovold wrote:
>>>>> On Wed, Dec 27, 2023 at 11:28:26PM +0100, Konrad Dybcio wrote:
>>>>>> The PCIe GDSCs are only related to the RCs. The PCIe PHYs on the other
>>>>>> hand, are powered by VDD_MX and their specific VDDA_PHY/PLL regulators.
>>>>>
>>>>> No, that does not seem to be entirely correct. I added the power-domains
>>>>> here precisely because they were needed to enable the PHYs.
>>>>>
>>>>> This is something I stumbled over when trying to figure out how to
>>>>> add support for the second lane pair (i.e. four-lane mode), and I just
>>>>> went back and confirmed that this is still the case.
>>>>>
>>>>> If you try to enable one of these PHYs without the corresponding GDSC
>>>>> being enabled, you end up with:
>>>>>
>>>>> [ 37.709324] ------------[ cut here ]------------
>>>>> [ 37.718196] gcc_pcie_3b_aux_clk status stuck at 'off'
>>>>> [ 37.718205] WARNING: CPU: 4 PID: 482 at drivers/clk/qcom/clk-branch.c:86 clk_branch_wait+0x144/0x15c
>>>>>
>>>>
>>>> Technically this patch is correct. PHYs are backed by MX domain only and not
>>>> GDSCs. Only the controllers (PCIe, UFS, USB) are backed by GDSCs. The fact that
>>>> you are seeing issue with PCIe Aux clock suggests me that this clock may not be
>>>> applicable to the PHY but it needs to be enabled for working of the PHY somehow.
>>>> I'll try to find the details on how exactly it is needed.
>>>>
>>>> But if I get the answer like, "This clock is also sourced to PHY directly", then
>>>> we may need to add dual power domain for PHY (both GDSC and MX).
>>>>
>>>
>>> So I answer I got from Qcom is that this clock is only applicable to the PCIe
>>> controller and not PHYs. On some platforms, there is a separate PCIE_PHY_AUX_CLK
>>> coming from GCC that is used during L1SS state. I think that caused confusion
>>> while adding PHY support for followup platforms and folks just used PCIE_AUX_CLK
>>> since they couldn't find the actual PCIE_PHY_AUX_CLK.
>>
>> Thanks for sorting that out.
>>
>>> I've prepared a series to fix this mess, but I want to know how you end up
>>> seeing the above "clk status stuck at off" issue. Is there an actual usecase for
>>> powering up PHY without controller or you just experimented with it?
>>
>> As I mentioned, I ran into this when experimenting with how to enable
>> the "companion" PHY for four-lane support. There shouldn't be any use
>> case for it (apart from using it to determine that the current
>> description of the PHY resources is incomplete or incorrect).
>>
>
> Ok. I tested by enabling the PHY clocks during qmp_pcie_clk_init() without
> PCIE_GDSC. It worked for one instance of the PHY which doesn't have
> PCIE_PHY_AUX_CLK, but for the PHY instance with this clock, I saw the same "clk
> stuck" issue. Then checking the internal documentation revealed that this clock
> needs PCIE_GDSC to become functional >.<
>
> So to conclude, PCIE_AUX_CLK belongs to the controller and it needs GDSC. And
> PCIE_PHY_AUX_CLK belongs to the PHY and it also needs GDSC.
>
> I will just submit a series to remove the PCIE_AUX_CLK from PHY nodes. Then
> in another series, I'll remove the GDSC for PHY instances that do not require
> PCIE_PHY_AUX_CLK.
>
> Hope this makes sense.
Thanks, Mani
Konrad
On Tue, Jan 23, 2024 at 10:36:14PM +0530, Manivannan Sadhasivam wrote:
> On Mon, Jan 22, 2024 at 06:36:51PM +0100, Johan Hovold wrote:
> Ok. I tested by enabling the PHY clocks during qmp_pcie_clk_init() without
> PCIE_GDSC. It worked for one instance of the PHY which doesn't have
> PCIE_PHY_AUX_CLK, but for the PHY instance with this clock, I saw the same "clk
> stuck" issue. Then checking the internal documentation revealed that this clock
> needs PCIE_GDSC to become functional >.<
>
> So to conclude, PCIE_AUX_CLK belongs to the controller and it needs GDSC. And
> PCIE_PHY_AUX_CLK belongs to the PHY and it also needs GDSC.
>
> I will just submit a series to remove the PCIE_AUX_CLK from PHY nodes. Then
> in another series, I'll remove the GDSC for PHY instances that do not require
> PCIE_PHY_AUX_CLK.
Sounds good, thanks.
Johan