Hello,
This series enables D3 support for PCI bridges found in Qcom SoCs. Currently,
PCI core will enable D3 support for PCI bridges only when the following
conditions are met:
1. Platform is ACPI based
2. Thunderbolt controller is used
3. pcie_port_pm=force passed in cmdline
While options 1 and 2 do not apply to Qcom SoCs, option 3 will make the life
harder for distro maintainers. Due to this, runtime PM is also not getting
enabled for the bridges.
Ideally, D3 support should be enabled by default for the recent PCI bridges,
but we do not have a sane way to detect them. So this series adds a new flag
"bridge_d3_capable" to "struct pci_dev" which could be set by the bridge drivers
for capable devices. This will allow the PCI core to enable D3 support for the
bridges during enumeration.
In the Qcom controller driver, this flag is only set for recent bridges with PID
(0x0110).
Testing
=======
This series is tested on SM8450 based development board.
- Mani
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
---
Manivannan Sadhasivam (2):
PCI: Add a flag to enable D3 support for PCI bridges
PCI: qcom: Enable D3 support for the recent PCI bridges
drivers/pci/controller/dwc/pcie-qcom.c | 6 ++++++
drivers/pci/pci.c | 3 +++
include/linux/pci.h | 1 +
3 files changed, 10 insertions(+)
---
base-commit: 6613476e225e090cc9aad49be7fa504e290dd33d
change-id: 20240131-pcie-qcom-bridge-b6802a9770a3
Best regards,
--
Manivannan Sadhasivam <[email protected]>
On Fri, Feb 02, 2024 at 12:24:16PM +0530, Manivannan Sadhasivam wrote:
> This series enables D3 support for PCI bridges found in Qcom SoCs. Currently,
> PCI core will enable D3 support for PCI bridges only when the following
> conditions are met:
>
> 1. Platform is ACPI based
> 2. Thunderbolt controller is used
> 3. pcie_port_pm=force passed in cmdline
>
> While options 1 and 2 do not apply to Qcom SoCs, option 3 will make the life
> harder for distro maintainers. Due to this, runtime PM is also not getting
> enabled for the bridges.
>
> Ideally, D3 support should be enabled by default for the recent PCI bridges,
> but we do not have a sane way to detect them. So this series adds a new flag
> "bridge_d3_capable" to "struct pci_dev" which could be set by the bridge
> drivers for capable devices. This will allow the PCI core to enable D3
> support for the bridges during enumeration.
I think the right way to do this is to use the existing call to
platform_pci_bridge_d3() in pci_bridge_d3_possible().
Please amend platform_pci_bridge_d3() to call a new of_pci_bridge_d3()
function which determines whether D3 is supported by the platform.
E.g. of_pci_bridge_d3() could contain a whitelist of supported VID/DID
tuples. Or it could be defined as a __weak function which always
returns false but can be overridden at link time by a function
defined somewhere in arch/arm/, arch/arm64/ or in some driver
whose Kconfig option is enabled in Qualcomm platforms.
Adding a bit to struct pci_dev essentially duplicates the existing
platform_pci_bridge_d3() functionality, which seems inelegant.
It increases the size of struct pci_dev even on platforms which
don't need it (e.g. ACPI).
Thanks,
Lukas
On Fri, Feb 02, 2024 at 10:00:33AM +0100, Lukas Wunner wrote:
> On Fri, Feb 02, 2024 at 12:24:16PM +0530, Manivannan Sadhasivam wrote:
> > This series enables D3 support for PCI bridges found in Qcom SoCs. Currently,
> > PCI core will enable D3 support for PCI bridges only when the following
> > conditions are met:
> >
> > 1. Platform is ACPI based
> > 2. Thunderbolt controller is used
> > 3. pcie_port_pm=force passed in cmdline
> >
> > While options 1 and 2 do not apply to Qcom SoCs, option 3 will make the life
> > harder for distro maintainers. Due to this, runtime PM is also not getting
> > enabled for the bridges.
> >
> > Ideally, D3 support should be enabled by default for the recent PCI bridges,
> > but we do not have a sane way to detect them. So this series adds a new flag
> > "bridge_d3_capable" to "struct pci_dev" which could be set by the bridge
> > drivers for capable devices. This will allow the PCI core to enable D3
> > support for the bridges during enumeration.
>
> I think the right way to do this is to use the existing call to
> platform_pci_bridge_d3() in pci_bridge_d3_possible().
>
> Please amend platform_pci_bridge_d3() to call a new of_pci_bridge_d3()
> function which determines whether D3 is supported by the platform.
>
> E.g. of_pci_bridge_d3() could contain a whitelist of supported VID/DID
> tuples. Or it could be defined as a __weak function which always
> returns false but can be overridden at link time by a function
> defined somewhere in arch/arm/, arch/arm64/ or in some driver
> whose Kconfig option is enabled in Qualcomm platforms.
>
Hmm. If we go with a DT based solution, then introducing a new property like
"d3-support" in the PCI bridge node would be the right approach. But then, it
also requires defining the PCI bridge node in all the DTs. But that should be
fine since it will help us to support WAKE# (per bridge) in the future.
Thanks for the review.
- Mani
--
மணிவண்ணன் சதாசிவம்
On Fri, Feb 02, 2024 at 03:30:41PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Feb 02, 2024 at 10:00:33AM +0100, Lukas Wunner wrote:
> > Please amend platform_pci_bridge_d3() to call a new of_pci_bridge_d3()
> > function which determines whether D3 is supported by the platform.
> >
> > E.g. of_pci_bridge_d3() could contain a whitelist of supported VID/DID
> > tuples. Or it could be defined as a __weak function which always
> > returns false but can be overridden at link time by a function
> > defined somewhere in arch/arm/, arch/arm64/ or in some driver
> > whose Kconfig option is enabled in Qualcomm platforms.
>
> Hmm. If we go with a DT based solution, then introducing a new property like
> "d3-support" in the PCI bridge node would be the right approach. But then, it
> also requires defining the PCI bridge node in all the DTs. But that should be
> fine since it will help us to support WAKE# (per bridge) in the future.
I'm not sure whether a "d3-support" property would be acceptable.
My understanding is that capabilities which can be auto-sensed by
the driver (or the PCI core in this case), e.g. by looking at the
PCI IDs or compatible string, should not be described in the DT.
My point was really that this should be determined by
platform_pci_bridge_d3(), that's what the function is for,
instead of inventing a new mechanism. Exactly how the capability
is detected by of_pci_bridge_d3() is up to DT schema maintainers.
A DT property does have the advantage of better maintainability,
unlike a whitelist which may need to constantly be extended.
Thanks,
Lukas
On Fri, Feb 02, 2024 at 08:33:26PM +0100, Lukas Wunner wrote:
> On Fri, Feb 02, 2024 at 03:30:41PM +0530, Manivannan Sadhasivam wrote:
> > On Fri, Feb 02, 2024 at 10:00:33AM +0100, Lukas Wunner wrote:
> > > Please amend platform_pci_bridge_d3() to call a new of_pci_bridge_d3()
> > > function which determines whether D3 is supported by the platform.
> > >
> > > E.g. of_pci_bridge_d3() could contain a whitelist of supported VID/DID
> > > tuples. Or it could be defined as a __weak function which always
> > > returns false but can be overridden at link time by a function
> > > defined somewhere in arch/arm/, arch/arm64/ or in some driver
> > > whose Kconfig option is enabled in Qualcomm platforms.
> >
> > Hmm. If we go with a DT based solution, then introducing a new property like
> > "d3-support" in the PCI bridge node would be the right approach. But then, it
> > also requires defining the PCI bridge node in all the DTs. But that should be
> > fine since it will help us to support WAKE# (per bridge) in the future.
>
> I'm not sure whether a "d3-support" property would be acceptable.
> My understanding is that capabilities which can be auto-sensed by
> the driver (or the PCI core in this case), e.g. by looking at the
> PCI IDs or compatible string, should not be described in the DT.
>
We cannot whitelist platforms in DT. DT should describe the hardware and its
capabilities. In this case, the "supports-d3" property as I proposed [1] tells
the OS that this bridge is capable of supporting D3.
Blacklisting/whitelisting belongs to the OS. We can however, whitelist the
bridges in PCI core. But that has the downside of not being useful to other OSes
supporting DT. Hence, a DT property that describes the hardware capability
makes sense to me.
- Mani
[1] https://github.com/devicetree-org/dt-schema/pull/127
--
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