Hi All,
This patch series introduces the Andes PMU extension, which serves the
same purpose as Sscofpmf and Smcntrpmf. Its non-standard local interrupt
is assigned to bit 18 in the custom S-mode local interrupt enable and
pending registers (slie/slip), while the interrupt cause is (256 + 18).
The series can be found on Andes Technology GitHub:
- https://github.com/andestech/linux/commits/andes-pmu-support-v9
The PMU device tree node used on AX45MP:
- https://github.com/riscv-software-src/opensbi/blob/master/docs/pmu_support.md#example-3
Locus Wei-Han Chen (1):
riscv: andes: Support specifying symbolic firmware and hardware raw
events
Yu Chien Peter Lin (9):
riscv: errata: Rename defines for Andes
irqchip/riscv-intc: Allow large non-standard interrupt number
irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
dt-bindings: riscv: Add Andes interrupt controller compatible string
riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes
INTC
perf: RISC-V: Eliminate redundant interrupt enable/disable operations
perf: RISC-V: Introduce Andes PMU to support perf event sampling
dt-bindings: riscv: Add Andes PMU extension description
riscv: dts: renesas: Add Andes PMU extension for r9a07g043f
.../devicetree/bindings/riscv/cpus.yaml | 6 +-
.../devicetree/bindings/riscv/extensions.yaml | 7 +
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 +-
arch/riscv/errata/andes/errata.c | 10 +-
arch/riscv/include/asm/errata_list.h | 13 +-
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/include/asm/vendorid_list.h | 2 +-
arch/riscv/kernel/alternative.c | 2 +-
arch/riscv/kernel/cpufeature.c | 1 +
drivers/irqchip/irq-riscv-intc.c | 82 +++++++++--
drivers/perf/Kconfig | 14 ++
drivers/perf/riscv_pmu_sbi.c | 37 ++++-
include/linux/soc/andes/irq.h | 18 +++
.../arch/riscv/andes/ax45/firmware.json | 68 ++++++++++
.../arch/riscv/andes/ax45/instructions.json | 127 ++++++++++++++++++
.../arch/riscv/andes/ax45/memory.json | 57 ++++++++
.../arch/riscv/andes/ax45/microarch.json | 77 +++++++++++
tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 +
18 files changed, 488 insertions(+), 39 deletions(-)
create mode 100644 include/linux/soc/andes/irq.h
create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json
create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json
create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json
create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json
--
2.34.1
Add support for the Andes hart-level interrupt controller. This
controller provides interrupt mask/unmask functions to access the
custom register (SLIE) where the non-standard S-mode local interrupt
enable bits are located. The base of custom interrupt number is set
to 256.
To share the riscv_intc_domain_map() with the generic RISC-V INTC and
ACPI, add a chip parameter to riscv_intc_init_common(), so it can be
passed to the irq_domain_set_info() as a private data.
Andes hart-level interrupt controller requires the "andestech,cpu-intc"
compatible string to be present in interrupt-controller of cpu node to
enable the use of custom local interrupt source.
e.g.,
cpu0: cpu@0 {
compatible = "andestech,ax45mp", "riscv";
...
cpu0-intc: interrupt-controller {
#interrupt-cells = <0x01>;
compatible = "andestech,cpu-intc", "riscv,cpu-intc";
interrupt-controller;
};
};
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Randolph <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
---
Changes v1 -> v2:
- New patch
Changes v2 -> v3:
- Return -ENXIO if no valid compatible INTC found
- Allow falling back to generic RISC-V INTC
Changes v3 -> v4: (Suggested by Thomas [1])
- Add comment to andes irq chip function
- Refine code flow to share with generic RISC-V INTC and ACPI
- Move Andes specific definitions to include/linux/soc/andes/irq.h
Changes v4 -> v5: (Suggested by Thomas)
- Fix commit message
- Subtract ANDES_SLI_CAUSE_BASE from d->hwirq to calculate the value of mask
- Do not set chip_data to the chip itself with irq_domain_set_info()
- Follow reverse fir tree order variable declarations
Changes v5 -> v6:
- To follow the naming on datasheet, rename ANDES_RV_IRQ_PMU to ANDES_RV_IRQ_PMOVI
- Initialize the riscv_intc_* global variables for Andes INTC (Suggested by Anup)
- Use BITS_PER_LONG to compute the bit mask of SIE/SLIE as they are 64-bit registers (32-bit for RV32)
Changes v6 -> v7:
- No change
Changes v7 -> v8:
- Include Reviewed-by tags from Anup
Changes v8 -> v9:
- No functional change
[1] https://patchwork.kernel.org/project/linux-riscv/patch/[email protected]/
---
drivers/irqchip/irq-riscv-intc.c | 58 ++++++++++++++++++++++++++++----
include/linux/soc/andes/irq.h | 18 ++++++++++
2 files changed, 69 insertions(+), 7 deletions(-)
create mode 100644 include/linux/soc/andes/irq.h
diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index 684875c39728..0cd6b48a5dbf 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -17,6 +17,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/smp.h>
+#include <linux/soc/andes/irq.h>
static struct irq_domain *intc_domain;
static unsigned int riscv_intc_nr_irqs __ro_after_init = BITS_PER_LONG;
@@ -48,6 +49,31 @@ static void riscv_intc_irq_unmask(struct irq_data *d)
csr_set(CSR_IE, BIT(d->hwirq));
}
+static void andes_intc_irq_mask(struct irq_data *d)
+{
+ /*
+ * Andes specific S-mode local interrupt causes (hwirq)
+ * are defined as (256 + n) and controlled by n-th bit
+ * of SLIE.
+ */
+ unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);
+
+ if (d->hwirq < ANDES_SLI_CAUSE_BASE)
+ csr_clear(CSR_IE, mask);
+ else
+ csr_clear(ANDES_CSR_SLIE, mask);
+}
+
+static void andes_intc_irq_unmask(struct irq_data *d)
+{
+ unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);
+
+ if (d->hwirq < ANDES_SLI_CAUSE_BASE)
+ csr_set(CSR_IE, mask);
+ else
+ csr_set(ANDES_CSR_SLIE, mask);
+}
+
static void riscv_intc_irq_eoi(struct irq_data *d)
{
/*
@@ -71,12 +97,21 @@ static struct irq_chip riscv_intc_chip = {
.irq_eoi = riscv_intc_irq_eoi,
};
+static struct irq_chip andes_intc_chip = {
+ .name = "RISC-V INTC",
+ .irq_mask = andes_intc_irq_mask,
+ .irq_unmask = andes_intc_irq_unmask,
+ .irq_eoi = riscv_intc_irq_eoi,
+};
+
static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hwirq)
{
+ struct irq_chip *chip = d->host_data;
+
irq_set_percpu_devid(irq);
- irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data,
- handle_percpu_devid_irq, NULL, NULL);
+ irq_domain_set_info(d, irq, hwirq, chip, NULL, handle_percpu_devid_irq,
+ NULL, NULL);
return 0;
}
@@ -122,11 +157,12 @@ static struct fwnode_handle *riscv_intc_hwnode(void)
return intc_domain->fwnode;
}
-static int __init riscv_intc_init_common(struct fwnode_handle *fn)
+static int __init riscv_intc_init_common(struct fwnode_handle *fn,
+ struct irq_chip *chip)
{
int rc;
- intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL);
+ intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, chip);
if (!intc_domain) {
pr_err("unable to add IRQ domain\n");
return -ENXIO;
@@ -152,8 +188,9 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
static int __init riscv_intc_init(struct device_node *node,
struct device_node *parent)
{
- int rc;
+ struct irq_chip *chip = &riscv_intc_chip;
unsigned long hartid;
+ int rc;
rc = riscv_of_parent_hartid(node, &hartid);
if (rc < 0) {
@@ -178,10 +215,17 @@ static int __init riscv_intc_init(struct device_node *node,
return 0;
}
- return riscv_intc_init_common(of_node_to_fwnode(node));
+ if (of_device_is_compatible(node, "andestech,cpu-intc")) {
+ riscv_intc_custom_base = ANDES_SLI_CAUSE_BASE;
+ riscv_intc_custom_nr_irqs = ANDES_RV_IRQ_LAST;
+ chip = &andes_intc_chip;
+ }
+
+ return riscv_intc_init_common(of_node_to_fwnode(node), chip);
}
IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);
+IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_intc_init);
#ifdef CONFIG_ACPI
@@ -208,7 +252,7 @@ static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header,
return -ENOMEM;
}
- return riscv_intc_init_common(fn);
+ return riscv_intc_init_common(fn, &riscv_intc_chip);
}
IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL,
diff --git a/include/linux/soc/andes/irq.h b/include/linux/soc/andes/irq.h
new file mode 100644
index 000000000000..edc3182d6e66
--- /dev/null
+++ b/include/linux/soc/andes/irq.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2023 Andes Technology Corporation
+ */
+#ifndef __ANDES_IRQ_H
+#define __ANDES_IRQ_H
+
+/* Andes PMU irq number */
+#define ANDES_RV_IRQ_PMOVI 18
+#define ANDES_RV_IRQ_LAST ANDES_RV_IRQ_PMOVI
+#define ANDES_SLI_CAUSE_BASE 256
+
+/* Andes PMU related registers */
+#define ANDES_CSR_SLIE 0x9c4
+#define ANDES_CSR_SLIP 0x9c5
+#define ANDES_CSR_SCOUNTEROF 0x9d4
+
+#endif /* __ANDES_IRQ_H */
--
2.34.1
Currently, the implementation of the RISC-V INTC driver uses the
interrupt cause as the hardware interrupt number, with a maximum of
64 interrupts. However, the platform can expand the interrupt number
further for custom local interrupts.
To fully utilize the available local interrupt sources, switch
to using irq_domain_create_tree() that creates the radix tree
map, add global variables (riscv_intc_nr_irqs, riscv_intc_custom_base
and riscv_intc_custom_nr_irqs) to determine the valid range of local
interrupt number (hwirq).
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Randolph <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
---
Changes v1 -> v2:
- Fixed irq mapping failure checking (suggested by Clément and Anup)
Changes v2 -> v3:
- No change
Changes v3 -> v4: (Suggested by Thomas [1])
- Use pr_warn_ratelimited instead
- Fix coding style and commit message
Changes v4 -> v5: (Suggested by Thomas)
- Fix commit message
Changes v5 -> v6: (Suggested by Anup [2])
- Add riscv_intc_* global variables for checking the range of valid
interrupt number in riscv_intc_domain_alloc()
- Advertise the number of interrupts allowed
Changes v6 -> v7:
- No functional change
Changes v7 -> v8:
- Include Reviewed-by tags from Anup and Atish
Changes v8 -> v9 (Suggested by Thomas [3]):
- Fix coding style
- Update hwirq range checks
- Update riscv_intc_* global variables initialization
[1] https://patchwork.kernel.org/project/linux-riscv/patch/[email protected]/#25573085
[2] https://patchwork.kernel.org/project/linux-riscv/patch/[email protected]/#25636589
[3] https://patchwork.kernel.org/project/linux-riscv/patch/[email protected]/#25710584
---
drivers/irqchip/irq-riscv-intc.c | 26 +++++++++++++++++++-------
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index e8d01b14ccdd..684875c39728 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -19,15 +19,16 @@
#include <linux/smp.h>
static struct irq_domain *intc_domain;
+static unsigned int riscv_intc_nr_irqs __ro_after_init = BITS_PER_LONG;
+static unsigned int riscv_intc_custom_base __ro_after_init = BITS_PER_LONG;
+static unsigned int riscv_intc_custom_nr_irqs __ro_after_init;
static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
{
unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;
- if (unlikely(cause >= BITS_PER_LONG))
- panic("unexpected interrupt cause");
-
- generic_handle_domain_irq(intc_domain, cause);
+ if (generic_handle_domain_irq(intc_domain, cause))
+ pr_warn_ratelimited("Failed to handle interrupt (cause: %ld)\n", cause);
}
/*
@@ -93,6 +94,14 @@ static int riscv_intc_domain_alloc(struct irq_domain *domain,
if (ret)
return ret;
+ /*
+ * Only allow hwirq for which we have corresponding standard or
+ * custom interrupt enable register.
+ */
+ if ((hwirq >= riscv_intc_nr_irqs && hwirq < riscv_intc_custom_base) ||
+ (hwirq >= riscv_intc_custom_base + riscv_intc_custom_nr_irqs))
+ return -EINVAL;
+
for (i = 0; i < nr_irqs; i++) {
ret = riscv_intc_domain_map(domain, virq + i, hwirq + i);
if (ret)
@@ -117,8 +126,7 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
{
int rc;
- intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG,
- &riscv_intc_domain_ops, NULL);
+ intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL);
if (!intc_domain) {
pr_err("unable to add IRQ domain\n");
return -ENXIO;
@@ -132,7 +140,11 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn)
riscv_set_intc_hwnode_fn(riscv_intc_hwnode);
- pr_info("%d local interrupts mapped\n", BITS_PER_LONG);
+ pr_info("%d local interrupts mapped\n", riscv_intc_nr_irqs);
+ if (riscv_intc_custom_nr_irqs) {
+ pr_info("%d custom local interrupts mapped\n",
+ riscv_intc_custom_nr_irqs);
+ }
return 0;
}
--
2.34.1
The interrupt enable/disable operations are already performed by the
IRQ chip functions riscv_intc_irq_unmask()/riscv_intc_irq_mask() during
enable_percpu_irq()/disable_percpu_irq(). It can be done only once.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Atish Patra <[email protected]>
---
This patch allows us to drop unnecessary ALT_SBI_PMU_OVF_{DISABLE,ENABLE}
in the initial PATCH3 [1].
[1] https://patchwork.kernel.org/project/linux-riscv/patch/[email protected]/
Changes v1 -> v2:
- New patch
Changes v2 -> v3:
- No change
Changes v3 -> v4:
- No change
Changes v4 -> v5:
- No change
Changes v5 -> v6:
- No change
Changes v6 -> v7:
- No change
Changes v7 -> v8:
- Include Reviewed-by tags from Atish
Changes v8 -> v9:
- No change
---
drivers/perf/riscv_pmu_sbi.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 16acd4dcdb96..2edbc37abadf 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -781,7 +781,6 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node)
if (riscv_pmu_use_irq) {
cpu_hw_evt->irq = riscv_pmu_irq;
csr_clear(CSR_IP, BIT(riscv_pmu_irq_num));
- csr_set(CSR_IE, BIT(riscv_pmu_irq_num));
enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE);
}
@@ -792,7 +791,6 @@ static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node)
{
if (riscv_pmu_use_irq) {
disable_percpu_irq(riscv_pmu_irq);
- csr_clear(CSR_IE, BIT(riscv_pmu_irq_num));
}
/* Disable all counters access for user mode now */
--
2.34.1
Add "andestech,cpu-intc" compatible string to indicate that
Andes specific local interrupt is supported on the core,
e.g. AX45MP cores have 3 types of non-standard local interrupt
which can be handled in supervisor mode:
- Slave port ECC error interrupt
- Bus write transaction error interrupt
- Performance monitor overflow interrupt
These interrupts are enabled/disabled via a custom register
SLIE instead of the standard interrupt enable register SIE.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
---
Changes v1 -> v2:
- New patch
Changes v2 -> v3:
- Updated commit message
- Fixed possible compatibles for Andes INTC
Changes v3 -> v4:
- Add const entry instead of enum (Suggested by Conor)
Changes v4 -> v5:
- Include Conor's Acked-by
- Include Prabhakar's Reviewed-by
Changes v5 -> v6:
- No change
Changes v6 -> v7:
- No change
Changes v7 -> v8:
- No change
Changes v8 -> v9:
- No change
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 9d8670c00e3b..6ccd75cbbc59 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -106,7 +106,11 @@ properties:
const: 1
compatible:
- const: riscv,cpu-intc
+ oneOf:
+ - items:
+ - const: andestech,cpu-intc
+ - const: riscv,cpu-intc
+ - const: riscv,cpu-intc
interrupt-controller: true
--
2.34.1
Use "ANDES" rather than "ANDESTECH" to unify the naming
convention with directory, file names, Kconfig options
and other definitions.
Signed-off-by: Yu Chien Peter Lin <[email protected]>
Reviewed-by: Charles Ci-Jyun Wu <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
---
Changes v1 -> v2:
- No change
Changes v2 -> v3:
- Rewrite commit message (suggested by Conor)
Changes v3 -> v4:
- Include Conor's Acked-by tag
Changes v4 -> v5:
- Include Prabhakar's RB tag
Changes v5 -> v6:
- No change
Changes v6 -> v7:
- No change
Changes v7 -> v8:
- No change
Changes v8 -> v9:
- No change
---
arch/riscv/errata/andes/errata.c | 10 +++++-----
arch/riscv/include/asm/errata_list.h | 4 ++--
arch/riscv/include/asm/vendorid_list.h | 2 +-
arch/riscv/kernel/alternative.c | 2 +-
4 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/riscv/errata/andes/errata.c b/arch/riscv/errata/andes/errata.c
index 17a904869724..f2708a9494a1 100644
--- a/arch/riscv/errata/andes/errata.c
+++ b/arch/riscv/errata/andes/errata.c
@@ -18,9 +18,9 @@
#include <asm/sbi.h>
#include <asm/vendorid_list.h>
-#define ANDESTECH_AX45MP_MARCHID 0x8000000000008a45UL
-#define ANDESTECH_AX45MP_MIMPID 0x500UL
-#define ANDESTECH_SBI_EXT_ANDES 0x0900031E
+#define ANDES_AX45MP_MARCHID 0x8000000000008a45UL
+#define ANDES_AX45MP_MIMPID 0x500UL
+#define ANDES_SBI_EXT_ANDES 0x0900031E
#define ANDES_SBI_EXT_IOCP_SW_WORKAROUND 1
@@ -32,7 +32,7 @@ static long ax45mp_iocp_sw_workaround(void)
* ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT checks if the IOCP is missing and
* cache is controllable only then CMO will be applied to the platform.
*/
- ret = sbi_ecall(ANDESTECH_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
+ ret = sbi_ecall(ANDES_SBI_EXT_ANDES, ANDES_SBI_EXT_IOCP_SW_WORKAROUND,
0, 0, 0, 0, 0, 0);
return ret.error ? 0 : ret.value;
@@ -50,7 +50,7 @@ static void errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigne
done = true;
- if (arch_id != ANDESTECH_AX45MP_MARCHID || impid != ANDESTECH_AX45MP_MIMPID)
+ if (arch_id != ANDES_AX45MP_MARCHID || impid != ANDES_AX45MP_MIMPID)
return;
if (!ax45mp_iocp_sw_workaround())
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index ea33288f8a25..96025eec5631 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -12,8 +12,8 @@
#include <asm/vendorid_list.h>
#ifdef CONFIG_ERRATA_ANDES
-#define ERRATA_ANDESTECH_NO_IOCP 0
-#define ERRATA_ANDESTECH_NUMBER 1
+#define ERRATA_ANDES_NO_IOCP 0
+#define ERRATA_ANDES_NUMBER 1
#endif
#ifdef CONFIG_ERRATA_SIFIVE
diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
index e55407ace0c3..2f2bb0c84f9a 100644
--- a/arch/riscv/include/asm/vendorid_list.h
+++ b/arch/riscv/include/asm/vendorid_list.h
@@ -5,7 +5,7 @@
#ifndef ASM_VENDOR_LIST_H
#define ASM_VENDOR_LIST_H
-#define ANDESTECH_VENDOR_ID 0x31e
+#define ANDES_VENDOR_ID 0x31e
#define SIFIVE_VENDOR_ID 0x489
#define THEAD_VENDOR_ID 0x5b7
diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
index 319a1da0358b..0128b161bfda 100644
--- a/arch/riscv/kernel/alternative.c
+++ b/arch/riscv/kernel/alternative.c
@@ -43,7 +43,7 @@ static void riscv_fill_cpu_mfr_info(struct cpu_manufacturer_info_t *cpu_mfr_info
switch (cpu_mfr_info->vendor_id) {
#ifdef CONFIG_ERRATA_ANDES
- case ANDESTECH_VENDOR_ID:
+ case ANDES_VENDOR_ID:
cpu_mfr_info->patch_func = andes_errata_patch_func;
break;
#endif
--
2.34.1
On Tue, Mar 12 2024 at 07:23, Palmer Dabbelt wrote:
> On Fri, 23 Feb 2024 01:06:44 PST (-0800), [email protected] wrote:
>> Contains:
>>
>> f4cc33e78ba8 ("irqchip/riscv-intc: Introduce Andes hart-level interrupt controller")
>> 96303bcb401c ("irqchip/riscv-intc: Allow large non-standard interrupt number")
>>
>> on top of v6.8-rc1
>
> Sorry I missed this. I just merged this into my testing tree, it might
> take a bit to show up because I've managed to break my VPN so I can't
> poke the tester box right now...
Alternatively you can just rebase on Linus tree. The interrupt changes
are already merged.
Hello:
This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <[email protected]>:
On Thu, 22 Feb 2024 16:39:36 +0800 you wrote:
> Hi All,
>
> This patch series introduces the Andes PMU extension, which serves the
> same purpose as Sscofpmf and Smcntrpmf. Its non-standard local interrupt
> is assigned to bit 18 in the custom S-mode local interrupt enable and
> pending registers (slie/slip), while the interrupt cause is (256 + 18).
>
> [...]
Here is the summary with links:
- [v9,01/10] riscv: errata: Rename defines for Andes
https://git.kernel.org/riscv/c/be5e8872b3fb
- [v9,02/10] irqchip/riscv-intc: Allow large non-standard interrupt number
https://git.kernel.org/riscv/c/96303bcb401c
- [v9,03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
https://git.kernel.org/riscv/c/f4cc33e78ba8
- [v9,04/10] dt-bindings: riscv: Add Andes interrupt controller compatible string
https://git.kernel.org/riscv/c/b88727d554f0
- [v9,05/10] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC
https://git.kernel.org/riscv/c/95113bb70515
- [v9,06/10] perf: RISC-V: Eliminate redundant interrupt enable/disable operations
https://git.kernel.org/riscv/c/ea0e0178e101
- [v9,07/10] perf: RISC-V: Introduce Andes PMU to support perf event sampling
https://git.kernel.org/riscv/c/bc969d6cc96a
- [v9,08/10] dt-bindings: riscv: Add Andes PMU extension description
https://git.kernel.org/riscv/c/61609bf2b29d
- [v9,09/10] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f
https://git.kernel.org/riscv/c/270fc77e7b0e
- [v9,10/10] riscv: andes: Support specifying symbolic firmware and hardware raw events
https://git.kernel.org/riscv/c/f5102e31c209
You are awesome, thank you!
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