The existing mv88e6xxx_g2_scratch_gpio_set_smi() cannot be used on the
88E6393X as it requires certain P0_MODE, it also checks the CPU mode
as it impacts the bit setting value.
This is all irrelevant for Amethyst (MV88E6191X/6193X/6393X) as only
the default value of the SMI_PHY Config bit is set to CPU_MGD bootstrap
pin value but it can be changed without restrictions so that GPIO pins
9 and 10 are used as SMI pins.
So, introduce Amethyst specific function and call that if the Amethyst
family wants to setup the external PHY.
Signed-off-by: Robert Marko <[email protected]>
---
drivers/net/dsa/mv88e6xxx/chip.c | 5 +++-
drivers/net/dsa/mv88e6xxx/global2.h | 2 ++
drivers/net/dsa/mv88e6xxx/global2_scratch.c | 31 +++++++++++++++++++++
3 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 9caecb4dfbfa..41426950da21 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -3712,7 +3712,10 @@ static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
if (external) {
mv88e6xxx_reg_lock(chip);
- err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
+ if (chip->info->family == MV88E6XXX_FAMILY_6393)
+ err = mv88e6393x_g2_scratch_gpio_set_smi(chip, true);
+ else
+ err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
mv88e6xxx_reg_unlock(chip);
if (err)
diff --git a/drivers/net/dsa/mv88e6xxx/global2.h b/drivers/net/dsa/mv88e6xxx/global2.h
index d9434f7cae53..3b3f8b6c82c8 100644
--- a/drivers/net/dsa/mv88e6xxx/global2.h
+++ b/drivers/net/dsa/mv88e6xxx/global2.h
@@ -380,6 +380,8 @@ extern const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops;
int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
bool external);
+int mv88e6393x_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
+ bool external);
int mv88e6352_g2_scratch_port_has_serdes(struct mv88e6xxx_chip *chip, int port);
int mv88e6xxx_g2_atu_stats_set(struct mv88e6xxx_chip *chip, u16 kind, u16 bin);
int mv88e6xxx_g2_atu_stats_get(struct mv88e6xxx_chip *chip, u16 *stats);
diff --git a/drivers/net/dsa/mv88e6xxx/global2_scratch.c b/drivers/net/dsa/mv88e6xxx/global2_scratch.c
index a9d6e40321a2..6998c687c553 100644
--- a/drivers/net/dsa/mv88e6xxx/global2_scratch.c
+++ b/drivers/net/dsa/mv88e6xxx/global2_scratch.c
@@ -290,6 +290,37 @@ int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
return mv88e6xxx_g2_scratch_write(chip, misc_cfg, val);
}
+/**
+ * mv88e6393x_g2_scratch_gpio_set_smi - set gpio muxing for external smi
+ * @chip: chip private data
+ * @external: set mux for external smi, or free for gpio usage
+ *
+ * MV88E6191X/6193X/6393X GPIO pins 9 and 10 can be configured as an
+ * external SMI interface or as regular GPIO-s.
+ *
+ * They however have a different register layout then the existing
+ * function.
+ */
+
+int mv88e6393x_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
+ bool external)
+{
+ int misc_cfg = MV88E6352_G2_SCRATCH_MISC_CFG;
+ int err;
+ u8 val;
+
+ err = mv88e6xxx_g2_scratch_read(chip, misc_cfg, &val);
+ if (err)
+ return err;
+
+ if (external)
+ val &= ~MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI;
+ else
+ val |= MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI;
+
+ return mv88e6xxx_g2_scratch_write(chip, misc_cfg, val);
+}
+
/**
* mv88e6352_g2_scratch_port_has_serdes - indicate if a port can have a serdes
* @chip: chip private data
--
2.43.2
On Sat, Feb 24, 2024 at 09:33:09PM +0100, Robert Marko wrote:
> The existing mv88e6xxx_g2_scratch_gpio_set_smi() cannot be used on the
> 88E6393X as it requires certain P0_MODE, it also checks the CPU mode
> as it impacts the bit setting value.
>
> This is all irrelevant for Amethyst (MV88E6191X/6193X/6393X) as only
> the default value of the SMI_PHY Config bit is set to CPU_MGD bootstrap
> pin value but it can be changed without restrictions so that GPIO pins
> 9 and 10 are used as SMI pins.
>
> So, introduce Amethyst specific function and call that if the Amethyst
> family wants to setup the external PHY.
This looks good. The only comment i have is maybe we should rename
mv88e6xxx_g2_scratch_gpio_set_smi() to something more specific. It
seems it is only applicable to MV88E6XXX_FAMILY_6390, so maybe
mv88e6390_g2_scratch_gpio_set_smi()?
Reviewed-by: Andrew Lunn <[email protected]>
Andrew
On Mon, 26 Feb 2024 at 14:57, Andrew Lunn <[email protected]> wrote:
>
> On Sat, Feb 24, 2024 at 09:33:09PM +0100, Robert Marko wrote:
> > The existing mv88e6xxx_g2_scratch_gpio_set_smi() cannot be used on the
> > 88E6393X as it requires certain P0_MODE, it also checks the CPU mode
> > as it impacts the bit setting value.
> >
> > This is all irrelevant for Amethyst (MV88E6191X/6193X/6393X) as only
> > the default value of the SMI_PHY Config bit is set to CPU_MGD bootstrap
> > pin value but it can be changed without restrictions so that GPIO pins
> > 9 and 10 are used as SMI pins.
> >
> > So, introduce Amethyst specific function and call that if the Amethyst
> > family wants to setup the external PHY.
>
> This looks good. The only comment i have is maybe we should rename
> mv88e6xxx_g2_scratch_gpio_set_smi() to something more specific. It
> seems it is only applicable to MV88E6XXX_FAMILY_6390, so maybe
> mv88e6390_g2_scratch_gpio_set_smi()?
That sounds like a good idea, want me to send a v2 with the rename as well?
Regards,
Robert
>
> Reviewed-by: Andrew Lunn <[email protected]>
>
> Andrew
> That sounds like a good idea, want me to send a v2 with the rename as well?
Yes please. 2 patches, and a cover letter.
Andrew