On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, this series adds a DT node for the
PCIe bridges across all SoCs.
There is no functionality change with this series, but the PCIe bridge
representation in DT will be necessary to add the DT node for the client
devices like the one proposed in power sequencing series [1].
- Mani
[1] https://lore.kernel.org/linux-arm-msm/[email protected]/
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
Changes in v2:
- Added label for bridges in sc8280xp
- Collected reviews
- Link to v1: https://lore.kernel.org/r/[email protected]
---
Manivannan Sadhasivam (21):
arm64: dts: qcom: sm8250: Add PCIe bridge node
arm64: dts: qcom: sdm845: Add PCIe bridge node
arm64: dts: qcom: sm8150: Add PCIe bridge node
arm64: dts: qcom: sm8350: Add PCIe bridge node
arm64: dts: qcom: sm8450: Add PCIe bridge node
arm64: dts: qcom: sm8550: Add PCIe bridge node
arm64: dts: qcom: sm8650: Add PCIe bridge node
arm64: dts: qcom: sa8775p: Add PCIe bridge node
arm64: dts: qcom: sc8280xp: Add PCIe bridge node
arm64: dts: qcom: msm8998: Add PCIe bridge node
arm64: dts: qcom: sc7280: Add PCIe bridge node
arm64: dts: qcom: qcs404: Add PCIe bridge node
arm64: dts: qcom: sc8180x: Add PCIe bridge node
arm64: dts: qcom: msm8996: Add PCIe bridge node
arm64: dts: qcom: ipq8074: Add PCIe bridge node
arm64: dts: qcom: ipq6018: Add PCIe bridge node
ARM: dts: qcom: ipq8064: Add PCIe bridge node
ARM: dts: qcom: ipq4019: Add PCIe bridge node
ARM: dts: qcom: apq8064: Add PCIe bridge node
ARM: dts: qcom: sdx55: Add PCIe bridge node
arm64: dts: qcom: sm8650: Use "pcie" as the node name instead of "pci"
arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 10 +++++
arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 10 +++++
arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 30 +++++++++++++
arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 10 +++++
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 +++++
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 20 +++++++++
arch/arm64/boot/dts/qcom/msm8996.dtsi | 30 +++++++++++++
arch/arm64/boot/dts/qcom/msm8998.dtsi | 10 +++++
arch/arm64/boot/dts/qcom/qcs404.dtsi | 10 +++++
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 20 +++++++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 +++++
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 40 +++++++++++++++++
.../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 20 +++------
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 50 ++++++++++++++++++++++
arch/arm64/boot/dts/qcom/sdm845.dtsi | 20 +++++++++
arch/arm64/boot/dts/qcom/sm8150.dtsi | 20 +++++++++
arch/arm64/boot/dts/qcom/sm8250.dtsi | 30 +++++++++++++
arch/arm64/boot/dts/qcom/sm8350.dtsi | 20 +++++++++
arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 +++++++++
arch/arm64/boot/dts/qcom/sm8550.dtsi | 20 +++++++++
arch/arm64/boot/dts/qcom/sm8650.dtsi | 24 ++++++++++-
21 files changed, 418 insertions(+), 16 deletions(-)
---
base-commit: 10569bb9fb9732cec670faa38cf1460cabeffa09
change-id: 20240221-pcie-qcom-bridge-dts-b83c0d1b642b
Best regards,
--
Manivannan Sadhasivam <[email protected]>
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 40 +++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index 32afc78d5b76..322ead0389c9 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -1777,6 +1777,16 @@ pcie0: pcie@1c00000 {
dma-coherent;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie0_phy: phy@1c06000 {
@@ -1888,6 +1898,16 @@ pcie3: pcie@1c08000 {
dma-coherent;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie3_phy: phy@1c0c000 {
@@ -2000,6 +2020,16 @@ pcie1: pcie@1c10000 {
dma-coherent;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie1_phy: phy@1c16000 {
@@ -2112,6 +2142,16 @@ pcie2: pcie@1c18000 {
dma-coherent;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie2_phy: phy@1c1c000 {
--
2.25.1
Qcom SoCs doesn't support legacy PCI, but only PCIe. So use the correct
node name for the controller instances.
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8650.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 06d2b6432ab1..b25fefd6a786 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -2208,7 +2208,7 @@ rng: rng@10c3000 {
reg = <0 0x010c3000 0 0x1000>;
};
- pcie0: pci@1c00000 {
+ pcie0: pcie@1c00000 {
device_type = "pci";
compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
reg = <0 0x01c00000 0 0x3000>,
@@ -2337,7 +2337,7 @@ pcie0_phy: phy@1c06000 {
status = "disabled";
};
- pcie1: pci@1c08000 {
+ pcie1: pcie@1c08000 {
device_type = "pci";
compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
reg = <0 0x01c08000 0 0x3000>,
--
2.25.1
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
index 681cb3fc8085..f09c123d9fa2 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
@@ -470,6 +470,16 @@ pcie0: pcie@40000000 {
"phy_ahb";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
qpic_bam: dma-controller@7984000 {
--
2.25.1
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
While at it, let's remove the bridge properties from board dts as they are
now redundant.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
.../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 20 +++------
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 50 ++++++++++++++++++++++
2 files changed, 56 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
index 15ae94c1602d..caf7dff446a6 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
@@ -731,22 +731,14 @@ &pcie4 {
pinctrl-0 = <&pcie4_default>;
status = "okay";
+};
- pcie@0 {
- device_type = "pci";
- reg = <0x0 0x0 0x0 0x0 0x0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- bus-range = <0x01 0xff>;
-
- wifi@0 {
- compatible = "pci17cb,1103";
- reg = <0x10000 0x0 0x0 0x0 0x0>;
+&pcie4_port0 {
+ wifi@0 {
+ compatible = "pci17cb,1103";
+ reg = <0x10000 0x0 0x0 0x0 0x0>;
- qcom,ath11k-calibration-variant = "LE_X13S";
- };
+ qcom,ath11k-calibration-variant = "LE_X13S";
};
};
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index a5b194813079..c7feebcb28b9 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -1779,6 +1779,16 @@ pcie4: pcie@1c00000 {
phy-names = "pciephy";
status = "disabled";
+
+ pcie4_port0: pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie4_phy: phy@1c06000 {
@@ -1877,6 +1887,16 @@ pcie3b: pcie@1c08000 {
phy-names = "pciephy";
status = "disabled";
+
+ pcie3b_port0: pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie3b_phy: phy@1c0e000 {
@@ -1975,6 +1995,16 @@ pcie3a: pcie@1c10000 {
phy-names = "pciephy";
status = "disabled";
+
+ pcie3a_port0: pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie3a_phy: phy@1c14000 {
@@ -2076,6 +2106,16 @@ pcie2b: pcie@1c18000 {
phy-names = "pciephy";
status = "disabled";
+
+ pcie2b_port0: pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie2b_phy: phy@1c1e000 {
@@ -2174,6 +2214,16 @@ pcie2a: pcie@1c20000 {
phy-names = "pciephy";
status = "disabled";
+
+ pcie2a_port0: pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie2a_phy: phy@1c24000 {
--
2.25.1
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <[email protected]>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index e5b89753aa5c..12324841d1b0 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -864,6 +864,16 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
"ahb",
"axi_m_sticky";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie0: pcie@20000000 {
@@ -929,6 +939,16 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
"axi_m_sticky",
"axi_s_sticky";
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
};
--
2.25.1
On 21.03.2024 12:16, Manivannan Sadhasivam wrote:
> On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
> for each controller instance. Hence, this series adds a DT node for the
> PCIe bridges across all SoCs.
>
> There is no functionality change with this series, but the PCIe bridge
> representation in DT will be necessary to add the DT node for the client
> devices like the one proposed in power sequencing series [1].
>
> - Mani
>
> [1] https://lore.kernel.org/linux-arm-msm/[email protected]/
>
> Signed-off-by: Manivannan Sadhasivam <[email protected]>
> ---
Everything looks good
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
On Thu, 21 Mar 2024 16:46:20 +0530, Manivannan Sadhasivam wrote:
> On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
> for each controller instance. Hence, this series adds a DT node for the
> PCIe bridges across all SoCs.
>
> There is no functionality change with this series, but the PCIe bridge
> representation in DT will be necessary to add the DT node for the client
> devices like the one proposed in power sequencing series [1].
>
> [...]
Applied, thanks!
[17/21] ARM: dts: qcom: ipq8064: Add PCIe bridge node
commit: 0c4d19b125401957123989a25094972cf0e77670
[18/21] ARM: dts: qcom: ipq4019: Add PCIe bridge node
commit: ed9b196418d4e2fa4f6c27b61a92c2038e1ba04d
[19/21] ARM: dts: qcom: apq8064: Add PCIe bridge node
commit: 27cb9eccf94cb163f9bf3b945f249ab7c42861db
[20/21] ARM: dts: qcom: sdx55: Add PCIe bridge node
commit: 669841a2eff4c0132841dea3ae40d9148a36f257
Best regards,
--
Bjorn Andersson <[email protected]>