Hi Krzysztof,
This series contains the dts, dtsi and sysreg bindings that enables UFS
on Pixel 6 (Oriole). From v3 onwards it has been split into separate series
as you requested.
Along with the various driver code UFS is now functional, the SKhynix
HN8T05BZGKX015 can be enumerated, partitions mounted etc.
UFS bindings in this series are proposed:
https://lore.kernel.org/linux-arm-kernel/[email protected]/
Clock cmu_hsi2 bindings are proposed:
https://lore.kernel.org/r/[email protected]
UFS phy bindings used here are already queued by Vinod
kind regards,
Peter.
lore v3: https://lore.kernel.org/lkml/[email protected]/
lore v2: https://lore.kernel.org/linux-kernel/[email protected]/
lore v1: https://lore.kernel.org/linux-clk/[email protected]/
Changes since v3:
- Fix unit address ordering in gs101.dtsi (Krzysztof)
Changes since v2:
- Split into separate subsystem series
- Split dts and dtsi patches (Krzysztof)
Changes since v1:
- Collect up tags
- fix google,gs101-hsi2-sysreg size (0x10000 not 0x1000) (Andre)
- use GPIO defines in DT and add TODO pmic comment (Krzysztof)
- Add sysreg clock to ufs node (Andre)
Peter Griffin (4):
dt-bindings: soc: google: exynos-sysreg: add dedicated hsi2 sysreg
compatible
arm64: dts: exynos: gs101: Add the hsi2 sysreg node
arm64: dts: exynos: gs101: Add ufs and ufs-phy dt nodes
arm64: dts: exynos: gs101: enable ufs, phy on oriole & define ufs
regulator
.../soc/samsung/samsung,exynos-sysreg.yaml | 2 +
.../boot/dts/exynos/google/gs101-oriole.dts | 18 ++++++++
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 42 +++++++++++++++++++
3 files changed, 62 insertions(+)
--
2.44.0.769.g3c40516874-goog
Add the ufs controller node and phy node for gs101.
Signed-off-by: Peter Griffin <[email protected]>
Acked-by: André Draszik <[email protected]>
---
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 36 ++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index 09044deede63..9330d99e12df 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -1277,6 +1277,42 @@ pinctrl_hsi2: pinctrl@14440000 {
interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
};
+ ufs_0: ufs@14700000 {
+ compatible = "google,gs101-ufs";
+ reg = <0x14700000 0x200>,
+ <0x14701100 0x200>,
+ <0x14780000 0xa000>,
+ <0x14600000 0x100>;
+ reg-names = "hci", "vs_hci", "unipro", "ufsp";
+ interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_ACLK>,
+ <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO>,
+ <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK>,
+ <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK>,
+ <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK>,
+ <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>;
+ clock-names = "core_clk", "sclk_unipro_main", "fmp",
+ "aclk", "pclk", "sysreg";
+ freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>;
+ pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
+ pinctrl-names = "default";
+ phys = <&ufs_0_phy>;
+ phy-names = "ufs-phy";
+ samsung,sysreg = <&sysreg_hsi2 0x710>;
+ status = "disabled";
+ };
+
+ ufs_0_phy: phy@0x14704000 {
+ compatible = "google,gs101-ufs-phy";
+ reg = <0x14704000 0x3000>;
+ reg-names = "phy-pma";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ #phy-cells = <0>;
+ clocks = <&ext_24_5m>;
+ clock-names = "ref_clk";
+ status = "disabled";
+ };
+
cmu_apm: clock-controller@17400000 {
compatible = "google,gs101-cmu-apm";
reg = <0x17400000 0x8000>;
--
2.44.0.769.g3c40516874-goog
Enable ufs & ufs phy nodes for Oriole. Also define the ufs regulator node.
ufs regulator is a stub until full s2mpg11 slave pmic support is added.
The gpio defined is for the BOOTLD0 (gs101) signal connected to
UFS_EN(s2mpg11) gpio enabled voltage rail for UFS.
Signed-off-by: Peter Griffin <[email protected]>
---
.../boot/dts/exynos/google/gs101-oriole.dts | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
index 6be15e990b65..fb32f6ce2a4d 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
+++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
@@ -53,6 +53,15 @@ button-power {
wakeup-source;
};
};
+
+ /* TODO: Remove this once S2MPG11 slave PMIC is implemented */
+ ufs_0_fixed_vcc_reg: regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "ufs-vcc";
+ gpio = <&gpp0 1 GPIO_ACTIVE_HIGH>;
+ regulator-boot-on;
+ enable-active-high;
+ };
};
&ext_24_5m {
@@ -106,6 +115,15 @@ &serial_0 {
status = "okay";
};
+&ufs_0 {
+ status = "okay";
+ vcc-supply = <&ufs_0_fixed_vcc_reg>;
+};
+
+&ufs_0_phy {
+ status = "okay";
+};
+
&usi_uart {
samsung,clkreq-on; /* needed for UART mode */
status = "okay";
--
2.44.0.769.g3c40516874-goog
This has some configuration bits such as sharability that
are required by UFS.
Signed-off-by: Peter Griffin <[email protected]>
Reviewed-by: André Draszik <[email protected]>
---
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index 38ac4fb1397e..09044deede63 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -1265,6 +1265,12 @@ cmu_hsi2: clock-controller@14400000 {
clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card";
};
+ sysreg_hsi2: syscon@14420000 {
+ compatible = "google,gs101-hsi2-sysreg", "syscon";
+ reg = <0x14420000 0x10000>;
+ clocks = <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>;
+ };
+
pinctrl_hsi2: pinctrl@14440000 {
compatible = "google,gs101-pinctrl";
reg = <0x14440000 0x00001000>;
--
2.44.0.769.g3c40516874-goog
Update dt schema to include the gs101 hsi2 sysreg compatible.
Signed-off-by: Peter Griffin <[email protected]>
Reviewed-by: André Draszik <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
.../devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
index c0c6ce8fc786..3ca220582897 100644
--- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
+++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
@@ -15,6 +15,7 @@ properties:
- items:
- enum:
- google,gs101-apm-sysreg
+ - google,gs101-hsi2-sysreg
- google,gs101-peric0-sysreg
- google,gs101-peric1-sysreg
- samsung,exynos3-sysreg
@@ -72,6 +73,7 @@ allOf:
compatible:
contains:
enum:
+ - google,gs101-hsi2-sysreg
- google,gs101-peric0-sysreg
- google,gs101-peric1-sysreg
- samsung,exynos850-cmgp-sysreg
--
2.44.0.769.g3c40516874-goog
On Mon, 29 Apr 2024 12:15:34 +0100, Peter Griffin wrote:
> Update dt schema to include the gs101 hsi2 sysreg compatible.
>
>
Applied, thanks!
[1/4] dt-bindings: soc: google: exynos-sysreg: add dedicated hsi2 sysreg compatible
https://git.kernel.org/krzk/linux/c/6d1434a7d95939d21cf300f73040e3e6a02e84f8
Best regards,
--
Krzysztof Kozlowski <[email protected]>
On 29/04/2024 13:15, Peter Griffin wrote:
> This has some configuration bits such as sharability that
> are required by UFS.
>
> Signed-off-by: Peter Griffin <[email protected]>
> Reviewed-by: André Draszik <[email protected]>
> ---
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> index 38ac4fb1397e..09044deede63 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> @@ -1265,6 +1265,12 @@ cmu_hsi2: clock-controller@14400000 {
> clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card";
> };
Does not apply anymore, please rebase.
Best regards,
Krzysztof
On 29/04/2024 13:15, Peter Griffin wrote:
> + ufs_0: ufs@14700000 {
> + compatible = "google,gs101-ufs";
> + reg = <0x14700000 0x200>,
> + <0x14701100 0x200>,
> + <0x14780000 0xa000>,
> + <0x14600000 0x100>;
> + reg-names = "hci", "vs_hci", "unipro", "ufsp";
> + interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_ACLK>,
> + <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO>,
> + <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK>,
> + <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK>,
> + <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK>,
> + <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>;
> + clock-names = "core_clk", "sclk_unipro_main", "fmp",
> + "aclk", "pclk", "sysreg";
> + freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>;
> + pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
> + pinctrl-names = "default";
> + phys = <&ufs_0_phy>;
> + phy-names = "ufs-phy";
> + samsung,sysreg = <&sysreg_hsi2 0x710>;
> + status = "disabled";
> + };
> +
> + ufs_0_phy: phy@0x14704000 {
Drop 0x from unit address.
Best regards,
Krzysztof
Hi Krzysztof,
On Mon, 29 Apr 2024 at 18:30, Krzysztof Kozlowski <[email protected]> wrote:
>
> On 29/04/2024 13:15, Peter Griffin wrote:
> > + ufs_0: ufs@14700000 {
> > + compatible = "google,gs101-ufs";
> > + reg = <0x14700000 0x200>,
> > + <0x14701100 0x200>,
> > + <0x14780000 0xa000>,
> > + <0x14600000 0x100>;
> > + reg-names = "hci", "vs_hci", "unipro", "ufsp";
> > + interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
> > + clocks = <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_ACLK>,
> > + <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO>,
> > + <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK>,
> > + <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK>,
> > + <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK>,
> > + <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>;
> > + clock-names = "core_clk", "sclk_unipro_main", "fmp",
> > + "aclk", "pclk", "sysreg";
> > + freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>;
> > + pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
> > + pinctrl-names = "default";
> > + phys = <&ufs_0_phy>;
> > + phy-names = "ufs-phy";
> > + samsung,sysreg = <&sysreg_hsi2 0x710>;
> > + status = "disabled";
> > + };
> > +
> > + ufs_0_phy: phy@0x14704000 {
>
> Drop 0x from unit address.
Thanks for the review, will fix.
Peter