Fixed 8mp EP mode problem.
imx6 actaully for all imx chips (imx6*, imx7*, imx8*, imx9*). To avoid
confuse, rename all imx6_* to imx_*, IMX6_* to IMX_*. pci-imx6.c to
pci-imx.c to avoid confuse.
Using callback to reduce switch case for core reset and refclk.
Add imx95 iommux and its stream id information.
Base on linux-pci/controller/imx
To: Richard Zhu <[email protected]>
To: Lucas Stach <[email protected]>
To: Lorenzo Pieralisi <[email protected]>
To: Krzysztof Wilczyński <[email protected]>
To: Rob Herring <[email protected]>
To: Bjorn Helgaas <[email protected]>
To: Shawn Guo <[email protected]>
To: Sascha Hauer <[email protected]>
To: Pengutronix Kernel Team <[email protected]>
To: Fabio Estevam <[email protected]>
To: NXP Linux Team <[email protected]>
To: Philipp Zabel <[email protected]>
To: Liam Girdwood <[email protected]>
To: Mark Brown <[email protected]>
To: Manivannan Sadhasivam <[email protected]>
To: Krzysztof Kozlowski <[email protected]>
To: Conor Dooley <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Frank Li <[email protected]>
Changes in v4:
- Improve comment message for patch 1 and 2.
- Rework commit message for patch 3 and add mani's review tag
- Remove file rename patch and update maintainer patch
- [PATCH v3 06/11] PCI: imx: Simplify switch-case logic by involve set_ref_clk callback
remove extra space.
keep original comments format (wrap at 80 column width)
update error message "'Failed to enable PCIe REFCLK'"
- PATCH v3 07/11] PCI: imx: Simplify switch-case logic by involve core_reset callback
keep exact the logic as original code
- Add patch to update comment about workaround ERR010728
- Add patch about help function imx_pcie_match_device()
- Using bus device notify to update LUT information for imx95 to avoid
parse iommu-map and msi-map in driver code. Bus notify will better and
only update lut when device added.
- split patch call PHY interface function.
- Improve commit message for imx8q. remove local-address dts proptery. and
use standard "range" to convert cpu address to bus address.
- Check entry in cpu_fix function is too late. Check it at probe
- Link to v3: https://lore.kernel.org/r/[email protected]
Changes in v3:
- Add an EP fixed patch
PCI: imx6: Fix PCIe link down when i.MX8MM and i.MX8MP PCIe is EP mode
PCI: imx6: Fix i.MX8MP PCIe EP can not trigger MSI
- Add 8qxp rc support
dt-bing yaml pass binding check
make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- -j8 dt_binding_check DT_SCHEMA_FILES=fsl,imx6q-pcie.yaml
LINT Documentation/devicetree/bindings
DTEX Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.example.dts
CHKDT Documentation/devicetree/bindings/processed-schema.json
SCHEMA Documentation/devicetree/bindings/processed-schema.json
DTC_CHK Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.example.dtb
- Link to v2: https://lore.kernel.org/r/[email protected]
Changes in v2:
- remove file to 'pcie-imx.c'
- keep CONFIG unchange.
- Link to v1: https://lore.kernel.org/r/[email protected]
---
Frank Li (8):
PCI: imx6: Rename imx6_* with imx_*
PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK
PCI: imx6: Simplify switch-case logic by involve core_reset callback
PCI: imx6: Improve comment for workaround ERR010728
PCI: imx6: Add help function imx_pcie_match_device()
PCI: imx6: Config look up table(LUT) to support MSI ITS and IOMMU for i.MX95
PCI: imx6: Consolidate redundant if-checks
PCI: imx6: Call: Common PHY API to set mode, speed, and submode
Richard Zhu (4):
PCI: imx6: Fix establish link failure in EP mode for iMX8MM and iMX8MP
PCI: imx6: Fix i.MX8MP PCIe EP's occasional failure to trigger MSI
dt-bindings: imx6q-pcie: Add i.MX8Q pcie compatible string
PCI: imx6: Add i.MX8Q PCIe root complex (RC) support
.../devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 16 +
drivers/pci/controller/dwc/pci-imx6.c | 1193 ++++++++++++--------
2 files changed, 736 insertions(+), 473 deletions(-)
---
base-commit: 9d8b196fd12e52820a40c21297a97ea6186aa87e
change-id: 20240227-pci2_upstream-0cdd19a15163
Best regards,
---
Frank Li <[email protected]>
Instead of using the switch case statement to assert/dassert the core reset
handled by this driver itself, let's introduce a new callback core_reset()
and define it for platforms that require it. This simplifies the code.
Signed-off-by: Frank Li <[email protected]>
---
drivers/pci/controller/dwc/pci-imx6.c | 134 ++++++++++++++++++----------------
1 file changed, 71 insertions(+), 63 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index cf1b487b3f625..7396f0d51119a 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -104,6 +104,7 @@ struct imx_pcie_drvdata {
const struct pci_epc_features *epc_features;
int (*init_phy)(struct imx_pcie *pcie);
int (*set_ref_clk)(struct imx_pcie *pcie, bool enable);
+ int (*core_reset)(struct imx_pcie *pcie, bool assert);
};
struct imx_pcie {
@@ -672,35 +673,75 @@ static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie)
clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks);
}
+static int imx6sx_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
+{
+ if (assert)
+ regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
+
+ /* Force PCIe PHY reset */
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, IMX6SX_GPR5_PCIE_BTNRST_RESET,
+ assert ? IMX6SX_GPR5_PCIE_BTNRST_RESET : 0);
+ return 0;
+}
+
+static int imx6qp_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
+{
+ regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_SW_RST,
+ assert ? IMX6Q_GPR1_PCIE_SW_RST : 0);
+ if (!assert)
+ usleep_range(200, 500);
+
+ return 0;
+}
+
+static int imx6q_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
+{
+ if (!assert)
+ return 0;
+
+ regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD);
+ regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN);
+
+ return 0;
+}
+
+static int imx7d_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
+{
+ struct dw_pcie *pci = imx_pcie->pci;
+ struct device *dev = pci->dev;
+
+ if (assert)
+ return 0;
+
+ /*
+ * Workaround for ERR010728, failure of PCI-e PLL VCO to
+ * oscillate, especially when cold. This turns off "Duty-cycle
+ * Corrector" and other mysterious undocumented things.
+ */
+
+ if (likely(imx_pcie->phy_base)) {
+ /* De-assert DCC_FB_EN */
+ writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, imx_pcie->phy_base + PCIE_PHY_CMN_REG4);
+ /* Assert RX_EQS and RX_EQS_SEL */
+ writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL | PCIE_PHY_CMN_REG24_RX_EQ,
+ imx_pcie->phy_base + PCIE_PHY_CMN_REG24);
+ /* Assert ATT_MODE */
+ writel(PCIE_PHY_CMN_REG26_ATT_MODE, imx_pcie->phy_base + PCIE_PHY_CMN_REG26);
+ } else {
+ dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n");
+ }
+ imx7d_pcie_wait_for_phy_pll_lock(imx_pcie);
+ return 0;
+}
+
static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)
{
reset_control_assert(imx_pcie->pciephy_reset);
reset_control_assert(imx_pcie->apps_reset);
- switch (imx_pcie->drvdata->variant) {
- case IMX6SX:
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
- IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
- IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
- /* Force PCIe PHY reset */
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5,
- IMX6SX_GPR5_PCIE_BTNRST_RESET,
- IMX6SX_GPR5_PCIE_BTNRST_RESET);
- break;
- case IMX6QP:
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
- IMX6Q_GPR1_PCIE_SW_RST,
- IMX6Q_GPR1_PCIE_SW_RST);
- break;
- case IMX6Q:
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
- IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
- IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
- break;
- default:
- break;
- }
+ if (imx_pcie->drvdata->core_reset)
+ imx_pcie->drvdata->core_reset(imx_pcie, true);
/* Some boards don't have PCIe reset GPIO. */
if (gpio_is_valid(imx_pcie->reset_gpio))
@@ -710,47 +751,10 @@ static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)
static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie)
{
- struct dw_pcie *pci = imx_pcie->pci;
- struct device *dev = pci->dev;
-
reset_control_deassert(imx_pcie->pciephy_reset);
- switch (imx_pcie->drvdata->variant) {
- case IMX7D:
- /* Workaround for ERR010728, failure of PCI-e PLL VCO to
- * oscillate, especially when cold. This turns off "Duty-cycle
- * Corrector" and other mysterious undocumented things.
- */
- if (likely(imx_pcie->phy_base)) {
- /* De-assert DCC_FB_EN */
- writel(PCIE_PHY_CMN_REG4_DCC_FB_EN,
- imx_pcie->phy_base + PCIE_PHY_CMN_REG4);
- /* Assert RX_EQS and RX_EQS_SEL */
- writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL
- | PCIE_PHY_CMN_REG24_RX_EQ,
- imx_pcie->phy_base + PCIE_PHY_CMN_REG24);
- /* Assert ATT_MODE */
- writel(PCIE_PHY_CMN_REG26_ATT_MODE,
- imx_pcie->phy_base + PCIE_PHY_CMN_REG26);
- } else {
- dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n");
- }
-
- imx7d_pcie_wait_for_phy_pll_lock(imx_pcie);
- break;
- case IMX6SX:
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5,
- IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
- break;
- case IMX6QP:
- regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1,
- IMX6Q_GPR1_PCIE_SW_RST, 0);
-
- usleep_range(200, 500);
- break;
- default:
- break;
- }
+ if (imx_pcie->drvdata->core_reset)
+ imx_pcie->drvdata->core_reset(imx_pcie, false);
/* Some boards don't have PCIe reset GPIO. */
if (gpio_is_valid(imx_pcie->reset_gpio)) {
@@ -1448,6 +1452,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.init_phy = imx_pcie_init_phy,
.set_ref_clk = imx6q_pcie_set_ref_clk,
+ .core_reset = imx6q_pcie_core_reset,
},
[IMX6SX] = {
.variant = IMX6SX,
@@ -1463,6 +1468,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.init_phy = imx6sx_pcie_init_phy,
.set_ref_clk = imx6sx_pcie_set_ref_clk,
+ .core_reset = imx6sx_pcie_core_reset,
},
[IMX6QP] = {
.variant = IMX6QP,
@@ -1479,6 +1485,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.init_phy = imx_pcie_init_phy,
.set_ref_clk = imx6q_pcie_set_ref_clk,
+ .core_reset = imx6qp_pcie_core_reset,
},
[IMX7D] = {
.variant = IMX7D,
@@ -1492,6 +1499,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
.mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE,
.init_phy = imx7d_pcie_init_phy,
.set_ref_clk = imx7d_pcie_set_ref_clk,
+ .core_reset = imx7d_pcie_core_reset,
},
[IMX8MQ] = {
.variant = IMX8MQ,
--
2.34.1
From: Richard Zhu <[email protected]>
Add i.MX8Q PCIe "fsl,imx8q-pcie" compatible strings. clock-names align dwc
common naming convension.
Signed-off-by: Richard Zhu <[email protected]>
Signed-off-by: Frank Li <[email protected]>
---
.../devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index 8b8d77b1154b5..1e05c560d7975 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -30,6 +30,7 @@ properties:
- fsl,imx8mm-pcie
- fsl,imx8mp-pcie
- fsl,imx95-pcie
+ - fsl,imx8q-pcie
clocks:
minItems: 3
@@ -184,6 +185,21 @@ allOf:
- const: pcie_bus
- const: pcie_aux
+ - if:
+ properties:
+ compatible:
+ enum:
+ - fsl,imx8q-pcie
+ then:
+ properties:
+ clocks:
+ maxItems: 3
+ clock-names:
+ items:
+ - const: dbi
+ - const: mstr
+ - const: slv
+
unevaluatedProperties: false
examples:
--
2.34.1
Invoke the common PHY API to configure mode, speed, and submode. While
these functions are optional in the PHY interface, they are necessary for
certain PHY drivers. Lack of support for these functions in a PHY driver
does not cause harm.
Signed-off-by: Frank Li <[email protected]>
---
drivers/pci/controller/dwc/pci-imx6.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 9d53b545540c6..df623977d8fe6 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -30,6 +30,7 @@
#include <linux/interrupt.h>
#include <linux/reset.h>
#include <linux/phy/phy.h>
+#include <linux/phy/pcie.h>
#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>
@@ -308,6 +309,10 @@ static void imx_pcie_configure_type(struct imx_pcie *imx_pcie)
id = imx_pcie->controller_id;
+ /* If mode_mask[0] is 0, means use phy driver to set mode */
+ if (!drvdata->mode_mask[0])
+ return;
+
/* If mode_mask[id] is zero, means each controller have its individual gpr */
if (!drvdata->mode_mask[id])
id = 0;
@@ -887,6 +892,7 @@ static void imx_pcie_ltssm_enable(struct device *dev)
struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
+ phy_set_speed(imx_pcie->phy, PCI_EXP_LNKCAP_SLS_2_5GB);
if (drvdata->ltssm_mask)
regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask,
drvdata->ltssm_mask);
@@ -899,6 +905,7 @@ static void imx_pcie_ltssm_disable(struct device *dev)
struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
+ phy_set_speed(imx_pcie->phy, 0);
if (drvdata->ltssm_mask)
regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off,
drvdata->ltssm_mask, 0);
@@ -1034,6 +1041,12 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
goto err_clk_disable;
}
+ ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC);
+ if (ret) {
+ dev_err(dev, "unable to set pcie PHY mode\n");
+ goto err_phy_off;
+ }
+
ret = phy_power_on(imx_pcie->phy);
if (ret) {
dev_err(dev, "waiting for PHY ready timeout!\n");
--
2.34.1
On Tue, May 07, 2024 at 02:45:48PM -0400, Frank Li wrote:
> From: Richard Zhu <[email protected]>
>
> Add i.MX8Q PCIe "fsl,imx8q-pcie" compatible strings. clock-names align dwc
> common naming convension.
>
> Signed-off-by: Richard Zhu <[email protected]>
> Signed-off-by: Frank Li <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Cheers,
Conor.
On Tue, 07 May 2024 14:45:48 -0400, Frank Li wrote:
> From: Richard Zhu <[email protected]>
>
> Add i.MX8Q PCIe "fsl,imx8q-pcie" compatible strings. clock-names align dwc
> common naming convension.
>
> Signed-off-by: Richard Zhu <[email protected]>
> Signed-off-by: Frank Li <[email protected]>
> ---
> .../devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
Reviewed-by: Rob Herring (Arm) <[email protected]>
On Tue, May 07, 2024 at 02:45:38PM -0400, Frank Li wrote:
> Fixed 8mp EP mode problem.
>
> imx6 actaully for all imx chips (imx6*, imx7*, imx8*, imx9*). To avoid
> confuse, rename all imx6_* to imx_*, IMX6_* to IMX_*. pci-imx6.c to
> pci-imx.c to avoid confuse.
>
> Using callback to reduce switch case for core reset and refclk.
>
> Add imx95 iommux and its stream id information.
>
Mani:
Do you have chance to check these again? I fixed what your said
at v3.
Frank Li
> Base on linux-pci/controller/imx
>
> To: Richard Zhu <[email protected]>
> To: Lucas Stach <[email protected]>
> To: Lorenzo Pieralisi <[email protected]>
> To: Krzysztof Wilczyński <[email protected]>
> To: Rob Herring <[email protected]>
> To: Bjorn Helgaas <[email protected]>
> To: Shawn Guo <[email protected]>
> To: Sascha Hauer <[email protected]>
> To: Pengutronix Kernel Team <[email protected]>
> To: Fabio Estevam <[email protected]>
> To: NXP Linux Team <[email protected]>
> To: Philipp Zabel <[email protected]>
> To: Liam Girdwood <[email protected]>
> To: Mark Brown <[email protected]>
> To: Manivannan Sadhasivam <[email protected]>
> To: Krzysztof Kozlowski <[email protected]>
> To: Conor Dooley <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Signed-off-by: Frank Li <[email protected]>
>
> Changes in v4:
> - Improve comment message for patch 1 and 2.
> - Rework commit message for patch 3 and add mani's review tag
> - Remove file rename patch and update maintainer patch
> - [PATCH v3 06/11] PCI: imx: Simplify switch-case logic by involve set_ref_clk callback
> remove extra space.
> keep original comments format (wrap at 80 column width)
> update error message "'Failed to enable PCIe REFCLK'"
> - PATCH v3 07/11] PCI: imx: Simplify switch-case logic by involve core_reset callback
> keep exact the logic as original code
> - Add patch to update comment about workaround ERR010728
> - Add patch about help function imx_pcie_match_device()
> - Using bus device notify to update LUT information for imx95 to avoid
> parse iommu-map and msi-map in driver code. Bus notify will better and
> only update lut when device added.
> - split patch call PHY interface function.
> - Improve commit message for imx8q. remove local-address dts proptery. and
> use standard "range" to convert cpu address to bus address.
> - Check entry in cpu_fix function is too late. Check it at probe
> - Link to v3: https://lore.kernel.org/r/[email protected]
>
> Changes in v3:
> - Add an EP fixed patch
> PCI: imx6: Fix PCIe link down when i.MX8MM and i.MX8MP PCIe is EP mode
> PCI: imx6: Fix i.MX8MP PCIe EP can not trigger MSI
> - Add 8qxp rc support
> dt-bing yaml pass binding check
> make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- -j8 dt_binding_check DT_SCHEMA_FILES=fsl,imx6q-pcie.yaml
> LINT Documentation/devicetree/bindings
> DTEX Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.example.dts
> CHKDT Documentation/devicetree/bindings/processed-schema.json
> SCHEMA Documentation/devicetree/bindings/processed-schema.json
> DTC_CHK Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.example.dtb
>
> - Link to v2: https://lore.kernel.org/r/[email protected]
>
> Changes in v2:
> - remove file to 'pcie-imx.c'
> - keep CONFIG unchange.
> - Link to v1: https://lore.kernel.org/r/[email protected]
>
> ---
> Frank Li (8):
> PCI: imx6: Rename imx6_* with imx_*
> PCI: imx6: Introduce SoC specific callbacks for controlling REFCLK
> PCI: imx6: Simplify switch-case logic by involve core_reset callback
> PCI: imx6: Improve comment for workaround ERR010728
> PCI: imx6: Add help function imx_pcie_match_device()
> PCI: imx6: Config look up table(LUT) to support MSI ITS and IOMMU for i.MX95
> PCI: imx6: Consolidate redundant if-checks
> PCI: imx6: Call: Common PHY API to set mode, speed, and submode
>
> Richard Zhu (4):
> PCI: imx6: Fix establish link failure in EP mode for iMX8MM and iMX8MP
> PCI: imx6: Fix i.MX8MP PCIe EP's occasional failure to trigger MSI
> dt-bindings: imx6q-pcie: Add i.MX8Q pcie compatible string
> PCI: imx6: Add i.MX8Q PCIe root complex (RC) support
>
> .../devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 16 +
> drivers/pci/controller/dwc/pci-imx6.c | 1193 ++++++++++++--------
> 2 files changed, 736 insertions(+), 473 deletions(-)
> ---
> base-commit: 9d8b196fd12e52820a40c21297a97ea6186aa87e
> change-id: 20240227-pci2_upstream-0cdd19a15163
>
> Best regards,
> ---
> Frank Li <[email protected]>
>