Hello,
This series adds the device-tree support for enabling PCIe and USB
functionality on J722S-EVM.
Since AM62P and J722S SoCs share most of the peripherals, the files have
been renamed to indicate the same. The main domain peripherals on both
SoCs that aren't shared are present in the "soc-main.dtsi" files.
This change has been made based on Roger's feedback at:
https://lore.kernel.org/r/[email protected]/
This series has been tested on J722S-EVM for PCIe and USB functionality:
https://gist.github.com/Siddharth-Vadapalli-at-TI/bb20e30a4a9e29e1a6772915c13dd214
Sanity testing on AM62P5-SK with this series:
https://gist.github.com/Siddharth-Vadapalli-at-TI/a8764b3180d20d7e380b167637136676
v3:
https://lore.kernel.org/r/[email protected]/
Changes since v3:
- Rebased series on next-20240531.
- Renamed files to indicate that they are shared between AM62P and J722S:
k3-am62p.dtsi => k3-am62p-j722s-common.dtsi
k3-am62p-main.dtsi => k3-am62p-j722s-common-main.dtsi
k3-am62p-mcu.dtsi => k3-am62p-j722s-common-mcu.dtsi
k3-am62p-wakeup.dtsi => k3-am62p-j722s-common-wakeup.dtsi
- Moved AM62P specific USB1 from the shared
k3-am62p-j722s-common-main.dtsi to AM62P specific k3-am62p-main.dtsi
- Updated k3-j722s.dtsi to include k3-am62p-j722s-common.dtsi instead of
including k3-am62p5.dtsi
- Added J722S specific main domain peripherals namely USB1, PCIe and
SERDES in k3-j722s-main.dtsi
Regards,
Siddharth.
Siddharth Vadapalli (7):
arm64: dts: ti: am62p: Rename am62p-{}.dtsi to
am62p-j722s-common-{}.dtsi
arm64: dts: ti: k3-am62p-j722s: Move AM62P specific USB1 to
am62p-main.dtsi
arm64: dts: ti: k3-j722s: Add main domain peripherals specific to
J722S
arm64: dts: ti: k3-j722s: Switch to k3-am62p-j722s-common.dtsi
arm64: dts: ti: k3-serdes: Add SERDES0/SERDES1 lane-muxing macros for
J722S
arm64: dts: ti: k3-j722s-main: Add SERDES and PCIe support
arm64: dts: ti: k3-j722s: Enable PCIe and USB support on J722S-EVM
.../dts/ti/k3-am62p-j722s-common-main.dtsi | 1067 +++++++++++++++++
...cu.dtsi => k3-am62p-j722s-common-mcu.dtsi} | 2 +-
...dtsi => k3-am62p-j722s-common-wakeup.dtsi} | 2 +-
...-am62p.dtsi => k3-am62p-j722s-common.dtsi} | 6 +-
arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 1060 ----------------
arch/arm64/boot/dts/ti/k3-am62p5.dtsi | 3 +-
arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 72 ++
arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 170 +++
arch/arm64/boot/dts/ti/k3-j722s.dtsi | 97 +-
arch/arm64/boot/dts/ti/k3-serdes.h | 8 +
10 files changed, 1420 insertions(+), 1067 deletions(-)
create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
rename arch/arm64/boot/dts/ti/{k3-am62p-mcu.dtsi => k3-am62p-j722s-common-mcu.dtsi} (98%)
rename arch/arm64/boot/dts/ti/{k3-am62p-wakeup.dtsi => k3-am62p-j722s-common-wakeup.dtsi} (97%)
rename arch/arm64/boot/dts/ti/{k3-am62p.dtsi => k3-am62p-j722s-common.dtsi} (97%)
create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
--
2.40.1
Update "k3-j722s.dtsi" to use "k3-am62p-j722s-common.dtsi" which
contains the nodes shared with AM62P, followed by including the J722S
specific main domain peripherals contained in "k3-j722s-main.dtsi".
Signed-off-by: Siddharth Vadapalli <[email protected]>
---
No changelog since this patch is introduced in this version of the
series.
arch/arm64/boot/dts/ti/k3-j722s.dtsi | 97 +++++++++++++++++++++++++++-
1 file changed, 96 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
index c75744edb143..9e04e6a5c0fd 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
@@ -10,12 +10,107 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
-#include "k3-am62p5.dtsi"
+#include "k3-am62p-j722s-common.dtsi"
+#include "k3-j722s-main.dtsi"
/ {
model = "Texas Instruments K3 J722S SoC";
compatible = "ti,j722s";
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0: cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ clocks = <&k3_clks 135 0>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ clocks = <&k3_clks 136 0>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53";
+ reg = <0x002>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ clocks = <&k3_clks 137 0>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53";
+ reg = <0x003>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&l2_0>;
+ clocks = <&k3_clks 138 0>;
+ };
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ cache-size = <0x80000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ };
+
cbass_main: bus@f0000 {
compatible = "simple-bus";
#address-cells = <2>;
--
2.40.1
The SERDES0 and SERDES1 instances of SERDES on J722S are single lane
SERDES which are individually muxed across different peripherals.
LANE0 of SERDES0 is muxed between USB and CPSW while LANE0 of SERDES1 is
muxed between PCIe and CPSW.
Define the lane-muxing macros to be used as the idle state values.
Co-developed-by: Ravi Gunasekaran <[email protected]>
Signed-off-by: Ravi Gunasekaran <[email protected]>
Signed-off-by: Siddharth Vadapalli <[email protected]>
---
v3:
https://lore.kernel.org/r/[email protected]/
and
https://lore.kernel.org/r/[email protected]/
Changes since v3:
- Above changes have been squashed into this patch.
arch/arm64/boot/dts/ti/k3-serdes.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h
index a011ad893b44..ef3606068140 100644
--- a/arch/arm64/boot/dts/ti/k3-serdes.h
+++ b/arch/arm64/boot/dts/ti/k3-serdes.h
@@ -201,4 +201,12 @@
#define J784S4_SERDES4_LANE3_USB 0x2
#define J784S4_SERDES4_LANE3_IP4_UNUSED 0x3
+/* J722S */
+
+#define J722S_SERDES0_LANE0_USB 0x0
+#define J722S_SERDES0_LANE0_QSGMII_LANE2 0x1
+
+#define J722S_SERDES1_LANE0_PCIE0_LANE0 0x0
+#define J722S_SERDES1_LANE0_QSGMII_LANE1 0x1
+
#endif /* DTS_ARM64_TI_K3_SERDES_H */
--
2.40.1
J722S SoC has two instances of SERDES namely SERDES0 and SERDES1 and one
instance of PCIe namely PCIe0. Both SERDES0 and SERDES1 are single lane
SERDES. The PCIe0 instance of PCIe is a Gen3 single lane PCIe controller.
Since SERDES and PCIe are not present on AM62P SoC, add the device-tree
nodes corresponding to them in the J722S SoC specific "k3-j722s-main.dtsi"
file.
Co-developed-by: Ravi Gunasekaran <[email protected]>
Signed-off-by: Ravi Gunasekaran <[email protected]>
Signed-off-by: Siddharth Vadapalli <[email protected]>
---
v3:
https://lore.kernel.org/r/[email protected]/
https://lore.kernel.org/r/[email protected]/
and
https://lore.kernel.org/r/[email protected]/
Changes since v3:
- The k3-j722s-main.dtsi specific changes in the above patches have been
squashed into this patch.
arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 131 ++++++++++++++++++++++
1 file changed, 131 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
index 3ca3f0041956..91489014f09e 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
@@ -4,7 +4,121 @@
* Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy-ti.h>
+
+/ {
+ serdes_refclk: clk-0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+};
+
&cbass_main {
+ serdes_wiz0: phy@f000000 {
+ compatible = "ti,am64-wiz-10g";
+ ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ num-lanes = <1>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+
+ assigned-clocks = <&k3_clks 279 1>;
+ assigned-clock-parents = <&k3_clks 279 5>;
+
+ serdes0: serdes@f000000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x0f000000 0x00010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz0 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 279 1>,
+ <&k3_clks 279 1>,
+ <&k3_clks 279 1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled"; /* Needs lane config */
+ };
+ };
+
+ serdes_wiz1: phy@f010000 {
+ compatible = "ti,am64-wiz-10g";
+ ranges = <0x0f010000 0x0 0x0f010000 0x00010000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ num-lanes = <1>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+
+ assigned-clocks = <&k3_clks 280 1>;
+ assigned-clock-parents = <&k3_clks 280 5>;
+
+ serdes1: serdes@f010000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x0f010000 0x00010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz1 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 280 1>,
+ <&k3_clks 280 1>,
+ <&k3_clks 280 1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+ };
+ };
+
+ pcie0_rc: pcie@f102000 {
+ compatible = "ti,j722s-pcie-host", "ti,j721e-pcie-host";
+ reg = <0x00 0x0f102000 0x00 0x1000>,
+ <0x00 0x0f100000 0x00 0x400>,
+ <0x00 0x0d000000 0x00 0x00800000>,
+ <0x00 0x68000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
+ <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ max-link-speed = <3>;
+ num-lanes = <1>;
+ power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 259 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>;
+ clock-names = "fck", "pcie_refclk";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x104c>;
+ device-id = <0xb010>;
+ cdns,no-bar-match-nbits = <64>;
+ ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
+ msi-map = <0x0 &gic_its 0x0 0x10000>;
+ status = "disabled";
+ };
+
usbss1: usb@f920000 {
compatible = "ti,j721e-usb";
reg = <0x00 0x0f920000 0x00 0x100>;
@@ -37,3 +151,20 @@ usb1: usb@31200000{
};
};
};
+
+&main_conf {
+ serdes_ln_ctrl: mux-controller@4080 {
+ compatible = "reg-mux";
+ reg = <0x4080 0x14>;
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x00 0x3>, /* SERDES0 lane0 select */
+ <0x10 0x3>; /* SERDES1 lane0 select */
+ };
+};
+
+&wkup_conf {
+ pcie0_ctrl: pcie0-ctrl@4070 {
+ compatible = "ti,j784s4-pcie-ctrl", "syscon";
+ reg = <0x4070 0x4>;
+ };
+};
--
2.40.1
Enable PCIe0 instance of PCIe in Root Complex mode of operation with Lane 0
of the SERDES1 instance of SERDES. Also enable USB0 instance of USB to
interface with the Type-C port via the USB hub, by configuring the pin P05
of the GPIO expander on the EVM. Enable USB1 instance of USB in SuperSpeed
mode of operation with Lane 0 of the SERDES0 instance of SERDES.
Co-developed-by: Ravi Gunasekaran <[email protected]>
Signed-off-by: Ravi Gunasekaran <[email protected]>
Signed-off-by: Siddharth Vadapalli <[email protected]>
---
v3:
https://lore.kernel.org/r/[email protected]/
and
https://lore.kernel.org/r/[email protected]/
Changes since v3:
- Above patches have been squashed into this patch.
arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 72 +++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
index bf3c246d13d1..3145e680e2d3 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
@@ -9,7 +9,9 @@
/dts-v1/;
#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy.h>
#include "k3-j722s.dtsi"
+#include "k3-serdes.h"
/ {
compatible = "ti,j722s-evm", "ti,j722s";
@@ -202,6 +204,12 @@ J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */
J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */
>;
};
+
+ main_usb1_pins_default: main-usb1-default-pins {
+ pinctrl-single,pins = <
+ J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */
+ >;
+ };
};
&cpsw3g {
@@ -301,6 +309,13 @@ exp1: gpio@23 {
"PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#",
"ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN",
"PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ";
+
+ p05-hog {
+ /* P05 - USB2.0_MUX_SEL */
+ gpio-hog;
+ gpios = <5 GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
};
};
@@ -384,3 +399,60 @@ &sdhci1 {
status = "okay";
bootph-all;
};
+
+&serdes_ln_ctrl {
+ idle-states = <J722S_SERDES0_LANE0_USB>,
+ <J722S_SERDES1_LANE0_PCIE0_LANE0>;
+};
+
+&serdes0 {
+ status = "okay";
+ serdes0_usb_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
+&serdes1 {
+ serdes1_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz1 1>;
+ };
+};
+
+&pcie0_rc {
+ status = "okay";
+ reset-gpios = <&exp1 18 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes1_pcie_link>;
+ phy-names = "pcie-phy";
+};
+
+&usbss0 {
+ ti,vbus-divider;
+ status = "okay";
+};
+
+&usb0 {
+ dr_mode = "otg";
+ usb-role-switch;
+};
+
+&usbss1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usb1_pins_default>;
+ ti,vbus-divider;
+ status = "okay";
+};
+
+&usb1 {
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+ phys = <&serdes0_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
--
2.40.1
On 6/1/24 7:15 AM, Siddharth Vadapalli wrote:
> J722S SoC has two instances of SERDES namely SERDES0 and SERDES1 and one
> instance of PCIe namely PCIe0. Both SERDES0 and SERDES1 are single lane
> SERDES. The PCIe0 instance of PCIe is a Gen3 single lane PCIe controller.
>
> Since SERDES and PCIe are not present on AM62P SoC, add the device-tree
> nodes corresponding to them in the J722S SoC specific "k3-j722s-main.dtsi"
> file.
>
> Co-developed-by: Ravi Gunasekaran <[email protected]>
> Signed-off-by: Ravi Gunasekaran <[email protected]>
> Signed-off-by: Siddharth Vadapalli <[email protected]>
> ---
> v3:
> https://lore.kernel.org/r/[email protected]/
> https://lore.kernel.org/r/[email protected]/
> and
> https://lore.kernel.org/r/[email protected]/
> Changes since v3:
> - The k3-j722s-main.dtsi specific changes in the above patches have been
> squashed into this patch.
>
> arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 131 ++++++++++++++++++++++
> 1 file changed, 131 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> index 3ca3f0041956..91489014f09e 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
> @@ -4,7 +4,121 @@
> * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
> */
>
> +#include <dt-bindings/phy/phy-cadence.h>
> +#include <dt-bindings/phy/phy-ti.h>
> +
> +/ {
> + serdes_refclk: clk-0 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <0>;
> + };
> +};
> +
> &cbass_main {
> + serdes_wiz0: phy@f000000 {
> + compatible = "ti,am64-wiz-10g";
> + ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
> + clock-names = "fck", "core_ref_clk", "ext_ref_clk";
> + num-lanes = <1>;
> + #reset-cells = <1>;
> + #clock-cells = <1>;
> +
> + assigned-clocks = <&k3_clks 279 1>;
> + assigned-clock-parents = <&k3_clks 279 5>;
> +
> + serdes0: serdes@f000000 {
> + compatible = "ti,j721e-serdes-10g";
> + reg = <0x0f000000 0x00010000>;
> + reg-names = "torrent_phy";
> + resets = <&serdes_wiz0 0>;
> + reset-names = "torrent_reset";
> + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
> + clock-names = "refclk", "phy_en_refclk";
> + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
> + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
> + assigned-clock-parents = <&k3_clks 279 1>,
> + <&k3_clks 279 1>,
> + <&k3_clks 279 1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #clock-cells = <1>;
> +
> + status = "disabled"; /* Needs lane config */
Does the other SERDES (serdes1) not need this config? It looks like
it does in the board file.. If so disable it too.
Andrew
> + };
> + };
> +
> + serdes_wiz1: phy@f010000 {
> + compatible = "ti,am64-wiz-10g";
> + ranges = <0x0f010000 0x0 0x0f010000 0x00010000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>;
> + clock-names = "fck", "core_ref_clk", "ext_ref_clk";
> + num-lanes = <1>;
> + #reset-cells = <1>;
> + #clock-cells = <1>;
> +
> + assigned-clocks = <&k3_clks 280 1>;
> + assigned-clock-parents = <&k3_clks 280 5>;
> +
> + serdes1: serdes@f010000 {
> + compatible = "ti,j721e-serdes-10g";
> + reg = <0x0f010000 0x00010000>;
> + reg-names = "torrent_phy";
> + resets = <&serdes_wiz1 0>;
> + reset-names = "torrent_reset";
> + clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
> + clock-names = "refclk", "phy_en_refclk";
> + assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
> + <&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
> + assigned-clock-parents = <&k3_clks 280 1>,
> + <&k3_clks 280 1>,
> + <&k3_clks 280 1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #clock-cells = <1>;
> + };
> + };
> +
> + pcie0_rc: pcie@f102000 {
> + compatible = "ti,j722s-pcie-host", "ti,j721e-pcie-host";
> + reg = <0x00 0x0f102000 0x00 0x1000>,
> + <0x00 0x0f100000 0x00 0x400>,
> + <0x00 0x0d000000 0x00 0x00800000>,
> + <0x00 0x68000000 0x00 0x00001000>;
> + reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
> + ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
> + <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
> + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
> + interrupt-names = "link_state";
> + interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
> + device_type = "pci";
> + max-link-speed = <3>;
> + num-lanes = <1>;
> + power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 259 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>;
> + clock-names = "fck", "pcie_refclk";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + bus-range = <0x0 0xff>;
> + vendor-id = <0x104c>;
> + device-id = <0xb010>;
> + cdns,no-bar-match-nbits = <64>;
> + ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
> + msi-map = <0x0 &gic_its 0x0 0x10000>;
> + status = "disabled";
> + };
> +
> usbss1: usb@f920000 {
> compatible = "ti,j721e-usb";
> reg = <0x00 0x0f920000 0x00 0x100>;
> @@ -37,3 +151,20 @@ usb1: usb@31200000{
> };
> };
> };
> +
> +&main_conf {
> + serdes_ln_ctrl: mux-controller@4080 {
> + compatible = "reg-mux";
> + reg = <0x4080 0x14>;
> + #mux-control-cells = <1>;
> + mux-reg-masks = <0x00 0x3>, /* SERDES0 lane0 select */
> + <0x10 0x3>; /* SERDES1 lane0 select */
> + };
> +};
> +
> +&wkup_conf {
> + pcie0_ctrl: pcie0-ctrl@4070 {
> + compatible = "ti,j784s4-pcie-ctrl", "syscon";
> + reg = <0x4070 0x4>;
> + };
> +};
On 6/1/24 7:15 AM, Siddharth Vadapalli wrote:
> Enable PCIe0 instance of PCIe in Root Complex mode of operation with Lane 0
> of the SERDES1 instance of SERDES. Also enable USB0 instance of USB to
> interface with the Type-C port via the USB hub, by configuring the pin P05
> of the GPIO expander on the EVM. Enable USB1 instance of USB in SuperSpeed
> mode of operation with Lane 0 of the SERDES0 instance of SERDES.
>
> Co-developed-by: Ravi Gunasekaran <[email protected]>
> Signed-off-by: Ravi Gunasekaran <[email protected]>
> Signed-off-by: Siddharth Vadapalli <[email protected]>
> ---
> v3:
> https://lore.kernel.org/r/[email protected]/
> and
> https://lore.kernel.org/r/[email protected]/
> Changes since v3:
> - Above patches have been squashed into this patch.
>
> arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 72 +++++++++++++++++++++++++
> 1 file changed, 72 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> index bf3c246d13d1..3145e680e2d3 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> @@ -9,7 +9,9 @@
> /dts-v1/;
>
> #include <dt-bindings/net/ti-dp83867.h>
> +#include <dt-bindings/phy/phy.h>
> #include "k3-j722s.dtsi"
> +#include "k3-serdes.h"
>
> / {
> compatible = "ti,j722s-evm", "ti,j722s";
> @@ -202,6 +204,12 @@ J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */
> J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */
> >;
> };
> +
> + main_usb1_pins_default: main-usb1-default-pins {
> + pinctrl-single,pins = <
> + J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */
> + >;
> + };
> };
>
> &cpsw3g {
> @@ -301,6 +309,13 @@ exp1: gpio@23 {
> "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#",
> "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN",
> "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ";
> +
> + p05-hog {
> + /* P05 - USB2.0_MUX_SEL */
> + gpio-hog;
> + gpios = <5 GPIO_ACTIVE_HIGH>;
> + output-high;
> + };
> };
> };
>
> @@ -384,3 +399,60 @@ &sdhci1 {
> status = "okay";
> bootph-all;
> };
> +
> +&serdes_ln_ctrl {
> + idle-states = <J722S_SERDES0_LANE0_USB>,
> + <J722S_SERDES1_LANE0_PCIE0_LANE0>;
> +};
> +
> +&serdes0 {
> + status = "okay";
> + serdes0_usb_link: phy@0 {
> + reg = <0>;
> + cdns,num-lanes = <1>;
> + #phy-cells = <0>;
> + cdns,phy-type = <PHY_TYPE_USB3>;
> + resets = <&serdes_wiz0 1>;
> + };
> +};
> +
> +&serdes1 {
> + serdes1_pcie_link: phy@0 {
> + reg = <0>;
> + cdns,num-lanes = <1>;
> + #phy-cells = <0>;
> + cdns,phy-type = <PHY_TYPE_PCIE>;
> + resets = <&serdes_wiz1 1>;
> + };
> +};
> +
> +&pcie0_rc {
> + status = "okay";
As much as I like these at the top, the new format rules seems to
suggest "status" properties should go at the bottom of the node.
Andrew
> + reset-gpios = <&exp1 18 GPIO_ACTIVE_HIGH>;
> + phys = <&serdes1_pcie_link>;
> + phy-names = "pcie-phy";
> +};
> +
> +&usbss0 {
> + ti,vbus-divider;
> + status = "okay";
> +};
> +
> +&usb0 {
> + dr_mode = "otg";
> + usb-role-switch;
> +};
> +
> +&usbss1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_usb1_pins_default>;
> + ti,vbus-divider;
> + status = "okay";
> +};
> +
> +&usb1 {
> + dr_mode = "host";
> + maximum-speed = "super-speed";
> + phys = <&serdes0_usb_link>;
> + phy-names = "cdns3,usb3-phy";
> +};
On Mon, Jun 03, 2024 at 09:17:43AM -0500, Andrew Davis wrote:
> On 6/1/24 7:15 AM, Siddharth Vadapalli wrote:
> > J722S SoC has two instances of SERDES namely SERDES0 and SERDES1 and one
> > instance of PCIe namely PCIe0. Both SERDES0 and SERDES1 are single lane
> > SERDES. The PCIe0 instance of PCIe is a Gen3 single lane PCIe controller.
> >
[...]
> > +
> > + serdes0: serdes@f000000 {
> > + compatible = "ti,j721e-serdes-10g";
> > + reg = <0x0f000000 0x00010000>;
> > + reg-names = "torrent_phy";
> > + resets = <&serdes_wiz0 0>;
> > + reset-names = "torrent_reset";
> > + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
> > + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
> > + clock-names = "refclk", "phy_en_refclk";
> > + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
> > + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
> > + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
> > + assigned-clock-parents = <&k3_clks 279 1>,
> > + <&k3_clks 279 1>,
> > + <&k3_clks 279 1>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + #clock-cells = <1>;
> > +
> > + status = "disabled"; /* Needs lane config */
>
> Does the other SERDES (serdes1) not need this config? It looks like
> it does in the board file.. If so disable it too.
The "lane config" being referred to here is set by the "serdes_ln_ctrl"
mux. The idle-states being set in the board file match the reset values
of the mux, so it is not technically necessary to disable it. However, I
will go ahead and disable SERDES1 as well and enable it in the board file
in the v5 series. Thank you for the review.
[...]
Regards,
Siddharth.
On Mon, Jun 03, 2024 at 09:21:11AM -0500, Andrew Davis wrote:
> On 6/1/24 7:15 AM, Siddharth Vadapalli wrote:
> > Enable PCIe0 instance of PCIe in Root Complex mode of operation with Lane 0
> > of the SERDES1 instance of SERDES. Also enable USB0 instance of USB to
> > interface with the Type-C port via the USB hub, by configuring the pin P05
> > of the GPIO expander on the EVM. Enable USB1 instance of USB in SuperSpeed
[...]
> > +
> > +&serdes0 {
> > + status = "okay";
> > + serdes0_usb_link: phy@0 {
> > + reg = <0>;
> > + cdns,num-lanes = <1>;
> > + #phy-cells = <0>;
> > + cdns,phy-type = <PHY_TYPE_USB3>;
> > + resets = <&serdes_wiz0 1>;
> > + };
> > +};
> > +
> > +&serdes1 {
> > + serdes1_pcie_link: phy@0 {
> > + reg = <0>;
> > + cdns,num-lanes = <1>;
> > + #phy-cells = <0>;
> > + cdns,phy-type = <PHY_TYPE_PCIE>;
> > + resets = <&serdes_wiz1 1>;
> > + };
> > +};
> > +
> > +&pcie0_rc {
> > + status = "okay";
>
> As much as I like these at the top, the new format rules seems to
> suggest "status" properties should go at the bottom of the node.
I failed to notice that. Thank you for pointing this out. I will fix
this in the v5 series.
[...]
Regards,
Siddharth.