These series add sdmmc, sdio, and other device nodes support for
rk322x SoCs, and also introduce rk3229 basic dtsi file specifically.
David Wu (1):
ARM: dts: rockchip: Add io-domain node for rk3228
Finley Xiao (1):
ARM: dts: rockchip: add efuse device node for rk3228
Frank Wang (1):
ARM: dts: rockchip: add basic dtsi file for RK3229 SoC
Shawn Lin (3):
Documentation: rockchip-dw-mshc: add description for rk3228
ARM: dts: rockchip: fix compatible string for eMMC node of rk3228 SoC
ARM: dts: rockchip: add sdmmc and sdio nodes for rk3228 SoC
.../devicetree/bindings/mmc/rockchip-dw-mshc.txt | 1 +
arch/arm/boot/dts/rk3229-evb.dts | 2 +-
arch/arm/boot/dts/rk3229.dtsi | 110 +++++++++++++++++++++
arch/arm/boot/dts/rk322x.dtsi | 84 +++++++++++++++-
4 files changed, 195 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/boot/dts/rk3229.dtsi
--
2.0.0
From: Shawn Lin <[email protected]>
Add "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc" for
dwmmc on rk322x platform.
Signed-off-by: Shawn Lin <[email protected]>
---
Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
index 520d61d..ce30dff 100644
--- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
@@ -15,6 +15,7 @@ Required Properties:
- "rockchip,rk3288-dw-mshc": for Rockchip RK3288
- "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RV1108
- "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3036
+ - "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK322X
- "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368
- "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3399
--
2.0.0
From: Shawn Lin <[email protected]>
This patch adds sdmmc/sdio controller nodes for rk3228 SoC.
Signed-off-by: Shawn Lin <[email protected]>
---
arch/arm/boot/dts/rk322x.dtsi | 60 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index a812422..5e7b54c 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -500,6 +500,32 @@
status = "disabled";
};
+ sdmmc: dwmmc@30000000 {
+ compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x30000000 0x4000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ fifo-depth = <0x100>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
+ status = "disabled";
+ };
+
+ sdio: dwmmc@30010000 {
+ compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x30010000 0x4000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
+ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ fifo-depth = <0x100>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
+ status = "disabled";
+ };
+
emmc: dwmmc@30020000 {
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30020000 0x4000>;
@@ -710,6 +736,40 @@
drive-strength = <12>;
};
+ sdmmc {
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
+ };
+
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
+ };
+
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+ <1 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+ <1 20 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+ <1 21 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
+ };
+ };
+
+ sdio {
+ sdio_clk: sdio-clk {
+ rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
+ };
+
+ sdio_cmd: sdio-cmd {
+ rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
+ };
+
+ sdio_bus4: sdio-bus4 {
+ rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+ <3 3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+ <3 4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+ <3 5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
+ };
+ };
+
emmc {
emmc_clk: emmc-clk {
rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
--
2.0.0
From: Shawn Lin <[email protected]>
This adds amend compatible content for eMMC of RK3228 SoC.
Signed-off-by: Shawn Lin <[email protected]>
---
arch/arm/boot/dts/rk322x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index f3e4ffd..a812422 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -501,7 +501,7 @@
};
emmc: dwmmc@30020000 {
- compatible = "rockchip,rk3288-dw-mshc";
+ compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30020000 0x4000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <37500000>;
--
2.0.0
Due to some tiny differences between RK3228 and RK3229, this patch
adds a basic dtsi file which includes a new CPU opp table and PSCI
brought up support for RK3229.
Signed-off-by: Frank Wang <[email protected]>
---
arch/arm/boot/dts/rk3229-evb.dts | 2 +-
arch/arm/boot/dts/rk3229.dtsi | 110 +++++++++++++++++++++++++++++++++++++++
2 files changed, 111 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/rk3229.dtsi
diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts
index 1b55192..82e8a53 100644
--- a/arch/arm/boot/dts/rk3229-evb.dts
+++ b/arch/arm/boot/dts/rk3229-evb.dts
@@ -40,7 +40,7 @@
/dts-v1/;
-#include "rk322x.dtsi"
+#include "rk3229.dtsi"
/ {
model = "Rockchip RK3229 Evaluation board";
diff --git a/arch/arm/boot/dts/rk3229.dtsi b/arch/arm/boot/dts/rk3229.dtsi
new file mode 100644
index 0000000..d43d133
--- /dev/null
+++ b/arch/arm/boot/dts/rk3229.dtsi
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "rk322x.dtsi"
+
+/ {
+ compatible = "rockchip,rk3229";
+
+ /delete-node/ opp-table0;
+
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <950000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <975000>;
+ };
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1175000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1275000>;
+ };
+ opp-1296000000 {
+ opp-hz = /bits/ 64 <1296000000>;
+ opp-microvolt = <1325000>;
+ };
+ opp-1392000000 {
+ opp-hz = /bits/ 64 <1392000000>;
+ opp-microvolt = <1375000>;
+ };
+ opp-1464000000 {
+ opp-hz = /bits/ 64 <1464000000>;
+ opp-microvolt = <1400000>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+};
+
+&cpu0 {
+ enable-method = "psci";
+};
+
+&cpu1 {
+ enable-method = "psci";
+};
+
+&cpu2 {
+ enable-method = "psci";
+};
+
+&cpu3 {
+ enable-method = "psci";
+};
--
2.0.0
From: David Wu <[email protected]>
This patch adds io-domain support for rk3228 SoC.
Signed-off-by: David Wu <[email protected]>
Signed-off-by: Frank Wang <[email protected]>
---
arch/arm/boot/dts/rk322x.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 5e7b54c..c2a78f4 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -215,6 +215,11 @@
#address-cells = <1>;
#size-cells = <1>;
+ io_domains: io-domains {
+ compatible = "rockchip,rk3228-io-voltage-domain";
+ status = "disabled";
+ };
+
u2phy0: usb2-phy@760 {
compatible = "rockchip,rk3228-usb2phy";
reg = <0x0760 0x0c>;
--
2.0.0
From: Finley Xiao <[email protected]>
Add a efuse node in the device tree for the rk3228 SoC.
Signed-off-by: Finley Xiao <[email protected]>
---
arch/arm/boot/dts/rk322x.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index c2a78f4..dad195e 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -314,6 +314,23 @@
status = "disabled";
};
+ efuse: efuse@11040000 {
+ compatible = "rockchip,rk322x-efuse";
+ reg = <0x11040000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cru PCLK_EFUSE_256>;
+ clock-names = "pclk_efuse";
+
+ /* Data cells */
+ efuse_id: id@7 {
+ reg = <0x7 0x10>;
+ };
+ cpu_leakage: cpu_leakage@17 {
+ reg = <0x17 0x1>;
+ };
+ };
+
i2c0: i2c@11050000 {
compatible = "rockchip,rk3228-i2c";
reg = <0x11050000 0x1000>;
--
2.0.0
Hi Frank,
Am Donnerstag, 15. Juni 2017, 15:16:16 CEST schrieb Frank Wang:
> From: Shawn Lin <[email protected]>
>
> Add "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc" for
> dwmmc on rk322x platform.
>
> Signed-off-by: Shawn Lin <[email protected]>
> ---
> Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
> b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt index
> 520d61d..ce30dff 100644
> --- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
> +++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
> @@ -15,6 +15,7 @@ Required Properties:
> - "rockchip,rk3288-dw-mshc": for Rockchip RK3288
> - "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip
> RV1108 - "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip
> RK3036 + - "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc": for
> Rockchip RK322X - "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for
> Rockchip RK3368 - "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for
> Rockchip RK3399
you might want to rebase this patch on top of Ulfs next branch [0],
as there is also the support for the rk3328 in there now.
Otherwise looks good to me, so
Reviewed-by: Heiko Stuebner <[email protected]>
[0] https://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc.git/log/?h=next
Hi Frank,
Am Donnerstag, 15. Juni 2017, 15:23:16 CEST schrieb Frank Wang:
> From: Finley Xiao <[email protected]>
>
> Add a efuse node in the device tree for the rk3228 SoC.
>
> Signed-off-by: Finley Xiao <[email protected]>
> ---
> arch/arm/boot/dts/rk322x.dtsi | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
> index c2a78f4..dad195e 100644
> --- a/arch/arm/boot/dts/rk322x.dtsi
> +++ b/arch/arm/boot/dts/rk322x.dtsi
> @@ -314,6 +314,23 @@
> status = "disabled";
> };
>
> + efuse: efuse@11040000 {
> + compatible = "rockchip,rk322x-efuse";
was this binding included already? Simply because compatibles should
not contain placeholders, so rockchip,rk3228-efuse please - same for
the driver side.
Heiko
> + reg = <0x11040000 0x20>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + clocks = <&cru PCLK_EFUSE_256>;
> + clock-names = "pclk_efuse";
> +
> + /* Data cells */
> + efuse_id: id@7 {
> + reg = <0x7 0x10>;
> + };
> + cpu_leakage: cpu_leakage@17 {
> + reg = <0x17 0x1>;
> + };
> + };
> +
> i2c0: i2c@11050000 {
> compatible = "rockchip,rk3228-i2c";
> reg = <0x11050000 0x1000>;
>
Hi Heiko,
On 2017/6/15 23:10, Heiko Stuebner wrote:
> Hi Frank,
>
> Am Donnerstag, 15. Juni 2017, 15:23:16 CEST schrieb Frank Wang:
>> From: Finley Xiao <[email protected]>
>>
>> Add a efuse node in the device tree for the rk3228 SoC.
>>
>> Signed-off-by: Finley Xiao <[email protected]>
>> ---
>> arch/arm/boot/dts/rk322x.dtsi | 17 +++++++++++++++++
>> 1 file changed, 17 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
>> index c2a78f4..dad195e 100644
>> --- a/arch/arm/boot/dts/rk322x.dtsi
>> +++ b/arch/arm/boot/dts/rk322x.dtsi
>> @@ -314,6 +314,23 @@
>> status = "disabled";
>> };
>>
>> + efuse: efuse@11040000 {
>> + compatible = "rockchip,rk322x-efuse";
> was this binding included already? Simply because compatibles should
> not contain placeholders, so rockchip,rk3228-efuse please - same for
> the driver side.
Actually, I always remember it should be without placeholders from the
first time you commented :-)
but I saw that the binding and driver (rockchip,rk322x-efuse) have
already been applied, so I send this one keep the same with driver side.
Shall I resend a new patch to correct both of them to
'rockchip,rk3228-efuse' ?
BR.
Frank
>
> Heiko
>
>
>> + reg = <0x11040000 0x20>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + clocks = <&cru PCLK_EFUSE_256>;
>> + clock-names = "pclk_efuse";
>> +
>> + /* Data cells */
>> + efuse_id: id@7 {
>> + reg = <0x7 0x10>;
>> + };
>> + cpu_leakage: cpu_leakage@17 {
>> + reg = <0x17 0x1>;
>> + };
>> + };
>> +
>> i2c0: i2c@11050000 {
>> compatible = "rockchip,rk3228-i2c";
>> reg = <0x11050000 0x1000>;
>>
Am Freitag, 16. Juni 2017, 17:24:23 CEST schrieb Frank Wang:
> Hi Heiko,
>
> On 2017/6/15 23:10, Heiko Stuebner wrote:
> > Hi Frank,
> >
> > Am Donnerstag, 15. Juni 2017, 15:23:16 CEST schrieb Frank Wang:
> >> From: Finley Xiao <[email protected]>
> >>
> >> Add a efuse node in the device tree for the rk3228 SoC.
> >>
> >> Signed-off-by: Finley Xiao <[email protected]>
> >> ---
> >>
> >> arch/arm/boot/dts/rk322x.dtsi | 17 +++++++++++++++++
> >> 1 file changed, 17 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/rk322x.dtsi
> >> b/arch/arm/boot/dts/rk322x.dtsi
> >> index c2a78f4..dad195e 100644
> >> --- a/arch/arm/boot/dts/rk322x.dtsi
> >> +++ b/arch/arm/boot/dts/rk322x.dtsi
> >> @@ -314,6 +314,23 @@
> >>
> >> status = "disabled";
> >>
> >> };
> >>
> >> + efuse: efuse@11040000 {
> >> + compatible = "rockchip,rk322x-efuse";
> >
> > was this binding included already? Simply because compatibles should
> > not contain placeholders, so rockchip,rk3228-efuse please - same for
> > the driver side.
>
> Actually, I always remember it should be without placeholders from the
> first time you commented :-)
> but I saw that the binding and driver (rockchip,rk322x-efuse) have
> already been applied, so I send this one keep the same with driver side.
> Shall I resend a new patch to correct both of them to
> 'rockchip,rk3228-efuse' ?
Yes please :-) .
As it was probably applied for 4.13, changing the compatible shouldn't be
a problem.
Thanks
Heiko
>
>
> BR.
> Frank
>
> > Heiko
> >
> >> + reg = <0x11040000 0x20>;
> >> + #address-cells = <1>;
> >> + #size-cells = <1>;
> >> + clocks = <&cru PCLK_EFUSE_256>;
> >> + clock-names = "pclk_efuse";
> >> +
> >> + /* Data cells */
> >> + efuse_id: id@7 {
> >> + reg = <0x7 0x10>;
> >> + };
> >> + cpu_leakage: cpu_leakage@17 {
> >> + reg = <0x17 0x1>;
> >> + };
> >> + };
> >> +
> >>
> >> i2c0: i2c@11050000 {
> >>
> >> compatible = "rockchip,rk3228-i2c";
> >> reg = <0x11050000 0x1000>;
Am Donnerstag, 15. Juni 2017, 15:16:15 CEST schrieb Frank Wang:
> Due to some tiny differences between RK3228 and RK3229, this patch
> adds a basic dtsi file which includes a new CPU opp table and PSCI
> brought up support for RK3229.
>
> Signed-off-by: Frank Wang <[email protected]>
> ---
> arch/arm/boot/dts/rk3229-evb.dts | 2 +-
> arch/arm/boot/dts/rk3229.dtsi | 110 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 111 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/boot/dts/rk3229.dtsi
>
> diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts
> index 1b55192..82e8a53 100644
> --- a/arch/arm/boot/dts/rk3229-evb.dts
> +++ b/arch/arm/boot/dts/rk3229-evb.dts
> @@ -40,7 +40,7 @@
>
> /dts-v1/;
>
> -#include "rk322x.dtsi"
> +#include "rk3229.dtsi"
>
> / {
> model = "Rockchip RK3229 Evaluation board";
> diff --git a/arch/arm/boot/dts/rk3229.dtsi b/arch/arm/boot/dts/rk3229.dtsi
> new file mode 100644
> index 0000000..d43d133
> --- /dev/null
> +++ b/arch/arm/boot/dts/rk3229.dtsi
> @@ -0,0 +1,110 @@
> +/*
> + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include "rk322x.dtsi"
> +
> +/ {
> + compatible = "rockchip,rk3229";
> +
> + /delete-node/ opp-table0;
> +
> + cpu0_opp_table: opp_table0 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-408000000 {
> + opp-hz = /bits/ 64 <408000000>;
> + opp-microvolt = <950000>;
> + clock-latency-ns = <40000>;
> + opp-suspend;
> + };
> + opp-600000000 {
> + opp-hz = /bits/ 64 <600000000>;
> + opp-microvolt = <975000>;
> + };
> + opp-816000000 {
> + opp-hz = /bits/ 64 <816000000>;
> + opp-microvolt = <1000000>;
> + };
> + opp-1008000000 {
> + opp-hz = /bits/ 64 <1008000000>;
> + opp-microvolt = <1175000>;
> + };
> + opp-1200000000 {
> + opp-hz = /bits/ 64 <1200000000>;
> + opp-microvolt = <1275000>;
> + };
> + opp-1296000000 {
> + opp-hz = /bits/ 64 <1296000000>;
> + opp-microvolt = <1325000>;
> + };
> + opp-1392000000 {
> + opp-hz = /bits/ 64 <1392000000>;
> + opp-microvolt = <1375000>;
> + };
> + opp-1464000000 {
> + opp-hz = /bits/ 64 <1464000000>;
> + opp-microvolt = <1400000>;
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0", "arm,psci-0.2";
> + method = "smc";
> + };
> +};
> +
> +&cpu0 {
> + enable-method = "psci";
> +};
Hmm, I don't really understand this.
What method of core-bringup does the rk3228 use? In the current
rk322x.dtsi there is no enable-method at all defined.
So is the rk3228 firmware using a different method than the rk3229?
And out of curiosity as this is a arm32 without atf, is the psci
implementation (for uboot?) you're using available somewhere?
Thanks
Heiko
> +
> +&cpu1 {
> + enable-method = "psci";
> +};
> +
> +&cpu2 {
> + enable-method = "psci";
> +};
> +
> +&cpu3 {
> + enable-method = "psci";
> +};
>
Hi Heiko,
On 2017/6/18 2:12, Heiko Stuebner wrote:
> Am Donnerstag, 15. Juni 2017, 15:16:15 CEST schrieb Frank Wang:
>> Due to some tiny differences between RK3228 and RK3229, this patch
>> adds a basic dtsi file which includes a new CPU opp table and PSCI
>> brought up support for RK3229.
>>
>> Signed-off-by: Frank Wang <[email protected]>
>> ---
>> arch/arm/boot/dts/rk3229-evb.dts | 2 +-
>> arch/arm/boot/dts/rk3229.dtsi | 110 +++++++++++++++++++++++++++++++++++++++
>> 2 files changed, 111 insertions(+), 1 deletion(-)
>> create mode 100644 arch/arm/boot/dts/rk3229.dtsi
>>
>> diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts
>> index 1b55192..82e8a53 100644
>> --- a/arch/arm/boot/dts/rk3229-evb.dts
>> +++ b/arch/arm/boot/dts/rk3229-evb.dts
>> @@ -40,7 +40,7 @@
>>
>> /dts-v1/;
>>
>> -#include "rk322x.dtsi"
>> +#include "rk3229.dtsi"
>>
>> / {
>> model = "Rockchip RK3229 Evaluation board";
>> diff --git a/arch/arm/boot/dts/rk3229.dtsi b/arch/arm/boot/dts/rk3229.dtsi
>> new file mode 100644
>> index 0000000..d43d133
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/rk3229.dtsi
>> @@ -0,0 +1,110 @@
>> +/*
>> + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + * a) This library is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> + * This library is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + * b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> + * restriction, including without limitation the rights to use,
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following
>> + * conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> + * included in all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + */
>> +
>> +#include "rk322x.dtsi"
>> +
>> +/ {
>> + compatible = "rockchip,rk3229";
>> +
>> + /delete-node/ opp-table0;
>> +
>> + cpu0_opp_table: opp_table0 {
>> + compatible = "operating-points-v2";
>> + opp-shared;
>> +
>> + opp-408000000 {
>> + opp-hz = /bits/ 64 <408000000>;
>> + opp-microvolt = <950000>;
>> + clock-latency-ns = <40000>;
>> + opp-suspend;
>> + };
>> + opp-600000000 {
>> + opp-hz = /bits/ 64 <600000000>;
>> + opp-microvolt = <975000>;
>> + };
>> + opp-816000000 {
>> + opp-hz = /bits/ 64 <816000000>;
>> + opp-microvolt = <1000000>;
>> + };
>> + opp-1008000000 {
>> + opp-hz = /bits/ 64 <1008000000>;
>> + opp-microvolt = <1175000>;
>> + };
>> + opp-1200000000 {
>> + opp-hz = /bits/ 64 <1200000000>;
>> + opp-microvolt = <1275000>;
>> + };
>> + opp-1296000000 {
>> + opp-hz = /bits/ 64 <1296000000>;
>> + opp-microvolt = <1325000>;
>> + };
>> + opp-1392000000 {
>> + opp-hz = /bits/ 64 <1392000000>;
>> + opp-microvolt = <1375000>;
>> + };
>> + opp-1464000000 {
>> + opp-hz = /bits/ 64 <1464000000>;
>> + opp-microvolt = <1400000>;
>> + };
>> + };
>> +
>> + psci {
>> + compatible = "arm,psci-1.0", "arm,psci-0.2";
>> + method = "smc";
>> + };
>> +};
>> +
>> +&cpu0 {
>> + enable-method = "psci";
>> +};
> Hmm, I don't really understand this.
> What method of core-bringup does the rk3228 use? In the current
> rk322x.dtsi there is no enable-method at all defined.
For non-security, the same with rk3036 SoC, we use rk3036-smp method to
bring-up cores, and for security, we use arm-psci method.
As security become more and more important and required, we would prefer
using arm-psci method, and it is also an easy way to use.
> So is the rk3228 firmware using a different method than the rk3229?
No, they are the same. How about I move these changes to rk322x.dtsi?
> And out of curiosity as this is a arm32 without atf, is the psci
> implementation (for uboot?) you're using available somewhere?
Ah, it is included in op-tee :-)
BR.
Frank
>
> Thanks
> Heiko
>
>> +
>> +&cpu1 {
>> + enable-method = "psci";
>> +};
>> +
>> +&cpu2 {
>> + enable-method = "psci";
>> +};
>> +
>> +&cpu3 {
>> + enable-method = "psci";
>> +};
>>
>
Hi Frank,
Am Montag, 19. Juni 2017, 18:34:27 CEST schrieb Frank Wang:
> On 2017/6/18 2:12, Heiko Stuebner wrote:
> > Am Donnerstag, 15. Juni 2017, 15:16:15 CEST schrieb Frank Wang:
> >> Due to some tiny differences between RK3228 and RK3229, this patch
> >> adds a basic dtsi file which includes a new CPU opp table and PSCI
> >> brought up support for RK3229.
> >>
> >> Signed-off-by: Frank Wang <[email protected]>
[...]
> >> + psci {
> >> + compatible = "arm,psci-1.0", "arm,psci-0.2";
> >> + method = "smc";
> >> + };
> >> +};
> >> +
> >> +&cpu0 {
> >> + enable-method = "psci";
> >> +};
> >
> > Hmm, I don't really understand this.
> > What method of core-bringup does the rk3228 use? In the current
> > rk322x.dtsi there is no enable-method at all defined.
>
> For non-security, the same with rk3036 SoC, we use rk3036-smp method to
> bring-up cores, and for security, we use arm-psci method.
> As security become more and more important and required, we would prefer
> using arm-psci method, and it is also an easy way to use.
>
> > So is the rk3228 firmware using a different method than the rk3229?
>
> No, they are the same. How about I move these changes to rk322x.dtsi?
yep, that is what I was getting at with my question ;-)
> > And out of curiosity as this is a arm32 without atf, is the psci
> > implementation (for uboot?) you're using available somewhere?
>
> Ah, it is included in op-tee :-)
Is that super secret or will this be part of the official op-tee [0]
at some point (Similar to the ATF stuff on arm64)?
Heiko
[0] https://github.com/OP-TEE/optee_os/tree/master/core/arch/arm
Hi Heiko,
On 2017/6/19 20:30, Heiko Stübner wrote:
> Hi Frank,
>
> Am Montag, 19. Juni 2017, 18:34:27 CEST schrieb Frank Wang:
>> On 2017/6/18 2:12, Heiko Stuebner wrote:
>>> Am Donnerstag, 15. Juni 2017, 15:16:15 CEST schrieb Frank Wang:
>>>> Due to some tiny differences between RK3228 and RK3229, this patch
>>>> adds a basic dtsi file which includes a new CPU opp table and PSCI
>>>> brought up support for RK3229.
>>>>
>>>> Signed-off-by: Frank Wang<[email protected]>
> [...]
>
>>>> + psci {
>>>> + compatible = "arm,psci-1.0", "arm,psci-0.2";
>>>> + method = "smc";
>>>> + };
>>>> +};
>>>> +
>>>> +&cpu0 {
>>>> + enable-method = "psci";
>>>> +};
>>> Hmm, I don't really understand this.
>>> What method of core-bringup does the rk3228 use? In the current
>>> rk322x.dtsi there is no enable-method at all defined.
>> For non-security, the same with rk3036 SoC, we use rk3036-smp method to
>> bring-up cores, and for security, we use arm-psci method.
>> As security become more and more important and required, we would prefer
>> using arm-psci method, and it is also an easy way to use.
>>
>>> So is the rk3228 firmware using a different method than the rk3229?
>> No, they are the same. How about I move these changes to rk322x.dtsi?
> yep, that is what I was getting at with my question ;-)
>
>
>>> And out of curiosity as this is a arm32 without atf, is the psci
>>> implementation (for uboot?) you're using available somewhere?
>> Ah, it is included in op-tee :-)
> Is that super secret or will this be part of the official op-tee [0]
> at some point (Similar to the ATF stuff on arm64)?
Hmm, the op-tee itself must keep secure, but the psci part in it can be
extracted to public, although it may have a bit of secure risk.
Due to Rockchip have amended the frame of op-tee to support psci, we can
try to upstream these changes to official op-tee or push them to source
codes of Rockchip in git-hub.
BR.
Frank
> Heiko
>
> [0]https://github.com/OP-TEE/optee_os/tree/master/core/arch/arm
>
>
Hi Frank,
Am Dienstag, 20. Juni 2017, 15:13:00 CEST schrieb Frank Wang:
> Hi Heiko,
>
> On 2017/6/19 20:30, Heiko St?bner wrote:
> > Hi Frank,
> >
> > Am Montag, 19. Juni 2017, 18:34:27 CEST schrieb Frank Wang:
> >> On 2017/6/18 2:12, Heiko Stuebner wrote:
> >>> Am Donnerstag, 15. Juni 2017, 15:16:15 CEST schrieb Frank Wang:
> >>>> Due to some tiny differences between RK3228 and RK3229, this patch
> >>>> adds a basic dtsi file which includes a new CPU opp table and PSCI
> >>>> brought up support for RK3229.
> >>>>
> >>>> Signed-off-by: Frank Wang<[email protected]>
> >
> > [...]
> >
> >>>> + psci {
> >>>> + compatible = "arm,psci-1.0", "arm,psci-0.2";
> >>>> + method = "smc";
> >>>> + };
> >>>> +};
> >>>> +
> >>>> +&cpu0 {
> >>>> + enable-method = "psci";
> >>>> +};
> >>>
> >>> Hmm, I don't really understand this.
> >>> What method of core-bringup does the rk3228 use? In the current
> >>> rk322x.dtsi there is no enable-method at all defined.
> >>
> >> For non-security, the same with rk3036 SoC, we use rk3036-smp method to
> >> bring-up cores, and for security, we use arm-psci method.
> >> As security become more and more important and required, we would prefer
> >> using arm-psci method, and it is also an easy way to use.
> >>
> >>> So is the rk3228 firmware using a different method than the rk3229?
> >>
> >> No, they are the same. How about I move these changes to rk322x.dtsi?
> >
> > yep, that is what I was getting at with my question ;-)
> >
> >>> And out of curiosity as this is a arm32 without atf, is the psci
> >>> implementation (for uboot?) you're using available somewhere?
> >>
> >> Ah, it is included in op-tee :-)
> >
> > Is that super secret or will this be part of the official op-tee [0]
> > at some point (Similar to the ATF stuff on arm64)?
>
> Hmm, the op-tee itself must keep secure, but the psci part in it can be
> extracted to public, although it may have a bit of secure risk.
> Due to Rockchip have amended the frame of op-tee to support psci, we can
> try to upstream these changes to official op-tee or push them to source
> codes of Rockchip in git-hub.
I just want to make sure, people can actually create a working system
with this, as there is mainline u-boot support for the rk3228/rk3229 in
the works - hopefully also with SPL support later on.
So I'm wondering how this is supposed to be setup?
On arm64 we now have the SPL load the ATF, which in turn loads uboot, so I
guess the mechanism for the op-tee would be somehow similar? And there all
necessary components are available to build everything from source.
I really don't care about all the other super-secret stuff happening in
that op-tee thingy, but I really want people to be able to build a complete
firmware on their machine, without having to rely on arbitary binary blobs.
Which is something companies adopting Rockchip socs seem to rely on
a lot these days ;-) .
One alternative I can think of, would be to also create a u-boot psci
implementation for arm32, like sunxi [0] and others use for example.
That way people could choose where their psci should come from (u-boot
itself or the op-tee).
Heiko
[0] http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv7/sunxi/psci.c
>
>
> BR.
> Frank
>
> > Heiko
> >
> > [0]https://github.com/OP-TEE/optee_os/tree/master/core/arch/arm
Hi Jacob and Heiko:
On 2017年06月21日 12:11, Jacob Chen wrote:
> Hi,
>
> 2017-06-20 18:48 GMT+08:00 Heiko Stübner <[email protected]
> <mailto:[email protected]>>:
> > Hi Frank,
> >
> > Am Dienstag, 20. Juni 2017, 15:13:00 CEST schrieb Frank Wang:
> >> Hi Heiko,
> >>
> >> On 2017/6/19 20:30, Heiko Stübner wrote:
> >> > Hi Frank,
> >> >
> >> > Am Montag, 19. Juni 2017, 18:34:27 CEST schrieb Frank Wang:
> >> >> On 2017/6/18 2:12, Heiko Stuebner wrote:
> >> >>> Am Donnerstag, 15. Juni 2017, 15:16:15 CEST schrieb Frank Wang:
> >> >>>> Due to some tiny differences between RK3228 and RK3229, this patch
> >> >>>> adds a basic dtsi file which includes a new CPU opp table and PSCI
> >> >>>> brought up support for RK3229.
> >> >>>>
> >> >>>> Signed-off-by: Frank Wang<[email protected]
> <mailto:[email protected]>>
> >> >
> >> > [...]
> >> >
> >> >>>> + psci {
> >> >>>> + compatible = "arm,psci-1.0", "arm,psci-0.2";
> >> >>>> + method = "smc";
> >> >>>> + };
> >> >>>> +};
> >> >>>> +
> >> >>>> +&cpu0 {
> >> >>>> + enable-method = "psci";
> >> >>>> +};
> >> >>>
> >> >>> Hmm, I don't really understand this.
> >> >>> What method of core-bringup does the rk3228 use? In the current
> >> >>> rk322x.dtsi there is no enable-method at all defined.
> >> >>
> >> >> For non-security, the same with rk3036 SoC, we use rk3036-smp
> method to
> >> >> bring-up cores, and for security, we use arm-psci method.
> >> >> As security become more and more important and required, we
> would prefer
> >> >> using arm-psci method, and it is also an easy way to use.
> >> >>
> >> >>> So is the rk3228 firmware using a different method than the rk3229?
> >> >>
> >> >> No, they are the same. How about I move these changes to
> rk322x.dtsi?
> >> >
> >> > yep, that is what I was getting at with my question ;-)
> >> >
> >> >>> And out of curiosity as this is a arm32 without atf, is the psci
> >> >>> implementation (for uboot?) you're using available somewhere?
> >> >>
> >> >> Ah, it is included in op-tee :-)
> >> >
> >> > Is that super secret or will this be part of the official op-tee [0]
> >> > at some point (Similar to the ATF stuff on arm64)?
> >>
> >> Hmm, the op-tee itself must keep secure, but the psci part in it can be
> >> extracted to public, although it may have a bit of secure risk.
> >> Due to Rockchip have amended the frame of op-tee to support psci,
> we can
> >> try to upstream these changes to official op-tee or push them to source
> >> codes of Rockchip in git-hub.
> >
> > I just want to make sure, people can actually create a working system
> > with this, as there is mainline u-boot support for the rk3228/rk3229 in
> > the works - hopefully also with SPL support later on.
> > So I'm wondering how this is supposed to be setup?
> >
> > On arm64 we now have the SPL load the ATF, which in turn loads
> uboot, so I
> > guess the mechanism for the op-tee would be somehow similar? And
> there all
> > necessary components are available to build everything from source.
> >
> > I really don't care about all the other super-secret stuff happening in
> > that op-tee thingy, but I really want people to be able to build a
> complete
> > firmware on their machine, without having to rely on arbitary binary
> blobs.
> >
> > Which is something companies adopting Rockchip socs seem to rely on
> > a lot these days ;-) .
> >
> >
> > One alternative I can think of, would be to also create a u-boot psci
> > implementation for arm32, like sunxi [0] and others use for example.
> > That way people could choose where their psci should come from (u-boot
> > itself or the op-tee).
> >
> >
> > Heiko
> >
> > [0]
> http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv7/sunxi/psci.c
> >
> >>
> >>
> >> BR.
> >> Frank
> >>
> >> > Heiko
> >> >
> >> > [0]https://github.com/OP-TEE/optee_os/tree/master/core/arch/arm
> >
> >
>
> ???? Implement psci in upstream u-boot sounds a good idea.
>
> I don't like the bundled solution, like if I want to enable power
> management in my board, i have to use OP-TEE, then i have to use
> vendor u-boot, then vendor kernel, rootfs, tools......
>
No. The kernel only depends on PSCI. Anyone can implement PSCI firmware
through
OPTEE/Trusty/U-Boot/UEFI or other open source implementation. We don't limit
people use vendor software or not. As Frank said, we will open source
OPTEE which
support PSCI for our chips.
BTW people can implement SMP/suspend function builtin in kernel as
usual. We just
hope use PSCI by default, so we can support TEE more easy as arm64.
Hi,
Am Mittwoch, 21. Juni 2017, 15:29:18 CEST schrieb Huang, Tao:
> Hi Jacob and Heiko:
>
> On 2017年06月21日 12:11, Jacob Chen wrote:
> > Hi,
> >
> > 2017-06-20 18:48 GMT+08:00 Heiko Stübner <[email protected]
> >
> > <mailto:[email protected]>>:
> > > Hi Frank,
> > >
> > > Am Dienstag, 20. Juni 2017, 15:13:00 CEST schrieb Frank Wang:
> > >> Hi Heiko,
> > >>
> > >> On 2017/6/19 20:30, Heiko Stübner wrote:
> > >> > Hi Frank,
> > >> >
> > >> > Am Montag, 19. Juni 2017, 18:34:27 CEST schrieb Frank Wang:
> > >> >> On 2017/6/18 2:12, Heiko Stuebner wrote:
> > >> >>> Am Donnerstag, 15. Juni 2017, 15:16:15 CEST schrieb Frank Wang:
> > >> >>>> Due to some tiny differences between RK3228 and RK3229, this patch
> > >> >>>> adds a basic dtsi file which includes a new CPU opp table and PSCI
> > >> >>>> brought up support for RK3229.
> > >> >>>>
> > >> >>>> Signed-off-by: Frank Wang<[email protected]
> >
> > <mailto:[email protected]>>
> >
> > >> > [...]
> > >> >
> > >> >>>> + psci {
> > >> >>>> + compatible = "arm,psci-1.0", "arm,psci-0.2";
> > >> >>>> + method = "smc";
> > >> >>>> + };
> > >> >>>> +};
> > >> >>>> +
> > >> >>>> +&cpu0 {
> > >> >>>> + enable-method = "psci";
> > >> >>>> +};
> > >> >>>
> > >> >>> Hmm, I don't really understand this.
> > >> >>> What method of core-bringup does the rk3228 use? In the current
> > >> >>> rk322x.dtsi there is no enable-method at all defined.
> > >> >>
> > >> >> For non-security, the same with rk3036 SoC, we use rk3036-smp
> >
> > method to
> >
> > >> >> bring-up cores, and for security, we use arm-psci method.
> > >> >> As security become more and more important and required, we
> >
> > would prefer
> >
> > >> >> using arm-psci method, and it is also an easy way to use.
> > >> >>
> > >> >>> So is the rk3228 firmware using a different method than the rk3229?
> > >> >>
> > >> >> No, they are the same. How about I move these changes to
> >
> > rk322x.dtsi?
> >
> > >> > yep, that is what I was getting at with my question ;-)
> > >> >
> > >> >>> And out of curiosity as this is a arm32 without atf, is the psci
> > >> >>> implementation (for uboot?) you're using available somewhere?
> > >> >>
> > >> >> Ah, it is included in op-tee :-)
> > >> >
> > >> > Is that super secret or will this be part of the official op-tee [0]
> > >> > at some point (Similar to the ATF stuff on arm64)?
> > >>
> > >> Hmm, the op-tee itself must keep secure, but the psci part in it can be
> > >> extracted to public, although it may have a bit of secure risk.
> > >> Due to Rockchip have amended the frame of op-tee to support psci,
> >
> > we can
> >
> > >> try to upstream these changes to official op-tee or push them to source
> > >> codes of Rockchip in git-hub.
> > >
> > > I just want to make sure, people can actually create a working system
> > > with this, as there is mainline u-boot support for the rk3228/rk3229 in
> > > the works - hopefully also with SPL support later on.
> > > So I'm wondering how this is supposed to be setup?
> > >
> > > On arm64 we now have the SPL load the ATF, which in turn loads
> >
> > uboot, so I
> >
> > > guess the mechanism for the op-tee would be somehow similar? And
> >
> > there all
> >
> > > necessary components are available to build everything from source.
> > >
> > > I really don't care about all the other super-secret stuff happening in
> > > that op-tee thingy, but I really want people to be able to build a
> >
> > complete
> >
> > > firmware on their machine, without having to rely on arbitary binary
> >
> > blobs.
> >
> > > Which is something companies adopting Rockchip socs seem to rely on
> > > a lot these days ;-) .
> > >
> > >
> > > One alternative I can think of, would be to also create a u-boot psci
> > > implementation for arm32, like sunxi [0] and others use for example.
> > > That way people could choose where their psci should come from (u-boot
> > > itself or the op-tee).
> > >
> > >
> > > Heiko
> > >
> > > [0]
> >
> > http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/cpu/armv7/sunxi/psci.c
> >
> > >> BR.
> > >> Frank
> > >>
> > >> > Heiko
> > >> >
> > >> > [0]https://github.com/OP-TEE/optee_os/tree/master/core/arch/arm
> >
> > ???? Implement psci in upstream u-boot sounds a good idea.
> >
> > I don't like the bundled solution, like if I want to enable power
> > management in my board, i have to use OP-TEE, then i have to use
> > vendor u-boot, then vendor kernel, rootfs, tools......
>
> No. The kernel only depends on PSCI. Anyone can implement PSCI firmware
> through
> OPTEE/Trusty/U-Boot/UEFI or other open source implementation. We don't limit
> people use vendor software or not. As Frank said, we will open source OPTEE
> which support PSCI for our chips.
That is great to hear. In Franks mail yesterday it didn't sound that certain
yet :-) .
I really only want to make sure people can build a complete firmware from
source. Without having to rely on binary stuff.
So if you're going to release the op-tee variant for it, we should be fine.
As I've also ordered one of the rk3229 tv-boxes for my boardfarm, do you
have any timeframe for that? [Sorry for being pushy :-) ].
> BTW people can implement SMP/suspend function builtin in kernel as
> usual. We just hope use PSCI by default, so we can support TEE more easy
> as arm64.
Yep, having smp in firmware is quite nice, as seen on arm64. So I definitly
encourage this, instead of doing the "legacy" smp option in the kernel.
Thanks
Heiko