Currently the DWC3 driver supports only single port controller which
requires at most two PHYs ie HS and SS PHYs. There are SoCs that has
DWC3 controller with multiple ports that can operate in host mode.
Some of the port supports both SS+HS and other port supports only HS
mode.
This change primarily refactors the Phy logic in core driver to allow
multiport support with Generic Phy's.
Chananges have been tested on QCOM SoC SA8295P which has 4 ports (2
are HS+SS capable and 2 are HS only capable).
Changes in v6:
Updated comments in code after.
Updated variables names appropriately as per review comments.
Updated commit text in patch-2 and added additional info as per review
comments.
The patch header in v5 doesn't have "PATHCH v5" notation present. Corrected
it in this version.
Changes in v5:
Added DT support for first port of Teritiary USB controller on SA8540-Ride
Added support for reading port info from XHCI Extended Params registers.
Changes in RFC v4:
Added DT support for SA8295p.
Changes in RFC v3:
Incase any PHY init fails, then clear/exit the PHYs that
are already initialized.
Changes in RFC v2:
Changed dwc3_count_phys to return the number of PHY Phandles in the node.
This will be used now in dwc3_extract_num_phys to increment num_usb2_phy
and num_usb3_phy.
Added new parameter "ss_idx" in dwc3_core_get_phy_ny_node and changed its
structure such that the first half is for HS-PHY and second half is for
SS-PHY.
In dwc3_core_get_phy, for multiport controller, only if SS-PHY phandle is
present, pass proper SS_IDX else pass -1.
Link to v5: https://lore.kernel.org/all/[email protected]/
Link to RFC v4: https://lore.kernel.org/all/[email protected]/
Link to RFC v3: https://lore.kernel.org/all/[email protected]/#r
Link to RFC v2: https://lore.kernel.org/all/[email protected]/#r
Krishna Kurapati (8):
dt-bindings: usb: Add bindings for multiport properties on DWC3
controller
usb: dwc3: core: Access XHCI address space temporarily to read port
info
usb: dwc3: core: Skip setting event buffers for host only controllers
usb: dwc3: core: Refactor PHY logic to support Multiport Controller
usb: dwc3: qcom: Add multiport controller support for qcom wrapper
arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280
arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB
ports
arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb
controller
.../devicetree/bindings/usb/snps,dwc3.yaml | 13 +-
arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 47 +++
arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 58 +++
drivers/usb/dwc3/core.c | 373 ++++++++++++++----
drivers/usb/dwc3/core.h | 71 +++-
drivers/usb/dwc3/drd.c | 13 +-
drivers/usb/dwc3/dwc3-qcom.c | 28 +-
8 files changed, 523 insertions(+), 102 deletions(-)
--
2.40.0
Add bindings to indicate properties required to support multiport
on Snps Dwc3 controller.
Suggested-by: Bjorn Andersson <[email protected]>
Signed-off-by: Krishna Kurapati <[email protected]>
---
Link to v5: https://lore.kernel.org/all/[email protected]/
.../devicetree/bindings/usb/snps,dwc3.yaml | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
index be36956af53b..96701eb5a17c 100644
--- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
@@ -81,15 +81,16 @@ properties:
phys:
minItems: 1
- maxItems: 2
+ maxItems: 8
phy-names:
minItems: 1
- maxItems: 2
- items:
- enum:
- - usb2-phy
- - usb3-phy
+ maxItems: 8
+ oneOf:
+ - items:
+ enum: [ usb2-phy, usb3-phy ]
+ - items:
+ pattern: "^usb[23]-port[0-3]$"
power-domains:
description:
--
2.40.0
Currently host-only capable DWC3 controllers support Multiport. Temporarily
map XHCI address space for host-only controllers and parse XHCI Extended
Capabilities registers to read number of usb2 ports and usb3 ports present on
multiport controller. Each USB Port is atleast HS capable.
The port info for usb2 and usb3 phy are identified as num_usb2_ports and
num_usb3_ports. The intention is as follows:
Wherever we need to perform phy operations like:
LOOP_OVER_NUMBER_OF_AVAILABLE_PORTS()
{
phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
}
If number of usb2 ports is 3, loop can go from index 0-2 for usb2_generic_phy.
If number of usb3-ports is 2, we don't know for sure, if the first 2 ports are
SS capable or some other ports like (2 and 3) are SS capable. So instead,
num_usb2_ports is used to loop around all phy's (both hs and ss) for
performing phy operations. If any usb3_generic_phy turns out to be NULL, phy
operation just bails out.
num_usb3_ports is used to modify GUSB3PIPECTL registers while setting up
phy's as we need to know how many SS capable ports are there for this.
Signed-off-by: Krishna Kurapati <[email protected]>
---
Link to v5: https://lore.kernel.org/all/[email protected]/
drivers/usb/dwc3/core.c | 69 +++++++++++++++++++++++++++++++++++++++++
drivers/usb/dwc3/core.h | 60 +++++++++++++++++++++++++++++++++++
2 files changed, 129 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 476b63618511..567ae79389a1 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1750,6 +1750,60 @@ static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
return edev;
}
+static int dwc3_read_port_info(struct dwc3 *dwc)
+{
+ void __iomem *regs;
+ u32 offset;
+ u32 temp;
+ u8 major_revision;
+ int ret = 0;
+
+ /*
+ * Remap xHCI address space to access XHCI ext cap regs,
+ * since it is needed to get port info.
+ */
+ regs = ioremap(dwc->xhci_resources[0].start,
+ resource_size(&dwc->xhci_resources[0]));
+ if (IS_ERR(regs)) {
+ return PTR_ERR(regs);
+ }
+
+ offset = dwc3_xhci_find_next_ext_cap(regs, 0,
+ XHCI_EXT_CAPS_PROTOCOL);
+ while (offset) {
+ temp = readl(regs + offset);
+ major_revision = XHCI_EXT_PORT_MAJOR(temp);;
+
+ temp = readl(regs + offset + 0x08);
+ if (major_revision == 0x03) {
+ dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(temp);
+ } else if (major_revision <= 0x02) {
+ dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(temp);
+ } else {
+ dev_err(dwc->dev, "port revision seems wrong\n");
+ ret = -EINVAL;
+ goto unmap_reg;
+ }
+
+ offset = dwc3_xhci_find_next_ext_cap(regs, offset,
+ XHCI_EXT_CAPS_PROTOCOL);
+ }
+
+ temp = readl(regs + DWC3_XHCI_HCSPARAMS1);
+ if (HCS_MAX_PORTS(temp) != (dwc->num_usb3_ports + dwc->num_usb2_ports)) {
+ dev_err(dwc->dev, "inconsistency in port info\n");
+ ret = -EINVAL;
+ goto unmap_reg;
+ }
+
+ dev_dbg(dwc->dev,
+ "hs-ports: %d ss-ports: %d\n", dwc->num_usb2_ports, dwc->num_usb3_ports);
+
+unmap_reg:
+ iounmap(regs);
+ return ret;
+}
+
static int dwc3_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -1757,6 +1811,7 @@ static int dwc3_probe(struct platform_device *pdev)
struct dwc3 *dwc;
int ret;
+ unsigned int hw_mode;
void __iomem *regs;
@@ -1880,6 +1935,20 @@ static int dwc3_probe(struct platform_device *pdev)
goto disable_clks;
}
+ /*
+ * Currently DWC3 controllers that are host-only capable
+ * support Multiport
+ */
+ hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
+ if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
+ ret = dwc3_read_port_info(dwc);
+ if (ret)
+ goto disable_clks;
+ } else {
+ dwc->num_usb2_ports = 1;
+ dwc->num_usb3_ports = 1;
+ }
+
spin_lock_init(&dwc->lock);
mutex_init(&dwc->mutex);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 4743e918dcaf..229b7da8c5bc 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -35,6 +35,17 @@
#define DWC3_MSG_MAX 500
+/* Define XHCI Extcap register offsets for getting multiport info */
+#define XHCI_HCC_PARAMS_OFFSET 0x10
+#define DWC3_XHCI_HCSPARAMS1 0x04
+#define XHCI_EXT_CAPS_PROTOCOL 2
+#define XHCI_HCC_EXT_CAPS(p) (((p)>>16)&0xffff)
+#define XHCI_EXT_CAPS_ID(p) (((p)>>0)&0xff)
+#define XHCI_EXT_CAPS_NEXT(p) (((p)>>8)&0xff)
+#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
+#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
+#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
+
/* Global constants */
#define DWC3_PULL_UP_TIMEOUT 500 /* ms */
#define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */
@@ -1023,6 +1034,10 @@ struct dwc3_scratchpad_array {
* @usb_psy: pointer to power supply interface.
* @usb2_phy: pointer to USB2 PHY
* @usb3_phy: pointer to USB3 PHY
+ * @num_usb2_ports: Indicates the number of usb2 ports to be serviced by the
+ * controller.
+ * @num_usb3_ports: Indicates the number of usb3 ports to be serviced by the
+ * controller.
* @usb2_generic_phy: pointer to USB2 PHY
* @usb3_generic_phy: pointer to USB3 PHY
* @phys_ready: flag to indicate that PHYs are ready
@@ -1158,6 +1173,8 @@ struct dwc3 {
struct usb_phy *usb2_phy;
struct usb_phy *usb3_phy;
+ u32 num_usb2_ports;
+ u32 num_usb3_ports;
struct phy *usb2_generic_phy;
struct phy *usb3_generic_phy;
@@ -1645,4 +1662,47 @@ static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
{ }
#endif
+/**
+ * Find the offset of the extended capabilities with capability ID id.
+ *
+ * @base PCI MMIO registers base address.
+ * @start address at which to start looking, (0 or HCC_PARAMS to start at
+ * beginning of list)
+ * @id Extended capability ID to search for, or 0 for the next
+ * capability
+ *
+ * Returns the offset of the next matching extended capability structure.
+ * Some capabilities can occur several times, e.g., the XHCI_EXT_CAPS_PROTOCOL,
+ * and this provides a way to find them all.
+ */
+
+static inline int dwc3_xhci_find_next_ext_cap(void __iomem *base, u32 start, int id)
+{
+ u32 val;
+ u32 next;
+ u32 offset;
+
+ offset = start;
+ if (!start || start == XHCI_HCC_PARAMS_OFFSET) {
+ val = readl(base + XHCI_HCC_PARAMS_OFFSET);
+ if (val == ~0)
+ return 0;
+ offset = XHCI_HCC_EXT_CAPS(val) << 2;
+ if (!offset)
+ return 0;
+ }
+ do {
+ val = readl(base + offset);
+ if (val == ~0)
+ return 0;
+ if (offset != start && (id == 0 || XHCI_EXT_CAPS_ID(val) == id))
+ return offset;
+
+ next = XHCI_EXT_CAPS_NEXT(val);
+ offset += next << 2;
+ } while (next);
+
+ return 0;
+}
+
#endif /* __DRIVERS_USB_DWC3_CORE_H */
--
2.40.0
On some SoC's like SA8295P where the tertiary controller is host-only
capable, GEVTADDRHI/LO, GEVTSIZ, GEVTCOUNT registers are not accessible.
Trying to setup them up during core_init leads to a crash.
For DRD/Peripheral supported controllers, event buffer setup is done
again in gadget_pullup. Skip setup or cleanup of event buffers if
controller is host-only capable.
Signed-off-by: Krishna Kurapati <[email protected]>
---
Link to v5: https://lore.kernel.org/all/[email protected]/
drivers/usb/dwc3/core.c | 20 ++++++++++++++------
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 567ae79389a1..2964bcaa0a27 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -839,7 +839,11 @@ static void dwc3_clk_disable(struct dwc3 *dwc)
static void dwc3_core_exit(struct dwc3 *dwc)
{
- dwc3_event_buffers_cleanup(dwc);
+ unsigned int hw_mode;
+
+ hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
+ if (hw_mode != DWC3_GHWPARAMS0_MODE_HOST)
+ dwc3_event_buffers_cleanup(dwc);
usb_phy_set_suspend(dwc->usb2_phy, 1);
usb_phy_set_suspend(dwc->usb3_phy, 1);
@@ -1176,10 +1180,12 @@ static int dwc3_core_init(struct dwc3 *dwc)
if (ret < 0)
goto err3;
- ret = dwc3_event_buffers_setup(dwc);
- if (ret) {
- dev_err(dwc->dev, "failed to setup event buffers\n");
- goto err4;
+ if (hw_mode != DWC3_GHWPARAMS0_MODE_HOST) {
+ ret = dwc3_event_buffers_setup(dwc);
+ if (ret) {
+ dev_err(dwc->dev, "failed to setup event buffers\n");
+ goto err4;
+ }
}
/*
@@ -2002,7 +2008,9 @@ static int dwc3_probe(struct platform_device *pdev)
err5:
dwc3_debugfs_exit(dwc);
- dwc3_event_buffers_cleanup(dwc);
+
+ if (hw_mode != DWC3_GHWPARAMS0_MODE_HOST)
+ dwc3_event_buffers_cleanup(dwc);
usb_phy_set_suspend(dwc->usb2_phy, 1);
usb_phy_set_suspend(dwc->usb3_phy, 1);
--
2.40.0
QCOM SoC SA8295P's tertiary quad port controller supports 2 HS+SS
ports and 2 HS only ports. Add support for configuring PWR_EVENT_IRQ's
for all the ports during suspend/resume.
Signed-off-by: Krishna Kurapati <[email protected]>
---
Link to v5: https://lore.kernel.org/all/[email protected]/
drivers/usb/dwc3/dwc3-qcom.c | 28 ++++++++++++++++++++++------
1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
index 959fc925ca7c..7a9bce66295d 100644
--- a/drivers/usb/dwc3/dwc3-qcom.c
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -37,7 +37,10 @@
#define PIPE3_PHYSTATUS_SW BIT(3)
#define PIPE_UTMI_CLK_DIS BIT(8)
-#define PWR_EVNT_IRQ_STAT_REG 0x58
+#define PWR_EVNT_IRQ1_STAT_REG 0x58
+#define PWR_EVNT_IRQ2_STAT_REG 0x1dc
+#define PWR_EVNT_IRQ3_STAT_REG 0x228
+#define PWR_EVNT_IRQ4_STAT_REG 0x238
#define PWR_EVNT_LPM_IN_L2_MASK BIT(4)
#define PWR_EVNT_LPM_OUT_L2_MASK BIT(5)
@@ -93,6 +96,13 @@ struct dwc3_qcom {
struct icc_path *icc_path_apps;
};
+static u32 pwr_evnt_irq_stat_reg_offset[4] = {
+ PWR_EVNT_IRQ1_STAT_REG,
+ PWR_EVNT_IRQ2_STAT_REG,
+ PWR_EVNT_IRQ3_STAT_REG,
+ PWR_EVNT_IRQ4_STAT_REG,
+};
+
static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
{
u32 reg;
@@ -413,13 +423,16 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
{
u32 val;
int i, ret;
+ struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
if (qcom->is_suspended)
return 0;
- val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG);
- if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
- dev_err(qcom->dev, "HS-PHY not in L2\n");
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ val = readl(qcom->qscratch_base + pwr_evnt_irq_stat_reg_offset[i]);
+ if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
+ dev_err(qcom->dev, "HS-PHY%d not in L2\n", i);
+ }
for (i = qcom->num_clocks - 1; i >= 0; i--)
clk_disable_unprepare(qcom->clks[i]);
@@ -446,6 +459,7 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup)
{
int ret;
int i;
+ struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
if (!qcom->is_suspended)
return 0;
@@ -467,8 +481,10 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup)
dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret);
/* Clear existing events from PHY related to L2 in/out */
- dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG,
- PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
+ for (i = 0; i < dwc->num_usb2_ports; i++)
+ dwc3_qcom_setbits(qcom->qscratch_base,
+ pwr_evnt_irq_stat_reg_offset[i],
+ PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
qcom->is_suspended = false;
--
2.40.0
Enable tertiary controller for SA8295P (based on SC8280XP).
Add pinctrl support for usb ports to provide VBUS to connected peripherals.
Signed-off-by: Krishna Kurapati <[email protected]>
---
Link to v5: https://lore.kernel.org/all/[email protected]/
arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 47 ++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
index fd253942e5e5..7e6061c43835 100644
--- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
+++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
@@ -584,6 +584,19 @@ &usb_1_qmpphy {
status = "okay";
};
+&usb_2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb2_en_state>,
+ <&usb3_en_state>,
+ <&usb4_en_state>,
+ <&usb5_en_state>;
+ status = "okay";
+};
+
+&usb_2_dwc3 {
+ dr_mode = "host";
+};
+
&usb_2_hsphy0 {
vdda-pll-supply = <&vreg_l5a>;
vdda18-supply = <&vreg_l7g>;
@@ -729,3 +742,37 @@ wake-n-pins {
};
};
};
+
+&pmm8540c_gpios {
+ usb2_en_state: usb2-en-state {
+ pins = "gpio9";
+ function = "normal";
+ output-high;
+ power-source = <0>;
+ };
+};
+
+&pmm8540e_gpios {
+ usb3_en_state: usb3-en-state {
+ pins = "gpio5";
+ function = "normal";
+ output-high;
+ power-source = <0>;
+ };
+};
+
+&pmm8540g_gpios {
+ usb4_en_state: usb4-en-state {
+ pins = "gpio5";
+ function = "normal";
+ output-high;
+ power-source = <0>;
+ };
+
+ usb5_en_state: usb5-en-state {
+ pins = "gpio9";
+ function = "normal";
+ output-high;
+ power-source = <0>;
+ };
+};
--
2.40.0
Currently the DWC3 driver supports only single port controller
which requires at most one HS and one SS PHY.
But the DWC3 USB controller can be connected to multiple ports and
each port can have their own PHYs. Each port of the multiport
controller can either be HS+SS capable or HS only capable
Proper quantification of them is required to modify GUSB2PHYCFG
and GUSB3PIPECTL registers appropriately.
Add support for detecting, obtaining and configuring phy's supported
by a multiport controller and limit the max number of ports
supported to 4.
Signed-off-by: Harsh Agarwal <[email protected]>
Signed-off-by: Krishna Kurapati <[email protected]>
---
Link to v5: https://lore.kernel.org/all/[email protected]/
drivers/usb/dwc3/core.c | 286 +++++++++++++++++++++++++++++-----------
drivers/usb/dwc3/core.h | 11 +-
drivers/usb/dwc3/drd.c | 13 +-
3 files changed, 225 insertions(+), 85 deletions(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 2964bcaa0a27..cb27cf8ff432 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -121,6 +121,7 @@ static void __dwc3_set_mode(struct work_struct *work)
struct dwc3 *dwc = work_to_dwc(work);
unsigned long flags;
int ret;
+ int i;
u32 reg;
u32 desired_dr_role;
@@ -200,8 +201,10 @@ static void __dwc3_set_mode(struct work_struct *work)
} else {
if (dwc->usb2_phy)
otg_set_vbus(dwc->usb2_phy->otg, true);
- phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
- phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
+ phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
+ }
if (dwc->dis_split_quirk) {
reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
reg |= DWC3_GUCTL3_SPLITDISABLE;
@@ -216,8 +219,8 @@ static void __dwc3_set_mode(struct work_struct *work)
if (dwc->usb2_phy)
otg_set_vbus(dwc->usb2_phy->otg, false);
- phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
- phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
+ phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
+ phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);
ret = dwc3_gadget_init(dwc);
if (ret)
@@ -659,22 +662,14 @@ static int dwc3_core_ulpi_init(struct dwc3 *dwc)
return ret;
}
-/**
- * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
- * @dwc: Pointer to our controller context structure
- *
- * Returns 0 on success. The USB PHY interfaces are configured but not
- * initialized. The PHY interfaces and the PHYs get initialized together with
- * the core in dwc3_core_init.
- */
-static int dwc3_phy_setup(struct dwc3 *dwc)
+static int dwc3_ss_phy_setup(struct dwc3 *dwc, int index)
{
unsigned int hw_mode;
u32 reg;
hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
- reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(index));
/*
* Make sure UX_EXIT_PX is cleared as that causes issues with some
@@ -729,9 +724,19 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
if (dwc->dis_del_phy_power_chg_quirk)
reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
- dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
+ dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(index), reg);
- reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
+ return 0;
+}
+
+static int dwc3_hs_phy_setup(struct dwc3 *dwc, int index)
+{
+ unsigned int hw_mode;
+ u32 reg;
+
+ hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
+
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(index));
/* Select the HS PHY interface */
switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
@@ -743,7 +748,7 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
} else if (dwc->hsphy_interface &&
!strncmp(dwc->hsphy_interface, "ulpi", 4)) {
reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
- dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
} else {
/* Relying on default value. */
if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
@@ -800,7 +805,35 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel)
reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
- dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
+
+ return 0;
+}
+
+/**
+ * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
+ * @dwc: Pointer to our controller context structure
+ *
+ * Returns 0 on success. The USB PHY interfaces are configured but not
+ * initialized. The PHY interfaces and the PHYs get initialized together with
+ * the core in dwc3_core_init.
+ */
+static int dwc3_phy_setup(struct dwc3 *dwc)
+{
+ int i;
+ int ret;
+
+ for (i = 0; i < dwc->num_usb3_ports; i++) {
+ ret = dwc3_ss_phy_setup(dwc, i);
+ if (ret)
+ return ret;
+ }
+
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ ret = dwc3_hs_phy_setup(dwc, i);
+ if (ret)
+ return ret;
+ }
return 0;
}
@@ -839,6 +872,7 @@ static void dwc3_clk_disable(struct dwc3 *dwc)
static void dwc3_core_exit(struct dwc3 *dwc)
{
+ int i;
unsigned int hw_mode;
hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
@@ -847,13 +881,19 @@ static void dwc3_core_exit(struct dwc3 *dwc)
usb_phy_set_suspend(dwc->usb2_phy, 1);
usb_phy_set_suspend(dwc->usb3_phy, 1);
- phy_power_off(dwc->usb2_generic_phy);
- phy_power_off(dwc->usb3_generic_phy);
+
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ phy_power_off(dwc->usb2_generic_phy[i]);
+ phy_power_off(dwc->usb3_generic_phy[i]);
+ }
usb_phy_shutdown(dwc->usb2_phy);
usb_phy_shutdown(dwc->usb3_phy);
- phy_exit(dwc->usb2_generic_phy);
- phy_exit(dwc->usb3_generic_phy);
+
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ phy_exit(dwc->usb2_generic_phy[i]);
+ phy_exit(dwc->usb3_generic_phy[i]);
+ }
dwc3_clk_disable(dwc);
reset_control_assert(dwc->reset);
@@ -1089,6 +1129,7 @@ static int dwc3_core_init(struct dwc3 *dwc)
unsigned int hw_mode;
u32 reg;
int ret;
+ int i, j;
hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
@@ -1123,14 +1164,27 @@ static int dwc3_core_init(struct dwc3 *dwc)
usb_phy_init(dwc->usb2_phy);
usb_phy_init(dwc->usb3_phy);
- ret = phy_init(dwc->usb2_generic_phy);
- if (ret < 0)
- goto err0a;
- ret = phy_init(dwc->usb3_generic_phy);
- if (ret < 0) {
- phy_exit(dwc->usb2_generic_phy);
- goto err0a;
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ ret = phy_init(dwc->usb2_generic_phy[i]);
+ if (ret < 0) {
+ /* clean up prior initialized HS PHYs */
+ for (j = 0; j < i; j++)
+ phy_exit(dwc->usb2_generic_phy[j]);
+ goto err0a;
+ }
+ }
+
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ ret = phy_init(dwc->usb3_generic_phy[i]);
+ if (ret < 0) {
+ /* clean up prior initialized SS PHYs */
+ for (j = 0; j < i; j++)
+ phy_exit(dwc->usb3_generic_phy[j]);
+ for (j = 0; j < dwc->num_usb2_ports; j++)
+ phy_exit(dwc->usb2_generic_phy[j]);
+ goto err0a;
+ }
}
ret = dwc3_core_soft_reset(dwc);
@@ -1140,15 +1194,19 @@ static int dwc3_core_init(struct dwc3 *dwc)
if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
if (!dwc->dis_u3_susphy_quirk) {
- reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
- reg |= DWC3_GUSB3PIPECTL_SUSPHY;
- dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
+ for (i = 0; i < dwc->num_usb3_ports; i++) {
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(i));
+ reg |= DWC3_GUSB3PIPECTL_SUSPHY;
+ dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(i), reg);
+ }
}
if (!dwc->dis_u2_susphy_quirk) {
- reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
- reg |= DWC3_GUSB2PHYCFG_SUSPHY;
- dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
+ reg |= DWC3_GUSB2PHYCFG_SUSPHY;
+ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
+ }
}
}
@@ -1172,13 +1230,24 @@ static int dwc3_core_init(struct dwc3 *dwc)
usb_phy_set_suspend(dwc->usb2_phy, 0);
usb_phy_set_suspend(dwc->usb3_phy, 0);
- ret = phy_power_on(dwc->usb2_generic_phy);
- if (ret < 0)
- goto err2;
- ret = phy_power_on(dwc->usb3_generic_phy);
- if (ret < 0)
- goto err3;
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ ret = phy_power_on(dwc->usb2_generic_phy[i]);
+ if (ret < 0) {
+ for (j = 0; j < i; j++)
+ phy_power_off(dwc->usb2_generic_phy[j]);
+ goto err2;
+ }
+ }
+
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ ret = phy_power_on(dwc->usb3_generic_phy[i]);
+ if (ret < 0) {
+ for (j = 0; j < i; j++)
+ phy_power_off(dwc->usb3_generic_phy[j]);
+ goto err3;
+ }
+ }
if (hw_mode != DWC3_GHWPARAMS0_MODE_HOST) {
ret = dwc3_event_buffers_setup(dwc);
@@ -1303,10 +1372,12 @@ static int dwc3_core_init(struct dwc3 *dwc)
return 0;
err4:
- phy_power_off(dwc->usb3_generic_phy);
+ for (i = 0; i < dwc->num_usb2_ports; i++)
+ phy_power_off(dwc->usb3_generic_phy[i]);
err3:
- phy_power_off(dwc->usb2_generic_phy);
+ for (i = 0; i < dwc->num_usb2_ports; i++)
+ phy_power_off(dwc->usb2_generic_phy[i]);
err2:
usb_phy_set_suspend(dwc->usb2_phy, 1);
@@ -1315,8 +1386,11 @@ static int dwc3_core_init(struct dwc3 *dwc)
err1:
usb_phy_shutdown(dwc->usb2_phy);
usb_phy_shutdown(dwc->usb3_phy);
- phy_exit(dwc->usb2_generic_phy);
- phy_exit(dwc->usb3_generic_phy);
+
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ phy_exit(dwc->usb2_generic_phy[i]);
+ phy_exit(dwc->usb3_generic_phy[i]);
+ }
err0a:
dwc3_ulpi_exit(dwc);
@@ -1325,6 +1399,42 @@ static int dwc3_core_init(struct dwc3 *dwc)
return ret;
}
+static int dwc3_get_multiport_phys(struct dwc3 *dwc)
+{
+ int ret;
+ struct device *dev = dwc->dev;
+ int i;
+ char phy_name[11];
+
+ /*
+ * Each port is atleast HS capable. So loop over num_usb2_ports
+ * to get available phy's.
+ */
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ sprintf(phy_name, "usb2-port%d", i);
+ dwc->usb2_generic_phy[i] = devm_phy_get(dev, phy_name);
+ if (IS_ERR(dwc->usb2_generic_phy[i])) {
+ ret = PTR_ERR(dwc->usb2_generic_phy[i]);
+ if (ret == -ENOSYS || ret == -ENODEV)
+ dwc->usb2_generic_phy[i] = NULL;
+ else
+ return dev_err_probe(dev, ret, "usb2 phy: %s not configured\n", phy_name);
+ }
+
+ sprintf(phy_name, "usb3-port%d", i);
+ dwc->usb3_generic_phy[i] = devm_phy_get(dev, phy_name);
+ if (IS_ERR(dwc->usb3_generic_phy[i])) {
+ ret = PTR_ERR(dwc->usb3_generic_phy[i]);
+ if (ret == -ENOSYS || ret == -ENODEV)
+ dwc->usb3_generic_phy[i] = NULL;
+ else
+ return dev_err_probe(dev, ret, "usb3 phy: %s not configured\n", phy_name);
+ }
+ }
+
+ return 0;
+}
+
static int dwc3_core_get_phy(struct dwc3 *dwc)
{
struct device *dev = dwc->dev;
@@ -1355,20 +1465,24 @@ static int dwc3_core_get_phy(struct dwc3 *dwc)
return dev_err_probe(dev, ret, "no usb3 phy configured\n");
}
- dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
- if (IS_ERR(dwc->usb2_generic_phy)) {
- ret = PTR_ERR(dwc->usb2_generic_phy);
+ if (dwc->num_usb2_ports > 1)
+ return dwc3_get_multiport_phys(dwc);
+
+
+ dwc->usb2_generic_phy[0] = devm_phy_get(dev, "usb2-phy");
+ if (IS_ERR(dwc->usb2_generic_phy[0])) {
+ ret = PTR_ERR(dwc->usb2_generic_phy[0]);
if (ret == -ENOSYS || ret == -ENODEV)
- dwc->usb2_generic_phy = NULL;
+ dwc->usb2_generic_phy[0] = NULL;
else
return dev_err_probe(dev, ret, "no usb2 phy configured\n");
}
- dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
- if (IS_ERR(dwc->usb3_generic_phy)) {
- ret = PTR_ERR(dwc->usb3_generic_phy);
+ dwc->usb3_generic_phy[0] = devm_phy_get(dev, "usb3-phy");
+ if (IS_ERR(dwc->usb3_generic_phy[0])) {
+ ret = PTR_ERR(dwc->usb3_generic_phy[0]);
if (ret == -ENOSYS || ret == -ENODEV)
- dwc->usb3_generic_phy = NULL;
+ dwc->usb3_generic_phy[0] = NULL;
else
return dev_err_probe(dev, ret, "no usb3 phy configured\n");
}
@@ -1380,6 +1494,7 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
{
struct device *dev = dwc->dev;
int ret;
+ int i;
switch (dwc->dr_mode) {
case USB_DR_MODE_PERIPHERAL:
@@ -1387,8 +1502,8 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
if (dwc->usb2_phy)
otg_set_vbus(dwc->usb2_phy->otg, false);
- phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
- phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
+ phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
+ phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);
ret = dwc3_gadget_init(dwc);
if (ret)
@@ -1399,8 +1514,10 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
if (dwc->usb2_phy)
otg_set_vbus(dwc->usb2_phy->otg, true);
- phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
- phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
+ phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
+ }
ret = dwc3_host_init(dwc);
if (ret)
@@ -1817,6 +1934,7 @@ static int dwc3_probe(struct platform_device *pdev)
struct dwc3 *dwc;
int ret;
+ int i;
unsigned int hw_mode;
void __iomem *regs;
@@ -1943,7 +2061,7 @@ static int dwc3_probe(struct platform_device *pdev)
/*
* Currently DWC3 controllers that are host-only capable
- * support Multiport
+ * support Multiport.
*/
hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
@@ -2014,13 +2132,19 @@ static int dwc3_probe(struct platform_device *pdev)
usb_phy_set_suspend(dwc->usb2_phy, 1);
usb_phy_set_suspend(dwc->usb3_phy, 1);
- phy_power_off(dwc->usb2_generic_phy);
- phy_power_off(dwc->usb3_generic_phy);
+
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ phy_power_off(dwc->usb2_generic_phy[i]);
+ phy_power_off(dwc->usb3_generic_phy[i]);
+ }
usb_phy_shutdown(dwc->usb2_phy);
usb_phy_shutdown(dwc->usb3_phy);
- phy_exit(dwc->usb2_generic_phy);
- phy_exit(dwc->usb3_generic_phy);
+
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ phy_exit(dwc->usb2_generic_phy[i]);
+ phy_exit(dwc->usb3_generic_phy[i]);
+ }
dwc3_ulpi_exit(dwc);
@@ -2102,6 +2226,7 @@ static int dwc3_core_init_for_resume(struct dwc3 *dwc)
static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
{
+ int i;
unsigned long flags;
u32 reg;
@@ -2122,17 +2247,21 @@ static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
/* Let controller to suspend HSPHY before PHY driver suspends */
if (dwc->dis_u2_susphy_quirk ||
dwc->dis_enblslpm_quirk) {
- reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
- reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
- DWC3_GUSB2PHYCFG_SUSPHY;
- dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
+ reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
+ DWC3_GUSB2PHYCFG_SUSPHY;
+ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
+ }
/* Give some time for USB2 PHY to suspend */
usleep_range(5000, 6000);
}
- phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
- phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ phy_pm_runtime_put_sync(dwc->usb2_generic_phy[i]);
+ phy_pm_runtime_put_sync(dwc->usb3_generic_phy[i]);
+ }
break;
case DWC3_GCTL_PRTCAP_OTG:
/* do nothing during runtime_suspend */
@@ -2161,6 +2290,7 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
{
unsigned long flags;
int ret;
+ int i;
u32 reg;
switch (dwc->current_dr_role) {
@@ -2181,17 +2311,21 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
break;
}
/* Restore GUSB2PHYCFG bits that were modified in suspend */
- reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
- if (dwc->dis_u2_susphy_quirk)
- reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
+ if (dwc->dis_u2_susphy_quirk)
+ reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
- if (dwc->dis_enblslpm_quirk)
- reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
+ if (dwc->dis_enblslpm_quirk)
+ reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
- dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
+ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
+ }
- phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
- phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ phy_pm_runtime_get_sync(dwc->usb2_generic_phy[i]);
+ phy_pm_runtime_get_sync(dwc->usb3_generic_phy[i]);
+ }
break;
case DWC3_GCTL_PRTCAP_OTG:
/* nothing to do on runtime_resume */
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 229b7da8c5bc..668ad30c151f 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -35,6 +35,9 @@
#define DWC3_MSG_MAX 500
+/* Numer of ports supported by a multiport controller */
+#define MAX_PORTS_SUPPORTED 4
+
/* Define XHCI Extcap register offsets for getting multiport info */
#define XHCI_HCC_PARAMS_OFFSET 0x10
#define DWC3_XHCI_HCSPARAMS1 0x04
@@ -1038,8 +1041,8 @@ struct dwc3_scratchpad_array {
* controller.
* @num_usb3_ports: Indicates the number of usb3 ports to be serviced by the
* controller.
- * @usb2_generic_phy: pointer to USB2 PHY
- * @usb3_generic_phy: pointer to USB3 PHY
+ * @usb2_generic_phy: pointer to array of USB2 PHY
+ * @usb3_generic_phy: pointer to array of USB3 PHY
* @phys_ready: flag to indicate that PHYs are ready
* @ulpi: pointer to ulpi interface
* @ulpi_ready: flag to indicate that ULPI is initialized
@@ -1175,8 +1178,8 @@ struct dwc3 {
u32 num_usb2_ports;
u32 num_usb3_ports;
- struct phy *usb2_generic_phy;
- struct phy *usb3_generic_phy;
+ struct phy *usb2_generic_phy[MAX_PORTS_SUPPORTED];
+ struct phy *usb3_generic_phy[MAX_PORTS_SUPPORTED];
bool phys_ready;
diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c
index 039bf241769a..0377295717ab 100644
--- a/drivers/usb/dwc3/drd.c
+++ b/drivers/usb/dwc3/drd.c
@@ -328,6 +328,7 @@ static void dwc3_otg_device_exit(struct dwc3 *dwc)
void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
{
int ret;
+ int i;
u32 reg;
int id;
unsigned long flags;
@@ -386,9 +387,11 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
} else {
if (dwc->usb2_phy)
otg_set_vbus(dwc->usb2_phy->otg, true);
- if (dwc->usb2_generic_phy)
- phy_set_mode(dwc->usb2_generic_phy,
- PHY_MODE_USB_HOST);
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ if (dwc->usb2_generic_phy[i])
+ phy_set_mode(dwc->usb2_generic_phy[i],
+ PHY_MODE_USB_HOST);
+ }
}
break;
case DWC3_OTG_ROLE_DEVICE:
@@ -400,8 +403,8 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
if (dwc->usb2_phy)
otg_set_vbus(dwc->usb2_phy->otg, false);
- if (dwc->usb2_generic_phy)
- phy_set_mode(dwc->usb2_generic_phy,
+ if (dwc->usb2_generic_phy[0])
+ phy_set_mode(dwc->usb2_generic_phy[0],
PHY_MODE_USB_DEVICE);
ret = dwc3_gadget_init(dwc);
if (ret)
--
2.40.0
Add USB and DWC3 node for tertiary port of SC8280 along with multiport
IRQ's and phy's. This will be used as a base for SA8295P and SA8295-Ride
platforms.
Signed-off-by: Krishna Kurapati <[email protected]>
---
Link to v5: https://lore.kernel.org/all/[email protected]/
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 58 ++++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 42bfa9fa5b96..7b81f2b0449d 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -3108,6 +3108,64 @@ usb_1_role_switch: endpoint {
};
};
+ usb_2: usb@a4f8800 {
+ compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
+ reg = <0 0x0a4f8800 0 0x400>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
+ <&gcc GCC_USB30_MP_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
+ <&gcc GCC_USB30_MP_SLEEP_CLK>,
+ <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
+ <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
+ <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
+ clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
+ "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
+
+ assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_MP_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>,
+ <&pdc 126 IRQ_TYPE_EDGE_RISING>,
+ <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "dp_hs_phy_irq", "dm_hs_phy_irq",
+ "ss_phy_irq";
+
+ power-domains = <&gcc USB30_MP_GDSC>;
+
+ resets = <&gcc GCC_USB30_MP_BCR>;
+
+ interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
+ interconnect-names = "usb-ddr", "apps-usb";
+
+ required-opps = <&rpmhpd_opp_nom>;
+
+ status = "disabled";
+
+ usb_2_dwc3: usb@a400000 {
+ compatible = "snps,dwc3";
+ reg = <0 0x0a400000 0 0xcd00>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&apps_smmu 0x800 0x0>;
+ phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>,
+ <&usb_2_hsphy1>, <&usb_2_qmpphy1>,
+ <&usb_2_hsphy2>,
+ <&usb_2_hsphy3>;
+ phy-names = "usb2-port0", "usb3-port0",
+ "usb2-port1", "usb3-port1",
+ "usb2-port2",
+ "usb2-port3";
+ };
+ };
+
mdss0: display-subsystem@ae00000 {
compatible = "qcom,sc8280xp-mdss";
reg = <0 0x0ae00000 0 0x1000>;
--
2.40.0
Enable first port of Quad port Tertiary USB controller for SA8540 Ride.
Signed-off-by: Krishna Kurapati <[email protected]>
---
Link to v5: https://lore.kernel.org/all/[email protected]/
arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
index 24fa449d48a6..53d47593306e 100644
--- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
@@ -309,6 +309,19 @@ &usb_2_qmpphy0 {
status = "okay";
};
+&usb_2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb2_en_state>;
+
+ status = "okay";
+};
+
+&usb_2_dwc3 {
+ dr_mode = "host";
+ phy-names = "usb2-port0", "usb3-port0";
+ phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>;
+};
+
&xo_board_clk {
clock-frequency = <38400000>;
};
@@ -401,4 +414,13 @@ wake-pins {
bias-pull-up;
};
};
+
+ usb2_en_state: usb2-en-state {
+ /* TS3USB221A USB2.0 mux select */
+ pins = "gpio24";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
};
--
2.40.0
On 05/04/2023 14:57, Krishna Kurapati wrote:
> Add bindings to indicate properties required to support multiport
> on Snps Dwc3 controller.
>
> Suggested-by: Bjorn Andersson <[email protected]>
> Signed-off-by: Krishna Kurapati <[email protected]>
> ---
> Link to v5: https://lore.kernel.org/all/[email protected]/
You did not test it at v4 and you got report for this. Your changelog in
commit msg does not mention fixing it.
It looks like you did not test it for the second time (or sixth time).
Best regards,
Krzysztof
On 4/5/2023 7:31 PM, Krzysztof Kozlowski wrote:
> On 05/04/2023 14:57, Krishna Kurapati wrote:
>> Add bindings to indicate properties required to support multiport
>> on Snps Dwc3 controller.
>>
>> Suggested-by: Bjorn Andersson <[email protected]>
>> Signed-off-by: Krishna Kurapati <[email protected]>
>> ---
>> Link to v5: https://lore.kernel.org/all/[email protected]/
>
> You did not test it at v4 and you got report for this. Your changelog in
> commit msg does not mention fixing it.
>
> It looks like you did not test it for the second time (or sixth time).
>
> Best regards,
> Krzysztof
>
Hi Krzysztof,
I did do a dt_binding_check and I got the following result:
kriskura@hu-kriskura-hyd:/local/mnt/workspace/krishna/skales2/skales/kernel$
make DT_CHECKER_FLAGS=-m dt_binding_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/usb/snps,dwc3.yaml
HOSTCC scripts/basic/fixdep
HOSTCC scripts/dtc/dtc.o
HOSTCC scripts/dtc/flattree.o
HOSTCC scripts/dtc/fstree.o
HOSTCC scripts/dtc/data.o
HOSTCC scripts/dtc/livetree.o
HOSTCC scripts/dtc/treesource.o
HOSTCC scripts/dtc/srcpos.o
HOSTCC scripts/dtc/checks.o
HOSTCC scripts/dtc/util.o
LEX scripts/dtc/dtc-lexer.lex.c
YACC scripts/dtc/dtc-parser.tab.[ch]
HOSTCC scripts/dtc/dtc-lexer.lex.o
HOSTCC scripts/dtc/dtc-parser.tab.o
HOSTLD scripts/dtc/dtc
LINT Documentation/devicetree/bindings
invalid config: unknown option "max-spaces-inside-empty" for rule "brackets"
xargs: /usr/bin/yamllint: exited with status 255; aborting
CHKDT Documentation/devicetree/bindings/processed-schema.json
SCHEMA Documentation/devicetree/bindings/processed-schema.json
/local/mnt/workspace/krishna/skales2/skales/kernel/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml:
ignoring, error in schema: properties: qcom,pre-emphasis-duration-bp
/local/mnt/workspace/krishna/skales2/skales/kernel/Documentation/devicetree/bindings/arm/vexpress-sysreg.yaml:
ignoring, error in schema: properties: gpio-controller
/local/mnt/workspace/krishna/skales2/skales/kernel/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml:
ignoring, error in schema: patternProperties: ^thermistor@: properties:
adi,excitation-current-nanoamp
/local/mnt/workspace/krishna/skales2/skales/kernel/Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml:
ignoring, error in schema: patternProperties: ^channel@([0-9a-f])$:
properties: adi,excitation-current-0-nanoamp
DTEX Documentation/devicetree/bindings/usb/snps,dwc3.example.dts
DTC_CHK Documentation/devicetree/bindings/usb/snps,dwc3.example.dtb
I can try upgrading the dt-schema and try again.
Regards,
Krishna,
On 05/04/2023 16:15, Krishna Kurapati PSSNV wrote:
>
>
> On 4/5/2023 7:31 PM, Krzysztof Kozlowski wrote:
>> On 05/04/2023 14:57, Krishna Kurapati wrote:
>>> Add bindings to indicate properties required to support multiport
>>> on Snps Dwc3 controller.
>>>
>>> Suggested-by: Bjorn Andersson <[email protected]>
>>> Signed-off-by: Krishna Kurapati <[email protected]>
>>> ---
>>> Link to v5: https://lore.kernel.org/all/[email protected]/
>>
>> You did not test it at v4 and you got report for this. Your changelog in
>> commit msg does not mention fixing it.
>>
>> It looks like you did not test it for the second time (or sixth time).
>>
>> Best regards,
>> Krzysztof
>>
> Hi Krzysztof,
>
> I did do a dt_binding_check and I got the following result:
>
> kriskura@hu-kriskura-hyd:/local/mnt/workspace/krishna/skales2/skales/kernel$
> make DT_CHECKER_FLAGS=-m dt_binding_check
> DT_SCHEMA_FILES=Documentation/devicetree/bindings/usb/snps,dwc3.yaml
> HOSTCC scripts/basic/fixdep
> HOSTCC scripts/dtc/dtc.o
> HOSTCC scripts/dtc/flattree.o
> HOSTCC scripts/dtc/fstree.o
> HOSTCC scripts/dtc/data.o
> HOSTCC scripts/dtc/livetree.o
> HOSTCC scripts/dtc/treesource.o
> HOSTCC scripts/dtc/srcpos.o
> HOSTCC scripts/dtc/checks.o
> HOSTCC scripts/dtc/util.o
> LEX scripts/dtc/dtc-lexer.lex.c
> YACC scripts/dtc/dtc-parser.tab.[ch]
> HOSTCC scripts/dtc/dtc-lexer.lex.o
> HOSTCC scripts/dtc/dtc-parser.tab.o
> HOSTLD scripts/dtc/dtc
> LINT Documentation/devicetree/bindings
> invalid config: unknown option "max-spaces-inside-empty" for rule "brackets"
> xargs: /usr/bin/yamllint: exited with status 255; aborting
> CHKDT Documentation/devicetree/bindings/processed-schema.json
> SCHEMA Documentation/devicetree/bindings/processed-schema.json
> /local/mnt/workspace/krishna/skales2/skales/kernel/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml:
> ignoring, error in schema: properties: qcom,pre-emphasis-duration-bp
> /local/mnt/workspace/krishna/skales2/skales/kernel/Documentation/devicetree/bindings/arm/vexpress-sysreg.yaml:
> ignoring, error in schema: properties: gpio-controller
> /local/mnt/workspace/krishna/skales2/skales/kernel/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml:
> ignoring, error in schema: patternProperties: ^thermistor@: properties:
> adi,excitation-current-nanoamp
> /local/mnt/workspace/krishna/skales2/skales/kernel/Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml:
> ignoring, error in schema: patternProperties: ^channel@([0-9a-f])$:
> properties: adi,excitation-current-0-nanoamp
All these are some errors, maybe coming from your schema, maybe from
next. You can narrow the tests with DT_SCHEMA_FILES (as mentioned in guide).
Best regards,
Krzysztof
On Wed, 05 Apr 2023 18:27:52 +0530, Krishna Kurapati wrote:
> Add bindings to indicate properties required to support multiport
> on Snps Dwc3 controller.
>
> Suggested-by: Bjorn Andersson <[email protected]>
> Signed-off-by: Krishna Kurapati <[email protected]>
> ---
> Link to v5: https://lore.kernel.org/all/[email protected]/
>
> .../devicetree/bindings/usb/snps,dwc3.yaml | 13 +++++++------
> 1 file changed, 7 insertions(+), 6 deletions(-)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
./Documentation/devicetree/bindings/usb/snps,dwc3.yaml:90:5: [warning] wrong indentation: expected 6 but found 4 (indentation)
dtschema/dtc warnings/errors:
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
On Wed, Apr 05, 2023 at 07:45:07PM +0530, Krishna Kurapati PSSNV wrote:
>
>
> On 4/5/2023 7:31 PM, Krzysztof Kozlowski wrote:
> > On 05/04/2023 14:57, Krishna Kurapati wrote:
> > > Add bindings to indicate properties required to support multiport
> > > on Snps Dwc3 controller.
> > >
> > > Suggested-by: Bjorn Andersson <[email protected]>
> > > Signed-off-by: Krishna Kurapati <[email protected]>
> > > ---
> > > Link to v5: https://lore.kernel.org/all/[email protected]/
> >
> > You did not test it at v4 and you got report for this. Your changelog in
> > commit msg does not mention fixing it.
> >
> > It looks like you did not test it for the second time (or sixth time).
> >
> > Best regards,
> > Krzysztof
> >
> Hi Krzysztof,
>
> I did do a dt_binding_check and I got the following result:
>
> kriskura@hu-kriskura-hyd:/local/mnt/workspace/krishna/skales2/skales/kernel$
> make DT_CHECKER_FLAGS=-m dt_binding_check
> DT_SCHEMA_FILES=Documentation/devicetree/bindings/usb/snps,dwc3.yaml
> HOSTCC scripts/basic/fixdep
> HOSTCC scripts/dtc/dtc.o
> HOSTCC scripts/dtc/flattree.o
> HOSTCC scripts/dtc/fstree.o
> HOSTCC scripts/dtc/data.o
> HOSTCC scripts/dtc/livetree.o
> HOSTCC scripts/dtc/treesource.o
> HOSTCC scripts/dtc/srcpos.o
> HOSTCC scripts/dtc/checks.o
> HOSTCC scripts/dtc/util.o
> LEX scripts/dtc/dtc-lexer.lex.c
> YACC scripts/dtc/dtc-parser.tab.[ch]
> HOSTCC scripts/dtc/dtc-lexer.lex.o
> HOSTCC scripts/dtc/dtc-parser.tab.o
> HOSTLD scripts/dtc/dtc
> LINT Documentation/devicetree/bindings
> invalid config: unknown option "max-spaces-inside-empty" for rule "brackets"
> xargs: /usr/bin/yamllint: exited with status 255; aborting
This indicates your yamllint version is too old.
Rob
Hi Krishna,
kernel test robot noticed the following build warnings:
[auto build test WARNING on usb/usb-linus]
[also build test WARNING on robh/for-next linus/master v6.3-rc5 next-20230405]
[cannot apply to usb/usb-testing usb/usb-next pza/reset/next pza/imx-drm/next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Krishna-Kurapati/dt-bindings-usb-Add-bindings-for-multiport-properties-on-DWC3-controller/20230405-210221
base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git usb-linus
patch link: https://lore.kernel.org/r/20230405125759.4201-3-quic_kriskura%40quicinc.com
patch subject: [PATCH v6 2/8] usb: dwc3: core: Access XHCI address space temporarily to read port info
reproduce:
# https://github.com/intel-lab-lkp/linux/commit/a0de434ac81429422ecdf84fe968bd8c3f73445b
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Krishna-Kurapati/dt-bindings-usb-Add-bindings-for-multiport-properties-on-DWC3-controller/20230405-210221
git checkout a0de434ac81429422ecdf84fe968bd8c3f73445b
make menuconfig
# enable CONFIG_COMPILE_TEST, CONFIG_WARN_MISSING_DOCUMENTS, CONFIG_WARN_ABI_ERRORS
make htmldocs
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
| Link: https://lore.kernel.org/oe-kbuild-all/[email protected]/
All warnings (new ones prefixed by >>):
>> ./drivers/usb/dwc3/core.h:1666: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
vim +1666 ./drivers/usb/dwc3/core.h
1664
1665 /**
> 1666 * Find the offset of the extended capabilities with capability ID id.
1667 *
1668 * @base PCI MMIO registers base address.
1669 * @start address at which to start looking, (0 or HCC_PARAMS to start at
1670 * beginning of list)
1671 * @id Extended capability ID to search for, or 0 for the next
1672 * capability
1673 *
1674 * Returns the offset of the next matching extended capability structure.
1675 * Some capabilities can occur several times, e.g., the XHCI_EXT_CAPS_PROTOCOL,
1676 * and this provides a way to find them all.
1677 */
1678
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests
On 4/6/2023 1:47 AM, Rob Herring wrote:
> On Wed, Apr 05, 2023 at 07:45:07PM +0530, Krishna Kurapati PSSNV wrote:
>>
>>
>> On 4/5/2023 7:31 PM, Krzysztof Kozlowski wrote:
>>> On 05/04/2023 14:57, Krishna Kurapati wrote:
>>>> Add bindings to indicate properties required to support multiport
>>>> on Snps Dwc3 controller.
>>>>
>>>> Suggested-by: Bjorn Andersson <[email protected]>
>>>> Signed-off-by: Krishna Kurapati <[email protected]>
>>>> ---
>>>> Link to v5: https://lore.kernel.org/all/[email protected]/
>>>
>>> You did not test it at v4 and you got report for this. Your changelog in
>>> commit msg does not mention fixing it.
>>>
>>> It looks like you did not test it for the second time (or sixth time).
>>>
>>> Best regards,
>>> Krzysztof
>>>
>> Hi Krzysztof,
>>
>> I did do a dt_binding_check and I got the following result:
>>
>> kriskura@hu-kriskura-hyd:/local/mnt/workspace/krishna/skales2/skales/kernel$
>> make DT_CHECKER_FLAGS=-m dt_binding_check
>> DT_SCHEMA_FILES=Documentation/devicetree/bindings/usb/snps,dwc3.yaml
>> HOSTCC scripts/basic/fixdep
>> HOSTCC scripts/dtc/dtc.o
>> HOSTCC scripts/dtc/flattree.o
>> HOSTCC scripts/dtc/fstree.o
>> HOSTCC scripts/dtc/data.o
>> HOSTCC scripts/dtc/livetree.o
>> HOSTCC scripts/dtc/treesource.o
>> HOSTCC scripts/dtc/srcpos.o
>> HOSTCC scripts/dtc/checks.o
>> HOSTCC scripts/dtc/util.o
>> LEX scripts/dtc/dtc-lexer.lex.c
>> YACC scripts/dtc/dtc-parser.tab.[ch]
>> HOSTCC scripts/dtc/dtc-lexer.lex.o
>> HOSTCC scripts/dtc/dtc-parser.tab.o
>> HOSTLD scripts/dtc/dtc
>> LINT Documentation/devicetree/bindings
>> invalid config: unknown option "max-spaces-inside-empty" for rule "brackets"
>> xargs: /usr/bin/yamllint: exited with status 255; aborting
>
> This indicates your yamllint version is too old.
>
> Rob
Let me give a try with latest version.
Thanks for pointing it out. ????
Regards,
Krishna,
On Wed, Apr 05, 2023, Krishna Kurapati wrote:
> Currently host-only capable DWC3 controllers support Multiport. Temporarily
> map XHCI address space for host-only controllers and parse XHCI Extended
> Capabilities registers to read number of usb2 ports and usb3 ports present on
> multiport controller. Each USB Port is atleast HS capable.
>
> The port info for usb2 and usb3 phy are identified as num_usb2_ports and
> num_usb3_ports. The intention is as follows:
>
> Wherever we need to perform phy operations like:
>
> LOOP_OVER_NUMBER_OF_AVAILABLE_PORTS()
> {
> phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
> phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
> }
>
> If number of usb2 ports is 3, loop can go from index 0-2 for usb2_generic_phy.
> If number of usb3-ports is 2, we don't know for sure, if the first 2 ports are
> SS capable or some other ports like (2 and 3) are SS capable. So instead,
> num_usb2_ports is used to loop around all phy's (both hs and ss) for
> performing phy operations. If any usb3_generic_phy turns out to be NULL, phy
> operation just bails out.
>
> num_usb3_ports is used to modify GUSB3PIPECTL registers while setting up
> phy's as we need to know how many SS capable ports are there for this.
>
> Signed-off-by: Krishna Kurapati <[email protected]>
> ---
> Link to v5: https://urldefense.com/v3/__https://lore.kernel.org/all/[email protected]/__;!!A4F2R9G_pg!eXaKJejrT053M_6af46mC8jjyBmdZBBhJ0bVKlyxFiIMR_V1RwlBs_9VdvXhpJuNBDHi0d8kdZDrI0MdFKnKA6VA0i6Fww$
>
> drivers/usb/dwc3/core.c | 69 +++++++++++++++++++++++++++++++++++++++++
> drivers/usb/dwc3/core.h | 60 +++++++++++++++++++++++++++++++++++
> 2 files changed, 129 insertions(+)
>
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 476b63618511..567ae79389a1 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -1750,6 +1750,60 @@ static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
> return edev;
> }
>
> +static int dwc3_read_port_info(struct dwc3 *dwc)
> +{
> + void __iomem *regs;
> + u32 offset;
> + u32 temp;
> + u8 major_revision;
> + int ret = 0;
> +
> + /*
> + * Remap xHCI address space to access XHCI ext cap regs,
> + * since it is needed to get port info.
> + */
> + regs = ioremap(dwc->xhci_resources[0].start,
> + resource_size(&dwc->xhci_resources[0]));
> + if (IS_ERR(regs)) {
> + return PTR_ERR(regs);
> + }
> +
> + offset = dwc3_xhci_find_next_ext_cap(regs, 0,
> + XHCI_EXT_CAPS_PROTOCOL);
> + while (offset) {
> + temp = readl(regs + offset);
> + major_revision = XHCI_EXT_PORT_MAJOR(temp);;
> +
> + temp = readl(regs + offset + 0x08);
> + if (major_revision == 0x03) {
> + dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(temp);
> + } else if (major_revision <= 0x02) {
> + dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(temp);
> + } else {
> + dev_err(dwc->dev, "port revision seems wrong\n");
> + ret = -EINVAL;
> + goto unmap_reg;
> + }
> +
> + offset = dwc3_xhci_find_next_ext_cap(regs, offset,
> + XHCI_EXT_CAPS_PROTOCOL);
> + }
> +
> + temp = readl(regs + DWC3_XHCI_HCSPARAMS1);
> + if (HCS_MAX_PORTS(temp) != (dwc->num_usb3_ports + dwc->num_usb2_ports)) {
> + dev_err(dwc->dev, "inconsistency in port info\n");
> + ret = -EINVAL;
> + goto unmap_reg;
> + }
> +
> + dev_dbg(dwc->dev,
> + "hs-ports: %d ss-ports: %d\n", dwc->num_usb2_ports, dwc->num_usb3_ports);
> +
> +unmap_reg:
> + iounmap(regs);
> + return ret;
> +}
> +
> static int dwc3_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> @@ -1757,6 +1811,7 @@ static int dwc3_probe(struct platform_device *pdev)
> struct dwc3 *dwc;
>
> int ret;
> + unsigned int hw_mode;
>
> void __iomem *regs;
>
> @@ -1880,6 +1935,20 @@ static int dwc3_probe(struct platform_device *pdev)
> goto disable_clks;
> }
>
> + /*
> + * Currently DWC3 controllers that are host-only capable
> + * support Multiport
> + */
> + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
> + if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
> + ret = dwc3_read_port_info(dwc);
> + if (ret)
> + goto disable_clks;
> + } else {
> + dwc->num_usb2_ports = 1;
> + dwc->num_usb3_ports = 1;
> + }
> +
> spin_lock_init(&dwc->lock);
> mutex_init(&dwc->mutex);
>
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index 4743e918dcaf..229b7da8c5bc 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -35,6 +35,17 @@
>
> #define DWC3_MSG_MAX 500
>
> +/* Define XHCI Extcap register offsets for getting multiport info */
> +#define XHCI_HCC_PARAMS_OFFSET 0x10
> +#define DWC3_XHCI_HCSPARAMS1 0x04
> +#define XHCI_EXT_CAPS_PROTOCOL 2
> +#define XHCI_HCC_EXT_CAPS(p) (((p)>>16)&0xffff)
> +#define XHCI_EXT_CAPS_ID(p) (((p)>>0)&0xff)
> +#define XHCI_EXT_CAPS_NEXT(p) (((p)>>8)&0xff)
Fix these spacing and naming inconsistency (x vs p).
> +#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
> +#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
> +#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
> +
> /* Global constants */
> #define DWC3_PULL_UP_TIMEOUT 500 /* ms */
> #define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */
> @@ -1023,6 +1034,10 @@ struct dwc3_scratchpad_array {
> * @usb_psy: pointer to power supply interface.
> * @usb2_phy: pointer to USB2 PHY
> * @usb3_phy: pointer to USB3 PHY
> + * @num_usb2_ports: Indicates the number of usb2 ports to be serviced by the
> + * controller.
Can we just say "number of usb2 ports".
> + * @num_usb3_ports: Indicates the number of usb3 ports to be serviced by the
> + * controller.
> * @usb2_generic_phy: pointer to USB2 PHY
> * @usb3_generic_phy: pointer to USB3 PHY
> * @phys_ready: flag to indicate that PHYs are ready
> @@ -1158,6 +1173,8 @@ struct dwc3 {
> struct usb_phy *usb2_phy;
> struct usb_phy *usb3_phy;
>
> + u32 num_usb2_ports;
> + u32 num_usb3_ports;
> struct phy *usb2_generic_phy;
> struct phy *usb3_generic_phy;
>
> @@ -1645,4 +1662,47 @@ static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
> { }
> #endif
>
> +/**
> + * Find the offset of the extended capabilities with capability ID id.
> + *
> + * @base PCI MMIO registers base address.
> + * @start address at which to start looking, (0 or HCC_PARAMS to start at
> + * beginning of list)
> + * @id Extended capability ID to search for, or 0 for the next
> + * capability
> + *
> + * Returns the offset of the next matching extended capability structure.
> + * Some capabilities can occur several times, e.g., the XHCI_EXT_CAPS_PROTOCOL,
> + * and this provides a way to find them all.
> + */
Documentation style is different?
> +
> +static inline int dwc3_xhci_find_next_ext_cap(void __iomem *base, u32 start, int id)
> +{
> + u32 val;
> + u32 next;
> + u32 offset;
> +
> + offset = start;
> + if (!start || start == XHCI_HCC_PARAMS_OFFSET) {
> + val = readl(base + XHCI_HCC_PARAMS_OFFSET);
> + if (val == ~0)
> + return 0;
> + offset = XHCI_HCC_EXT_CAPS(val) << 2;
> + if (!offset)
> + return 0;
> + }
> + do {
> + val = readl(base + offset);
> + if (val == ~0)
> + return 0;
> + if (offset != start && (id == 0 || XHCI_EXT_CAPS_ID(val) == id))
> + return offset;
> +
> + next = XHCI_EXT_CAPS_NEXT(val);
> + offset += next << 2;
> + } while (next);
> +
> + return 0;
> +}
> +
> #endif /* __DRIVERS_USB_DWC3_CORE_H */
> --
> 2.40.0
>
My checkpatch reports some errors. Can you check?
Thanks,
Thinh
On Wed, Apr 05, 2023, Krishna Kurapati wrote:
> Currently the DWC3 driver supports only single port controller which
> requires at most two PHYs ie HS and SS PHYs. There are SoCs that has
> DWC3 controller with multiple ports that can operate in host mode.
> Some of the port supports both SS+HS and other port supports only HS
> mode.
>
> This change primarily refactors the Phy logic in core driver to allow
> multiport support with Generic Phy's.
>
> Chananges have been tested on QCOM SoC SA8295P which has 4 ports (2
> are HS+SS capable and 2 are HS only capable).
>
> Changes in v6:
> Updated comments in code after.
> Updated variables names appropriately as per review comments.
> Updated commit text in patch-2 and added additional info as per review
> comments.
> The patch header in v5 doesn't have "PATHCH v5" notation present. Corrected
> it in this version.
>
> Changes in v5:
> Added DT support for first port of Teritiary USB controller on SA8540-Ride
> Added support for reading port info from XHCI Extended Params registers.
>
> Changes in RFC v4:
> Added DT support for SA8295p.
>
> Changes in RFC v3:
> Incase any PHY init fails, then clear/exit the PHYs that
> are already initialized.
>
> Changes in RFC v2:
> Changed dwc3_count_phys to return the number of PHY Phandles in the node.
> This will be used now in dwc3_extract_num_phys to increment num_usb2_phy
> and num_usb3_phy.
>
> Added new parameter "ss_idx" in dwc3_core_get_phy_ny_node and changed its
> structure such that the first half is for HS-PHY and second half is for
> SS-PHY.
>
> In dwc3_core_get_phy, for multiport controller, only if SS-PHY phandle is
> present, pass proper SS_IDX else pass -1.
>
> Link to v5: https://urldefense.com/v3/__https://lore.kernel.org/all/[email protected]/__;!!A4F2R9G_pg!b6YnNIov1GQE0nNkw05sW71n3ZpTM04st-Y-J5ksBUel2ZZfWr9ZA_AE4ZtBAADuCpJ4C4RCr9Di1-fOfqJk1O7oBPDywQ$
> Link to RFC v4: https://urldefense.com/v3/__https://lore.kernel.org/all/[email protected]/__;!!A4F2R9G_pg!b6YnNIov1GQE0nNkw05sW71n3ZpTM04st-Y-J5ksBUel2ZZfWr9ZA_AE4ZtBAADuCpJ4C4RCr9Di1-fOfqJk1O5p58Ga7A$
> Link to RFC v3: https://urldefense.com/v3/__https://lore.kernel.org/all/[email protected]/*r__;Iw!!A4F2R9G_pg!b6YnNIov1GQE0nNkw05sW71n3ZpTM04st-Y-J5ksBUel2ZZfWr9ZA_AE4ZtBAADuCpJ4C4RCr9Di1-fOfqJk1O5eLTSOZg$
> Link to RFC v2: https://urldefense.com/v3/__https://lore.kernel.org/all/[email protected]/*r__;Iw!!A4F2R9G_pg!b6YnNIov1GQE0nNkw05sW71n3ZpTM04st-Y-J5ksBUel2ZZfWr9ZA_AE4ZtBAADuCpJ4C4RCr9Di1-fOfqJk1O5CAsP83Q$
>
> Krishna Kurapati (8):
> dt-bindings: usb: Add bindings for multiport properties on DWC3
> controller
> usb: dwc3: core: Access XHCI address space temporarily to read port
> info
> usb: dwc3: core: Skip setting event buffers for host only controllers
> usb: dwc3: core: Refactor PHY logic to support Multiport Controller
> usb: dwc3: qcom: Add multiport controller support for qcom wrapper
> arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280
> arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB
> ports
> arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb
> controller
>
> .../devicetree/bindings/usb/snps,dwc3.yaml | 13 +-
> arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 47 +++
> arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 58 +++
> drivers/usb/dwc3/core.c | 373 ++++++++++++++----
> drivers/usb/dwc3/core.h | 71 +++-
> drivers/usb/dwc3/drd.c | 13 +-
> drivers/usb/dwc3/dwc3-qcom.c | 28 +-
> 8 files changed, 523 insertions(+), 102 deletions(-)
>
> --
> 2.40.0
>
Please check if your patches and mailing client. Looks like they are
corrupted.
Thanks,
Thinh
On 08/04/2023 03:42, Thinh Nguyen wrote:
>> Krishna Kurapati (8):
>> dt-bindings: usb: Add bindings for multiport properties on DWC3
>> controller
>> usb: dwc3: core: Access XHCI address space temporarily to read port
>> info
>> usb: dwc3: core: Skip setting event buffers for host only controllers
>> usb: dwc3: core: Refactor PHY logic to support Multiport Controller
>> usb: dwc3: qcom: Add multiport controller support for qcom wrapper
>> arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280
>> arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB
>> ports
>> arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb
>> controller
>>
>> .../devicetree/bindings/usb/snps,dwc3.yaml | 13 +-
>> arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 47 +++
>> arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++
>> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 58 +++
>> drivers/usb/dwc3/core.c | 373 ++++++++++++++----
>> drivers/usb/dwc3/core.h | 71 +++-
>> drivers/usb/dwc3/drd.c | 13 +-
>> drivers/usb/dwc3/dwc3-qcom.c | 28 +-
>> 8 files changed, 523 insertions(+), 102 deletions(-)
>>
>> --
>> 2.40.0
>>
>
> Please check if your patches and mailing client. Looks like they are
> corrupted.
All patches look from patch-syntax and apply fine. What is exactly
corrupted?
Best regards,
Krzysztof
On Sat, Apr 08, 2023, Krzysztof Kozlowski wrote:
> On 08/04/2023 03:42, Thinh Nguyen wrote:
> >> Krishna Kurapati (8):
> >> dt-bindings: usb: Add bindings for multiport properties on DWC3
> >> controller
> >> usb: dwc3: core: Access XHCI address space temporarily to read port
> >> info
> >> usb: dwc3: core: Skip setting event buffers for host only controllers
> >> usb: dwc3: core: Refactor PHY logic to support Multiport Controller
> >> usb: dwc3: qcom: Add multiport controller support for qcom wrapper
> >> arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280
> >> arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB
> >> ports
> >> arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb
> >> controller
> >>
> >> .../devicetree/bindings/usb/snps,dwc3.yaml | 13 +-
> >> arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 47 +++
> >> arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++
> >> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 58 +++
> >> drivers/usb/dwc3/core.c | 373 ++++++++++++++----
> >> drivers/usb/dwc3/core.h | 71 +++-
> >> drivers/usb/dwc3/drd.c | 13 +-
> >> drivers/usb/dwc3/dwc3-qcom.c | 28 +-
> >> 8 files changed, 523 insertions(+), 102 deletions(-)
> >>
> >> --
> >> 2.40.0
> >>
> >
> > Please check if your patches and mailing client. Looks like they are
> > corrupted.
>
> All patches look from patch-syntax and apply fine. What is exactly
> corrupted?
>
Hm... perhaps it's an encoding issue from my mail client then. I get
this from my automated checks:
<snip>
ERROR: spaces required around that '=' (ctx:WxV)
#429: FILE: drivers/usb/dwc3/core.h:1697:
+ if (offset !=3D start && (id =3D=3D 0 || XHCI_EXT_CAPS_ID(val) =3D=3D id=
^
ERROR: spaces required around that '=' (ctx:VxV)
#429: FILE: drivers/usb/dwc3/core.h:1697:
+ if (offset !=3D start && (id =3D=3D 0 || XHCI_EXT_CAPS_ID(val) =3D=3D id=
^
ERROR: spaces required around that '=' (ctx:VxE)
#429: FILE: drivers/usb/dwc3/core.h:1697:
+ if (offset !=3D start && (id =3D=3D 0 || XHCI_EXT_CAPS_ID(val) =3D=3D id=
^
ERROR: do not use assignment in if condition
#429: FILE: drivers/usb/dwc3/core.h:1697:
+ if (offset !=3D start && (id =3D=3D 0 || XHCI_EXT_CAPS_ID(val) =3D=3D id=
ERROR: spaces required around that '=' (ctx:WxV)
#433: FILE: drivers/usb/dwc3/core.h:1700:
+ next =3D XHCI_EXT_CAPS_NEXT(val);
^
ERROR: spaces required around that '+=' (ctx:WxV)
#434: FILE: drivers/usb/dwc3/core.h:1701:
+ offset +=3D next << 2;
</snip>
The "=" gets encoded to =3D, which is strange. It never happened before.
I need to check my mail client. Sorry for the noise.
Thanks,
Thinh
On 09/04/2023 01:09, Thinh Nguyen wrote:
> On Sat, Apr 08, 2023, Krzysztof Kozlowski wrote:
>> On 08/04/2023 03:42, Thinh Nguyen wrote:
>>>> Krishna Kurapati (8):
>>>> dt-bindings: usb: Add bindings for multiport properties on DWC3
>>>> controller
>>>> usb: dwc3: core: Access XHCI address space temporarily to read port
>>>> info
>>>> usb: dwc3: core: Skip setting event buffers for host only controllers
>>>> usb: dwc3: core: Refactor PHY logic to support Multiport Controller
>>>> usb: dwc3: qcom: Add multiport controller support for qcom wrapper
>>>> arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280
>>>> arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB
>>>> ports
>>>> arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb
>>>> controller
>>>>
>>>> .../devicetree/bindings/usb/snps,dwc3.yaml | 13 +-
>>>> arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 47 +++
>>>> arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++
>>>> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 58 +++
>>>> drivers/usb/dwc3/core.c | 373 ++++++++++++++----
>>>> drivers/usb/dwc3/core.h | 71 +++-
>>>> drivers/usb/dwc3/drd.c | 13 +-
>>>> drivers/usb/dwc3/dwc3-qcom.c | 28 +-
>>>> 8 files changed, 523 insertions(+), 102 deletions(-)
>>>>
>>>> --
>>>> 2.40.0
>>>>
>>>
>>> Please check if your patches and mailing client. Looks like they are
>>> corrupted.
>>
>> All patches look from patch-syntax and apply fine. What is exactly
>> corrupted?
>>
>
> Hm... perhaps it's an encoding issue from my mail client then. I get
> this from my automated checks:
>
> <snip>
>
> ERROR: spaces required around that '=' (ctx:WxV)
> #429: FILE: drivers/usb/dwc3/core.h:1697:
> + if (offset !=3D start && (id =3D=3D 0 || XHCI_EXT_CAPS_ID(val) =3D=3D id=
> ^
>
> ERROR: spaces required around that '=' (ctx:VxV)
> #429: FILE: drivers/usb/dwc3/core.h:1697:
> + if (offset !=3D start && (id =3D=3D 0 || XHCI_EXT_CAPS_ID(val) =3D=3D id=
> ^
>
> ERROR: spaces required around that '=' (ctx:VxE)
> #429: FILE: drivers/usb/dwc3/core.h:1697:
> + if (offset !=3D start && (id =3D=3D 0 || XHCI_EXT_CAPS_ID(val) =3D=3D id=
> ^
>
> ERROR: do not use assignment in if condition
> #429: FILE: drivers/usb/dwc3/core.h:1697:
> + if (offset !=3D start && (id =3D=3D 0 || XHCI_EXT_CAPS_ID(val) =3D=3D id=
>
> ERROR: spaces required around that '=' (ctx:WxV)
> #433: FILE: drivers/usb/dwc3/core.h:1700:
> + next =3D XHCI_EXT_CAPS_NEXT(val);
> ^
>
> ERROR: spaces required around that '+=' (ctx:WxV)
> #434: FILE: drivers/usb/dwc3/core.h:1701:
> + offset +=3D next << 2;
>
> </snip>
>
>
> The "=" gets encoded to =3D, which is strange. It never happened before.
> I need to check my mail client. Sorry for the noise.
I don't see it, but I did not check each patch thoroughly. I also do not
know to which patch do you refer to. It is the easiest to reply inline
under the block which is corrupted. If you suspect you email client is
the cause, just check on lore.
Best regards,
Krzysztof
Hi,
> Krishna Kurapati (8):
> dt-bindings: usb: Add bindings for multiport properties on DWC3
> controller
> usb: dwc3: core: Access XHCI address space temporarily to read port
> info
> usb: dwc3: core: Skip setting event buffers for host only controllers
> usb: dwc3: core: Refactor PHY logic to support Multiport Controller
> usb: dwc3: qcom: Add multiport controller support for qcom wrapper
> arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280
> arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB
> ports
> arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb
> controller
>
> .../devicetree/bindings/usb/snps,dwc3.yaml | 13 +-
> arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 47 +++
> arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 58 +++
> drivers/usb/dwc3/core.c | 373 ++++++++++++++----
> drivers/usb/dwc3/core.h | 71 +++-
> drivers/usb/dwc3/drd.c | 13 +-
> drivers/usb/dwc3/dwc3-qcom.c | 28 +-
> 8 files changed, 523 insertions(+), 102 deletions(-)
I tested this series on the sa8540p-ride, with a USB Ethernet adapter
plugged into the board. The device shows up as expected:
# lsusb -tv
/: Bus 02.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/2p, 10000M
ID 1d6b:0003 Linux Foundation 3.0 root hub
|__ Port 1: Dev 2, If 0, Class=Vendor Specific Class, Driver=r8152, 5000M
ID 0bda:8153 Realtek Semiconductor Corp. RTL8153 Gigabit Ethernet Adapter
/: Bus 01.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/4p, 480M
ID 1d6b:0002 Linux Foundation 2.0 root hub
Tested-by: Adrien Thierry <[email protected]> # sa8540p-ride
On 4/14/2023 12:24 AM, Adrien Thierry wrote:
> Hi,
>
>> Krishna Kurapati (8):
>> dt-bindings: usb: Add bindings for multiport properties on DWC3
>> controller
>> usb: dwc3: core: Access XHCI address space temporarily to read port
>> info
>> usb: dwc3: core: Skip setting event buffers for host only controllers
>> usb: dwc3: core: Refactor PHY logic to support Multiport Controller
>> usb: dwc3: qcom: Add multiport controller support for qcom wrapper
>> arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280
>> arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB
>> ports
>> arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb
>> controller
>>
>> .../devicetree/bindings/usb/snps,dwc3.yaml | 13 +-
>> arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 47 +++
>> arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++
>> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 58 +++
>> drivers/usb/dwc3/core.c | 373 ++++++++++++++----
>> drivers/usb/dwc3/core.h | 71 +++-
>> drivers/usb/dwc3/drd.c | 13 +-
>> drivers/usb/dwc3/dwc3-qcom.c | 28 +-
>> 8 files changed, 523 insertions(+), 102 deletions(-)
>
> I tested this series on the sa8540p-ride, with a USB Ethernet adapter
> plugged into the board. The device shows up as expected:
>
> # lsusb -tv
> /: Bus 02.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/2p, 10000M
> ID 1d6b:0003 Linux Foundation 3.0 root hub
> |__ Port 1: Dev 2, If 0, Class=Vendor Specific Class, Driver=r8152, 5000M
> ID 0bda:8153 Realtek Semiconductor Corp. RTL8153 Gigabit Ethernet Adapter
> /: Bus 01.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/4p, 480M
> ID 1d6b:0002 Linux Foundation 2.0 root hub
>
> Tested-by: Adrien Thierry <[email protected]> # sa8540p-ride
>
Hi Adrien,
Thanks for testing out the patches.
Regards,
Krishna,
On Wed, Apr 05, 2023 at 06:27:57PM +0530, Krishna Kurapati wrote:
> Add USB and DWC3 node for tertiary port of SC8280 along with multiport
> IRQ's and phy's. This will be used as a base for SA8295P and SA8295-Ride
> platforms.
>
> Signed-off-by: Krishna Kurapati <[email protected]>
> ---
> Link to v5: https://lore.kernel.org/all/[email protected]/
>
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 58 ++++++++++++++++++++++++++
> 1 file changed, 58 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 42bfa9fa5b96..7b81f2b0449d 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -3108,6 +3108,64 @@ usb_1_role_switch: endpoint {
> };
> };
>
> + usb_2: usb@a4f8800 {
> + compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
> + reg = <0 0x0a4f8800 0 0x400>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
> + <&gcc GCC_USB30_MP_MASTER_CLK>,
> + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
> + <&gcc GCC_USB30_MP_SLEEP_CLK>,
> + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
> + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
> + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
> + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
> + <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
> + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
> + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
> +
> + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
> + <&gcc GCC_USB30_MP_MASTER_CLK>;
> + assigned-clock-rates = <19200000>, <200000000>;
> +
> + interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>,
> + <&pdc 126 IRQ_TYPE_EDGE_RISING>,
> + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
> +
> + interrupt-names = "dp_hs_phy_irq", "dm_hs_phy_irq",
> + "ss_phy_irq";
> +
This is breaking the current schema (with the full series applied),
I am not sure if a pwr_event IRQ exists or but it maybe necessary to
modify qcom,dwc3.yaml in order to explain hardware if it doesn't exist:
(dtschema) ahalaney@halaney-x13s ~/git/linux-next (git)-[718f2024524f] % make CHECK_DTBS=y DT_SCHEMA_FILES=/usb/qcom,dwc3.yaml qcom/sa8540p-ride.dtb :(
LINT Documentation/devicetree/bindings
CHKDT Documentation/devicetree/bindings/processed-schema.json
SCHEMA Documentation/devicetree/bindings/processed-schema.json
DTC_CHK arch/arm64/boot/dts/qcom/sa8540p-ride.dtb
/home/ahalaney/git/linux-next/arch/arm64/boot/dts/qcom/sa8540p-ride.dtb: usb@a4f8800: interrupt-names:0: 'pwr_event' was expected
From schema: /home/ahalaney/git/linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
/home/ahalaney/git/linux-next/arch/arm64/boot/dts/qcom/sa8540p-ride.dtb: usb@a4f8800: interrupt-names:1: 'dp_hs_phy_irq' was expected
From schema: /home/ahalaney/git/linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
/home/ahalaney/git/linux-next/arch/arm64/boot/dts/qcom/sa8540p-ride.dtb: usb@a4f8800: interrupt-names:2: 'dm_hs_phy_irq' was expected
From schema: /home/ahalaney/git/linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
/home/ahalaney/git/linux-next/arch/arm64/boot/dts/qcom/sa8540p-ride.dtb: usb@a4f8800: interrupt-names: ['dp_hs_phy_irq', 'dm_hs_phy_irq', 'ss_phy_irq'] is too short
From schema: /home/ahalaney/git/linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
/home/ahalaney/git/linux-next/arch/arm64/boot/dts/qcom/sa8540p-ride.dtb: usb@a4f8800: interrupts-extended: [[99, 127, 1], [99, 126, 1], [99, 16, 4]] is too short
From schema: /home/ahalaney/git/linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
make CHECK_DTBS=y DT_SCHEMA_FILES=/usb/qcom,dwc3.yaml qcom/sa8540p-ride.dtb 22.61s user 0.54s system 99% cpu 23.172 total
(dtschema) ahalaney@halaney-x13s ~/git/linux-next (git)-[718f2024524f] %
Thanks,
Andrew
On Wed, Apr 05, 2023 at 06:27:59PM +0530, Krishna Kurapati wrote:
> Enable first port of Quad port Tertiary USB controller for SA8540 Ride.
>
> Signed-off-by: Krishna Kurapati <[email protected]>
This is nitpicky, but I liked some of the description in the first[0]
version of this patch that I authored for you:
From dcb27d07f079194ebd7efe1c9bec64da78beb290 Mon Sep 17 00:00:00 2001
From: Andrew Halaney <[email protected]>
Date: Thu, 19 Jan 2023 14:53:38 -0600
Subject: [PATCH] arm64: dts: qcom: sa8540p-ride: Enable usb_2
Content-type: text/plain
There is now support for the multiport USB controller this uses
so enable it.
The board only has a single port hooked up (despite it being wired up to
the multiport IP on the SoC). There's also a USB 2.0 mux hooked up,
which by default on boot is selected to mux properly. Grab the gpio
controlling that and ensure it stays in the right position so USB 2.0
continues to be routed from the external port to the SoC.
Signed-off-by: Andrew Halaney <[email protected]>
Specifically the bit helping explain what the mux, its default state,
etc are things I find explain some of the hardware/patch better. Personal
opinion of course but I'll highlight it since you dropped it out :)
[0] https://lore.kernel.org/linux-arm-msm/20230119220942.ja5gbo3t3fl63gpy@halaney-x13s/
Either way, thanks for taking the patch along and working on this.
Thanks,
Andrew
On 4/14/2023 9:15 PM, Andrew Halaney wrote:
> On Wed, Apr 05, 2023 at 06:27:57PM +0530, Krishna Kurapati wrote:
>> Add USB and DWC3 node for tertiary port of SC8280 along with multiport
>> IRQ's and phy's. This will be used as a base for SA8295P and SA8295-Ride
>> platforms.
>>
>> Signed-off-by: Krishna Kurapati <[email protected]>
>> ---
>> Link to v5: https://lore.kernel.org/all/[email protected]/
>>
>> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 58 ++++++++++++++++++++++++++
>> 1 file changed, 58 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> index 42bfa9fa5b96..7b81f2b0449d 100644
>> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> @@ -3108,6 +3108,64 @@ usb_1_role_switch: endpoint {
>> };
>> };
>>
>> + usb_2: usb@a4f8800 {
>> + compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
>> + reg = <0 0x0a4f8800 0 0x400>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
>> + <&gcc GCC_USB30_MP_MASTER_CLK>,
>> + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
>> + <&gcc GCC_USB30_MP_SLEEP_CLK>,
>> + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
>> + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
>> + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
>> + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
>> + <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
>> + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
>> + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
>> +
>> + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
>> + <&gcc GCC_USB30_MP_MASTER_CLK>;
>> + assigned-clock-rates = <19200000>, <200000000>;
>> +
>> + interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>,
>> + <&pdc 126 IRQ_TYPE_EDGE_RISING>,
>> + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + interrupt-names = "dp_hs_phy_irq", "dm_hs_phy_irq",
>> + "ss_phy_irq";
>> +
>
> This is breaking the current schema (with the full series applied),
> I am not sure if a pwr_event IRQ exists or but it maybe necessary to
> modify qcom,dwc3.yaml in order to explain hardware if it doesn't exist:
>
> (dtschema) ahalaney@halaney-x13s ~/git/linux-next (git)-[718f2024524f] % make CHECK_DTBS=y DT_SCHEMA_FILES=/usb/qcom,dwc3.yaml qcom/sa8540p-ride.dtb :(
> LINT Documentation/devicetree/bindings
> CHKDT Documentation/devicetree/bindings/processed-schema.json
> SCHEMA Documentation/devicetree/bindings/processed-schema.json
> DTC_CHK arch/arm64/boot/dts/qcom/sa8540p-ride.dtb
> /home/ahalaney/git/linux-next/arch/arm64/boot/dts/qcom/sa8540p-ride.dtb: usb@a4f8800: interrupt-names:0: 'pwr_event' was expected
> From schema: /home/ahalaney/git/linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> /home/ahalaney/git/linux-next/arch/arm64/boot/dts/qcom/sa8540p-ride.dtb: usb@a4f8800: interrupt-names:1: 'dp_hs_phy_irq' was expected
> From schema: /home/ahalaney/git/linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> /home/ahalaney/git/linux-next/arch/arm64/boot/dts/qcom/sa8540p-ride.dtb: usb@a4f8800: interrupt-names:2: 'dm_hs_phy_irq' was expected
> From schema: /home/ahalaney/git/linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> /home/ahalaney/git/linux-next/arch/arm64/boot/dts/qcom/sa8540p-ride.dtb: usb@a4f8800: interrupt-names: ['dp_hs_phy_irq', 'dm_hs_phy_irq', 'ss_phy_irq'] is too short
> From schema: /home/ahalaney/git/linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> /home/ahalaney/git/linux-next/arch/arm64/boot/dts/qcom/sa8540p-ride.dtb: usb@a4f8800: interrupts-extended: [[99, 127, 1], [99, 126, 1], [99, 16, 4]] is too short
> From schema: /home/ahalaney/git/linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> make CHECK_DTBS=y DT_SCHEMA_FILES=/usb/qcom,dwc3.yaml qcom/sa8540p-ride.dtb 22.61s user 0.54s system 99% cpu 23.172 total
> (dtschema) ahalaney@halaney-x13s ~/git/linux-next (git)-[718f2024524f] %
>
> Thanks,
> Andrew
>
Hi Andrew,
Thanks for pointing it out. Let me check and get back on the
pwr_event_irq.
Probably I might have missed it ????. If so, will make sure to add it in
next version.
Regards,
Krishna,
On 4/14/2023 9:21 PM, Andrew Halaney wrote:
> On Wed, Apr 05, 2023 at 06:27:59PM +0530, Krishna Kurapati wrote:
>> Enable first port of Quad port Tertiary USB controller for SA8540 Ride.
>>
>> Signed-off-by: Krishna Kurapati <[email protected]>
>
> This is nitpicky, but I liked some of the description in the first[0]
> version of this patch that I authored for you:
>
> From dcb27d07f079194ebd7efe1c9bec64da78beb290 Mon Sep 17 00:00:00 2001
> From: Andrew Halaney <[email protected]>
> Date: Thu, 19 Jan 2023 14:53:38 -0600
> Subject: [PATCH] arm64: dts: qcom: sa8540p-ride: Enable usb_2
> Content-type: text/plain
>
> There is now support for the multiport USB controller this uses
> so enable it.
>
> The board only has a single port hooked up (despite it being wired up to
> the multiport IP on the SoC). There's also a USB 2.0 mux hooked up,
> which by default on boot is selected to mux properly. Grab the gpio
> controlling that and ensure it stays in the right position so USB 2.0
> continues to be routed from the external port to the SoC.
>
> Signed-off-by: Andrew Halaney <[email protected]>
>
> Specifically the bit helping explain what the mux, its default state,
> etc are things I find explain some of the hardware/patch better. Personal
> opinion of course but I'll highlight it since you dropped it out :)
>
> [0] https://lore.kernel.org/linux-arm-msm/20230119220942.ja5gbo3t3fl63gpy@halaney-x13s/
>
> Either way, thanks for taking the patch along and working on this.
>
> Thanks,
> Andrew
>
Hi Andrew, Sorry for that. Will make sure to update the commit text with
this info in the next version.
Regards,
Krishna,
On 4/16/2023 12:34 AM, Krishna Kurapati PSSNV wrote:
>
>
> On 4/14/2023 9:15 PM, Andrew Halaney wrote:
>> On Wed, Apr 05, 2023 at 06:27:57PM +0530, Krishna Kurapati wrote:
>>> Add USB and DWC3 node for tertiary port of SC8280 along with multiport
>>> IRQ's and phy's. This will be used as a base for SA8295P and SA8295-Ride
>>> platforms.
>>>
>>> Signed-off-by: Krishna Kurapati <[email protected]>
>>> ---
>>> Link to v5:
>>> https://lore.kernel.org/all/[email protected]/
>>>
>>> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 58 ++++++++++++++++++++++++++
>>> 1 file changed, 58 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>>> b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>>> index 42bfa9fa5b96..7b81f2b0449d 100644
>>> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>>> @@ -3108,6 +3108,64 @@ usb_1_role_switch: endpoint {
>>> };
>>> };
>>> + usb_2: usb@a4f8800 {
>>> + compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
>>> + reg = <0 0x0a4f8800 0 0x400>;
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + ranges;
>>> +
>>> + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
>>> + <&gcc GCC_USB30_MP_MASTER_CLK>,
>>> + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
>>> + <&gcc GCC_USB30_MP_SLEEP_CLK>,
>>> + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
>>> + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
>>> + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
>>> + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
>>> + <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
>>> + clock-names = "cfg_noc", "core", "iface", "sleep",
>>> "mock_utmi",
>>> + "noc_aggr", "noc_aggr_north",
>>> "noc_aggr_south", "noc_sys";
>>> +
>>> + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
>>> + <&gcc GCC_USB30_MP_MASTER_CLK>;
>>> + assigned-clock-rates = <19200000>, <200000000>;
>>> +
>>> + interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>,
>>> + <&pdc 126 IRQ_TYPE_EDGE_RISING>,
>>> + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
>>> +
>>> + interrupt-names = "dp_hs_phy_irq", "dm_hs_phy_irq",
>>> + "ss_phy_irq";
>>> +
>>
>> This is breaking the current schema (with the full series applied),
>> I am not sure if a pwr_event IRQ exists or but it maybe necessary to
>> modify qcom,dwc3.yaml in order to explain hardware if it doesn't exist:
>>
>> (dtschema) ahalaney@halaney-x13s ~/git/linux-next (git)-[718f2024524f]
>> % make CHECK_DTBS=y DT_SCHEMA_FILES=/usb/qcom,dwc3.yaml
>> qcom/sa8540p-ride.dtb :(
>> LINT Documentation/devicetree/bindings
>> CHKDT Documentation/devicetree/bindings/processed-schema.json
>> SCHEMA Documentation/devicetree/bindings/processed-schema.json
>> DTC_CHK arch/arm64/boot/dts/qcom/sa8540p-ride.dtb
>> /home/ahalaney/git/linux-next/arch/arm64/boot/dts/qcom/sa8540p-ride.dtb: usb@a4f8800: interrupt-names:0: 'pwr_event' was expected
>> From schema:
>> /home/ahalaney/git/linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
>> /home/ahalaney/git/linux-next/arch/arm64/boot/dts/qcom/sa8540p-ride.dtb: usb@a4f8800: interrupt-names:1: 'dp_hs_phy_irq' was expected
>> From schema:
>> /home/ahalaney/git/linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
>> /home/ahalaney/git/linux-next/arch/arm64/boot/dts/qcom/sa8540p-ride.dtb: usb@a4f8800: interrupt-names:2: 'dm_hs_phy_irq' was expected
>> From schema:
>> /home/ahalaney/git/linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
>> /home/ahalaney/git/linux-next/arch/arm64/boot/dts/qcom/sa8540p-ride.dtb: usb@a4f8800: interrupt-names: ['dp_hs_phy_irq', 'dm_hs_phy_irq', 'ss_phy_irq'] is too short
>> From schema:
>> /home/ahalaney/git/linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
>> /home/ahalaney/git/linux-next/arch/arm64/boot/dts/qcom/sa8540p-ride.dtb: usb@a4f8800: interrupts-extended: [[99, 127, 1], [99, 126, 1], [99, 16, 4]] is too short
>> From schema:
>> /home/ahalaney/git/linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
>> make CHECK_DTBS=y DT_SCHEMA_FILES=/usb/qcom,dwc3.yaml
>> qcom/sa8540p-ride.dtb 22.61s user 0.54s system 99% cpu 23.172 total
>> (dtschema) ahalaney@halaney-x13s ~/git/linux-next (git)-[718f2024524f] %
>>
>> Thanks,
>> Andrew
>>
>
> Hi Andrew,
>
> Thanks for pointing it out. Let me check and get back on the
> pwr_event_irq.
>
> Probably I might have missed it ????. If so, will make sure to add it in
> next version.
>
> Regards,
> Krishna,
Hi Andrew, Johan,
I was looking at the pwr_event_irq interrupts for Multiport
controller and see that there are two of them as per HW specs. All
targets till date have only 1 pwr_event_irq required.
The reason I thought I missed pwr_event_irq in my patches is because in
downstream this is a required IRQ for all targets, so I was under
assumption that we need it for upstream targets as well. But upstream
qcom driver doesn't have support for this IRQ yet. And this has been
made a required one only for SC8280 [1]/[2].
Probably we can proceed in one of the following ways:
1. Remove pwr_event_irq in both bindings and DT as driver support is not
present currently.
2. Update the bindings for SC8280 to include an optional secondary
pwr_event_irq for multiport controller.
I would prefer option-1 as removing them would be better because they
are not being used. Please let me know your thoughts on this.
[1]:
https://lore.kernel.org/all/[email protected]/
[2]:
https://lore.kernel.org/all/[email protected]/
Regards,
Krishna,
On Sat, Apr 22, 2023 at 09:38:44PM +0530, Krishna Kurapati PSSNV wrote:
>
>
> On 4/16/2023 12:34 AM, Krishna Kurapati PSSNV wrote:
> >
> >
> > On 4/14/2023 9:15 PM, Andrew Halaney wrote:
> > > On Wed, Apr 05, 2023 at 06:27:57PM +0530, Krishna Kurapati wrote:
> > > > Add USB and DWC3 node for tertiary port of SC8280 along with multiport
> > > > IRQ's and phy's. This will be used as a base for SA8295P and SA8295-Ride
> > > > platforms.
> > > >
> > > > Signed-off-by: Krishna Kurapati <[email protected]>
> > > > ---
> > > > Link to v5: https://lore.kernel.org/all/[email protected]/
> > > >
> > > > arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 58 ++++++++++++++++++++++++++
> > > > 1 file changed, 58 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > > > b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > > > index 42bfa9fa5b96..7b81f2b0449d 100644
> > > > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > > > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > > > @@ -3108,6 +3108,64 @@ usb_1_role_switch: endpoint {
> > > > };
> > > > };
> > > > + usb_2: usb@a4f8800 {
> > > > + compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
> > > > + reg = <0 0x0a4f8800 0 0x400>;
> > > > + #address-cells = <2>;
> > > > + #size-cells = <2>;
> > > > + ranges;
> > > > +
> > > > + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
> > > > + <&gcc GCC_USB30_MP_MASTER_CLK>,
> > > > + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
> > > > + <&gcc GCC_USB30_MP_SLEEP_CLK>,
> > > > + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
> > > > + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
> > > > + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
> > > > + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
> > > > + <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
> > > > + clock-names = "cfg_noc", "core", "iface", "sleep",
> > > > "mock_utmi",
> > > > + "noc_aggr", "noc_aggr_north",
> > > > "noc_aggr_south", "noc_sys";
> > > > +
> > > > + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
> > > > + <&gcc GCC_USB30_MP_MASTER_CLK>;
> > > > + assigned-clock-rates = <19200000>, <200000000>;
> > > > +
> > > > + interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>,
> > > > + <&pdc 126 IRQ_TYPE_EDGE_RISING>,
> > > > + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
> > > > +
> > > > + interrupt-names = "dp_hs_phy_irq", "dm_hs_phy_irq",
> > > > + "ss_phy_irq";
> > > > +
> > >
> > > This is breaking the current schema (with the full series applied),
> > > I am not sure if a pwr_event IRQ exists or but it maybe necessary to
> > > modify qcom,dwc3.yaml in order to explain hardware if it doesn't exist:
> > >
> > > (dtschema) ahalaney@halaney-x13s ~/git/linux-next
> > > (git)-[718f2024524f] % make CHECK_DTBS=y
> > > DT_SCHEMA_FILES=/usb/qcom,dwc3.yaml qcom/sa8540p-ride.dtb
> > > :(
> > > LINT Documentation/devicetree/bindings
> > > CHKDT Documentation/devicetree/bindings/processed-schema.json
> > > SCHEMA Documentation/devicetree/bindings/processed-schema.json
> > > DTC_CHK arch/arm64/boot/dts/qcom/sa8540p-ride.dtb
> > > /home/ahalaney/git/linux-next/arch/arm64/boot/dts/qcom/sa8540p-ride.dtb: usb@a4f8800: interrupt-names:0: 'pwr_event' was expected
> > > From schema: /home/ahalaney/git/linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> > > /home/ahalaney/git/linux-next/arch/arm64/boot/dts/qcom/sa8540p-ride.dtb: usb@a4f8800: interrupt-names:1: 'dp_hs_phy_irq' was expected
> > > From schema: /home/ahalaney/git/linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> > > /home/ahalaney/git/linux-next/arch/arm64/boot/dts/qcom/sa8540p-ride.dtb: usb@a4f8800: interrupt-names:2: 'dm_hs_phy_irq' was expected
> > > From schema: /home/ahalaney/git/linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> > > /home/ahalaney/git/linux-next/arch/arm64/boot/dts/qcom/sa8540p-ride.dtb: usb@a4f8800: interrupt-names: ['dp_hs_phy_irq', 'dm_hs_phy_irq', 'ss_phy_irq'] is too short
> > > From schema: /home/ahalaney/git/linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> > > /home/ahalaney/git/linux-next/arch/arm64/boot/dts/qcom/sa8540p-ride.dtb: usb@a4f8800: interrupts-extended: [[99, 127, 1], [99, 126, 1], [99, 16, 4]] is too short
> > > From schema: /home/ahalaney/git/linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> > > make CHECK_DTBS=y DT_SCHEMA_FILES=/usb/qcom,dwc3.yaml
> > > qcom/sa8540p-ride.dtb 22.61s user 0.54s system 99% cpu 23.172 total
> > > (dtschema) ahalaney@halaney-x13s ~/git/linux-next (git)-[718f2024524f] %
> > >
> > > Thanks,
> > > Andrew
> > >
> >
> > Hi Andrew,
> >
> > Thanks for pointing it out. Let me check and get back on the
> > pwr_event_irq.
> >
> > Probably I might have missed it ????. If so, will make sure to add it in
> > next version.
> >
> > Regards,
> > Krishna,
>
>
> Hi Andrew, Johan,
>
> I was looking at the pwr_event_irq interrupts for Multiport controller and
> see that there are two of them as per HW specs. All targets till date have
> only 1 pwr_event_irq required.
>
> The reason I thought I missed pwr_event_irq in my patches is because in
> downstream this is a required IRQ for all targets, so I was under assumption
> that we need it for upstream targets as well. But upstream qcom driver
> doesn't have support for this IRQ yet. And this has been made a required one
> only for SC8280 [1]/[2].
>
> Probably we can proceed in one of the following ways:
> 1. Remove pwr_event_irq in both bindings and DT as driver support is not
> present currently.
> 2. Update the bindings for SC8280 to include an optional secondary
> pwr_event_irq for multiport controller.
>
> I would prefer option-1 as removing them would be better because they are
> not being used. Please let me know your thoughts on this.
>
> [1]:
> https://lore.kernel.org/all/[email protected]/
> [2]:
> https://lore.kernel.org/all/[email protected]/
>
Personally, I prefer option 2 since the IRQ does exist technically
(although it isn't currently used), I like it being described... it
makes the dt-binding a more complete description of the hardware.
I am unsure of the rules wrt dt-bindings and usage in drivers, but I
always like to view it as "this is a description of the hardware", and
the driver bit is just nice to have to ensure that whoever is adding the
binding is actually describing things sufficiently.
You could probably add a new compatible string for the multiport
sc8280xp IP as well, and make the second IRQ non-optional in dt-binding
evaluation? That seems more inline with reality, the regular IP has 1
pwr_event_irq, multiport on this platform has 2, they behave slightly
differently and thus they deserve their own string to match on despite
being on the same platform.
Please note, I'm just a contributor -- I would not be surprised to find
out that my view is not aligned with what maintainers here think, but
that's my interpretation of things!
Hope that helps,
Andrew
On Tue, Apr 25, 2023 at 03:33:28PM -0500, Andrew Halaney wrote:
> On Sat, Apr 22, 2023 at 09:38:44PM +0530, Krishna Kurapati PSSNV wrote:
> > Hi Andrew, Johan,
> >
> > I was looking at the pwr_event_irq interrupts for Multiport controller and
> > see that there are two of them as per HW specs. All targets till date have
> > only 1 pwr_event_irq required.
> >
> > The reason I thought I missed pwr_event_irq in my patches is because in
> > downstream this is a required IRQ for all targets, so I was under assumption
> > that we need it for upstream targets as well. But upstream qcom driver
> > doesn't have support for this IRQ yet. And this has been made a required one
> > only for SC8280 [1]/[2].
> >
> > Probably we can proceed in one of the following ways:
> > 1. Remove pwr_event_irq in both bindings and DT as driver support is not
> > present currently.
> > 2. Update the bindings for SC8280 to include an optional secondary
> > pwr_event_irq for multiport controller.
> >
> > I would prefer option-1 as removing them would be better because they are
> > not being used. Please let me know your thoughts on this.
> >
> > [1]:
> > https://lore.kernel.org/all/[email protected]/
> > [2]:
> > https://lore.kernel.org/all/[email protected]/
> >
>
> Personally, I prefer option 2 since the IRQ does exist technically
> (although it isn't currently used), I like it being described... it
> makes the dt-binding a more complete description of the hardware.
>
> I am unsure of the rules wrt dt-bindings and usage in drivers, but I
> always like to view it as "this is a description of the hardware", and
> the driver bit is just nice to have to ensure that whoever is adding the
> binding is actually describing things sufficiently.
As Andrew mentioned, the binding should reflect the hardware and not
what is currently supported in some version of software.
It looks like you even had four of these pwr_event interrupt line
judging from your last iteration of this series.
Johan