First patch splits n25q512a and mt25qu512a into two as they are
different devices. Second patch adds support for more mt25q devices and
last patch adds USE_FSR flag for n25q entries where missing.
Tested with mt25qu512a flash
Vignesh Raghavendra (3):
mtd: spi-nor: Split mt25qu512a (n25q512a) entry into two
mtd: spi-nor: Add entries for mt25q variants
mtd: spi-nor: Add USE_FSR flag for n25q* entries
drivers/mtd/spi-nor/spi-nor.c | 31 +++++++++++++++++++++++--------
1 file changed, 23 insertions(+), 8 deletions(-)
--
2.24.0
mt25q family is different from n25q family of devices, even though manf
ID and device IDs are same. mt25q flash has bit 6 set in 5th byte of
READ ID response which can be used to distinguish it from n25q variant.
mt25q flashes support stateless 4 Byte addressing opcodes where as n25q
flashes don't. Therefore, have two separate entries for mt25qu512a and
n25q512a.
Fixes: 9607af6f857f ("mtd: spi-nor: Rename "n25q512a" to "mt25qu512a (n25q512a)"")
Signed-off-by: Vignesh Raghavendra <[email protected]>
---
drivers/mtd/spi-nor/spi-nor.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index f4afe123e9dc..01efea022990 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -2459,15 +2459,16 @@ static const struct flash_info spi_nor_ids[] = {
{ "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
{ "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
+ { "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024,
+ SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
+ SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K |
+ SPI_NOR_QUAD_READ) },
{ "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096,
SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
NO_CHIP_ERASE) },
- { "mt25qu512a (n25q512a)", INFO(0x20bb20, 0, 64 * 1024, 1024,
- SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
- SPI_NOR_QUAD_READ |
- SPI_NOR_4B_OPCODES) },
{ "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
/* Micron */
--
2.24.0
Add USE_FSR flag to all variants of n25q entries that support Flag Status
Register.
Signed-off-by: Vignesh Raghavendra <[email protected]>
---
drivers/mtd/spi-nor/spi-nor.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index a5cb647378f0..1082b6bb1393 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -2454,16 +2454,21 @@ static const struct flash_info spi_nor_ids[] = {
{ "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
{ "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
{ "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
- { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
- { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
+ { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K |
+ USE_FSR | SPI_NOR_QUAD_READ) },
+ { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K |
+ USE_FSR | SPI_NOR_QUAD_READ) },
{ "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512,
SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
- { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K |
+ USE_FSR | SPI_NOR_DUAL_READ |
+ SPI_NOR_QUAD_READ) },
{ "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512,
SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
- { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
+ { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K |
+ USE_FSR | SPI_NOR_QUAD_READ) },
{ "mt25ql512a", INFO6(0x20ba20, 0x104400, 64 * 1024, 1024,
SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
@@ -2472,7 +2477,7 @@ static const struct flash_info spi_nor_ids[] = {
SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K |
- SPI_NOR_QUAD_READ) },
+ USE_FSR | SPI_NOR_QUAD_READ) },
{ "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096,
--
2.24.0
Add entries for mt25q*256a and mt25q*512a flashes. These are similar to
existing n25q variants but support stateless 4 byte addressing opcodes
Signed-off-by: Vignesh Raghavendra <[email protected]>
---
drivers/mtd/spi-nor/spi-nor.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 01efea022990..a5cb647378f0 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -2456,8 +2456,17 @@ static const struct flash_info spi_nor_ids[] = {
{ "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
{ "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
{ "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
+ { "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512,
+ SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
+ SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512,
+ SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
+ SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
+ { "mt25ql512a", INFO6(0x20ba20, 0x104400, 64 * 1024, 1024,
+ SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
+ SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
{ "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024,
SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
--
2.24.0
Hi Vignesh,
> -----Original Message-----
> From: Vignesh Raghavendra <[email protected]>
> Sent: Thursday, December 5, 2019 12:30 PM
> To: Tudor Ambarus <[email protected]>
> Cc: Miquel Raynal <[email protected]>; Richard Weinberger
> <[email protected]>; Vignesh Raghavendra <[email protected]>; Ashish Kumar
> <[email protected]>; [email protected]; linux-
> [email protected]; John Garry <[email protected]>
> Subject: [EXT] [PATCH 1/3] mtd: spi-nor: Split mt25qu512a (n25q512a) entry
> into two
>
> Caution: EXT Email
>
> mt25q family is different from n25q family of devices, even though manf ID
> and device IDs are same. mt25q flash has bit 6 set in 5th byte of READ ID
> response which can be used to distinguish it from n25q variant.
> mt25q flashes support stateless 4 Byte addressing opcodes where as n25q
> flashes don't. Therefore, have two separate entries for mt25qu512a and
> n25q512a.
>
> Fixes: 9607af6f857f ("mtd: spi-nor: Rename "n25q512a" to "mt25qu512a
> (n25q512a)"")
> Signed-off-by: Vignesh Raghavendra <[email protected]>
> ---
> drivers/mtd/spi-nor/spi-nor.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index f4afe123e9dc..01efea022990 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -2459,15 +2459,16 @@ static const struct flash_info spi_nor_ids[] = {
> { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K |
> SPI_NOR_QUAD_READ) },
> { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR |
> SPI_NOR_QUAD_READ) },
> + { "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024,
> + SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
> + SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
It seems you have moved back to my original patch [1], wrt mt25qu512a.
Regards
Ashish
> + { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K |
> + SPI_NOR_QUAD_READ) },
> { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR |
> SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR |
> SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> { "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096,
> SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
> NO_CHIP_ERASE) },
> - { "mt25qu512a (n25q512a)", INFO(0x20bb20, 0, 64 * 1024, 1024,
> - SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
> - SPI_NOR_QUAD_READ |
> - SPI_NOR_4B_OPCODES) },
> { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR |
> SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>
> /* Micron */
> --
> 2.24.0
[1]: http://patchwork.ozlabs.org/patch/1146197/
On 05/12/2019 06:59, Vignesh Raghavendra wrote:
> Add USE_FSR flag to all variants of n25q entries that support Flag Status
> Register.
>
> Signed-off-by: Vignesh Raghavendra <[email protected]>
Tested-by: John Garry <[email protected]> #for n25q128a13
> ---
> drivers/mtd/spi-nor/spi-nor.c | 15 ++++++++++-----
> 1 file changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index a5cb647378f0..1082b6bb1393 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -2454,16 +2454,21 @@ static const struct flash_info spi_nor_ids[] = {
> { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
> { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
> { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
> - { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
> - { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
> + { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K |
> + USE_FSR | SPI_NOR_QUAD_READ) },
> + { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K |
> + USE_FSR | SPI_NOR_QUAD_READ) },
> { "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512,
> SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
> SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> - { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> + { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K |
> + USE_FSR | SPI_NOR_DUAL_READ |
> + SPI_NOR_QUAD_READ) },
> { "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512,
> SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
> SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> - { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
> + { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K |
> + USE_FSR | SPI_NOR_QUAD_READ) },
> { "mt25ql512a", INFO6(0x20ba20, 0x104400, 64 * 1024, 1024,
> SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
> SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> @@ -2472,7 +2477,7 @@ static const struct flash_info spi_nor_ids[] = {
> SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
> SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K |
> - SPI_NOR_QUAD_READ) },
> + USE_FSR | SPI_NOR_QUAD_READ) },
> { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> { "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096,
>
On 12/5/2019 12:54 PM, Ashish Kumar wrote:
> Hi Vignesh,
[...]
>> drivers/mtd/spi-nor/spi-nor.c | 9 +++++----
>> 1 file changed, 5 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
>> index f4afe123e9dc..01efea022990 100644
>> --- a/drivers/mtd/spi-nor/spi-nor.c
>> +++ b/drivers/mtd/spi-nor/spi-nor.c
>> @@ -2459,15 +2459,16 @@ static const struct flash_info spi_nor_ids[] = {
>> { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K |
>> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>> { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K |
>> SPI_NOR_QUAD_READ) },
>> { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR |
>> SPI_NOR_QUAD_READ) },
>> + { "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024,
>> + SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
>> + SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> It seems you have moved back to my original patch [1], wrt mt25qu512a.
>
Yes, it seems like n25q and mt25q are not really same... mt25q supports
stateless 4 byte addressing opcodes where as n25q does not. Hence we
cannot add SPI_NOR_4B_OPCODES to n25q's idcodes.
This patch is outcome of from U-Boot discussion here (I believe you were
cc'd as well):
https://patchwork.ozlabs.org/patch/1160501/
Regards
Vignesh
> Regards
> Ashish
>> + { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K |
>> + SPI_NOR_QUAD_READ) },
>> { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR |
>> SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>> { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR |
>> SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>> { "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096,
>> SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
>> NO_CHIP_ERASE) },
>> - { "mt25qu512a (n25q512a)", INFO(0x20bb20, 0, 64 * 1024, 1024,
>> - SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
>> - SPI_NOR_QUAD_READ |
>> - SPI_NOR_4B_OPCODES) },
>> { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR |
>> SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>>
>> /* Micron */
>> --
>> 2.24.0
> [1]: http://patchwork.ozlabs.org/patch/1146197/
>
Hi, Vignesh,
On 12/5/19 8:59 AM, Vignesh Raghavendra wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Add USE_FSR flag to all variants of n25q entries that support Flag Status
> Register.
On a first look, all Micron flashes define the Flag Status Register. Do you know
if there are any Micron flash that don't support FSR? If not, would you be
interested in doing some documentation work to check this?
I think we can do this more generic, always set SNOR_F_USE_FSR for micron
flashes, like below. More, if FSR is specific just for Micron, we can get rid of
the USE_FSR flag too.
Thanks, Vignesh.
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index f4afe123e9dc..fe10beea60c3 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -4595,7 +4595,7 @@ static void sst_set_default_init(struct spi_nor *nor)
static void st_micron_set_default_init(struct spi_nor *nor)
{
- nor->flags |= SNOR_F_HAS_LOCK;
+ nor->flags |= SNOR_F_HAS_LOCK | SNOR_F_USE_FSR;
nor->params.quad_enable = NULL;
nor->params.set_4byte = st_micron_set_4byte;
}
Hi Tudor,
On 10/12/19 10:11 pm, [email protected] wrote:
> Hi, Vignesh,
>
> On 12/5/19 8:59 AM, Vignesh Raghavendra wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> Add USE_FSR flag to all variants of n25q entries that support Flag Status
>> Register.
>
> On a first look, all Micron flashes define the Flag Status Register. Do you know
> if there are any Micron flash that don't support FSR? If not, would you be
> interested in doing some documentation work to check this?
>
n25q and mt25 series support FSR but older m25p/m45p parts don't have
FSR. I don't know any easy way of finding out if flash part is m25p type.
> I think we can do this more generic, always set SNOR_F_USE_FSR for micron
> flashes, like below. More, if FSR is specific just for Micron, we can get rid of
> the USE_FSR flag too.
>
AFAIK, FSR is definitely Micron specific (other flash vendors have
different registers/bits providing similar information though).
> Thanks, Vignesh.
>
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index f4afe123e9dc..fe10beea60c3 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -4595,7 +4595,7 @@ static void sst_set_default_init(struct spi_nor *nor)
>
> static void st_micron_set_default_init(struct spi_nor *nor)
> {
> - nor->flags |= SNOR_F_HAS_LOCK;
> + nor->flags |= SNOR_F_HAS_LOCK | SNOR_F_USE_FSR;
> nor->params.quad_enable = NULL;
> nor->params.set_4byte = st_micron_set_4byte;
> }
>
--
Regards
Vignesh
On 12/5/19 8:59 AM, Vignesh Raghavendra wrote:
> First patch splits n25q512a and mt25qu512a into two as they are
> different devices. Second patch adds support for more mt25q devices and
> last patch adds USE_FSR flag for n25q entries where missing.
>
> Tested with mt25qu512a flash
>
> Vignesh Raghavendra (3):
> mtd: spi-nor: Split mt25qu512a (n25q512a) entry into two
> mtd: spi-nor: Add entries for mt25q variants
> mtd: spi-nor: Add USE_FSR flag for n25q* entries
>
> drivers/mtd/spi-nor/spi-nor.c | 31 +++++++++++++++++++++++--------
> 1 file changed, 23 insertions(+), 8 deletions(-)
All applied, thanks.
ta