From: Peng Fan <[email protected]>
i.MX93 Device Unique ID(UID) is in eFuse that could be read through
OCOTP Fuse Shadow Block. i.MX93 UID is 128 bits long, so introduce
soc_uid_high to indicate the higher 64bits.
The overall logic is similar as i.MX8M, so reuse soc-imx8m driver
for i.MX93.
Signed-off-by: Peng Fan <[email protected]>
---
V3:
Update commit log
Drop uneeded {}
V2:
The ocotp yaml has got R-b from DT maintainer
drivers/soc/imx/Makefile | 2 +-
drivers/soc/imx/soc-imx8m.c | 63 ++++++++++++++++++++++++++++++++++++-
2 files changed, 63 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile
index a28c44a1f16a..83aff181ae51 100644
--- a/drivers/soc/imx/Makefile
+++ b/drivers/soc/imx/Makefile
@@ -7,5 +7,5 @@ obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o
obj-$(CONFIG_IMX8M_BLK_CTRL) += imx8m-blk-ctrl.o
obj-$(CONFIG_IMX8M_BLK_CTRL) += imx8mp-blk-ctrl.o
-obj-$(CONFIG_SOC_IMX9) += imx93-src.o imx93-pd.o
+obj-$(CONFIG_SOC_IMX9) += soc-imx8m.o imx93-src.o imx93-pd.o
obj-$(CONFIG_IMX9_BLK_CTRL) += imx93-blk-ctrl.o
diff --git a/drivers/soc/imx/soc-imx8m.c b/drivers/soc/imx/soc-imx8m.c
index 1dcd243df567..6723ac6c0f04 100644
--- a/drivers/soc/imx/soc-imx8m.c
+++ b/drivers/soc/imx/soc-imx8m.c
@@ -25,8 +25,11 @@
#define IMX8MP_OCOTP_UID_OFFSET 0x10
+#define IMX93_OCOTP_UID_OFFSET 0x80c0
+
/* Same as ANADIG_DIGPROG_IMX7D */
#define ANADIG_DIGPROG_IMX8MM 0x800
+#define ANADIG_DIGPROG_IMX93 0x800
struct imx8_soc_data {
char *name;
@@ -34,6 +37,7 @@ struct imx8_soc_data {
};
static u64 soc_uid;
+static u64 soc_uid_h;
#ifdef CONFIG_HAVE_ARM_SMCCC
static u32 imx8mq_soc_revision_from_atf(void)
@@ -141,6 +145,53 @@ static u32 __init imx8mm_soc_revision(void)
return rev;
}
+static void __init imx93_soc_uid(void)
+{
+ void __iomem *ocotp_base;
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx93-ocotp");
+ if (!np)
+ return;
+
+ ocotp_base = of_iomap(np, 0);
+ WARN_ON(!ocotp_base);
+
+ soc_uid = readl_relaxed(ocotp_base + IMX93_OCOTP_UID_OFFSET + 0x8);
+ soc_uid <<= 32;
+ soc_uid |= readl_relaxed(ocotp_base + IMX93_OCOTP_UID_OFFSET + 0xC);
+
+ soc_uid_h = readl_relaxed(ocotp_base + IMX93_OCOTP_UID_OFFSET + 0x0);
+ soc_uid_h <<= 32;
+ soc_uid_h |= readl_relaxed(ocotp_base + IMX93_OCOTP_UID_OFFSET + 0x4);
+
+ iounmap(ocotp_base);
+ of_node_put(np);
+}
+
+static u32 __init imx93_soc_revision(void)
+{
+ struct device_node *np;
+ void __iomem *anatop_base;
+ u32 rev;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx93-anatop");
+ if (!np)
+ return 0;
+
+ anatop_base = of_iomap(np, 0);
+ WARN_ON(!anatop_base);
+
+ rev = readl_relaxed(anatop_base + ANADIG_DIGPROG_IMX93);
+
+ iounmap(anatop_base);
+ of_node_put(np);
+
+ imx93_soc_uid();
+
+ return rev;
+}
+
static const struct imx8_soc_data imx8mq_soc_data = {
.name = "i.MX8MQ",
.soc_revision = imx8mq_soc_revision,
@@ -161,11 +212,17 @@ static const struct imx8_soc_data imx8mp_soc_data = {
.soc_revision = imx8mm_soc_revision,
};
+static const struct imx8_soc_data imx93_soc_data = {
+ .name = "i.MX93",
+ .soc_revision = imx93_soc_revision,
+};
+
static __maybe_unused const struct of_device_id imx8_soc_match[] = {
{ .compatible = "fsl,imx8mq", .data = &imx8mq_soc_data, },
{ .compatible = "fsl,imx8mm", .data = &imx8mm_soc_data, },
{ .compatible = "fsl,imx8mn", .data = &imx8mn_soc_data, },
{ .compatible = "fsl,imx8mp", .data = &imx8mp_soc_data, },
+ { .compatible = "fsl,imx93", .data = &imx93_soc_data, },
{ }
};
@@ -212,7 +269,11 @@ static int __init imx8_soc_init(void)
goto free_soc;
}
- soc_dev_attr->serial_number = kasprintf(GFP_KERNEL, "%016llX", soc_uid);
+ if (soc_uid_h)
+ soc_dev_attr->serial_number = kasprintf(GFP_KERNEL, "%016llX%016llX",
+ soc_uid_h, soc_uid);
+ else
+ soc_dev_attr->serial_number = kasprintf(GFP_KERNEL, "%016llX", soc_uid);
if (!soc_dev_attr->serial_number) {
ret = -ENOMEM;
goto free_rev;
--
2.37.1
On 15/05/2023 08.37, Peng Fan (OSS) wrote:
> From: Peng Fan <[email protected]>
>
> i.MX93 Device Unique ID(UID) is in eFuse that could be read through
> OCOTP Fuse Shadow Block. i.MX93 UID is 128 bits long, so introduce
> soc_uid_high to indicate the higher 64bits.
So apparently, the imx8mp also has 128 bits, at least according to the
reference manual, which mentions a "UNIQUE_ID[127:64]" at offset 0xe00 -
0xe10 (i.e. bank 40, words 0 and 1).
However, no further mention of these upper bits can be found anywhere in
the RM, or in linux or u-boot, mainline or downstream NXP. Furthermore,
quick experiments on both an imx8mp-evk and a custom imx8mp board
reveals that those words are not locked down (they do seem to have some
contents from the factory, but I can still set more bits in them).
Could someone from NXP please explain what exactly bank 40, words 0 and
1, on imx8mp are for? What do their initial value mean, why are they not
locked down, and why does the RM indicate that they should be part of a
unique_id?
Also, assuming that the RM is just wrong (wouldn't be the first time;
the description of the lower 64 bits is also wonky in its own special
way), an obvious follow-up question is: Are the currently exposed
(lower) 64 bits unique among all imx8mp SOCs, i.e. does those 64 bits by
themselves actually work as a uid?
Rasmus
> Subject: Re: [PATCH V3] soc: imx: support i.MX93 soc device
>
> On 15/05/2023 08.37, Peng Fan (OSS) wrote:
> > From: Peng Fan <[email protected]>
> >
> > i.MX93 Device Unique ID(UID) is in eFuse that could be read through
> > OCOTP Fuse Shadow Block. i.MX93 UID is 128 bits long, so introduce
> > soc_uid_high to indicate the higher 64bits.
>
> So apparently, the imx8mp also has 128 bits, at least according to the
It is 64bits. The RM maybe wrong.
> reference manual, which mentions a "UNIQUE_ID[127:64]" at offset 0xe00 -
> 0xe10 (i.e. bank 40, words 0 and 1).
Which chatper?
>
> However, no further mention of these upper bits can be found anywhere in
> the RM, or in linux or u-boot, mainline or downstream NXP. Furthermore,
> quick experiments on both an imx8mp-evk and a custom imx8mp board
> reveals that those words are not locked down (they do seem to have some
> contents from the factory, but I can still set more bits in them).
>
> Could someone from NXP please explain what exactly bank 40, words 0 and
> 1, on imx8mp are for? What do their initial value mean, why are they not
> locked down, and why does the RM indicate that they should be part of a
> unique_id?
RM should be wrong. UID is in Bank 0.
>
> Also, assuming that the RM is just wrong (wouldn't be the first time; the
> description of the lower 64 bits is also wonky in its own special way), an
> obvious follow-up question is: Are the currently exposed
> (lower) 64 bits unique among all imx8mp SOCs, i.e. does those 64 bits by
> themselves actually work as a uid?
Just as what the driver indicates, UID is at register address 0x420 and 0x430.
For bank 0x40, I could not reveal information if RM or Secure RM not say
something.
You could raise tickets in community.nxp.com to ask people follow up
on RM issue or else.
Thanks,
Peng.
>
> Rasmus
On 25/05/2023 02.01, Peng Fan wrote:
>> Subject: Re: [PATCH V3] soc: imx: support i.MX93 soc device
>>
>> On 15/05/2023 08.37, Peng Fan (OSS) wrote:
>>> From: Peng Fan <[email protected]>
>>>
>>> i.MX93 Device Unique ID(UID) is in eFuse that could be read through
>>> OCOTP Fuse Shadow Block. i.MX93 UID is 128 bits long, so introduce
>>> soc_uid_high to indicate the higher 64bits.
>>
>> So apparently, the imx8mp also has 128 bits, at least according to the
>
> It is 64bits. The RM maybe wrong.
OK. I assume you've raised a ticket internally with the documentation
team to get that fixed?
And while you're at it, could you draw their attention to the lower bits
as well:
0x420[10:0] UNIQUE_ID[42:0] 43
0x430[15:11] UNIQUE_ID[47:43] 5
0x430[23:16] UNIQUE_ID[55:48] 8
0x430[31:24] UNIQUE_ID[63:56] 8
I mean, it's a really amazing piece of hardware that manages to cram 43
bits of information into a 32 bit word.
>> reference manual, which mentions a "UNIQUE_ID[127:64]" at offset 0xe00 -
>> 0xe10 (i.e. bank 40, words 0 and 1).
>
> Which chatper?
>>
In my copy, which identifies as "i.MX 8M Plus Applications Processor
Reference Manual, Rev. 1, 06/2021", it's in Table 6-35, page 823.
>> obvious follow-up question is: Are the currently exposed
>> (lower) 64 bits unique among all imx8mp SOCs, i.e. does those 64 bits by
>> themselves actually work as a uid?
>
> Just as what the driver indicates, UID is at register address 0x420
and 0x430.
So, for the record, for the iMX8MP, the SOC UID consists of precisely
those 64 bits found in those two words. And no two iMX8MPs ever produced
will have the same value. OK. Except:
> For bank 0x40, I could not reveal information if RM or Secure RM not say
> something.
>
> You could raise tickets in community.nxp.com to ask people follow up
> on RM issue or else.
Very interesting, though, that somebody else tried to do just that
(https://community.nxp.com/t5/i-MX-Processors/Question-about-UID-UNIQUE-ID-of-i-MX8MP/m-p/1582383#M200077)
and have unambiguously been told by "joanxie" from NXP TechSupport
refer to the reference manual, lower 64bits from
0x420[10:0]-0x430[11:31]and higher 64bits from 0xE00-0xE10
and later
the higher 64 bits thus bank 40 word 0 and bank40 word1.
and again
since this soc uses 128bits as UID, try to use 128bits
But you are clearly stating the opposite, that bank 40, words 0 and 1,
do not form part of the UID, a statement supported by the experimental
fact that those words are not locked down from the factory.
Apart from the still unanswered question about what those two words then
actually contain, represent and/or are used for, this leaves me with yet
another question:
- What's the value of asking questions at community.nxp.com if the
answers one can expect to get are not rooted in reality?
Rasmus
> Subject: Re: [PATCH V3] soc: imx: support i.MX93 soc device
>
> On 25/05/2023 02.01, Peng Fan wrote:
> >> Subject: Re: [PATCH V3] soc: imx: support i.MX93 soc device
> >>
> >> On 15/05/2023 08.37, Peng Fan (OSS) wrote:
> >>> From: Peng Fan <[email protected]>
> >>>
> >>> i.MX93 Device Unique ID(UID) is in eFuse that could be read through
> >>> OCOTP Fuse Shadow Block. i.MX93 UID is 128 bits long, so introduce
> >>> soc_uid_high to indicate the higher 64bits.
> >>
> >> So apparently, the imx8mp also has 128 bits, at least according to
> >> the
> >
> > It is 64bits. The RM maybe wrong.
>
> OK. I assume you've raised a ticket internally with the documentation team
> to get that fixed?
>
> And while you're at it, could you draw their attention to the lower bits as
> well:
>
> 0x420[10:0] UNIQUE_ID[42:0] 43
> 0x430[15:11] UNIQUE_ID[47:43] 5
> 0x430[23:16] UNIQUE_ID[55:48] 8
> 0x430[31:24] UNIQUE_ID[63:56] 8
>
> I mean, it's a really amazing piece of hardware that manages to cram 43 bits
> of information into a 32 bit word.
>
> >> reference manual, which mentions a "UNIQUE_ID[127:64]" at offset
> >> 0xe00 -
> >> 0xe10 (i.e. bank 40, words 0 and 1).
> >
> > Which chatper?
> >>
>
> In my copy, which identifies as "i.MX 8M Plus Applications Processor
> Reference Manual, Rev. 1, 06/2021", it's in Table 6-35, page 823.
>
>
> >> obvious follow-up question is: Are the currently exposed
> >> (lower) 64 bits unique among all imx8mp SOCs, i.e. does those 64 bits
> >> by themselves actually work as a uid?
> >
> > Just as what the driver indicates, UID is at register address 0x420
> and 0x430.
>
> So, for the record, for the iMX8MP, the SOC UID consists of precisely those
> 64 bits found in those two words. And no two iMX8MPs ever produced will
> have the same value. OK. Except:
>
> > For bank 0x40, I could not reveal information if RM or Secure RM not
> > say something.
> >
> > You could raise tickets in community.nxp.com to ask people follow up
> > on RM issue or else.
>
> Very interesting, though, that somebody else tried to do just that
> (https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fcom
> munity.nxp.com%2Ft5%2Fi-MX-Processors%2FQuestion-about-UID-
> UNIQUE-ID-of-i-MX8MP%2Fm-
> p%2F1582383%23M200077&data=05%7C01%7Cpeng.fan%40nxp.com%7Ce
> e14840685854a192dc008db5cee5230%7C686ea1d3bc2b4c6fa92cd99c5c301
> 635%7C0%7C0%7C638205950874432380%7CUnknown%7CTWFpbGZsb3d8e
> yJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D
> %7C3000%7C%7C%7C&sdata=fEXtlp0UTJjo8GGpdqqRurJd3yfamxZmiHkI4Zs
> MKMo%3D&reserved=0)
> and have unambiguously been told by "joanxie" from NXP TechSupport
>
> refer to the reference manual, lower 64bits from 0x420[10:0]-
> 0x430[11:31]and higher 64bits from 0xE00-0xE10
>
> and later
>
> the higher 64 bits thus bank 40 word 0 and bank40 word1.
>
> and again
>
> since this soc uses 128bits as UID, try to use 128bits
>
> But you are clearly stating the opposite, that bank 40, words 0 and 1, do not
> form part of the UID, a statement supported by the experimental fact that
> those words are not locked down from the factory.
>
> Apart from the still unanswered question about what those two words then
> actually contain, represent and/or are used for, this leaves me with yet
> another question:
>
> - What's the value of asking questions at community.nxp.com if the answers
> one can expect to get are not rooted in reality?
[Peng Fan]
Sorry, I am wrong, RM is correct, I overlooked the fuse at address 0xe00.
Regards,
Peng.
>
> Rasmus
On Wed, May 24, 2023 at 03:30:01PM +0200, Rasmus Villemoes wrote:
> On 15/05/2023 08.37, Peng Fan (OSS) wrote:
> > From: Peng Fan <[email protected]>
> >
> > i.MX93 Device Unique ID(UID) is in eFuse that could be read through
> > OCOTP Fuse Shadow Block. i.MX93 UID is 128 bits long, so introduce
> > soc_uid_high to indicate the higher 64bits.
>
> So apparently, the imx8mp also has 128 bits, at least according to the
> reference manual, which mentions a "UNIQUE_ID[127:64]" at offset 0xe00 -
> 0xe10 (i.e. bank 40, words 0 and 1).
>
> However, no further mention of these upper bits can be found anywhere in
> the RM, or in linux or u-boot, mainline or downstream NXP. Furthermore,
> quick experiments on both an imx8mp-evk and a custom imx8mp board
> reveals that those words are not locked down (they do seem to have some
> contents from the factory, but I can still set more bits in them).
>
> Could someone from NXP please explain what exactly bank 40, words 0 and
> 1, on imx8mp are for? What do their initial value mean, why are they not
> locked down, and why does the RM indicate that they should be part of a
> unique_id?
>
> Also, assuming that the RM is just wrong (wouldn't be the first time;
> the description of the lower 64 bits is also wonky in its own special
> way), an obvious follow-up question is: Are the currently exposed
> (lower) 64 bits unique among all imx8mp SOCs, i.e. does those 64 bits by
> themselves actually work as a uid?
Rasmus,
Are you fine with the patch itself? Or do you expect more clarification
in the commit log?
Shawn
Hi Shawn,
> Subject: Re: [PATCH V3] soc: imx: support i.MX93 soc device
>
> On Wed, May 24, 2023 at 03:30:01PM +0200, Rasmus Villemoes wrote:
> > On 15/05/2023 08.37, Peng Fan (OSS) wrote:
> > > From: Peng Fan <[email protected]>
> > >
> > > i.MX93 Device Unique ID(UID) is in eFuse that could be read through
> > > OCOTP Fuse Shadow Block. i.MX93 UID is 128 bits long, so introduce
> > > soc_uid_high to indicate the higher 64bits.
> >
> > So apparently, the imx8mp also has 128 bits, at least according to the
> > reference manual, which mentions a "UNIQUE_ID[127:64]" at offset 0xe00
> > -
> > 0xe10 (i.e. bank 40, words 0 and 1).
> >
> > However, no further mention of these upper bits can be found anywhere
> > in the RM, or in linux or u-boot, mainline or downstream NXP.
> > Furthermore, quick experiments on both an imx8mp-evk and a custom
> > imx8mp board reveals that those words are not locked down (they do
> > seem to have some contents from the factory, but I can still set more bits
> in them).
> >
> > Could someone from NXP please explain what exactly bank 40, words 0
> > and 1, on imx8mp are for? What do their initial value mean, why are
> > they not locked down, and why does the RM indicate that they should be
> > part of a unique_id?
> >
> > Also, assuming that the RM is just wrong (wouldn't be the first time;
> > the description of the lower 64 bits is also wonky in its own special
> > way), an obvious follow-up question is: Are the currently exposed
> > (lower) 64 bits unique among all imx8mp SOCs, i.e. does those 64 bits
> > by themselves actually work as a uid?
>
> Rasmus,
>
> Are you fine with the patch itself? Or do you expect more clarification in the
> commit log?
Rasmus's comments is for i.MX8MP, this patch is for i.MX93.
But anyway I just sent out V4 patch to address i.MX8MP support and
then add i.MX93 support.
Thanks,
Peng.
>
> Shawn