These series add sdmmc, sdio, and other device nodes support for
rk322x SoCs, and also introduce rk3229 basic dtsi file specifically.
Changes from v1:
- Extracted cpu enable-method from rk3229.dtsi to rk322x.dtsi
- Updated the 'Reviewed-by' tag from Heiko Stuebner <[email protected]> for [PATCH v2 3/7].
David Wu (1):
ARM: dts: rockchip: Add io-domain node for rk3228
Finley Xiao (1):
ARM: dts: rockchip: add efuse device node for rk3228
Frank Wang (2):
ARM: dts: rockchip: add cpu enable method for rk3228 SoC
ARM: dts: rockchip: add basic dtsi file for RK3229 SoC
Shawn Lin (3):
Documentation: rockchip-dw-mshc: add description for rk3228
ARM: dts: rockchip: fix compatible string for eMMC node of rk3228 SoC
ARM: dts: rockchip: add sdmmc and sdio nodes for rk3228 SoC
.../devicetree/bindings/mmc/rockchip-dw-mshc.txt | 1 +
arch/arm/boot/dts/rk3229-evb.dts | 2 +-
arch/arm/boot/dts/rk3229.dtsi | 89 +++++++++++++++++++++
arch/arm/boot/dts/rk322x.dtsi | 93 +++++++++++++++++++++-
4 files changed, 183 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/boot/dts/rk3229.dtsi
--
2.0.0
From: Shawn Lin <[email protected]>
Add "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc" for
dwmmc on rk322x platform.
Signed-off-by: Shawn Lin <[email protected]>
Reviewed-by: Heiko Stuebner <[email protected]>
---
Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
index 18e33cb..a600833 100644
--- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
@@ -15,6 +15,7 @@ Required Properties:
- "rockchip,rk3288-dw-mshc": for Rockchip RK3288
- "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RV1108
- "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3036
+ - "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK322X
- "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3328
- "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368
- "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3399
--
2.0.0
Due to some tiny differences between RK3228 and RK3229, this patch adds
a basic dtsi file which first includes a new CPU opp table for RK3229.
Signed-off-by: Frank Wang <[email protected]>
---
arch/arm/boot/dts/rk3229-evb.dts | 2 +-
arch/arm/boot/dts/rk3229.dtsi | 89 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 90 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/rk3229.dtsi
diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts
index 1b55192..82e8a53 100644
--- a/arch/arm/boot/dts/rk3229-evb.dts
+++ b/arch/arm/boot/dts/rk3229-evb.dts
@@ -40,7 +40,7 @@
/dts-v1/;
-#include "rk322x.dtsi"
+#include "rk3229.dtsi"
/ {
model = "Rockchip RK3229 Evaluation board";
diff --git a/arch/arm/boot/dts/rk3229.dtsi b/arch/arm/boot/dts/rk3229.dtsi
new file mode 100644
index 0000000..6fe6c15
--- /dev/null
+++ b/arch/arm/boot/dts/rk3229.dtsi
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "rk322x.dtsi"
+
+/ {
+ compatible = "rockchip,rk3229";
+
+ /delete-node/ opp-table0;
+
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <950000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <975000>;
+ };
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <1175000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1275000>;
+ };
+ opp-1296000000 {
+ opp-hz = /bits/ 64 <1296000000>;
+ opp-microvolt = <1325000>;
+ };
+ opp-1392000000 {
+ opp-hz = /bits/ 64 <1392000000>;
+ opp-microvolt = <1375000>;
+ };
+ opp-1464000000 {
+ opp-hz = /bits/ 64 <1464000000>;
+ opp-microvolt = <1400000>;
+ };
+ };
+};
--
2.0.0
This patch sets PSCI as the default cpu enable-method for RK3228 SoC.
Signed-off-by: Frank Wang <[email protected]>
---
arch/arm/boot/dts/rk322x.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 31e04e9..34d175e 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -70,6 +70,7 @@
#cooling-cells = <2>; /* min followed by max */
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
+ enable-method = "psci";
};
cpu1: cpu@f01 {
@@ -78,6 +79,7 @@
reg = <0xf01>;
resets = <&cru SRST_CORE1>;
operating-points-v2 = <&cpu0_opp_table>;
+ enable-method = "psci";
};
cpu2: cpu@f02 {
@@ -86,6 +88,7 @@
reg = <0xf02>;
resets = <&cru SRST_CORE2>;
operating-points-v2 = <&cpu0_opp_table>;
+ enable-method = "psci";
};
cpu3: cpu@f03 {
@@ -94,6 +97,7 @@
reg = <0xf03>;
resets = <&cru SRST_CORE3>;
operating-points-v2 = <&cpu0_opp_table>;
+ enable-method = "psci";
};
};
@@ -151,6 +155,11 @@
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
timer {
compatible = "arm,armv7-timer";
arm,cpu-registers-not-fw-configured;
--
2.0.0
From: Shawn Lin <[email protected]>
This adds amend compatible content for eMMC of RK3228 SoC.
Signed-off-by: Shawn Lin <[email protected]>
---
arch/arm/boot/dts/rk322x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 34d175e..c4d43ce 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -523,7 +523,7 @@
};
emmc: dwmmc@30020000 {
- compatible = "rockchip,rk3288-dw-mshc";
+ compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30020000 0x4000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <37500000>;
--
2.0.0
From: Shawn Lin <[email protected]>
This patch adds sdmmc/sdio controller nodes for rk3228 SoC.
Signed-off-by: Shawn Lin <[email protected]>
---
arch/arm/boot/dts/rk322x.dtsi | 60 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index c4d43ce..66578fa 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -522,6 +522,32 @@
status = "disabled";
};
+ sdmmc: dwmmc@30000000 {
+ compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x30000000 0x4000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ fifo-depth = <0x100>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
+ status = "disabled";
+ };
+
+ sdio: dwmmc@30010000 {
+ compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x30010000 0x4000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
+ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ fifo-depth = <0x100>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
+ status = "disabled";
+ };
+
emmc: dwmmc@30020000 {
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30020000 0x4000>;
@@ -732,6 +758,40 @@
drive-strength = <12>;
};
+ sdmmc {
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
+ };
+
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
+ };
+
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+ <1 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+ <1 20 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+ <1 21 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
+ };
+ };
+
+ sdio {
+ sdio_clk: sdio-clk {
+ rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
+ };
+
+ sdio_cmd: sdio-cmd {
+ rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
+ };
+
+ sdio_bus4: sdio-bus4 {
+ rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+ <3 3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+ <3 4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+ <3 5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
+ };
+ };
+
emmc {
emmc_clk: emmc-clk {
rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
--
2.0.0
From: David Wu <[email protected]>
This patch adds io-domain support for rk3228 SoC.
Signed-off-by: David Wu <[email protected]>
Signed-off-by: Frank Wang <[email protected]>
---
arch/arm/boot/dts/rk322x.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 66578fa..bd7ef53 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -237,6 +237,11 @@
#address-cells = <1>;
#size-cells = <1>;
+ io_domains: io-domains {
+ compatible = "rockchip,rk3228-io-voltage-domain";
+ status = "disabled";
+ };
+
u2phy0: usb2-phy@760 {
compatible = "rockchip,rk3228-usb2phy";
reg = <0x0760 0x0c>;
--
2.0.0
From: Finley Xiao <[email protected]>
Add a efuse node in the device tree for the rk3228 SoC.
Signed-off-by: Finley Xiao <[email protected]>
---
arch/arm/boot/dts/rk322x.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index bd7ef53..a8697fe 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -336,6 +336,23 @@
status = "disabled";
};
+ efuse: efuse@11040000 {
+ compatible = "rockchip,rk322x-efuse";
+ reg = <0x11040000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cru PCLK_EFUSE_256>;
+ clock-names = "pclk_efuse";
+
+ /* Data cells */
+ efuse_id: id@7 {
+ reg = <0x7 0x10>;
+ };
+ cpu_leakage: cpu_leakage@17 {
+ reg = <0x17 0x1>;
+ };
+ };
+
i2c0: i2c@11050000 {
compatible = "rockchip,rk3228-i2c";
reg = <0x11050000 0x1000>;
--
2.0.0
Hi Frank,
Am Donnerstag, 22. Juni 2017, 15:24:38 CEST schrieb Frank Wang:
> From: Finley Xiao <[email protected]>
>
> Add a efuse node in the device tree for the rk3228 SoC.
>
> Signed-off-by: Finley Xiao <[email protected]>
> ---
> arch/arm/boot/dts/rk322x.dtsi | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
> index bd7ef53..a8697fe 100644
> --- a/arch/arm/boot/dts/rk322x.dtsi
> +++ b/arch/arm/boot/dts/rk322x.dtsi
> @@ -336,6 +336,23 @@
> status = "disabled";
> };
>
> + efuse: efuse@11040000 {
> + compatible = "rockchip,rk322x-efuse";
you wanted to update the compatible in the efuse driver + binding txt
and then here as well (aka rk3228-efuse).
Heiko
> + reg = <0x11040000 0x20>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + clocks = <&cru PCLK_EFUSE_256>;
> + clock-names = "pclk_efuse";
> +
> + /* Data cells */
> + efuse_id: id@7 {
> + reg = <0x7 0x10>;
> + };
> + cpu_leakage: cpu_leakage@17 {
> + reg = <0x17 0x1>;
> + };
> + };
> +
> i2c0: i2c@11050000 {
> compatible = "rockchip,rk3228-i2c";
> reg = <0x11050000 0x1000>;
>
Hi Heiko,
On 2017/6/22 15:27, Heiko Stuebner wrote:
> Hi Frank,
>
> Am Donnerstag, 22. Juni 2017, 15:24:38 CEST schrieb Frank Wang:
>> From: Finley Xiao <[email protected]>
>>
>> Add a efuse node in the device tree for the rk3228 SoC.
>>
>> Signed-off-by: Finley Xiao <[email protected]>
>> ---
>> arch/arm/boot/dts/rk322x.dtsi | 17 +++++++++++++++++
>> 1 file changed, 17 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
>> index bd7ef53..a8697fe 100644
>> --- a/arch/arm/boot/dts/rk322x.dtsi
>> +++ b/arch/arm/boot/dts/rk322x.dtsi
>> @@ -336,6 +336,23 @@
>> status = "disabled";
>> };
>>
>> + efuse: efuse@11040000 {
>> + compatible = "rockchip,rk322x-efuse";
> you wanted to update the compatible in the efuse driver + binding txt
> and then here as well (aka rk3228-efuse).
Sorry, I will fix it and resend these series soon.
BR.
Frank
>
> Heiko
>
>> + reg = <0x11040000 0x20>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + clocks = <&cru PCLK_EFUSE_256>;
>> + clock-names = "pclk_efuse";
>> +
>> + /* Data cells */
>> + efuse_id: id@7 {
>> + reg = <0x7 0x10>;
>> + };
>> + cpu_leakage: cpu_leakage@17 {
>> + reg = <0x17 0x1>;
>> + };
>> + };
>> +
>> i2c0: i2c@11050000 {
>> compatible = "rockchip,rk3228-i2c";
>> reg = <0x11050000 0x1000>;
>>
>
>
>
>