This series adds the base device tree files and DTS support for the
Qualcomm QDU1000 and QRU1000 IDP SoCs, including the clocks, tlmm, smmu,
regulators, mmc, interconnects, cpufreq, and qup.
This patchset is based off of [1] which adds support for the PMIC arb used
on these SoCs.
The Qualcomm Technologies, Inc. Distributed Unit 1000 and Radio Unit
1000 are new SoCs meant for enabling Open RAN solutions. See more at
https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/qualcomm_5g_ran_platforms_product_brief.pdf
[1] https://lore.kernel.org/all/[email protected]/
Melody Olvera (19):
arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs
arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs
arm64: dts: qcom: qdru1000: Add tlmm nodes
arm64: dts: qcom: qdu1000: Add reserved memory nodes
arm64: dts: qcom: qru1000: Add reserved memory nodes
arm64: dts: qcom: qdru1000: Add smmu nodes
arm64: dts: qcom: qdu1000-idp: Add RPMH regulators nodes
arm64: dts: qcom: qru1000-idp: Add RPMH regulators nodes
arm64: dts: qcom: qdru1000: Add interconnect nodes
arm64: dts: qcom: qdru1000: Add rpmhpd node
arm64: dts: qcom: qdru1000: Add spmi node
arm64: dts: qcom: qdu1000-idp: Include pmic file
arm64: dts: qcom: qru1000-idp: Include pmic file
arm64: dts: qcom: qdru1000: Add cpufreq support
arm64: dts: qcom: qdru1000: Add additional QUP nodes
arm64: dts: qcom: qdru1000: Add gpi_dma nodes
arm64: dts: qcom: qdru1000: Add I2C nodes for QUP
arm64: dts: qcom: qdru1000: Add SPI devices to QUP nodes
arm64: dts: qcom: qdru1000: Add additional UART instances
arch/arm64/boot/dts/qcom/Makefile | 2 +
arch/arm64/boot/dts/qcom/qdru1000.dtsi | 1499 ++++++++++++++++++++++
arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 231 ++++
arch/arm64/boot/dts/qcom/qdu1000.dtsi | 160 +++
arch/arm64/boot/dts/qcom/qru1000-idp.dts | 231 ++++
arch/arm64/boot/dts/qcom/qru1000.dtsi | 155 +++
6 files changed, 2278 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/qdru1000.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/qdu1000-idp.dts
create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/qru1000-idp.dts
create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi
base-commit: 987a926c1d8a40e4256953b04771fbdb63bc7938
prerequisite-patch-id: 79eb132c9ff1a0feb653bef87e3e93f6841f81ee
prerequisite-patch-id: e25ad91d89a9d4a24f1081e5c03cb20678c6e94b
prerequisite-patch-id: e882ee6dbd8d55069a313e9c2b10a1ea7f6b80fb
prerequisite-patch-id: 85c1f1845b2e69ef50e7e8391426e6cab6c66381
prerequisite-patch-id: 5fd7e4f92a95a7dedc49fd39fdffd5e02c838190
prerequisite-patch-id: c8d9475d6bb2d24102e5bfee65f74d2c0365db68
prerequisite-patch-id: a03c3288ed927cbab6a42d3ad49df4347cfc9722
prerequisite-patch-id: aa7ddf85d2a1c02e4d649632425910e44f73a567
prerequisite-patch-id: 5e7a02607aecd3f5346a2f450982601cf6935e54
--
2.37.3
Add smmu nodes for the QDU1000 and QRU1000 SoCs.
Signed-off-by: Melody Olvera <[email protected]>
---
arch/arm64/boot/dts/qcom/qdru1000.dtsi | 57 ++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
index 39b9a00d3ad8..8c2af08b8329 100644
--- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
@@ -396,5 +396,62 @@ arch_timer: timer {
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <19200000>;
};
+
+ apps_smmu: apps-smmu@15000000 {
+ compatible = "qcom,qdu1000-smmu-500", "qcom,qru1000-smmu-500",
+ "arm,mmu-500";
+ reg = <0x0 0x15000000 0x0 0x100000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
};
--
2.37.3
Add tlmm node for the QDU1000 and QRU1000 SoCs and the uart pin
configuration.
Signed-off-by: Melody Olvera <[email protected]>
---
arch/arm64/boot/dts/qcom/qdru1000.dtsi | 30 ++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
index 3610f94bef35..39b9a00d3ad8 100644
--- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
@@ -235,6 +235,8 @@ uart7: serial@99c000 {
reg = <0x0 0x99c000 0x0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart7_default>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -248,6 +250,34 @@ tcsr_mutex: hwlock@1f40000 {
#hwlock-cells = <1>;
};
+ tlmm: pinctrl@f000000 {
+ compatible = "qcom,qdu1000-tlmm", "qcom,qru1000-tlmm";
+ reg = <0x0 0xf000000 0x0 0x1000000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 151>;
+ wakeup-parent = <&pdc>;
+
+ qup_uart7_default: qup-uart7-default {
+ tx {
+ pins = "gpio134";
+ function = "qup0_se7_l2";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ rx {
+ pins = "gpio135";
+ function = "qup0_se7_l3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,pdc";
reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
--
2.37.3
Add cpufreq-epss node for the QDU1000 and QRU1000 SoCs
and add references to it from the cpu nodes.
Signed-off-by: Melody Olvera <[email protected]>
---
arch/arm64/boot/dts/qcom/qdru1000.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
index 62a6a6e8ca59..2fd449df3706 100644
--- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
@@ -45,6 +45,7 @@ CPU0: cpu@0 {
enable-method = "psci";
power-domain-names = "psci";
power-domains = <&CPU_PD0>;
+ qcom,freq-domains = <&cpufreq_hw 0>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
@@ -62,6 +63,7 @@ CPU1: cpu@100 {
enable-method = "psci";
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
+ qcom,freq-domains = <&cpufreq_hw 0>;
next-level-cache = <&L2_100>;
L2_100: l2-cache {
compatible = "cache";
@@ -77,6 +79,7 @@ CPU2: cpu@200 {
enable-method = "psci";
power-domains = <&CPU_PD2>;
power-domain-names = "psci";
+ qcom,freq-domains = <&cpufreq_hw 0>;
next-level-cache = <&L2_200>;
L2_200: l2-cache {
compatible = "cache";
@@ -91,6 +94,7 @@ CPU3: cpu@300 {
enable-method = "psci";
power-domains = <&CPU_PD3>;
power-domain-names = "psci";
+ qcom,freq-domains = <&cpufreq_hw 0>;
next-level-cache = <&L2_300>;
L2_300: l2-cache {
compatible = "cache";
@@ -246,6 +250,18 @@ uart7: serial@99c000 {
};
};
+ cpufreq_hw: cpufreq@17d91000 {
+ compatible = "qcom, qdu1000-cpufreq-epss", "qcom, qru1000-cpufreq-epss",
+ "qcom,cpufreq-epss";
+ reg = <0x0 0x17d91000 0x0 0x1000>;
+ reg-names = "freq-domain0";
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dcvsh0_int";
+ #freq-domain-cells = <1>;
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x1f40000 0x0 0x20000>;
--
2.37.3
On Sat, 1 Oct 2022 at 06:09, Melody Olvera <[email protected]> wrote:
>
> Add smmu nodes for the QDU1000 and QRU1000 SoCs.
>
> Signed-off-by: Melody Olvera <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/qdru1000.dtsi | 57 ++++++++++++++++++++++++++
> 1 file changed, 57 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> index 39b9a00d3ad8..8c2af08b8329 100644
> --- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> @@ -396,5 +396,62 @@ arch_timer: timer {
> <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> clock-frequency = <19200000>;
> };
> +
> + apps_smmu: apps-smmu@15000000 {
Please insert the node according to its address.
> + compatible = "qcom,qdu1000-smmu-500", "qcom,qru1000-smmu-500",
> + "arm,mmu-500";
--
With best wishes
Dmitry
On Sat, 1 Oct 2022 at 06:09, Melody Olvera <[email protected]> wrote:
>
> This series adds the base device tree files and DTS support for the
> Qualcomm QDU1000 and QRU1000 IDP SoCs, including the clocks, tlmm, smmu,
> regulators, mmc, interconnects, cpufreq, and qup.
>
> This patchset is based off of [1] which adds support for the PMIC arb used
> on these SoCs.
>
> The Qualcomm Technologies, Inc. Distributed Unit 1000 and Radio Unit
> 1000 are new SoCs meant for enabling Open RAN solutions. See more at
> https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/qualcomm_5g_ran_platforms_product_brief.pdf
>
> [1] https://lore.kernel.org/all/[email protected]/
>
> Melody Olvera (19):
> arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs
> arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs
No need to split IDT commits too much. Splitting the main DT is fine
for me, it eases review. For IDT, I'd just squash them together.
> arm64: dts: qcom: qdru1000: Add tlmm nodes
> arm64: dts: qcom: qdu1000: Add reserved memory nodes
> arm64: dts: qcom: qru1000: Add reserved memory nodes
> arm64: dts: qcom: qdru1000: Add smmu nodes
> arm64: dts: qcom: qdu1000-idp: Add RPMH regulators nodes
> arm64: dts: qcom: qru1000-idp: Add RPMH regulators nodes
> arm64: dts: qcom: qdru1000: Add interconnect nodes
> arm64: dts: qcom: qdru1000: Add rpmhpd node
> arm64: dts: qcom: qdru1000: Add spmi node
> arm64: dts: qcom: qdu1000-idp: Include pmic file
> arm64: dts: qcom: qru1000-idp: Include pmic file
> arm64: dts: qcom: qdru1000: Add cpufreq support
> arm64: dts: qcom: qdru1000: Add additional QUP nodes
> arm64: dts: qcom: qdru1000: Add gpi_dma nodes
> arm64: dts: qcom: qdru1000: Add I2C nodes for QUP
> arm64: dts: qcom: qdru1000: Add SPI devices to QUP nodes
> arm64: dts: qcom: qdru1000: Add additional UART instances
>
> arch/arm64/boot/dts/qcom/Makefile | 2 +
> arch/arm64/boot/dts/qcom/qdru1000.dtsi | 1499 ++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 231 ++++
> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 160 +++
> arch/arm64/boot/dts/qcom/qru1000-idp.dts | 231 ++++
> arch/arm64/boot/dts/qcom/qru1000.dtsi | 155 +++
> 6 files changed, 2278 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/qdru1000.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000-idp.dts
> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/qru1000-idp.dts
> create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi
>
>
> base-commit: 987a926c1d8a40e4256953b04771fbdb63bc7938
> prerequisite-patch-id: 79eb132c9ff1a0feb653bef87e3e93f6841f81ee
> prerequisite-patch-id: e25ad91d89a9d4a24f1081e5c03cb20678c6e94b
> prerequisite-patch-id: e882ee6dbd8d55069a313e9c2b10a1ea7f6b80fb
> prerequisite-patch-id: 85c1f1845b2e69ef50e7e8391426e6cab6c66381
> prerequisite-patch-id: 5fd7e4f92a95a7dedc49fd39fdffd5e02c838190
> prerequisite-patch-id: c8d9475d6bb2d24102e5bfee65f74d2c0365db68
> prerequisite-patch-id: a03c3288ed927cbab6a42d3ad49df4347cfc9722
> prerequisite-patch-id: aa7ddf85d2a1c02e4d649632425910e44f73a567
> prerequisite-patch-id: 5e7a02607aecd3f5346a2f450982601cf6935e54
> --
> 2.37.3
>
--
With best wishes
Dmitry
On Sat, 1 Oct 2022 at 06:09, Melody Olvera <[email protected]> wrote:
>
> Add tlmm node for the QDU1000 and QRU1000 SoCs and the uart pin
> configuration.
>
> Signed-off-by: Melody Olvera <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/qdru1000.dtsi | 30 ++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> index 3610f94bef35..39b9a00d3ad8 100644
> --- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> @@ -235,6 +235,8 @@ uart7: serial@99c000 {
> reg = <0x0 0x99c000 0x0 0x4000>;
> clock-names = "se";
> clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_uart7_default>;
> interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -248,6 +250,34 @@ tcsr_mutex: hwlock@1f40000 {
> #hwlock-cells = <1>;
> };
>
> + tlmm: pinctrl@f000000 {
> + compatible = "qcom,qdu1000-tlmm", "qcom,qru1000-tlmm";
> + reg = <0x0 0xf000000 0x0 0x1000000>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-ranges = <&tlmm 0 0 151>;
> + wakeup-parent = <&pdc>;
> +
> + qup_uart7_default: qup-uart7-default {
> + tx {
> + pins = "gpio134";
> + function = "qup0_se7_l2";
This looks strange. Usually we'd have a single 'qup7' function here.
I'd go back to the interconnect driver. Maybe the functions are not
correctly defined there.
> + drive-strength = <2>;
> + bias-disable;
'drive-strength' and 'bias-disable' are to be patched in in the board dts file.
> + };
> +
> + rx {
> + pins = "gpio135";
> + function = "qup0_se7_l3";
> + drive-strength = <2>;
> + bias-disable;
> + };
> + };
> + };
> +
> pdc: interrupt-controller@b220000 {
> compatible = "qcom,pdc";
> reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
> --
> 2.37.3
>
--
With best wishes
Dmitry
On 01/10/2022 05:06, Melody Olvera wrote:
> Add tlmm node for the QDU1000 and QRU1000 SoCs and the uart pin
> configuration.
The patchset should be squashed with previous. There is no point in
bringing support piece by piece. You can bring support in steps if you
submissions are separate in time. But if you have everything ready -
your patch must be complete and bisectable.
>
> Signed-off-by: Melody Olvera <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/qdru1000.dtsi | 30 ++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> index 3610f94bef35..39b9a00d3ad8 100644
> --- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> @@ -235,6 +235,8 @@ uart7: serial@99c000 {
> reg = <0x0 0x99c000 0x0 0x4000>;
> clock-names = "se";
> clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_uart7_default>;
> interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -248,6 +250,34 @@ tcsr_mutex: hwlock@1f40000 {
> #hwlock-cells = <1>;
> };
>
> + tlmm: pinctrl@f000000 {
> + compatible = "qcom,qdu1000-tlmm", "qcom,qru1000-tlmm";
> + reg = <0x0 0xf000000 0x0 0x1000000>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-ranges = <&tlmm 0 0 151>;
> + wakeup-parent = <&pdc>;
> +
> + qup_uart7_default: qup-uart7-default {
Suffix "-state"
> + tx {
Suffix "-pins"
> + pins = "gpio134";
> + function = "qup0_se7_l2";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + rx {
Suffix "-pins"
> + pins = "gpio135";
> + function = "qup0_se7_l3";
> + drive-strength = <2>;
> + bias-disable;
> + };
> + };
> + };
> +
> pdc: interrupt-controller@b220000 {
> compatible = "qcom,pdc";
> reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
Best regards,
Krzysztof
On 10/1/2022 12:26 AM, Dmitry Baryshkov wrote:
> On Sat, 1 Oct 2022 at 06:09, Melody Olvera <[email protected]> wrote:
>> Add tlmm node for the QDU1000 and QRU1000 SoCs and the uart pin
>> configuration.
>>
>> Signed-off-by: Melody Olvera <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/qdru1000.dtsi | 30 ++++++++++++++++++++++++++
>> 1 file changed, 30 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
>> index 3610f94bef35..39b9a00d3ad8 100644
>> --- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
>> @@ -235,6 +235,8 @@ uart7: serial@99c000 {
>> reg = <0x0 0x99c000 0x0 0x4000>;
>> clock-names = "se";
>> clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_uart7_default>;
>> interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
>> #address-cells = <1>;
>> #size-cells = <0>;
>> @@ -248,6 +250,34 @@ tcsr_mutex: hwlock@1f40000 {
>> #hwlock-cells = <1>;
>> };
>>
>> + tlmm: pinctrl@f000000 {
>> + compatible = "qcom,qdu1000-tlmm", "qcom,qru1000-tlmm";
>> + reg = <0x0 0xf000000 0x0 0x1000000>;
>> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + gpio-ranges = <&tlmm 0 0 151>;
>> + wakeup-parent = <&pdc>;
>> +
>> + qup_uart7_default: qup-uart7-default {
>> + tx {
>> + pins = "gpio134";
>> + function = "qup0_se7_l2";
> This looks strange. Usually we'd have a single 'qup7' function here.
> I'd go back to the interconnect driver. Maybe the functions are not
> correctly defined there.
Yeah; will correct. Pinctrl driver was not in line with upstream standards.
>
>> + drive-strength = <2>;
>> + bias-disable;
> 'drive-strength' and 'bias-disable' are to be patched in in the board dts file.
Really? Looking at sm8450.dtsi and sm8350.dtsi I see them defined in the dtsi file instead of the
dts file. Is this new?
>
>> + };
>> +
>> + rx {
>> + pins = "gpio135";
>> + function = "qup0_se7_l3";
>> + drive-strength = <2>;
>> + bias-disable;
>> + };
>> + };
>> + };
>> +
>> pdc: interrupt-controller@b220000 {
>> compatible = "qcom,pdc";
>> reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
>> --
>> 2.37.3
>>
>
Thanks,
Melody
On 10/1/2022 2:14 AM, Krzysztof Kozlowski wrote:
> On 01/10/2022 05:06, Melody Olvera wrote:
>> Add tlmm node for the QDU1000 and QRU1000 SoCs and the uart pin
>> configuration.
> The patchset should be squashed with previous. There is no point in
> bringing support piece by piece. You can bring support in steps if you
> submissions are separate in time. But if you have everything ready -
> your patch must be complete and bisectable.
To be clear, does it make more sense to submit the base dt first, then submit each
driver with all the dt changes as one patchset?
>
>> Signed-off-by: Melody Olvera <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/qdru1000.dtsi | 30 ++++++++++++++++++++++++++
>> 1 file changed, 30 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
>> index 3610f94bef35..39b9a00d3ad8 100644
>> --- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
>> @@ -235,6 +235,8 @@ uart7: serial@99c000 {
>> reg = <0x0 0x99c000 0x0 0x4000>;
>> clock-names = "se";
>> clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_uart7_default>;
>> interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
>> #address-cells = <1>;
>> #size-cells = <0>;
>> @@ -248,6 +250,34 @@ tcsr_mutex: hwlock@1f40000 {
>> #hwlock-cells = <1>;
>> };
>>
>> + tlmm: pinctrl@f000000 {
>> + compatible = "qcom,qdu1000-tlmm", "qcom,qru1000-tlmm";
>> + reg = <0x0 0xf000000 0x0 0x1000000>;
>> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + gpio-ranges = <&tlmm 0 0 151>;
>> + wakeup-parent = <&pdc>;
>> +
>> + qup_uart7_default: qup-uart7-default {
> Suffix "-state"
Ack.
>
>> + tx {
> Suffix "-pins"
Ack.
>
>> + pins = "gpio134";
>> + function = "qup0_se7_l2";
>> + drive-strength = <2>;
>> + bias-disable;
>> + };
>> +
>> + rx {
> Suffix "-pins"
Ack.
>
>
>> + pins = "gpio135";
>> + function = "qup0_se7_l3";
>> + drive-strength = <2>;
>> + bias-disable;
>> + };
>> + };
>> + };
>> +
>> pdc: interrupt-controller@b220000 {
>> compatible = "qcom,pdc";
>> reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
> Best regards,
> Krzysztof
>
Thanks,
Melody
On 11/10/2022 14:48, Melody Olvera wrote:
>
>
> On 10/1/2022 2:14 AM, Krzysztof Kozlowski wrote:
>> On 01/10/2022 05:06, Melody Olvera wrote:
>>> Add tlmm node for the QDU1000 and QRU1000 SoCs and the uart pin
>>> configuration.
>> The patchset should be squashed with previous. There is no point in
>> bringing support piece by piece. You can bring support in steps if you
>> submissions are separate in time. But if you have everything ready -
>> your patch must be complete and bisectable.
> To be clear, does it make more sense to submit the base dt first, then submit each
> driver with all the dt changes as one patchset?
No, because you have DTS ready. There is no incremental work here.
Best regards,
Krzysztof
On 11/10/2022 15:05, Melody Olvera wrote:
>
>
> On 10/11/2022 11:57 AM, Krzysztof Kozlowski wrote:
>> On 11/10/2022 14:48, Melody Olvera wrote:
>>>
>>> On 10/1/2022 2:14 AM, Krzysztof Kozlowski wrote:
>>>> On 01/10/2022 05:06, Melody Olvera wrote:
>>>>> Add tlmm node for the QDU1000 and QRU1000 SoCs and the uart pin
>>>>> configuration.
>>>> The patchset should be squashed with previous. There is no point in
>>>> bringing support piece by piece. You can bring support in steps if you
>>>> submissions are separate in time. But if you have everything ready -
>>>> your patch must be complete and bisectable.
>>> To be clear, does it make more sense to submit the base dt first, then submit each
>>> driver with all the dt changes as one patchset?
>> No, because you have DTS ready. There is no incremental work here.
> Ah ok so just squash all these commits into one and submit.
Except the board DTS. Other bigger, self-contained pieces of work can be
also kept separate, but such work is not "add a DMA". Such work could be
- add display (with clocks, DMA, GPU, power domains) or sound (again
multiple separate devices added).
Best regards,
Krzysztof
On 10/11/2022 11:57 AM, Krzysztof Kozlowski wrote:
> On 11/10/2022 14:48, Melody Olvera wrote:
>>
>> On 10/1/2022 2:14 AM, Krzysztof Kozlowski wrote:
>>> On 01/10/2022 05:06, Melody Olvera wrote:
>>>> Add tlmm node for the QDU1000 and QRU1000 SoCs and the uart pin
>>>> configuration.
>>> The patchset should be squashed with previous. There is no point in
>>> bringing support piece by piece. You can bring support in steps if you
>>> submissions are separate in time. But if you have everything ready -
>>> your patch must be complete and bisectable.
>> To be clear, does it make more sense to submit the base dt first, then submit each
>> driver with all the dt changes as one patchset?
> No, because you have DTS ready. There is no incremental work here.
Ah ok so just squash all these commits into one and submit.
>
> Best regards,
> Krzysztof
>
Thanks,
Melody
On 10/11/2022 12:19 PM, Krzysztof Kozlowski wrote:
> On 11/10/2022 15:05, Melody Olvera wrote:
>>
>> On 10/11/2022 11:57 AM, Krzysztof Kozlowski wrote:
>>> On 11/10/2022 14:48, Melody Olvera wrote:
>>>> On 10/1/2022 2:14 AM, Krzysztof Kozlowski wrote:
>>>>> On 01/10/2022 05:06, Melody Olvera wrote:
>>>>>> Add tlmm node for the QDU1000 and QRU1000 SoCs and the uart pin
>>>>>> configuration.
>>>>> The patchset should be squashed with previous. There is no point in
>>>>> bringing support piece by piece. You can bring support in steps if you
>>>>> submissions are separate in time. But if you have everything ready -
>>>>> your patch must be complete and bisectable.
>>>> To be clear, does it make more sense to submit the base dt first, then submit each
>>>> driver with all the dt changes as one patchset?
>>> No, because you have DTS ready. There is no incremental work here.
>> Ah ok so just squash all these commits into one and submit.
> Except the board DTS. Other bigger, self-contained pieces of work can be
> also kept separate, but such work is not "add a DMA". Such work could be
> - add display (with clocks, DMA, GPU, power domains) or sound (again
> multiple separate devices added).
Understood. Yeah I figured leave the dts files as a separate commit, but do one big commit
for the dtsi file, and one for the dts files.
>
> Best regards,
> Krzysztof
>
Thanks,
Melody