LinuxLists.cc - [PATCH V4 0/4] Add ZynqMP efuse access support

2024-02-02 11:40:38

Subject: [PATCH V4 0/4] Add ZynqMP efuse access support

- Add ZynqMP efuse firmware API for efuse access
- zynqmp_nvmem_probe cleanup
- Add support to read/write ZynqMP efuse memory

The first patch depends on
https://lore.kernel.org/linux-arm-kernel/[email protected]/

---
V3 patch link:
https://lore.kernel.org/all/[email protected]/
V4 Changes:
- Removed [2/3] dt-bindings: nvmem: Convert xlnx,zynqmp-nvmem.txt to yaml
as it got applied https://lore.kernel.org/all/[email protected]/#r
- Split patches as per comments
---

Praveen Teja Kundanala (4):
firmware: xilinx: Add ZynqMP efuse access API
nvmem: zynqmp_nvmem: zynqmp_nvmem_probe cleanup
nvmem: zynqmp_nvmem: Add support to access efuse
MAINTAINERS: Add maintainers for ZynqMP NVMEM driver

MAINTAINERS | 8 +
drivers/firmware/xilinx/zynqmp.c | 25 ++++
drivers/nvmem/zynqmp_nvmem.c | 215 +++++++++++++++++++++++----
include/linux/firmware/xlnx-zynqmp.h | 8 +
4 files changed, 225 insertions(+), 31 deletions(-)

--
2.37.6

2024-02-02 11:40:42

by Praveen Teja Kundanala

[permalink] [raw]

Subject: [PATCH V4 2/4] nvmem: zynqmp_nvmem: zynqmp_nvmem_probe cleanup

- Remove static nvmem_config declaration
- Remove zynqmp_nvmem_data

Signed-off-by: Praveen Teja Kundanala <[email protected]>
---
drivers/nvmem/zynqmp_nvmem.c | 37 ++++++++++++------------------------
1 file changed, 12 insertions(+), 25 deletions(-)

diff --git a/drivers/nvmem/zynqmp_nvmem.c b/drivers/nvmem/zynqmp_nvmem.c
index 7f15aa89a9d0..391d8e88b270 100644
--- a/drivers/nvmem/zynqmp_nvmem.c
+++ b/drivers/nvmem/zynqmp_nvmem.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Xilinx, Inc.
+ * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
*/

#include <linux/module.h>
@@ -11,36 +12,25 @@

#define SILICON_REVISION_MASK 0xF

-struct zynqmp_nvmem_data {
- struct device *dev;
- struct nvmem_device *nvmem;
-};

static int zynqmp_nvmem_read(void *context, unsigned int offset,
void *val, size_t bytes)
{
+ struct device *dev = context;
int ret;
- int idcode, version;
- struct zynqmp_nvmem_data *priv = context;
+ int idcode;
+ int version;

ret = zynqmp_pm_get_chipid(&idcode, &version);
if (ret < 0)
return ret;

- dev_dbg(priv->dev, "Read chipid val %x %x\n", idcode, version);
+ dev_dbg(dev, "Read chipid val %x %x\n", idcode, version);
*(int *)val = version & SILICON_REVISION_MASK;

return 0;
}

-static struct nvmem_config econfig = {
- .name = "zynqmp-nvmem",
- .owner = THIS_MODULE,
- .word_size = 1,
- .size = 1,
- .read_only = true,
-};
-
static const struct of_device_id zynqmp_nvmem_match[] = {
{ .compatible = "xlnx,zynqmp-nvmem-fw", },
{ /* sentinel */ },
@@ -50,21 +40,18 @@ MODULE_DEVICE_TABLE(of, zynqmp_nvmem_match);
static int zynqmp_nvmem_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
- struct zynqmp_nvmem_data *priv;
+ struct nvmem_config econfig = {};

- priv = devm_kzalloc(dev, sizeof(struct zynqmp_nvmem_data), GFP_KERNEL);
- if (!priv)
- return -ENOMEM;
-
- priv->dev = dev;
+ econfig.name = "zynqmp-nvmem";
+ econfig.owner = THIS_MODULE;
+ econfig.word_size = 1;
+ econfig.size = 1;
econfig.dev = dev;
econfig.add_legacy_fixed_of_cells = true;
+ econfig.read_only = true;
econfig.reg_read = zynqmp_nvmem_read;
- econfig.priv = priv;
-
- priv->nvmem = devm_nvmem_register(dev, &econfig);

- return PTR_ERR_OR_ZERO(priv->nvmem);
+ return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &econfig));
}

static struct platform_driver zynqmp_nvmem_driver = {
--
2.37.6

2024-02-02 11:41:08

by Praveen Teja Kundanala

[permalink] [raw]

Subject: [PATCH V4 3/4] nvmem: zynqmp_nvmem: Add support to access efuse

Add support to read/write efuse memory map of ZynqMP.
Below are the offsets of ZynqMP efuse memory map
0 - SOC version(read only)
0xC - 0xFC -ZynqMP specific purpose efuses
0x100 - 0x17F - Physical Unclonable Function(PUF)
efuses repurposed as user efuses

Signed-off-by: Praveen Teja Kundanala <[email protected]>
---
drivers/nvmem/zynqmp_nvmem.c | 186 +++++++++++++++++++++++++++++++++--
1 file changed, 176 insertions(+), 10 deletions(-)

diff --git a/drivers/nvmem/zynqmp_nvmem.c b/drivers/nvmem/zynqmp_nvmem.c
index 391d8e88b270..8682adaacd69 100644
--- a/drivers/nvmem/zynqmp_nvmem.c
+++ b/drivers/nvmem/zynqmp_nvmem.c
@@ -4,6 +4,7 @@
* Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
*/

+#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/nvmem-provider.h>
#include <linux/of.h>
@@ -11,24 +12,189 @@
#include <linux/firmware/xlnx-zynqmp.h>

#define SILICON_REVISION_MASK 0xF
+#define P_USER_0_64_UPPER_MASK GENMASK(31, 16)
+#define P_USER_127_LOWER_4_BIT_MASK GENMASK(3, 0)
+#define WORD_INBYTES 4
+#define SOC_VER_SIZE 0x4
+#define EFUSE_MEMORY_SIZE 0x177
+#define UNUSED_SPACE 0x8
+#define ZYNQMP_NVMEM_SIZE (SOC_VER_SIZE + UNUSED_SPACE + \
+ EFUSE_MEMORY_SIZE)
+#define SOC_VERSION_OFFSET 0x0
+#define EFUSE_START_OFFSET 0xC
+#define EFUSE_END_OFFSET 0xFC
+#define EFUSE_PUF_START_OFFSET 0x100
+#define EFUSE_PUF_MID_OFFSET 0x140
+#define EFUSE_PUF_END_OFFSET 0x17F
+#define EFUSE_NOT_ENABLED 29

+/*
+ * efuse access type
+ */
+enum efuse_access {
+ EFUSE_READ = 0,
+ EFUSE_WRITE
+};
+
+/**
+ * struct xilinx_efuse - the basic structure
+ * @src: address of the buffer to store the data to be write/read
+ * @size: read/write word count
+ * @offset: read/write offset
+ * @flag: 0 - represents efuse read and 1- represents efuse write
+ * @pufuserfuse:0 - represents non-puf efuses, offset is used for read/write
+ * 1 - represents puf user fuse row number.
+ *
+ * this structure stores all the required details to
+ * read/write efuse memory.
+ */
+struct xilinx_efuse {
+ u64 src;
+ u32 size;
+ u32 offset;
+ enum efuse_access flag;
+ u32 pufuserfuse;
+};
+
+static int zynqmp_efuse_access(void *context, unsigned int offset,
+ void *val, size_t bytes, enum efuse_access flag,
+ unsigned int pufflag)
+{
+ struct device *dev = context;
+ struct xilinx_efuse *efuse;
+ dma_addr_t dma_addr;
+ dma_addr_t dma_buf;
+ size_t words = bytes / WORD_INBYTES;
+ int ret;
+ int value;
+ char *data;
+
+ if (bytes % WORD_INBYTES != 0) {
+ dev_err(dev, "Bytes requested should be word aligned\n");
+ return -EOPNOTSUPP;
+ }
+
+ if (pufflag == 0 && offset % WORD_INBYTES) {
+ dev_err(dev, "Offset requested should be word aligned\n");
+ return -EOPNOTSUPP;
+ }
+
+ if (pufflag == 1 && flag == EFUSE_WRITE) {
+ memcpy(&value, val, bytes);
+ if ((offset == EFUSE_PUF_START_OFFSET ||
+ offset == EFUSE_PUF_MID_OFFSET) &&
+ value & P_USER_0_64_UPPER_MASK) {
+ dev_err(dev, "Only lower 4 bytes are allowed to be programmed in P_USER_0 & P_USER_64\n");
+ return -EOPNOTSUPP;
+ }
+
+ if (offset == EFUSE_PUF_END_OFFSET &&
+ (value & P_USER_127_LOWER_4_BIT_MASK)) {
+ dev_err(dev, "Only MSB 28 bits are allowed to be programmed for P_USER_127\n");
+ return -EOPNOTSUPP;
+ }
+ }
+
+ efuse = dma_alloc_coherent(dev, sizeof(struct xilinx_efuse),
+ &dma_addr, GFP_KERNEL);
+ if (!efuse)
+ return -ENOMEM;

-static int zynqmp_nvmem_read(void *context, unsigned int offset,
- void *val, size_t bytes)
+ data = dma_alloc_coherent(dev, sizeof(bytes),
+ &dma_buf, GFP_KERNEL);
+ if (!data) {
+ ret = -ENOMEM;
+ goto efuse_data_fail;
+ }
+
+ if (flag == EFUSE_WRITE) {
+ memcpy(data, val, bytes);
+ efuse->flag = EFUSE_WRITE;
+ } else {
+ efuse->flag = EFUSE_READ;
+ }
+
+ efuse->src = dma_buf;
+ efuse->size = words;
+ efuse->offset = offset;
+ efuse->pufuserfuse = pufflag;
+
+ zynqmp_pm_efuse_access(dma_addr, (u32 *)&ret);
+ if (ret != 0) {
+ if (ret == EFUSE_NOT_ENABLED) {
+ dev_err(dev, "efuse access is not enabled\n");
+ ret = -EOPNOTSUPP;
+ } else {
+ dev_err(dev, "Error in efuse read %x\n", ret);
+ ret = -EPERM;
+ }
+ goto efuse_access_err;
+ }
+
+ if (flag == EFUSE_READ)
+ memcpy(val, data, bytes);
+efuse_access_err:
+ dma_free_coherent(dev, sizeof(bytes),
+ data, dma_buf);
+efuse_data_fail:
+ dma_free_coherent(dev, sizeof(struct xilinx_efuse),
+ efuse, dma_addr);
+
+ return ret;
+}
+
+static int zynqmp_nvmem_read(void *context, unsigned int offset, void *val, size_t bytes)
{
struct device *dev = context;
int ret;
+ int pufflag = 0;
int idcode;
int version;

- ret = zynqmp_pm_get_chipid(&idcode, &version);
- if (ret < 0)
- return ret;
+ if (offset >= EFUSE_PUF_START_OFFSET && offset <= EFUSE_PUF_END_OFFSET)
+ pufflag = 1;
+
+ switch (offset) {
+ /* Soc version offset is zero */
+ case SOC_VERSION_OFFSET:
+ if (bytes != SOC_VER_SIZE)
+ return -EOPNOTSUPP;
+
+ ret = zynqmp_pm_get_chipid((u32 *)&idcode, (u32 *)&version);
+ if (ret < 0)
+ return ret;
+
+ dev_dbg(dev, "Read chipid val %x %x\n", idcode, version);
+ *(int *)val = version & SILICON_REVISION_MASK;
+ break;
+ /* Efuse offset starts from 0xc */
+ case EFUSE_START_OFFSET ... EFUSE_END_OFFSET:
+ case EFUSE_PUF_START_OFFSET ... EFUSE_PUF_END_OFFSET:
+ ret = zynqmp_efuse_access(context, offset, val,
+ bytes, EFUSE_READ, pufflag);
+ break;
+ default:
+ *(u32 *)val = 0xDEADBEEF;
+ ret = 0;
+ break;
+ }
+
+ return ret;
+}
+
+static int zynqmp_nvmem_write(void *context,
+ unsigned int offset, void *val, size_t bytes)
+{
+ int pufflag = 0;
+
+ if (offset < EFUSE_START_OFFSET || offset > EFUSE_PUF_END_OFFSET)
+ return -EOPNOTSUPP;

- dev_dbg(dev, "Read chipid val %x %x\n", idcode, version);
- *(int *)val = version & SILICON_REVISION_MASK;
+ if (offset >= EFUSE_PUF_START_OFFSET && offset <= EFUSE_PUF_END_OFFSET)
+ pufflag = 1;

- return 0;
+ return zynqmp_efuse_access(context, offset,
+ val, bytes, EFUSE_WRITE, pufflag);
}

static const struct of_device_id zynqmp_nvmem_match[] = {
@@ -45,11 +211,11 @@ static int zynqmp_nvmem_probe(struct platform_device *pdev)
econfig.name = "zynqmp-nvmem";
econfig.owner = THIS_MODULE;
econfig.word_size = 1;
- econfig.size = 1;
+ econfig.size = ZYNQMP_NVMEM_SIZE;
econfig.dev = dev;
econfig.add_legacy_fixed_of_cells = true;
- econfig.read_only = true;
econfig.reg_read = zynqmp_nvmem_read;
+ econfig.reg_write = zynqmp_nvmem_write;

return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &econfig));
}
--
2.37.6

2024-02-02 12:04:33

by Praveen Teja Kundanala

[permalink] [raw]

Subject: [PATCH V4 1/4] firmware: xilinx: Add ZynqMP efuse access API

Add zynqmp_pm_efuse_access API in the ZynqMP
firmware for read/write access of efuse memory.

Signed-off-by: Praveen Teja Kundanala <[email protected]>
---
drivers/firmware/xilinx/zynqmp.c | 25 +++++++++++++++++++++++++
include/linux/firmware/xlnx-zynqmp.h | 8 ++++++++
2 files changed, 33 insertions(+)

diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 79789f0563f6..9bc45357e1a8 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -3,6 +3,7 @@
* Xilinx Zynq MPSoC Firmware layer
*
* Copyright (C) 2014-2022 Xilinx, Inc.
+ * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <[email protected]>
* Davorin Mista <[email protected]>
@@ -1384,6 +1385,30 @@ int zynqmp_pm_aes_engine(const u64 address, u32 *out)
}
EXPORT_SYMBOL_GPL(zynqmp_pm_aes_engine);

+/**
+ * zynqmp_pm_efuse_access - Provides access to efuse memory.
+ * @address: Address of the efuse params structure
+ * @out: Returned output value
+ *
+ * Return: Returns status, either success or error code.
+ */
+int zynqmp_pm_efuse_access(const u64 address, u32 *out)
+{
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ int ret;
+
+ if (!out)
+ return -EINVAL;
+
+ ret = zynqmp_pm_invoke_fn(PM_EFUSE_ACCESS, ret_payload, 2,
+ upper_32_bits(address),
+ lower_32_bits(address));
+ *out = ret_payload[1];
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_efuse_access);
+
/**
* zynqmp_pm_sha_hash - Access the SHA engine to calculate the hash
* @address: Address of the data/ Address of output buffer where
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 9a7e52739251..1a069a56c961 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -3,6 +3,7 @@
* Xilinx Zynq MPSoC Firmware layer
*
* Copyright (C) 2014-2021 Xilinx
+ * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
*
* Michal Simek <[email protected]>
* Davorin Mista <[email protected]>
@@ -171,6 +172,7 @@ enum pm_api_id {
PM_CLOCK_GETPARENT = 44,
PM_FPGA_READ = 46,
PM_SECURE_AES = 47,
+ PM_EFUSE_ACCESS = 53,
PM_FEATURE_CHECK = 63,
};

@@ -562,6 +564,7 @@ int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
const u32 qos,
const enum zynqmp_pm_request_ack ack);
int zynqmp_pm_aes_engine(const u64 address, u32 *out);
+int zynqmp_pm_efuse_access(const u64 address, u32 *out);
int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags);
int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
int zynqmp_pm_fpga_get_status(u32 *value);
@@ -749,6 +752,11 @@ static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
return -ENODEV;
}

+static inline int zynqmp_pm_efuse_access(const u64 address, u32 *out)
+{
+ return -ENODEV;
+}
+
static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size,
const u32 flags)
{
--
2.37.6

2024-02-02 12:05:28

by Praveen Teja Kundanala

[permalink] [raw]

Subject: [PATCH V4 4/4] MAINTAINERS: Add maintainers for ZynqMP NVMEM driver

Add maintainers for ZynqMP NVMEM driver and driver document.

Signed-off-by: Praveen Teja Kundanala <[email protected]>
---
MAINTAINERS | 8 ++++++++
1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 8d1052fa6a69..b3103e03015e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -24233,6 +24233,14 @@ M: Harsha <[email protected]>
S: Maintained
F: drivers/crypto/xilinx/zynqmp-sha.c

+XILINX ZYNQMP NVMEM DRIVER
+M: Praveen Teja Kundanala <[email protected]>
+M: Kalyani Akula <[email protected]>
+R: Michal Simek <[email protected]>
+S: Maintained
+F: Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.yaml
+F: drivers/nvmem/zynqmp_nvmem.c
+
XILLYBUS DRIVER
M: Eli Billauer <[email protected]>
L: [email protected]
--
2.37.6

2024-02-05 07:03:15

by Michal Simek

[permalink] [raw]

Subject: Re: [PATCH V4 1/4] firmware: xilinx: Add ZynqMP efuse access API

On 2/2/24 12:38, Praveen Teja Kundanala wrote:
> Add zynqmp_pm_efuse_access API in the ZynqMP
> firmware for read/write access of efuse memory.
>
> Signed-off-by: Praveen Teja Kundanala <[email protected]>
> ---
> drivers/firmware/xilinx/zynqmp.c | 25 +++++++++++++++++++++++++
> include/linux/firmware/xlnx-zynqmp.h | 8 ++++++++
> 2 files changed, 33 insertions(+)
>
> diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
> index 79789f0563f6..9bc45357e1a8 100644
> --- a/drivers/firmware/xilinx/zynqmp.c
> +++ b/drivers/firmware/xilinx/zynqmp.c
> @@ -3,6 +3,7 @@
> * Xilinx Zynq MPSoC Firmware layer
> *
> * Copyright (C) 2014-2022 Xilinx, Inc.
> + * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
> *
> * Michal Simek <[email protected]>
> * Davorin Mista <[email protected]>
> @@ -1384,6 +1385,30 @@ int zynqmp_pm_aes_engine(const u64 address, u32 *out)
> }
> EXPORT_SYMBOL_GPL(zynqmp_pm_aes_engine);
>
> +/**
> + * zynqmp_pm_efuse_access - Provides access to efuse memory.
> + * @address: Address of the efuse params structure
> + * @out: Returned output value
> + *
> + * Return: Returns status, either success or error code.
> + */
> +int zynqmp_pm_efuse_access(const u64 address, u32 *out)
> +{
> + u32 ret_payload[PAYLOAD_ARG_CNT];
> + int ret;
> +
> + if (!out)
> + return -EINVAL;
> +
> + ret = zynqmp_pm_invoke_fn(PM_EFUSE_ACCESS, ret_payload, 2,
> + upper_32_bits(address),
> + lower_32_bits(address));
> + *out = ret_payload[1];
> +
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(zynqmp_pm_efuse_access);
> +
> /**
> * zynqmp_pm_sha_hash - Access the SHA engine to calculate the hash
> * @address: Address of the data/ Address of output buffer where
> diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
> index 9a7e52739251..1a069a56c961 100644
> --- a/include/linux/firmware/xlnx-zynqmp.h
> +++ b/include/linux/firmware/xlnx-zynqmp.h
> @@ -3,6 +3,7 @@
> * Xilinx Zynq MPSoC Firmware layer
> *
> * Copyright (C) 2014-2021 Xilinx
> + * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
> *
> * Michal Simek <[email protected]>
> * Davorin Mista <[email protected]>
> @@ -171,6 +172,7 @@ enum pm_api_id {
> PM_CLOCK_GETPARENT = 44,
> PM_FPGA_READ = 46,
> PM_SECURE_AES = 47,
> + PM_EFUSE_ACCESS = 53,
> PM_FEATURE_CHECK = 63,
> };
>
> @@ -562,6 +564,7 @@ int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
> const u32 qos,
> const enum zynqmp_pm_request_ack ack);
> int zynqmp_pm_aes_engine(const u64 address, u32 *out);
> +int zynqmp_pm_efuse_access(const u64 address, u32 *out);
> int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags);
> int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
> int zynqmp_pm_fpga_get_status(u32 *value);
> @@ -749,6 +752,11 @@ static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
> return -ENODEV;
> }
>
> +static inline int zynqmp_pm_efuse_access(const u64 address, u32 *out)
> +{
> + return -ENODEV;
> +}
> +
> static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size,
> const u32 flags)
> {

Acked-by: Michal Simek <[email protected]>

Thanks,
Michal

2024-02-08 06:48:18

by Akula, Kalyani

[permalink] [raw]

Subject: RE: [PATCH V4 2/4] nvmem: zynqmp_nvmem: zynqmp_nvmem_probe cleanup

2024-02-08 06:48:48

by Akula, Kalyani

[permalink] [raw]

Subject: RE: [PATCH V4 3/4] nvmem: zynqmp_nvmem: Add support to access efuse

>-----Original Message-----
>From: Praveen Teja Kundanala <[email protected]>
>Sent: Friday, February 2, 2024 5:09 PM
>To: [email protected]; Simek, Michal <[email protected]>;
>Akula, Kalyani <[email protected]>; Kundanala, Praveen Teja
><[email protected]>; [email protected]; linux-arm-
>[email protected]
>Cc: [email protected]
>Subject: [PATCH V4 3/4] nvmem: zynqmp_nvmem: Add support to access efuse
>
>Add support to read/write efuse memory map of ZynqMP.
>Below are the offsets of ZynqMP efuse memory map
> 0 - SOC version(read only)
> 0xC - 0xFC -ZynqMP specific purpose efuses
> 0x100 - 0x17F - Physical Unclonable Function(PUF)
> efuses repurposed as user efuses
>
>Signed-off-by: Praveen Teja Kundanala <[email protected]>
>---
> drivers/nvmem/zynqmp_nvmem.c | 186
>+++++++++++++++++++++++++++++++++--
> 1 file changed, 176 insertions(+), 10 deletions(-)
>
>diff --git a/drivers/nvmem/zynqmp_nvmem.c
>b/drivers/nvmem/zynqmp_nvmem.c index 391d8e88b270..8682adaacd69
>100644
>--- a/drivers/nvmem/zynqmp_nvmem.c
>+++ b/drivers/nvmem/zynqmp_nvmem.c
>@@ -4,6 +4,7 @@
> * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc.
> */
>
>+#include <linux/dma-mapping.h>
> #include <linux/module.h>
> #include <linux/nvmem-provider.h>
> #include <linux/of.h>
>@@ -11,24 +12,189 @@
> #include <linux/firmware/xlnx-zynqmp.h>
>
> #define SILICON_REVISION_MASK 0xF
>+#define P_USER_0_64_UPPER_MASK GENMASK(31, 16)
>+#define P_USER_127_LOWER_4_BIT_MASK GENMASK(3, 0)
>+#define WORD_INBYTES 4
>+#define SOC_VER_SIZE 0x4
>+#define EFUSE_MEMORY_SIZE 0x177
>+#define UNUSED_SPACE 0x8
>+#define ZYNQMP_NVMEM_SIZE (SOC_VER_SIZE + UNUSED_SPACE + \
>+ EFUSE_MEMORY_SIZE)
>+#define SOC_VERSION_OFFSET 0x0
>+#define EFUSE_START_OFFSET 0xC
>+#define EFUSE_END_OFFSET 0xFC
>+#define EFUSE_PUF_START_OFFSET 0x100
>+#define EFUSE_PUF_MID_OFFSET 0x140
>+#define EFUSE_PUF_END_OFFSET 0x17F
>+#define EFUSE_NOT_ENABLED 29
>
>+/*
>+ * efuse access type
>+ */
>+enum efuse_access {
>+ EFUSE_READ = 0,
>+ EFUSE_WRITE
>+};
>+
>+/**
>+ * struct xilinx_efuse - the basic structure
>+ * @src: address of the buffer to store the data to be write/read
>+ * @size: read/write word count
>+ * @offset: read/write offset
>+ * @flag: 0 - represents efuse read and 1- represents efuse write
>+ * @pufuserfuse:0 - represents non-puf efuses, offset is used for read/write
>+ * 1 - represents puf user fuse row number.
>+ *
>+ * this structure stores all the required details to
>+ * read/write efuse memory.
>+ */
>+struct xilinx_efuse {
>+ u64 src;
>+ u32 size;
>+ u32 offset;
>+ enum efuse_access flag;
>+ u32 pufuserfuse;
>+};
>+
>+static int zynqmp_efuse_access(void *context, unsigned int offset,
>+ void *val, size_t bytes, enum efuse_access flag,
>+ unsigned int pufflag)
>+{
>+ struct device *dev = context;
>+ struct xilinx_efuse *efuse;
>+ dma_addr_t dma_addr;
>+ dma_addr_t dma_buf;
>+ size_t words = bytes / WORD_INBYTES;
>+ int ret;
>+ int value;
>+ char *data;
>+
>+ if (bytes % WORD_INBYTES != 0) {
>+ dev_err(dev, "Bytes requested should be word aligned\n");
>+ return -EOPNOTSUPP;
>+ }
>+
>+ if (pufflag == 0 && offset % WORD_INBYTES) {
>+ dev_err(dev, "Offset requested should be word aligned\n");
>+ return -EOPNOTSUPP;
>+ }
>+
>+ if (pufflag == 1 && flag == EFUSE_WRITE) {
>+ memcpy(&value, val, bytes);
>+ if ((offset == EFUSE_PUF_START_OFFSET ||
>+ offset == EFUSE_PUF_MID_OFFSET) &&
>+ value & P_USER_0_64_UPPER_MASK) {
>+ dev_err(dev, "Only lower 4 bytes are allowed to be
>programmed in P_USER_0 & P_USER_64\n");
>+ return -EOPNOTSUPP;
>+ }
>+
>+ if (offset == EFUSE_PUF_END_OFFSET &&
>+ (value & P_USER_127_LOWER_4_BIT_MASK)) {
>+ dev_err(dev, "Only MSB 28 bits are allowed to be
>programmed for P_USER_127\n");
>+ return -EOPNOTSUPP;
>+ }
>+ }
>+
>+ efuse = dma_alloc_coherent(dev, sizeof(struct xilinx_efuse),
>+ &dma_addr, GFP_KERNEL);
>+ if (!efuse)
>+ return -ENOMEM;
>
>-static int zynqmp_nvmem_read(void *context, unsigned int offset,
>- void *val, size_t bytes)
>+ data = dma_alloc_coherent(dev, sizeof(bytes),
>+ &dma_buf, GFP_KERNEL);
>+ if (!data) {
>+ ret = -ENOMEM;
>+ goto efuse_data_fail;
>+ }
>+
>+ if (flag == EFUSE_WRITE) {
>+ memcpy(data, val, bytes);
>+ efuse->flag = EFUSE_WRITE;
>+ } else {
>+ efuse->flag = EFUSE_READ;
>+ }
>+
>+ efuse->src = dma_buf;
>+ efuse->size = words;
>+ efuse->offset = offset;
>+ efuse->pufuserfuse = pufflag;
>+
>+ zynqmp_pm_efuse_access(dma_addr, (u32 *)&ret);
>+ if (ret != 0) {
>+ if (ret == EFUSE_NOT_ENABLED) {
>+ dev_err(dev, "efuse access is not enabled\n");
>+ ret = -EOPNOTSUPP;
>+ } else {
>+ dev_err(dev, "Error in efuse read %x\n", ret);
>+ ret = -EPERM;
>+ }
>+ goto efuse_access_err;
>+ }
>+
>+ if (flag == EFUSE_READ)
>+ memcpy(val, data, bytes);
>+efuse_access_err:
>+ dma_free_coherent(dev, sizeof(bytes),
>+ data, dma_buf);
>+efuse_data_fail:
>+ dma_free_coherent(dev, sizeof(struct xilinx_efuse),
>+ efuse, dma_addr);
>+
>+ return ret;
>+}
>+
>+static int zynqmp_nvmem_read(void *context, unsigned int offset, void
>+*val, size_t bytes)
> {
> struct device *dev = context;
> int ret;
>+ int pufflag = 0;
> int idcode;
> int version;
>
>- ret = zynqmp_pm_get_chipid(&idcode, &version);
>- if (ret < 0)
>- return ret;
>+ if (offset >= EFUSE_PUF_START_OFFSET && offset <=
>EFUSE_PUF_END_OFFSET)
>+ pufflag = 1;
>+
>+ switch (offset) {
>+ /* Soc version offset is zero */
>+ case SOC_VERSION_OFFSET:
>+ if (bytes != SOC_VER_SIZE)
>+ return -EOPNOTSUPP;
>+
>+ ret = zynqmp_pm_get_chipid((u32 *)&idcode, (u32
>*)&version);
>+ if (ret < 0)
>+ return ret;
>+
>+ dev_dbg(dev, "Read chipid val %x %x\n", idcode, version);
>+ *(int *)val = version & SILICON_REVISION_MASK;
>+ break;
>+ /* Efuse offset starts from 0xc */
>+ case EFUSE_START_OFFSET ... EFUSE_END_OFFSET:
>+ case EFUSE_PUF_START_OFFSET ... EFUSE_PUF_END_OFFSET:
>+ ret = zynqmp_efuse_access(context, offset, val,
>+ bytes, EFUSE_READ, pufflag);
>+ break;
>+ default:
>+ *(u32 *)val = 0xDEADBEEF;
>+ ret = 0;
>+ break;
>+ }
>+
>+ return ret;
>+}
>+
>+static int zynqmp_nvmem_write(void *context,
>+ unsigned int offset, void *val, size_t bytes) {
>+ int pufflag = 0;
>+
>+ if (offset < EFUSE_START_OFFSET || offset > EFUSE_PUF_END_OFFSET)
>+ return -EOPNOTSUPP;
>
>- dev_dbg(dev, "Read chipid val %x %x\n", idcode, version);
>- *(int *)val = version & SILICON_REVISION_MASK;
>+ if (offset >= EFUSE_PUF_START_OFFSET && offset <=
>EFUSE_PUF_END_OFFSET)
>+ pufflag = 1;
>
>- return 0;
>+ return zynqmp_efuse_access(context, offset,
>+ val, bytes, EFUSE_WRITE, pufflag);
> }
>
> static const struct of_device_id zynqmp_nvmem_match[] = { @@ -45,11
>+211,11 @@ static int zynqmp_nvmem_probe(struct platform_device *pdev)
> econfig.name = "zynqmp-nvmem";
> econfig.owner = THIS_MODULE;
> econfig.word_size = 1;
>- econfig.size = 1;
>+ econfig.size = ZYNQMP_NVMEM_SIZE;
> econfig.dev = dev;
> econfig.add_legacy_fixed_of_cells = true;
>- econfig.read_only = true;
> econfig.reg_read = zynqmp_nvmem_read;
>+ econfig.reg_write = zynqmp_nvmem_write;
>
> return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &econfig)); }
>--
>2.37.6

Acked-by: Kalyani Akula <[email protected]>

Regards,
Kalyani

2024-02-13 13:01:05

by Srinivas Kandagatla

[permalink] [raw]

Subject: Re: [PATCH V4 0/4] Add ZynqMP efuse access support

On Fri, 02 Feb 2024 17:08:39 +0530, Praveen Teja Kundanala wrote:
> - Add ZynqMP efuse firmware API for efuse access
> - zynqmp_nvmem_probe cleanup
> - Add support to read/write ZynqMP efuse memory
>
> The first patch depends on
> https://lore.kernel.org/linux-arm-kernel/[email protected]/
>
> [...]

Applied, thanks!

[1/4] firmware: xilinx: Add ZynqMP efuse access API
commit: 88f70b7f94747e8e52930a57d6d11d1bd83224c4
[2/4] nvmem: zynqmp_nvmem: zynqmp_nvmem_probe cleanup
commit: 71e2473b51515f61c4edd50aa8e841526a2963ae
[3/4] nvmem: zynqmp_nvmem: Add support to access efuse
commit: fcb1413edbd8b3da53081735b1b1585cbce0e23e
[4/4] MAINTAINERS: Add maintainers for ZynqMP NVMEM driver
commit: 81ef75cac58fe75554a01db5f34b9c093241c05d

Best regards,
--
Srinivas Kandagatla <[email protected]>