This series introduces dt-bindings documents for miscellaneous register
blocks implemented in Socionext Uniphier SoCs.
These are previously defined in the devicetree and used in the examples of
subnodes' dt-bindings, however, not documented.
These include two types of the blocks
* independent block including miscellaneous registers and functions for
the whole SoC (system controller and SoC-glue logic)
* sideband logic including control registers in the component (others)
This series is part of the previous series shown below:
https://lore.kernel.org/linux-arm-kernel/[email protected]
Kunihiko Hayashi (8):
dt-bindings: soc: socionext: Add UniPhier system controller
dt-bindings: soc: socionext: Add UniPhier SoC-glue logic
dt-bindings: soc: socionext: Add UniPhier peripheral block
dt-bindings: soc: socionext: Add UniPhier media I/O block
dt-bindings: soc: socionext: Add UniPhier SD interface block
dt-bindings: soc: socionext: Add UniPhier ADAMV block
dt-bindings: soc: socionext: Add UniPhier DWC3 USB glue layer
dt-bindings: soc: socionext: Add UniPhier AHCI glue layer
.../socionext/socionext,uniphier-adamv.yaml | 52 +++++++++
.../socionext,uniphier-ahci-glue.yaml | 78 +++++++++++++
.../socionext,uniphier-dwc3-glue.yaml | 106 ++++++++++++++++++
.../socionext/socionext,uniphier-mioctrl.yaml | 67 +++++++++++
.../socionext,uniphier-perictrl.yaml | 67 +++++++++++
.../socionext/socionext,uniphier-sdctrl.yaml | 63 +++++++++++
.../socionext,uniphier-soc-glue.yaml | 94 ++++++++++++++++
.../socionext/socionext,uniphier-sysctrl.yaml | 84 ++++++++++++++
MAINTAINERS | 1 +
9 files changed, 612 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-adamv.yaml
create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-ahci-glue.yaml
create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml
create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-mioctrl.yaml
create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml
create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-sdctrl.yaml
create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue.yaml
create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-sysctrl.yaml
--
2.25.1
Add devicetree binding schema for the SoC-glue logic implemented on
Socionext Uniphier SoCs.
This SoC-glue logic is a set of miscellaneous function registers
handling signals for specific devices outside system components,
and also has multiple functions such as I/O pinmux, usb-phy, debug,
clock-mux for a specific SoC, and so on.
Signed-off-by: Kunihiko Hayashi <[email protected]>
---
.../socionext,uniphier-soc-glue.yaml | 94 +++++++++++++++++++
1 file changed, 94 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue.yaml
diff --git a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue.yaml b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue.yaml
new file mode 100644
index 000000000000..3f571e3e1339
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Socionext UniPhier SoC-glue logic
+
+maintainers:
+ - Kunihiko Hayashi <[email protected]>
+
+description: |+
+ SoC-glue logic implemented on Socionext UniPhier SoCs is a collection of
+ miscellaneous function registers handling signals outside system components.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - socionext,uniphier-ld4-soc-glue
+ - socionext,uniphier-pro4-soc-glue
+ - socionext,uniphier-pro5-soc-glue
+ - socionext,uniphier-pxs2-soc-glue
+ - socionext,uniphier-ld6b-soc-glue
+ - socionext,uniphier-sld8-soc-glue
+ - socionext,uniphier-ld11-soc-glue
+ - socionext,uniphier-ld20-soc-glue
+ - socionext,uniphier-pxs3-soc-glue
+ - socionext,uniphier-nx1-soc-glue
+ - socionext,uniphier-soc-glue
+ - const: simple-mfd
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+patternProperties:
+ "^pinctrl(@[0-9a-f]+)?$":
+ $ref: /schemas/pinctrl/socionext,uniphier-pinctrl.yaml#
+
+ "^usb-controller(@[0-9a-f]+)?$":
+ $ref: /schemas/phy/socionext,uniphier-usb2-phy.yaml#
+
+ "^clock-controller(@[0-9a-f]+)?$":
+ $ref: /schemas/clock/socionext,uniphier-clock.yaml#
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@5f800000 {
+ compatible = "socionext,uniphier-pro4-soc-glue",
+ "simple-mfd", "syscon";
+ reg = <0x5f800000 0x2000>;
+
+ pinctrl {
+ compatible = "socionext,uniphier-pro4-pinctrl";
+ };
+
+ usb-controller {
+ compatible = "socionext,uniphier-pro4-usb2-phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+ };
+
+ clock-controller {
+ compatible = "socionext,uniphier-pro4-sg-clock";
+ #clock-cells = <1>;
+ };
+ };
--
2.25.1
Add DT binding schema for components belonging to the platform-specific
AHCI glue layer implemented in UniPhier SoCs.
This AHCI glue layer works as a sideband logic for the host controller,
including core reset, PHYs, and some signals to the controller.
Signed-off-by: Kunihiko Hayashi <[email protected]>
---
.../socionext,uniphier-ahci-glue.yaml | 78 +++++++++++++++++++
1 file changed, 78 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-ahci-glue.yaml
diff --git a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-ahci-glue.yaml b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-ahci-glue.yaml
new file mode 100644
index 000000000000..bf37be8a778d
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-ahci-glue.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-ahci-glue.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Socionext UniPhier SoC AHCI glue layer
+
+maintainers:
+ - Kunihiko Hayashi <[email protected]>
+
+description: |+
+ AHCI glue layer implemented on Socionext UniPhier SoCs is a sideband
+ logic handling signals to AHCI host controller inside AHCI component.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - socionext,uniphier-pro4-ahci-glue
+ - socionext,uniphier-pxs2-ahci-glue
+ - socionext,uniphier-pxs3-ahci-glue
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+ ranges: true
+
+patternProperties:
+ "^reset-controller@[0-9a-f]+$":
+ $ref: /schemas/reset/socionext,uniphier-glue-reset.yaml#
+
+ "phy@[0-9a-f]+$":
+ $ref: /schemas/phy/socionext,uniphier-ahci-phy.yaml#
+
+required:
+ - compatible
+ - reg
+
+additionalProperties:
+ type: object
+
+examples:
+ - |
+ sata-controller@65700000 {
+ compatible = "socionext,uniphier-pxs3-ahci-glue", "simple-mfd";
+ reg = <0x65b00000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x65700000 0x100>;
+
+ reset-controller@0 {
+ compatible = "socionext,uniphier-pxs3-ahci-reset";
+ reg = <0x0 0x4>;
+ clock-names = "link";
+ clocks = <&sys_clk 28>;
+ reset-names = "link";
+ resets = <&sys_rst 28>;
+ #reset-cells = <1>;
+ };
+
+ phy@10 {
+ compatible = "socionext,uniphier-pxs3-ahci-phy";
+ reg = <0x10 0x10>;
+ clock-names = "link", "phy";
+ clocks = <&sys_clk 28>, <&sys_clk 30>;
+ reset-names = "link", "phy";
+ resets = <&sys_rst 28>, <&sys_rst 30>;
+ #phy-cells = <0>;
+ };
+ };
--
2.25.1
Add DT binding schema for components belonging to the platform-specific
DWC3 USB glue layer implemented in UniPhier SoCs.
This USB glue layer works as a sideband logic for the host controller,
including core reset, vbus control, PHYs, and some signals to the
controller.
Signed-off-by: Kunihiko Hayashi <[email protected]>
---
.../socionext,uniphier-dwc3-glue.yaml | 106 ++++++++++++++++++
1 file changed, 106 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml
diff --git a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml
new file mode 100644
index 000000000000..66f8786dd305
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-dwc3-glue.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Socionext UniPhier SoC DWC3 USB3.0 glue layer
+
+maintainers:
+ - Kunihiko Hayashi <[email protected]>
+
+description: |+
+ DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is
+ a sideband logic handling signals to DWC3 host controller inside
+ USB3.0 component.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - socionext,uniphier-pro4-dwc3-glue
+ - socionext,uniphier-pro5-dwc3-glue
+ - socionext,uniphier-pxs2-dwc3-glue
+ - socionext,uniphier-ld20-dwc3-glue
+ - socionext,uniphier-pxs3-dwc3-glue
+ - socionext,uniphier-nx1-dwc3-glue
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+ ranges: true
+
+patternProperties:
+ "^reset-controller@[0-9a-f]+$":
+ $ref: /schemas/reset/socionext,uniphier-glue-reset.yaml#
+
+ "^regulator@[0-9a-f]+$":
+ $ref: /schemas/regulator/socionext,uniphier-regulator.yaml#
+
+ "^phy@[0-9a-f]+$":
+ oneOf:
+ - $ref: /schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
+ - $ref: /schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ usb-controller@65b00000 {
+ compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd";
+ reg = <0x65b00000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x65b00000 0x400>;
+
+ reset-controller@0 {
+ compatible = "socionext,uniphier-ld20-usb3-reset";
+ reg = <0x0 0x4>;
+ #reset-cells = <1>;
+ clock-names = "link";
+ clocks = <&sys_clk 14>;
+ reset-names = "link";
+ resets = <&sys_rst 14>;
+ };
+
+ regulator@100 {
+ compatible = "socionext,uniphier-ld20-usb3-regulator";
+ reg = <0x100 0x10>;
+ clock-names = "link";
+ clocks = <&sys_clk 14>;
+ reset-names = "link";
+ resets = <&sys_rst 14>;
+ };
+
+ phy@200 {
+ compatible = "socionext,uniphier-ld20-usb3-hsphy";
+ reg = <0x200 0x10>;
+ #phy-cells = <0>;
+ clock-names = "link", "phy";
+ clocks = <&sys_clk 14>, <&sys_clk 16>;
+ reset-names = "link", "phy";
+ resets = <&sys_rst 14>, <&sys_rst 16>;
+ };
+
+ phy@300 {
+ compatible = "socionext,uniphier-ld20-usb3-ssphy";
+ reg = <0x300 0x10>;
+ #phy-cells = <0>;
+ clock-names = "link", "phy";
+ clocks = <&sys_clk 14>, <&sys_clk 18>;
+ reset-names = "link", "phy";
+ resets = <&sys_rst 14>, <&sys_rst 18>;
+ };
+ };
+
--
2.25.1
Add devicetree binding schema for the ADAMV block implemented on Socionext
Uniphier SoCs.
The ADAMV block is analog signal amplifier that is a part of the external
video and audio I/O system. This block is implemented on LD11 and LD20,
and this is defined for controlling audio I/O reset only.
Signed-off-by: Kunihiko Hayashi <[email protected]>
---
.../socionext/socionext,uniphier-adamv.yaml | 52 +++++++++++++++++++
1 file changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-adamv.yaml
diff --git a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-adamv.yaml b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-adamv.yaml
new file mode 100644
index 000000000000..ae806960b3f1
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-adamv.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-adamv.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Socionext UniPhier ADAMV block
+
+maintainers:
+ - Kunihiko Hayashi <[email protected]>
+
+description: |+
+ ADAMV block implemented on Socionext UniPhier SoCs is an analog signal
+ amplifier that is a part of the external video and audio I/O system.
+
+ This block is defined for controlling audio I/O reset only.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - socionext,uniphier-ld11-adamv
+ - socionext,uniphier-ld20-adamv
+ - socionext,uniphier-adamv
+ - const: simple-mfd
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+patternProperties:
+ "^reset-controller(@[0-9a-f]+)?$":
+ $ref: /schemas/reset/socionext,uniphier-reset.yaml#
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@57920000 {
+ compatible = "socionext,uniphier-ld20-adamv",
+ "simple-mfd", "syscon";
+ reg = <0x57920000 0x1000>;
+
+ reset-controller {
+ compatible = "socionext,uniphier-ld20-adamv-reset";
+ #reset-cells = <1>;
+ };
+ };
--
2.25.1
Add devicetree binding schema for the media I/O block implemented on
Socionext Uniphier SoCs. This block is implemented on LD4, sLD8, Pro4,
and LD11 SoCs.
Media I/O block implemented on Socionext UniPhier SoCs is an integrated
component of the stream type peripherals including SD, USB2.0, eMMC,
and MIO-DMAC.
Media I/O block has a common logic to control the component.
Signed-off-by: Kunihiko Hayashi <[email protected]>
---
.../socionext/socionext,uniphier-mioctrl.yaml | 67 +++++++++++++++++++
1 file changed, 67 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-mioctrl.yaml
diff --git a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-mioctrl.yaml b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-mioctrl.yaml
new file mode 100644
index 000000000000..b2d7cab10935
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-mioctrl.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-mioctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Socionext UniPhier media I/O block (MIO) controller
+
+maintainers:
+ - Kunihiko Hayashi <[email protected]>
+
+description: |+
+ Media I/O block implemented on Socionext UniPhier SoCs is a legacy
+ integrated component of the stream type peripherals including USB2.0,
+ SD/eMMC, and MIO-DMAC.
+ Media I/O block has a common logic to control the component.
+
+ Recent SoCs have SD interface logic specialized only for SD functions
+ as a subset of media I/O block. See socionext,uniphier-sdctrl.yaml.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - socionext,uniphier-ld4-mioctrl
+ - socionext,uniphier-pro4-mioctrl
+ - socionext,uniphier-sld8-mioctrl
+ - socionext,uniphier-ld11-mioctrl
+ - socionext,uniphier-mioctrl
+ - const: simple-mfd
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+patternProperties:
+ "^clock-controller(@[0-9a-f]+)?$":
+ $ref: /schemas/clock/socionext,uniphier-clock.yaml#
+
+ "^reset-controller(@[0-9a-f]+)?$":
+ $ref: /schemas/reset/socionext,uniphier-reset.yaml#
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@5b3e0000 {
+ compatible = "socionext,uniphier-ld11-mioctrl",
+ "simple-mfd", "syscon";
+ reg = <0x5b3e0000 0x800>;
+
+ clock-controller {
+ compatible = "socionext,uniphier-ld11-mio-clock";
+ #clock-cells = <1>;
+ };
+
+ reset-controller {
+ compatible = "socionext,uniphier-ld11-mio-reset";
+ #reset-cells = <1>;
+ resets = <&sys_rst 7>;
+ };
+ };
+
--
2.25.1
Add devicetree binding schema for the peripheral block implemented on
Socionext Uniphier SoCs.
Peripheral block implemented on Socionext UniPhier SoCs is an integrated
component of the peripherals including UART, I2C/FI2C, and SCSSI.
Peripheral block has some function logics to control the component.
Signed-off-by: Kunihiko Hayashi <[email protected]>
---
.../socionext,uniphier-perictrl.yaml | 67 +++++++++++++++++++
1 file changed, 67 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml
diff --git a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml
new file mode 100644
index 000000000000..080b6ab3ea1a
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-perictrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Socionext UniPhier peripheral block controller
+
+maintainers:
+ - Kunihiko Hayashi <[email protected]>
+
+description: |+
+ Peripheral block implemented on Socionext UniPhier SoCs is an integrated
+ component of the peripherals including UART, I2C/FI2C, and SCSSI.
+ Peripheral block controller is a logic to control the component.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - socionext,uniphier-ld4-perictrl
+ - socionext,uniphier-pro4-perictrl
+ - socionext,uniphier-pro5-perictrl
+ - socionext,uniphier-pxs2-perictrl
+ - socionext,uniphier-ld6b-perictrl
+ - socionext,uniphier-sld8-perictrl
+ - socionext,uniphier-ld11-perictrl
+ - socionext,uniphier-ld20-perictrl
+ - socionext,uniphier-pxs3-perictrl
+ - socionext,uniphier-nx1-perictrl
+ - socionext,uniphier-perictrl
+ - const: simple-mfd
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+patternProperties:
+ "^clock-controller(@[0-9a-f]+)?$":
+ $ref: /schemas/clock/socionext,uniphier-clock.yaml#
+
+ "^reset-controller(@[0-9a-f]+)?$":
+ $ref: /schemas/reset/socionext,uniphier-reset.yaml#
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon@59820000 {
+ compatible = "socionext,uniphier-ld20-perictrl",
+ "simple-mfd", "syscon";
+ reg = <0x59820000 0x200>;
+
+ clock-controller {
+ compatible = "socionext,uniphier-ld20-peri-clock";
+ #clock-cells = <1>;
+ };
+
+ reset-controller {
+ compatible = "socionext,uniphier-ld20-peri-reset";
+ #reset-cells = <1>;
+ };
+ };
--
2.25.1
On Tue, 29 Nov 2022 19:35:04 +0900, Kunihiko Hayashi wrote:
> Add devicetree binding schema for the peripheral block implemented on
> Socionext Uniphier SoCs.
>
> Peripheral block implemented on Socionext UniPhier SoCs is an integrated
> component of the peripherals including UART, I2C/FI2C, and SCSSI.
>
> Peripheral block has some function logics to control the component.
>
> Signed-off-by: Kunihiko Hayashi <[email protected]>
> ---
> .../socionext,uniphier-perictrl.yaml | 67 +++++++++++++++++++
> 1 file changed, 67 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/reset/socionext,uniphier-reset.example.dtb: perictrl@59820000: 'reset' does not match any of the regexes: '^clock-controller(@[0-9a-f]+)?$', '^reset-controller(@[0-9a-f]+)?$', 'pinctrl-[0-9]+'
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/socionext,uniphier-clock.example.dtb: perictrl@59820000: 'clock' does not match any of the regexes: '^clock-controller(@[0-9a-f]+)?$', '^reset-controller(@[0-9a-f]+)?$', 'pinctrl-[0-9]+'
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command.
On Tue, 29 Nov 2022 19:35:07 +0900, Kunihiko Hayashi wrote:
> Add devicetree binding schema for the ADAMV block implemented on Socionext
> Uniphier SoCs.
>
> The ADAMV block is analog signal amplifier that is a part of the external
> video and audio I/O system. This block is implemented on LD11 and LD20,
> and this is defined for controlling audio I/O reset only.
>
> Signed-off-by: Kunihiko Hayashi <[email protected]>
> ---
> .../socionext/socionext,uniphier-adamv.yaml | 52 +++++++++++++++++++
> 1 file changed, 52 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-adamv.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/reset/socionext,uniphier-reset.example.dtb: adamv@57920000: 'reset' does not match any of the regexes: '^reset-controller(@[0-9a-f]+)?$', 'pinctrl-[0-9]+'
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-adamv.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command.
On Tue, 29 Nov 2022 19:35:05 +0900, Kunihiko Hayashi wrote:
> Add devicetree binding schema for the media I/O block implemented on
> Socionext Uniphier SoCs. This block is implemented on LD4, sLD8, Pro4,
> and LD11 SoCs.
>
> Media I/O block implemented on Socionext UniPhier SoCs is an integrated
> component of the stream type peripherals including SD, USB2.0, eMMC,
> and MIO-DMAC.
>
> Media I/O block has a common logic to control the component.
>
> Signed-off-by: Kunihiko Hayashi <[email protected]>
> ---
> .../socionext/socionext,uniphier-mioctrl.yaml | 67 +++++++++++++++++++
> 1 file changed, 67 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-mioctrl.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/reset/socionext,uniphier-reset.example.dtb: mioctrl@59810000: 'reset' does not match any of the regexes: '^clock-controller(@[0-9a-f]+)?$', '^reset-controller(@[0-9a-f]+)?$', 'pinctrl-[0-9]+'
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-mioctrl.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/socionext,uniphier-clock.example.dtb: mioctrl@59810000: 'clock' does not match any of the regexes: '^clock-controller(@[0-9a-f]+)?$', '^reset-controller(@[0-9a-f]+)?$', 'pinctrl-[0-9]+'
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-mioctrl.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command.
On Tue, 29 Nov 2022 19:35:08 +0900, Kunihiko Hayashi wrote:
> Add DT binding schema for components belonging to the platform-specific
> DWC3 USB glue layer implemented in UniPhier SoCs.
>
> This USB glue layer works as a sideband logic for the host controller,
> including core reset, vbus control, PHYs, and some signals to the
> controller.
>
> Signed-off-by: Kunihiko Hayashi <[email protected]>
> ---
> .../socionext,uniphier-dwc3-glue.yaml | 106 ++++++++++++++++++
> 1 file changed, 106 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.example.dtb: usb-glue@65b00000: 'reg' is a required property
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.example.dtb: usb-glue@65b00000: 'ss-phy@300' does not match any of the regexes: '^phy@[0-9a-f]+$', '^regulator@[0-9a-f]+$', '^reset-controller@[0-9a-f]+$', 'pinctrl-[0-9]+'
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.example.dtb: usb-glue@65b00000: 'reg' is a required property
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.example.dtb: usb-glue@65b00000: 'hs-phy@200' does not match any of the regexes: '^phy@[0-9a-f]+$', '^regulator@[0-9a-f]+$', '^reset-controller@[0-9a-f]+$', 'pinctrl-[0-9]+'
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command.
On Tue, 29 Nov 2022 19:35:09 +0900, Kunihiko Hayashi wrote:
> Add DT binding schema for components belonging to the platform-specific
> AHCI glue layer implemented in UniPhier SoCs.
>
> This AHCI glue layer works as a sideband logic for the host controller,
> including core reset, PHYs, and some signals to the controller.
>
> Signed-off-by: Kunihiko Hayashi <[email protected]>
> ---
> .../socionext,uniphier-ahci-glue.yaml | 78 +++++++++++++++++++
> 1 file changed, 78 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-ahci-glue.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.example.dtb: ahci-glue@65700000: 'reg' is a required property
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-ahci-glue.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command.
On 29/11/2022 11:35, Kunihiko Hayashi wrote:
> Add devicetree binding schema for the SoC-glue logic implemented on
> Socionext Uniphier SoCs.
>
> This SoC-glue logic is a set of miscellaneous function registers
> handling signals for specific devices outside system components,
> and also has multiple functions such as I/O pinmux, usb-phy, debug,
> clock-mux for a specific SoC, and so on.
>
> Signed-off-by: Kunihiko Hayashi <[email protected]>
> ---
> .../socionext,uniphier-soc-glue.yaml | 94 +++++++++++++++++++
> 1 file changed, 94 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue.yaml
>
> diff --git a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue.yaml b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue.yaml
> new file mode 100644
> index 000000000000..3f571e3e1339
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue.yaml
> @@ -0,0 +1,94 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Socionext UniPhier SoC-glue logic
> +
> +maintainers:
> + - Kunihiko Hayashi <[email protected]>
> +
> +description: |+
> + SoC-glue logic implemented on Socionext UniPhier SoCs is a collection of
> + miscellaneous function registers handling signals outside system components.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - socionext,uniphier-ld4-soc-glue
> + - socionext,uniphier-pro4-soc-glue
> + - socionext,uniphier-pro5-soc-glue
> + - socionext,uniphier-pxs2-soc-glue
> + - socionext,uniphier-ld6b-soc-glue
> + - socionext,uniphier-sld8-soc-glue
> + - socionext,uniphier-ld11-soc-glue
> + - socionext,uniphier-ld20-soc-glue
> + - socionext,uniphier-pxs3-soc-glue
> + - socionext,uniphier-nx1-soc-glue
> + - socionext,uniphier-soc-glue
This one looks generic - why having it next to specific ones?
Same question for your previous patch - socionext,uniphier-sysctrl.
And similarly to previous patch, do you expect child nodes everywhere?
> + - const: simple-mfd
> + - const: syscon
> +
> + reg:
> + maxItems: 1
> +
> +patternProperties:
> + "^pinctrl(@[0-9a-f]+)?$":
> + $ref: /schemas/pinctrl/socionext,uniphier-pinctrl.yaml#
> +
> + "^usb-controller(@[0-9a-f]+)?$":
> + $ref: /schemas/phy/socionext,uniphier-usb2-phy.yaml#
> +
> + "^clock-controller(@[0-9a-f]+)?$":
> + $ref: /schemas/clock/socionext,uniphier-clock.yaml#
> +
Best regards,
Krzysztof
On 29/11/2022 11:35, Kunihiko Hayashi wrote:
> Add DT binding schema for components belonging to the platform-specific
> DWC3 USB glue layer implemented in UniPhier SoCs.
>
> This USB glue layer works as a sideband logic for the host controller,
> including core reset, vbus control, PHYs, and some signals to the
> controller.
>
> Signed-off-by: Kunihiko Hayashi <[email protected]>
> ---
> .../socionext,uniphier-dwc3-glue.yaml | 106 ++++++++++++++++++
> 1 file changed, 106 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml
>
> diff --git a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml
> new file mode 100644
> index 000000000000..66f8786dd305
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml
> @@ -0,0 +1,106 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-dwc3-glue.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Socionext UniPhier SoC DWC3 USB3.0 glue layer
> +
> +maintainers:
> + - Kunihiko Hayashi <[email protected]>
> +
> +description: |+
> + DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is
> + a sideband logic handling signals to DWC3 host controller inside
> + USB3.0 component.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - socionext,uniphier-pro4-dwc3-glue
> + - socionext,uniphier-pro5-dwc3-glue
> + - socionext,uniphier-pxs2-dwc3-glue
> + - socionext,uniphier-ld20-dwc3-glue
> + - socionext,uniphier-pxs3-dwc3-glue
> + - socionext,uniphier-nx1-dwc3-glue
> + - const: simple-mfd
> +
> + reg:
> + maxItems: 1
> +
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 1
> +
> + ranges: true
> +
> +patternProperties:
> + "^reset-controller@[0-9a-f]+$":
> + $ref: /schemas/reset/socionext,uniphier-glue-reset.yaml#
> +
> + "^regulator@[0-9a-f]+$":
> + $ref: /schemas/regulator/socionext,uniphier-regulator.yaml#
> +
> + "^phy@[0-9a-f]+$":
> + oneOf:
> + - $ref: /schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
> + - $ref: /schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + usb-controller@65b00000 {
Node name: usb. There is no usage of "usb-controller".
> + compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd";
> + reg = <0x65b00000 0x400>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x65b00000 0x400>;
> +
> + reset-controller@0 {
> + compatible = "socionext,uniphier-ld20-usb3-reset";
> + reg = <0x0 0x4>;
So now I see the unit addresses, which means none of your previous
patches needed them. This raises next question - why this device is
special and does not use syscon but own unit address?
Are the children here - regulator, reset controller and phys - related
to the USB?
Best regards,
Krzysztof
On 29/11/2022 11:35, Kunihiko Hayashi wrote:
> Add devicetree binding schema for the peripheral block implemented on
> Socionext Uniphier SoCs.
>
> Peripheral block implemented on Socionext UniPhier SoCs is an integrated
> component of the peripherals including UART, I2C/FI2C, and SCSSI.
>
> Peripheral block has some function logics to control the component.
>
> Signed-off-by: Kunihiko Hayashi <[email protected]>
> ---
> .../socionext,uniphier-perictrl.yaml | 67 +++++++++++++++++++
> 1 file changed, 67 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml
> new file mode 100644
> index 000000000000..080b6ab3ea1a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml
> @@ -0,0 +1,67 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-perictrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Socionext UniPhier peripheral block controller
> +
> +maintainers:
> + - Kunihiko Hayashi <[email protected]>
> +
> +description: |+
> + Peripheral block implemented on Socionext UniPhier SoCs is an integrated
> + component of the peripherals including UART, I2C/FI2C, and SCSSI.
> + Peripheral block controller is a logic to control the component.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - socionext,uniphier-ld4-perictrl
> + - socionext,uniphier-pro4-perictrl
> + - socionext,uniphier-pro5-perictrl
> + - socionext,uniphier-pxs2-perictrl
> + - socionext,uniphier-ld6b-perictrl
> + - socionext,uniphier-sld8-perictrl
> + - socionext,uniphier-ld11-perictrl
> + - socionext,uniphier-ld20-perictrl
> + - socionext,uniphier-pxs3-perictrl
> + - socionext,uniphier-nx1-perictrl
> + - socionext,uniphier-perictrl
> + - const: simple-mfd
> + - const: syscon
> +
> + reg:
> + maxItems: 1
> +
> +patternProperties:
> + "^clock-controller(@[0-9a-f]+)?$":
> + $ref: /schemas/clock/socionext,uniphier-clock.yaml#
> +
> + "^reset-controller(@[0-9a-f]+)?$":
> + $ref: /schemas/reset/socionext,uniphier-reset.yaml#
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + syscon@59820000 {
> + compatible = "socionext,uniphier-ld20-perictrl",
> + "simple-mfd", "syscon";
> + reg = <0x59820000 0x200>;
> +
> + clock-controller {
None of your children in examples and in DTS have unit addresses.
However you explicitly mentioned them in the patternProperties. Do you
expect adding unit addresses?
Best regards,
Krzysztof
Hi Krzysztof,
On 2022/11/29 23:52, Krzysztof Kozlowski wrote:
> On 29/11/2022 11:35, Kunihiko Hayashi wrote:
>> Add DT binding schema for components belonging to the platform-specific
>> DWC3 USB glue layer implemented in UniPhier SoCs.
>>
>> This USB glue layer works as a sideband logic for the host controller,
>> including core reset, vbus control, PHYs, and some signals to the
>> controller.
>>
>> Signed-off-by: Kunihiko Hayashi <[email protected]>
>> ---
>> .../socionext,uniphier-dwc3-glue.yaml | 106 ++++++++++++++++++
>> 1 file changed, 106 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml
>>
>> diff --git
>> a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml
>> b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml
>> new file mode 100644
>> index 000000000000..66f8786dd305
>> --- /dev/null
>> +++
>> b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml
>> @@ -0,0 +1,106 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id:
>> http://devicetree.org/schemas/soc/socionext/socionext,uniphier-dwc3-glue.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Socionext UniPhier SoC DWC3 USB3.0 glue layer
>> +
>> +maintainers:
>> + - Kunihiko Hayashi <[email protected]>
>> +
>> +description: |+
>> + DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is
>> + a sideband logic handling signals to DWC3 host controller inside
>> + USB3.0 component.
>> +
>> +properties:
>> + compatible:
>> + items:
>> + - enum:
>> + - socionext,uniphier-pro4-dwc3-glue
>> + - socionext,uniphier-pro5-dwc3-glue
>> + - socionext,uniphier-pxs2-dwc3-glue
>> + - socionext,uniphier-ld20-dwc3-glue
>> + - socionext,uniphier-pxs3-dwc3-glue
>> + - socionext,uniphier-nx1-dwc3-glue
>> + - const: simple-mfd
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + '#address-cells':
>> + const: 1
>> +
>> + '#size-cells':
>> + const: 1
>> +
>> + ranges: true
>> +
>> +patternProperties:
>> + "^reset-controller@[0-9a-f]+$":
>> + $ref: /schemas/reset/socionext,uniphier-glue-reset.yaml#
>> +
>> + "^regulator@[0-9a-f]+$":
>> + $ref: /schemas/regulator/socionext,uniphier-regulator.yaml#
>> +
>> + "^phy@[0-9a-f]+$":
>> + oneOf:
>> + - $ref: /schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
>> + - $ref: /schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
>> +
>> +required:
>> + - compatible
>> + - reg
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + usb-controller@65b00000 {
>
> Node name: usb. There is no usage of "usb-controller".
I'm confusing about that.
This is an interface logic and doesn't have USB functions by itself.
Surely there is a USB host controller node "usb@..." in the same SoC.
Can this node be renamed to "usb"?
I've renamed the dts node name once in commit 4cc752a88ca9
("arm64: dts: uniphier: Rename usb-glue node for USB3 to usb-controller").
>> + compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd";
>> + reg = <0x65b00000 0x400>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0 0x65b00000 0x400>;
>> +
>> + reset-controller@0 {
>> + compatible = "socionext,uniphier-ld20-usb3-reset";
>> + reg = <0x0 0x4>;
>
> So now I see the unit addresses, which means none of your previous
> patches needed them. This raises next question - why this device is
> special and does not use syscon but own unit address?
The glue layer has a fixed register address for each child unlike
the previous patch.
This layer has also the other registers for USB core outside
the child nodes, however, there is no parent device that manages
these registers, so this layer node itself should take care of these
registers.
> Are the children here - regulator, reset controller and phys - related
> to the USB?
Yes, this "glue layer" is an interface of the USB controller, so these
children are only used for the USB controller.
Thank you,
---
Best Regards
Kunihiko Hayashi
Hi Krzysztof,
On 2022/11/29 23:43, Krzysztof Kozlowski wrote:
> On 29/11/2022 11:35, Kunihiko Hayashi wrote:
>> Add devicetree binding schema for the SoC-glue logic implemented on
>> Socionext Uniphier SoCs.
>>
>> This SoC-glue logic is a set of miscellaneous function registers
>> handling signals for specific devices outside system components,
>> and also has multiple functions such as I/O pinmux, usb-phy, debug,
>> clock-mux for a specific SoC, and so on.
>>
>> Signed-off-by: Kunihiko Hayashi <[email protected]>
>> ---
>> .../socionext,uniphier-soc-glue.yaml | 94 +++++++++++++++++++
>> 1 file changed, 94 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue.yaml
>>
>> diff --git
>> a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue.yaml
>> b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue.yaml
>> new file mode 100644
>> index 000000000000..3f571e3e1339
>> --- /dev/null
>> +++
>> b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue.yaml
>> @@ -0,0 +1,94 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id:
>> http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Socionext UniPhier SoC-glue logic
>> +
>> +maintainers:
>> + - Kunihiko Hayashi <[email protected]>
>> +
>> +description: |+
>> + SoC-glue logic implemented on Socionext UniPhier SoCs is a collection
>> of
>> + miscellaneous function registers handling signals outside system
>> components.
>> +
>> +properties:
>> + compatible:
>> + items:
>> + - enum:
>> + - socionext,uniphier-ld4-soc-glue
>> + - socionext,uniphier-pro4-soc-glue
>> + - socionext,uniphier-pro5-soc-glue
>> + - socionext,uniphier-pxs2-soc-glue
>> + - socionext,uniphier-ld6b-soc-glue
>> + - socionext,uniphier-sld8-soc-glue
>> + - socionext,uniphier-ld11-soc-glue
>> + - socionext,uniphier-ld20-soc-glue
>> + - socionext,uniphier-pxs3-soc-glue
>> + - socionext,uniphier-nx1-soc-glue
>> + - socionext,uniphier-soc-glue
>
> This one looks generic - why having it next to specific ones?
SoC-glue has the same register set, but different implementations
for each SoC.
I thought of defining the same register set as a common specs,
but each compatibles are sufficient. I'll remove it.
> Same question for your previous patch - socionext,uniphier-sysctrl.
>
> And similarly to previous patch, do you expect child nodes everywhere?
In case of this SoC-glue logic, all SoCs has pinctrl, however,
only SoCs with USB2 host has usb-controller (phy-hub).
And only legacy SoCs implement clock-controller (clk-mux) here.
Should child nodes that exist only in a specific "compatible" be defined
conditionally?
>> + - const: simple-mfd
>> + - const: syscon
>> +
>> + reg:
>> + maxItems: 1
>> +
>> +patternProperties:
>> + "^pinctrl(@[0-9a-f]+)?$":
>> + $ref: /schemas/pinctrl/socionext,uniphier-pinctrl.yaml#
>> +
>> + "^usb-controller(@[0-9a-f]+)?$":
>> + $ref: /schemas/phy/socionext,uniphier-usb2-phy.yaml#
>> +
>> + "^clock-controller(@[0-9a-f]+)?$":
>> + $ref: /schemas/clock/socionext,uniphier-clock.yaml#
>> +
Thank you,
---
Best Regards
Kunihiko Hayashi
Hi Krzysztof,
On 2022/11/29 23:46, Krzysztof Kozlowski wrote:
> On 29/11/2022 11:35, Kunihiko Hayashi wrote:
>> Add devicetree binding schema for the peripheral block implemented on
>> Socionext Uniphier SoCs.
>>
>> Peripheral block implemented on Socionext UniPhier SoCs is an integrated
>> component of the peripherals including UART, I2C/FI2C, and SCSSI.
>>
>> Peripheral block has some function logics to control the component.
>>
>> Signed-off-by: Kunihiko Hayashi <[email protected]>
>> ---
>> .../socionext,uniphier-perictrl.yaml | 67 +++++++++++++++++++
>> 1 file changed, 67 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml
>>
>> diff --git
>> a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml
>> b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml
>> new file mode 100644
>> index 000000000000..080b6ab3ea1a
>> --- /dev/null
>> +++
>> b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-perictrl.yaml
>> @@ -0,0 +1,67 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id:
>> http://devicetree.org/schemas/soc/socionext/socionext,uniphier-perictrl.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Socionext UniPhier peripheral block controller
>> +
>> +maintainers:
>> + - Kunihiko Hayashi <[email protected]>
>> +
>> +description: |+
>> + Peripheral block implemented on Socionext UniPhier SoCs is an
>> integrated
>> + component of the peripherals including UART, I2C/FI2C, and SCSSI.
>> + Peripheral block controller is a logic to control the component.
>> +
>> +properties:
>> + compatible:
>> + items:
>> + - enum:
>> + - socionext,uniphier-ld4-perictrl
>> + - socionext,uniphier-pro4-perictrl
>> + - socionext,uniphier-pro5-perictrl
>> + - socionext,uniphier-pxs2-perictrl
>> + - socionext,uniphier-ld6b-perictrl
>> + - socionext,uniphier-sld8-perictrl
>> + - socionext,uniphier-ld11-perictrl
>> + - socionext,uniphier-ld20-perictrl
>> + - socionext,uniphier-pxs3-perictrl
>> + - socionext,uniphier-nx1-perictrl
>> + - socionext,uniphier-perictrl
>> + - const: simple-mfd
>> + - const: syscon
>> +
>> + reg:
>> + maxItems: 1
>> +
>> +patternProperties:
>> + "^clock-controller(@[0-9a-f]+)?$":
>> + $ref: /schemas/clock/socionext,uniphier-clock.yaml#
>> +
>> + "^reset-controller(@[0-9a-f]+)?$":
>> + $ref: /schemas/reset/socionext,uniphier-reset.yaml#
>> +
>> +required:
>> + - compatible
>> + - reg
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + syscon@59820000 {
>> + compatible = "socionext,uniphier-ld20-perictrl",
>> + "simple-mfd", "syscon";
>> + reg = <0x59820000 0x200>;
>> +
>> + clock-controller {
>
> None of your children in examples and in DTS have unit addresses.
> However you explicitly mentioned them in the patternProperties. Do you
> expect adding unit addresses?
Currently, children's registers are partially mixed and it's hard
to specify the unit address.
The address pattern was added as option for the future, however,
not needed for the current implementation. I'll remove them in next.
Thank you,
---
Best Regards
Kunihiko Hayashi
On 30/11/2022 09:59, Kunihiko Hayashi wrote:
> Hi Krzysztof,
>
> On 2022/11/29 23:43, Krzysztof Kozlowski wrote:
>> On 29/11/2022 11:35, Kunihiko Hayashi wrote:
>>> Add devicetree binding schema for the SoC-glue logic implemented on
>>> Socionext Uniphier SoCs.
>>>
>>> This SoC-glue logic is a set of miscellaneous function registers
>>> handling signals for specific devices outside system components,
>>> and also has multiple functions such as I/O pinmux, usb-phy, debug,
>>> clock-mux for a specific SoC, and so on.
>>>
>>> Signed-off-by: Kunihiko Hayashi <[email protected]>
>>> ---
>>> .../socionext,uniphier-soc-glue.yaml | 94 +++++++++++++++++++
>>> 1 file changed, 94 insertions(+)
>>> create mode 100644
>>> Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue.yaml
>>>
>>> diff --git
>>> a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue.yaml
>>> b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue.yaml
>>> new file mode 100644
>>> index 000000000000..3f571e3e1339
>>> --- /dev/null
>>> +++
>>> b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue.yaml
>>> @@ -0,0 +1,94 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id:
>>> http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Socionext UniPhier SoC-glue logic
>>> +
>>> +maintainers:
>>> + - Kunihiko Hayashi <[email protected]>
>>> +
>>> +description: |+
>>> + SoC-glue logic implemented on Socionext UniPhier SoCs is a collection
>>> of
>>> + miscellaneous function registers handling signals outside system
>>> components.
>>> +
>>> +properties:
>>> + compatible:
>>> + items:
>>> + - enum:
>>> + - socionext,uniphier-ld4-soc-glue
>>> + - socionext,uniphier-pro4-soc-glue
>>> + - socionext,uniphier-pro5-soc-glue
>>> + - socionext,uniphier-pxs2-soc-glue
>>> + - socionext,uniphier-ld6b-soc-glue
>>> + - socionext,uniphier-sld8-soc-glue
>>> + - socionext,uniphier-ld11-soc-glue
>>> + - socionext,uniphier-ld20-soc-glue
>>> + - socionext,uniphier-pxs3-soc-glue
>>> + - socionext,uniphier-nx1-soc-glue
>>> + - socionext,uniphier-soc-glue
>>
>> This one looks generic - why having it next to specific ones?
>
> SoC-glue has the same register set, but different implementations
> for each SoC.
Sure, but you did not model it as a compatible fallback, but like one of
variants. It is not tied to specific SoC, thus too generic.
> I thought of defining the same register set as a common specs,
> but each compatibles are sufficient. I'll remove it.
>
>> Same question for your previous patch - socionext,uniphier-sysctrl.
>>
>> And similarly to previous patch, do you expect child nodes everywhere?
>
> In case of this SoC-glue logic, all SoCs has pinctrl, however,
> only SoCs with USB2 host has usb-controller (phy-hub).
> And only legacy SoCs implement clock-controller (clk-mux) here.
>
> Should child nodes that exist only in a specific "compatible" be defined
> conditionally?
No, rather define them in top level but disallow for specific compatibles:
allOf:
- if:
....
then:
patternProperties:
...: false
Assuming that this does not over-complicate schema.
Best regards,
Krzysztof
On 30/11/2022 10:00, Kunihiko Hayashi wrote:
> Hi Krzysztof,
>
> On 2022/11/29 23:52, Krzysztof Kozlowski wrote:
>> On 29/11/2022 11:35, Kunihiko Hayashi wrote:
>>> Add DT binding schema for components belonging to the platform-specific
>>> DWC3 USB glue layer implemented in UniPhier SoCs.
>>>
>>> This USB glue layer works as a sideband logic for the host controller,
>>> including core reset, vbus control, PHYs, and some signals to the
>>> controller.
>>>
>>> Signed-off-by: Kunihiko Hayashi <[email protected]>
>>> ---
>>> .../socionext,uniphier-dwc3-glue.yaml | 106 ++++++++++++++++++
>>> 1 file changed, 106 insertions(+)
>>> create mode 100644
>>> Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml
>>>
>>> diff --git
>>> a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml
>>> b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml
>>> new file mode 100644
>>> index 000000000000..66f8786dd305
>>> --- /dev/null
>>> +++
>>> b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-dwc3-glue.yaml
>>> @@ -0,0 +1,106 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id:
>>> http://devicetree.org/schemas/soc/socionext/socionext,uniphier-dwc3-glue.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Socionext UniPhier SoC DWC3 USB3.0 glue layer
>>> +
>>> +maintainers:
>>> + - Kunihiko Hayashi <[email protected]>
>>> +
>>> +description: |+
>>> + DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is
>>> + a sideband logic handling signals to DWC3 host controller inside
>>> + USB3.0 component.
>>> +
>>> +properties:
>>> + compatible:
>>> + items:
>>> + - enum:
>>> + - socionext,uniphier-pro4-dwc3-glue
>>> + - socionext,uniphier-pro5-dwc3-glue
>>> + - socionext,uniphier-pxs2-dwc3-glue
>>> + - socionext,uniphier-ld20-dwc3-glue
>>> + - socionext,uniphier-pxs3-dwc3-glue
>>> + - socionext,uniphier-nx1-dwc3-glue
>>> + - const: simple-mfd
>>> +
>>> + reg:
>>> + maxItems: 1
>>> +
>>> + '#address-cells':
>>> + const: 1
>>> +
>>> + '#size-cells':
>>> + const: 1
>>> +
>>> + ranges: true
>>> +
>>> +patternProperties:
>>> + "^reset-controller@[0-9a-f]+$":
>>> + $ref: /schemas/reset/socionext,uniphier-glue-reset.yaml#
>>> +
>>> + "^regulator@[0-9a-f]+$":
>>> + $ref: /schemas/regulator/socionext,uniphier-regulator.yaml#
>>> +
>>> + "^phy@[0-9a-f]+$":
>>> + oneOf:
>>> + - $ref: /schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
>>> + - $ref: /schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
>>> +
>>> +required:
>>> + - compatible
>>> + - reg
>>> +
>>> +additionalProperties: false
>>> +
>>> +examples:
>>> + - |
>>> + usb-controller@65b00000 {
>>
>> Node name: usb. There is no usage of "usb-controller".
>
> I'm confusing about that.
>
> This is an interface logic and doesn't have USB functions by itself.
> Surely there is a USB host controller node "usb@..." in the same SoC.
> Can this node be renamed to "usb"?
>
> I've renamed the dts node name once in commit 4cc752a88ca9
> ("arm64: dts: uniphier: Rename usb-glue node for USB3 to usb-controller").
In (almost?) all other cases it is still called "usb". A bit akward to
have usb in usb, but usb-controller did not stick...
>
>>> + compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd";
>>> + reg = <0x65b00000 0x400>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges = <0 0x65b00000 0x400>;
>>> +
>>> + reset-controller@0 {
>>> + compatible = "socionext,uniphier-ld20-usb3-reset";
>>> + reg = <0x0 0x4>;
>>
>> So now I see the unit addresses, which means none of your previous
>> patches needed them. This raises next question - why this device is
>> special and does not use syscon but own unit address?
>
> The glue layer has a fixed register address for each child unlike
> the previous patch.
>
> This layer has also the other registers for USB core outside
> the child nodes, however, there is no parent device that manages
> these registers, so this layer node itself should take care of these
> registers.
>
>> Are the children here - regulator, reset controller and phys - related
>> to the USB?
>
> Yes, this "glue layer" is an interface of the USB controller, so these
> children are only used for the USB controller.
OK
Best regards,
Krzysztof
On 2022/12/01 0:27, Krzysztof Kozlowski wrote:
> On 30/11/2022 09:59, Kunihiko Hayashi wrote:
>> Hi Krzysztof,
>>
>> On 2022/11/29 23:43, Krzysztof Kozlowski wrote:
>>> On 29/11/2022 11:35, Kunihiko Hayashi wrote:
>>>> Add devicetree binding schema for the SoC-glue logic implemented on
>>>> Socionext Uniphier SoCs.
>>>>
>>>> This SoC-glue logic is a set of miscellaneous function registers
>>>> handling signals for specific devices outside system components,
>>>> and also has multiple functions such as I/O pinmux, usb-phy, debug,
>>>> clock-mux for a specific SoC, and so on.
>>>>
>>>> Signed-off-by: Kunihiko Hayashi <[email protected]>
>>>> ---
>>>> .../socionext,uniphier-soc-glue.yaml | 94 +++++++++++++++++++
>>>> 1 file changed, 94 insertions(+)
>>>> create mode 100644
>>>> Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue.yaml
>>>>
>>>> diff --git
>>>> a/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue.yaml
>>>> b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue.yaml
>>>> new file mode 100644
>>>> index 000000000000..3f571e3e1339
>>>> --- /dev/null
>>>> +++
>>>> b/Documentation/devicetree/bindings/soc/socionext/socionext,uniphier-soc-glue.yaml
>>>> @@ -0,0 +1,94 @@
>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>> +%YAML 1.2
>>>> +---
>>>> +$id:
>>>> http://devicetree.org/schemas/soc/socionext/socionext,uniphier-soc-glue.yaml#
>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>> +
>>>> +title: Socionext UniPhier SoC-glue logic
>>>> +
>>>> +maintainers:
>>>> + - Kunihiko Hayashi <[email protected]>
>>>> +
>>>> +description: |+
>>>> + SoC-glue logic implemented on Socionext UniPhier SoCs is a collection
>>>> of
>>>> + miscellaneous function registers handling signals outside system
>>>> components.
>>>> +
>>>> +properties:
>>>> + compatible:
>>>> + items:
>>>> + - enum:
>>>> + - socionext,uniphier-ld4-soc-glue
>>>> + - socionext,uniphier-pro4-soc-glue
>>>> + - socionext,uniphier-pro5-soc-glue
>>>> + - socionext,uniphier-pxs2-soc-glue
>>>> + - socionext,uniphier-ld6b-soc-glue
>>>> + - socionext,uniphier-sld8-soc-glue
>>>> + - socionext,uniphier-ld11-soc-glue
>>>> + - socionext,uniphier-ld20-soc-glue
>>>> + - socionext,uniphier-pxs3-soc-glue
>>>> + - socionext,uniphier-nx1-soc-glue
>>>> + - socionext,uniphier-soc-glue
>>>
>>> This one looks generic - why having it next to specific ones?
>>
>> SoC-glue has the same register set, but different implementations
>> for each SoC.
>
> Sure, but you did not model it as a compatible fallback, but like one of
> variants. It is not tied to specific SoC, thus too generic.
I understand. It should be placed in parallel with enum.
item:
- enum:
- ...
- ...
- const: socionext,uniphier-soc-glue
>> I thought of defining the same register set as a common specs,
>> but each compatibles are sufficient. I'll remove it.
So currently drop it.
>>
>>> Same question for your previous patch - socionext,uniphier-sysctrl.
>>>
>>> And similarly to previous patch, do you expect child nodes everywhere?
>>
>> In case of this SoC-glue logic, all SoCs has pinctrl, however,
>> only SoCs with USB2 host has usb-controller (phy-hub).
>> And only legacy SoCs implement clock-controller (clk-mux) here.
>>
>> Should child nodes that exist only in a specific "compatible" be defined
>> conditionally?
>
> No, rather define them in top level but disallow for specific compatibles:
>
> allOf:
> - if:
> ....
> then:
> patternProperties:
> ...: false
>
> Assuming that this does not over-complicate schema.
OK. Some properties are applied for a few compatibles, so I think it is
available to use "else:".
allOf:
- if:
...
else:
patternProperties:
...: false
Thank you,
---
Best Regards
Kunihiko Hayashi
On 2022/12/01 0:32, Krzysztof Kozlowski wrote:
> On 30/11/2022 10:00, Kunihiko Hayashi wrote:
>> Hi Krzysztof,
>>
>> On 2022/11/29 23:52, Krzysztof Kozlowski wrote:
>>> On 29/11/2022 11:35, Kunihiko Hayashi wrote:
>>>> Add DT binding schema for components belonging to the platform-specific
>>>> DWC3 USB glue layer implemented in UniPhier SoCs.
>>>>
>>>> This USB glue layer works as a sideband logic for the host controller,
>>>> including core reset, vbus control, PHYs, and some signals to the
>>>> controller.
>>>>
>>>> Signed-off-by: Kunihiko Hayashi <[email protected]>
(snip)
>>>> +examples:
>>>> + - |
>>>> + usb-controller@65b00000 {
>>>
>>> Node name: usb. There is no usage of "usb-controller".
>>
>> I'm confusing about that.
>>
>> This is an interface logic and doesn't have USB functions by itself.
>> Surely there is a USB host controller node "usb@..." in the same SoC.
>> Can this node be renamed to "usb"?
>>
>> I've renamed the dts node name once in commit 4cc752a88ca9
>> ("arm64: dts: uniphier: Rename usb-glue node for USB3 to usb-controller").
>
> In (almost?) all other cases it is still called "usb". A bit akward to
> have usb in usb, but usb-controller did not stick...
I see.
I understand that it is still better to use the generic name "usb"
rather than "usb-controller".
Thank you,
---
Best Regards
Kunihiko Hayashi
Hi Krzysztof,
On 2022/11/29 19:35, Kunihiko Hayashi wrote:
> Add DT binding schema for components belonging to the platform-specific
> AHCI glue layer implemented in UniPhier SoCs.
>
> This AHCI glue layer works as a sideband logic for the host controller,
> including core reset, PHYs, and some signals to the controller.
>
> Signed-off-by: Kunihiko Hayashi <[email protected]>
(snip)
> +examples:
> + - |
> + sata-controller@65700000 {
> + compatible = "socionext,uniphier-pxs3-ahci-glue", "simple-mfd";
> + reg = <0x65b00000 0x400>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x65700000 0x100>;
In PATCH 7/8, you suggested that the node name of "USB glue layer" should
changes to the generic node name "usb@...".
However, in case of this "AHCI glue layer", I can't change "sata-controller"
to the generic node name "sata@...", because ata/sata-common.yaml has pattern
"^sata(@.*)?$", and the changed node matches this pattern unintentionally.
This layer isn't a sata host controller, so it's hard to give a generic name
to this node. I'd like you opinion.
Thank you,
---
Best Regards
Kunihiko Hayashi
On 2022/12/02 21:08, Krzysztof Kozlowski wrote:
> On 01/12/2022 10:30, Kunihiko Hayashi wrote:
>> Hi Krzysztof,
>>
>> On 2022/11/29 19:35, Kunihiko Hayashi wrote:
>>> Add DT binding schema for components belonging to the platform-specific
>>> AHCI glue layer implemented in UniPhier SoCs.
>>>
>>> This AHCI glue layer works as a sideband logic for the host controller,
>>> including core reset, PHYs, and some signals to the controller.
>>>
>>> Signed-off-by: Kunihiko Hayashi <[email protected]>
>>
>> (snip)
>>
>>> +examples:
>>> + - |
>>> + sata-controller@65700000 {
>>> + compatible = "socionext,uniphier-pxs3-ahci-glue", "simple-mfd";
>>> + reg = <0x65b00000 0x400>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges = <0 0x65700000 0x100>;
>>
>> In PATCH 7/8, you suggested that the node name of "USB glue layer" should
>> changes to the generic node name "usb@...".
>>
>> However, in case of this "AHCI glue layer", I can't change
>> "sata-controller"
>> to the generic node name "sata@...", because ata/sata-common.yaml has
>> pattern
>> "^sata(@.*)?$", and the changed node matches this pattern unintentionally.
>>
>> This layer isn't a sata host controller, so it's hard to give a generic
>> name
>> to this node. I'd like you opinion.
>
> Yeah, I think it's fine. We do not have good names for such nodes.
OK, I leave the name for this node.
Thank you,
---
Best Regards
Kunihiko Hayashi
On 01/12/2022 10:30, Kunihiko Hayashi wrote:
> Hi Krzysztof,
>
> On 2022/11/29 19:35, Kunihiko Hayashi wrote:
>> Add DT binding schema for components belonging to the platform-specific
>> AHCI glue layer implemented in UniPhier SoCs.
>>
>> This AHCI glue layer works as a sideband logic for the host controller,
>> including core reset, PHYs, and some signals to the controller.
>>
>> Signed-off-by: Kunihiko Hayashi <[email protected]>
>
> (snip)
>
>> +examples:
>> + - |
>> + sata-controller@65700000 {
>> + compatible = "socionext,uniphier-pxs3-ahci-glue", "simple-mfd";
>> + reg = <0x65b00000 0x400>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0 0x65700000 0x100>;
>
> In PATCH 7/8, you suggested that the node name of "USB glue layer" should
> changes to the generic node name "usb@...".
>
> However, in case of this "AHCI glue layer", I can't change "sata-controller"
> to the generic node name "sata@...", because ata/sata-common.yaml has pattern
> "^sata(@.*)?$", and the changed node matches this pattern unintentionally.
>
> This layer isn't a sata host controller, so it's hard to give a generic name
> to this node. I'd like you opinion.
Yeah, I think it's fine. We do not have good names for such nodes.
Best regards,
Krzysztof