From: Lai Jiangshan <[email protected]>
This patchset uses kvm_vcpu_flush_tlb_guest() instead of kvm_mmu_reset_context()
when X86_CR4_PGE is changed or X86_CR4_PCIDE is changed 1->0.
Neither X86_CR4_PGE nor X86_CR4_PCIDE participates in kvm_mmu_role, so
kvm_mmu_reset_context() is not required to be invoked. Only flushing tlb
is required as SDM says.
The patchset has nothing to do with performance, because the overheads of
kvm_mmu_reset_context() and kvm_vcpu_flush_tlb_guest() are the same. And
even in the [near] future, kvm_vcpu_flush_tlb_guest() will be optimized,
the code is not in the hot path.
This patchset makes the code more clear when to reset the mmu context.
And it makes KVM_MMU_CR4_ROLE_BITS consistent with kvm_mmu_role.
Lai Jiangshan (2):
KVM: X86: Don't reset mmu context when X86_CR4_PCIDE 1->0
KVM: X86: Don't reset mmu context when toggling X86_CR4_PGE
arch/x86/kvm/mmu.h | 5 ++---
arch/x86/kvm/x86.c | 7 +++++--
2 files changed, 7 insertions(+), 5 deletions(-)
--
2.19.1.6.gb485710b
From: Lai Jiangshan <[email protected]>
X86_CR4_PCIDE doesn't participate in kvm_mmu_role, so the mmu context
doesn't need to be reset. It is only required to flush all the guest
tlb.
Signed-off-by: Lai Jiangshan <[email protected]>
---
arch/x86/kvm/x86.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 86539c1686fa..7494ea0e7922 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -116,6 +116,7 @@ static void enter_smm(struct kvm_vcpu *vcpu);
static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
static void store_regs(struct kvm_vcpu *vcpu);
static int sync_regs(struct kvm_vcpu *vcpu);
+static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu);
static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
@@ -1042,9 +1043,10 @@ EXPORT_SYMBOL_GPL(kvm_is_valid_cr4);
void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4)
{
- if (((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS) ||
- (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
+ if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS)
kvm_mmu_reset_context(vcpu);
+ else if (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))
+ kvm_vcpu_flush_tlb_guest(vcpu);
}
EXPORT_SYMBOL_GPL(kvm_post_set_cr4);
--
2.19.1.6.gb485710b
From: Lai Jiangshan <[email protected]>
X86_CR4_PGE doesn't participate in kvm_mmu_role, so the mmu context
doesn't need to be reset. It is only required to flush all the guest
tlb.
It is also inconsistent that X86_CR4_PGE is in KVM_MMU_CR4_ROLE_BITS
while kvm_mmu_role doesn't use X86_CR4_PGE. So X86_CR4_PGE is also
removed from KVM_MMU_CR4_ROLE_BITS.
Signed-off-by: Lai Jiangshan <[email protected]>
---
arch/x86/kvm/mmu.h | 5 ++---
arch/x86/kvm/x86.c | 3 ++-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h
index 75367af1a6d3..e53ef2ae958f 100644
--- a/arch/x86/kvm/mmu.h
+++ b/arch/x86/kvm/mmu.h
@@ -44,9 +44,8 @@
#define PT32_ROOT_LEVEL 2
#define PT32E_ROOT_LEVEL 3
-#define KVM_MMU_CR4_ROLE_BITS (X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE | \
- X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE | \
- X86_CR4_LA57)
+#define KVM_MMU_CR4_ROLE_BITS (X86_CR4_PSE | X86_CR4_PAE | X86_CR4_LA57 | \
+ X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE)
#define KVM_MMU_CR0_ROLE_BITS (X86_CR0_PG | X86_CR0_WP)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 7494ea0e7922..97772e37e8ee 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1045,7 +1045,8 @@ void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned lon
{
if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS)
kvm_mmu_reset_context(vcpu);
- else if (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))
+ else if (((cr4 ^ old_cr4) & X86_CR4_PGE) ||
+ (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
kvm_vcpu_flush_tlb_guest(vcpu);
}
EXPORT_SYMBOL_GPL(kvm_post_set_cr4);
--
2.19.1.6.gb485710b
Ping
On 2021/9/19 10:42, Lai Jiangshan wrote:
> From: Lai Jiangshan <[email protected]>
>
> This patchset uses kvm_vcpu_flush_tlb_guest() instead of kvm_mmu_reset_context()
> when X86_CR4_PGE is changed or X86_CR4_PCIDE is changed 1->0.
>
> Neither X86_CR4_PGE nor X86_CR4_PCIDE participates in kvm_mmu_role, so
> kvm_mmu_reset_context() is not required to be invoked. Only flushing tlb
> is required as SDM says.
>
> The patchset has nothing to do with performance, because the overheads of
> kvm_mmu_reset_context() and kvm_vcpu_flush_tlb_guest() are the same. And
> even in the [near] future, kvm_vcpu_flush_tlb_guest() will be optimized,
> the code is not in the hot path.
>
> This patchset makes the code more clear when to reset the mmu context.
> And it makes KVM_MMU_CR4_ROLE_BITS consistent with kvm_mmu_role.
>
> Lai Jiangshan (2):
> KVM: X86: Don't reset mmu context when X86_CR4_PCIDE 1->0
> KVM: X86: Don't reset mmu context when toggling X86_CR4_PGE
>
> arch/x86/kvm/mmu.h | 5 ++---
> arch/x86/kvm/x86.c | 7 +++++--
> 2 files changed, 7 insertions(+), 5 deletions(-)
>
On Sun, Sep 19, 2021, Lai Jiangshan wrote:
> From: Lai Jiangshan <[email protected]>
>
> X86_CR4_PCIDE doesn't participate in kvm_mmu_role, so the mmu context
> doesn't need to be reset. It is only required to flush all the guest
> tlb.
>
> Signed-off-by: Lai Jiangshan <[email protected]>
> ---
> arch/x86/kvm/x86.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> index 86539c1686fa..7494ea0e7922 100644
> --- a/arch/x86/kvm/x86.c
> +++ b/arch/x86/kvm/x86.c
> @@ -116,6 +116,7 @@ static void enter_smm(struct kvm_vcpu *vcpu);
> static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
> static void store_regs(struct kvm_vcpu *vcpu);
> static int sync_regs(struct kvm_vcpu *vcpu);
> +static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu);
>
> static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
> static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
> @@ -1042,9 +1043,10 @@ EXPORT_SYMBOL_GPL(kvm_is_valid_cr4);
>
> void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4)
> {
> - if (((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS) ||
> - (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
> + if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS)
> kvm_mmu_reset_context(vcpu);
> + else if (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))
> + kvm_vcpu_flush_tlb_guest(vcpu);
Unless there's a corner case I'm missing, I would prefer this to use
kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu) instead of calling
kvm_vcpu_flush_tlb_guest() directly. The odds of flushes actually being batched
is low, it's more to document that kvm_post_set_cr4() _isn't_ special.
On Sun, Sep 19, 2021, Lai Jiangshan wrote:
> From: Lai Jiangshan <[email protected]>
>
> X86_CR4_PGE doesn't participate in kvm_mmu_role, so the mmu context
> doesn't need to be reset. It is only required to flush all the guest
> tlb.
>
> It is also inconsistent that X86_CR4_PGE is in KVM_MMU_CR4_ROLE_BITS
> while kvm_mmu_role doesn't use X86_CR4_PGE. So X86_CR4_PGE is also
> removed from KVM_MMU_CR4_ROLE_BITS.
>
> Signed-off-by: Lai Jiangshan <[email protected]>
> ---
With the KVM_REQ_TLB_FLUSH_GUEST caveat,
Reviewed-by: Sean Christopherson <[email protected]>
On Thu, Oct 14, 2021, Sean Christopherson wrote:
> On Sun, Sep 19, 2021, Lai Jiangshan wrote:
> > From: Lai Jiangshan <[email protected]>
> >
> > X86_CR4_PCIDE doesn't participate in kvm_mmu_role, so the mmu context
> > doesn't need to be reset. It is only required to flush all the guest
> > tlb.
> >
> > Signed-off-by: Lai Jiangshan <[email protected]>
> > ---
> > arch/x86/kvm/x86.c | 6 ++++--
> > 1 file changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> > index 86539c1686fa..7494ea0e7922 100644
> > --- a/arch/x86/kvm/x86.c
> > +++ b/arch/x86/kvm/x86.c
> > @@ -116,6 +116,7 @@ static void enter_smm(struct kvm_vcpu *vcpu);
> > static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
> > static void store_regs(struct kvm_vcpu *vcpu);
> > static int sync_regs(struct kvm_vcpu *vcpu);
> > +static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu);
> >
> > static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
> > static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
> > @@ -1042,9 +1043,10 @@ EXPORT_SYMBOL_GPL(kvm_is_valid_cr4);
> >
> > void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4)
> > {
> > - if (((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS) ||
> > - (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
> > + if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS)
> > kvm_mmu_reset_context(vcpu);
> > + else if (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE))
> > + kvm_vcpu_flush_tlb_guest(vcpu);
>
> Unless there's a corner case I'm missing, I would prefer this to use
> kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu) instead of calling
> kvm_vcpu_flush_tlb_guest() directly. The odds of flushes actually being batched
> is low, it's more to document that kvm_post_set_cr4() _isn't_ special.
Forgot to say, with the change to KVM_REQ_TLB_FLUSH_GUEST:
Reviewed-by: Sean Christopherson <[email protected]>
On 14/10/21 18:03, Lai Jiangshan wrote:
> Ping
>
> On 2021/9/19 10:42, Lai Jiangshan wrote:
>> From: Lai Jiangshan <[email protected]>
>>
>> This patchset uses kvm_vcpu_flush_tlb_guest() instead of
>> kvm_mmu_reset_context()
>> when X86_CR4_PGE is changed or X86_CR4_PCIDE is changed 1->0.
>>
>> Neither X86_CR4_PGE nor X86_CR4_PCIDE participates in kvm_mmu_role, so
>> kvm_mmu_reset_context() is not required to be invoked. Only flushing tlb
>> is required as SDM says.
>>
>> The patchset has nothing to do with performance, because the overheads of
>> kvm_mmu_reset_context() and kvm_vcpu_flush_tlb_guest() are the same. And
>> even in the [near] future, kvm_vcpu_flush_tlb_guest() will be optimized,
>> the code is not in the hot path.
>>
>> This patchset makes the code more clear when to reset the mmu context.
>> And it makes KVM_MMU_CR4_ROLE_BITS consistent with kvm_mmu_role.
>>
>> Lai Jiangshan (2):
>> KVM: X86: Don't reset mmu context when X86_CR4_PCIDE 1->0
>> KVM: X86: Don't reset mmu context when toggling X86_CR4_PGE
>>
>> arch/x86/kvm/mmu.h | 5 ++---
>> arch/x86/kvm/x86.c | 7 +++++--
>> 2 files changed, 7 insertions(+), 5 deletions(-)
>>
>
Queued with kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu) replacement,
thanks.
Paolo