Hi!
Follow-up on the v3: https://patchwork.kernel.org/cover/11331343/.
The main purpose of this series is to upstream the dts change and the
binding document, but I wanted to see how far I could probe the GPU, to
check that the binding is indeed correct. The rest of the patches are
RFC/work-in-progress, but I think some of them could already be picked up.
So this is tested on MT8183 with a chromeos-4.19 kernel, and a ton of
backports to get the latest panfrost driver (I should probably try on
linux-next at some point but this was the path of least resistance).
I tested it as a module as it's more challenging (originally probing would
work built-in, on boot, but not as a module, as I didn't have the power
domain changes, and all power domains are on by default during boot).
Probing logs looks like this, currently. They look sane.
[ 501.319728] panfrost 13040000.gpu: clock rate = 511999970
[ 501.320041] panfrost 13040000.gpu: Linked as a consumer to regulator.14
[ 501.320102] panfrost 13040000.gpu: Linked as a consumer to regulator.31
[ 501.320651] panfrost 13040000.gpu: Linked as a consumer to genpd:0:13040000.gpu
[ 501.320954] panfrost 13040000.gpu: Linked as a consumer to genpd:1:13040000.gpu
[ 501.321062] panfrost 13040000.gpu: Linked as a consumer to genpd:2:13040000.gpu
[ 501.321734] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
[ 501.321741] panfrost 13040000.gpu: features: 00000000,13de77ff, issues: 00000000,00000400
[ 501.321747] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
[ 501.321752] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
[ 501.324951] [drm] Initialized panfrost 1.1.0 20180908 for 13040000.gpu on minor 2
Some more changes are still required to get devfreq working, and of course
I do not have a userspace driver to test this with.
I believe at least patches 1, 2, and 3 can be merged. 4 and 5 are mostly
useful in conjunction with 6 and 7 (which are not ready yet), so I'll let
maintainers decide.
Thanks!
Nicolas Boichat (7):
dt-bindings: gpu: mali-bifrost: Add Mediatek MT8183
arm64: dts: mt8183: Add node for the Mali GPU
drm/panfrost: Improve error reporting in panfrost_gpu_power_on
drm/panfrost: Add support for multiple regulators
drm/panfrost: Add support for multiple power domains
RFC: drm/panfrost: Add mt8183-mali compatible string
RFC: drm/panfrost: devfreq: Add support for 2 regulators
.../bindings/gpu/arm,mali-bifrost.yaml | 25 ++++
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 7 +
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 105 +++++++++++++++
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 17 +++
drivers/gpu/drm/panfrost/panfrost_device.c | 123 +++++++++++++++---
drivers/gpu/drm/panfrost/panfrost_device.h | 27 +++-
drivers/gpu/drm/panfrost/panfrost_drv.c | 41 ++++--
drivers/gpu/drm/panfrost/panfrost_gpu.c | 11 +-
8 files changed, 326 insertions(+), 30 deletions(-)
--
2.25.0.341.g760bfbb309-goog
It is useful to know which component cannot be powered on.
Signed-off-by: Nicolas Boichat <[email protected]>
Reviewed-by: Steven Price <[email protected]>
Reviewed-by: Alyssa Rosenzweig <[email protected]>
---
Was useful when trying to probe Bifrost GPU, to understand what
issue we are facing.
v4:
- No change
v3:
- Rebased on https://patchwork.kernel.org/patch/11325689/
drivers/gpu/drm/panfrost/panfrost_gpu.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panfrost/panfrost_gpu.c
index 460fc190de6e815..856f2fd1fa8ed27 100644
--- a/drivers/gpu/drm/panfrost/panfrost_gpu.c
+++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c
@@ -308,17 +308,20 @@ void panfrost_gpu_power_on(struct panfrost_device *pfdev)
gpu_write(pfdev, L2_PWRON_LO, pfdev->features.l2_present);
ret = readl_relaxed_poll_timeout(pfdev->iomem + L2_READY_LO,
val, val == pfdev->features.l2_present, 100, 1000);
+ if (ret)
+ dev_err(pfdev->dev, "error powering up gpu L2");
gpu_write(pfdev, SHADER_PWRON_LO, pfdev->features.shader_present);
- ret |= readl_relaxed_poll_timeout(pfdev->iomem + SHADER_READY_LO,
+ ret = readl_relaxed_poll_timeout(pfdev->iomem + SHADER_READY_LO,
val, val == pfdev->features.shader_present, 100, 1000);
+ if (ret)
+ dev_err(pfdev->dev, "error powering up gpu shader");
gpu_write(pfdev, TILER_PWRON_LO, pfdev->features.tiler_present);
- ret |= readl_relaxed_poll_timeout(pfdev->iomem + TILER_READY_LO,
+ ret = readl_relaxed_poll_timeout(pfdev->iomem + TILER_READY_LO,
val, val == pfdev->features.tiler_present, 100, 1000);
-
if (ret)
- dev_err(pfdev->dev, "error powering up gpu");
+ dev_err(pfdev->dev, "error powering up gpu tiler");
}
void panfrost_gpu_power_off(struct panfrost_device *pfdev)
--
2.25.0.341.g760bfbb309-goog
Add a basic GPU node for mt8183.
Signed-off-by: Nicolas Boichat <[email protected]>
Reviewed-by: Alyssa Rosenzweig <[email protected]>
---
Upstreaming what matches existing bindings from our Chromium OS tree:
https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-4.19/arch/arm64/boot/dts/mediatek/mt8183.dtsi#1348
The evb part of this change depends on this patch to add PMIC dtsi:
https://patchwork.kernel.org/patch/10928161/
The binding we use with out-of-tree Mali drivers includes more
clocks, this is used for devfreq: the out-of-tree driver switches
clk_mux to clk_sub_parent (26Mhz), adjusts clk_main_parent, then
switches clk_mux back to clk_main_parent:
(see https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-4.19/drivers/gpu/arm/midgard/platform/mediatek/mali_kbase_runtime_pm.c#423)
clocks =
<&topckgen CLK_TOP_MFGPLL_CK>,
<&topckgen CLK_TOP_MUX_MFG>,
<&clk26m>,
<&mfgcfg CLK_MFG_BG3D>;
clock-names =
"clk_main_parent",
"clk_mux",
"clk_sub_parent",
"subsys_mfg_cg";
v4:
- Add power-domain-names to describe the 3 domains.
(kept Alyssa's reviewed-by as the change is minor)
v3:
- No changes
v2:
- Use sram instead of mali_sram as SRAM supply name.
- Rename mali@ to gpu@.
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 7 ++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 105 ++++++++++++++++++++
2 files changed, 112 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
index 1fb195c683c3d01..7d609e0cd9b4975 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "mt8183.dtsi"
+#include "mt6358.dtsi"
/ {
model = "MediaTek MT8183 evaluation board";
@@ -30,6 +31,12 @@ &auxadc {
status = "okay";
};
+&gpu {
+ supply-names = "mali", "sram";
+ mali-supply = <&mt6358_vgpu_reg>;
+ sram-supply = <&mt6358_vsram_gpu_reg>;
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c_pins_0>;
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 124f9d3e09f532c..74b5305f663f740 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -599,6 +599,111 @@ mfgcfg: syscon@13000000 {
#clock-cells = <1>;
};
+ gpu: gpu@13040000 {
+ compatible = "mediatek,mt8183-mali", "arm,mali-bifrost";
+ reg = <0 0x13040000 0 0x4000>;
+ interrupts =
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 279 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "job", "mmu", "gpu";
+
+ clocks = <&topckgen CLK_TOP_MFGPLL_CK>;
+
+ power-domains =
+ <&scpsys MT8183_POWER_DOMAIN_MFG_CORE0>,
+ <&scpsys MT8183_POWER_DOMAIN_MFG_CORE1>,
+ <&scpsys MT8183_POWER_DOMAIN_MFG_2D>;
+ power-domain-names = "core0", "core1", "2d";
+
+ operating-points-v2 = <&gpu_opp_table>;
+ };
+
+ gpu_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <625000>, <850000>;
+ };
+
+ opp-320000000 {
+ opp-hz = /bits/ 64 <320000000>;
+ opp-microvolt = <631250>, <850000>;
+ };
+
+ opp-340000000 {
+ opp-hz = /bits/ 64 <340000000>;
+ opp-microvolt = <637500>, <850000>;
+ };
+
+ opp-360000000 {
+ opp-hz = /bits/ 64 <360000000>;
+ opp-microvolt = <643750>, <850000>;
+ };
+
+ opp-380000000 {
+ opp-hz = /bits/ 64 <380000000>;
+ opp-microvolt = <650000>, <850000>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <656250>, <850000>;
+ };
+
+ opp-420000000 {
+ opp-hz = /bits/ 64 <420000000>;
+ opp-microvolt = <662500>, <850000>;
+ };
+
+ opp-460000000 {
+ opp-hz = /bits/ 64 <460000000>;
+ opp-microvolt = <675000>, <850000>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <687500>, <850000>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ opp-microvolt = <700000>, <850000>;
+ };
+
+ opp-580000000 {
+ opp-hz = /bits/ 64 <580000000>;
+ opp-microvolt = <712500>, <850000>;
+ };
+
+ opp-620000000 {
+ opp-hz = /bits/ 64 <620000000>;
+ opp-microvolt = <725000>, <850000>;
+ };
+
+ opp-653000000 {
+ opp-hz = /bits/ 64 <653000000>;
+ opp-microvolt = <743750>, <850000>;
+ };
+
+ opp-698000000 {
+ opp-hz = /bits/ 64 <698000000>;
+ opp-microvolt = <768750>, <868750>;
+ };
+
+ opp-743000000 {
+ opp-hz = /bits/ 64 <743000000>;
+ opp-microvolt = <793750>, <893750>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <825000>, <925000>;
+ };
+ };
+
mmsys: syscon@14000000 {
compatible = "mediatek,mt8183-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
--
2.25.0.341.g760bfbb309-goog
The Bifrost GPU on MT8183 uses 2 regulators (core and SRAM) for
devfreq, and provides OPP table with 2 sets of voltages.
TODO: This is incomplete as we'll need add support for setting
a pair of voltages as well.
Signed-off-by: Nicolas Boichat <[email protected]>
---
drivers/gpu/drm/panfrost/panfrost_devfreq.c | 17 +++++++++++++++++
drivers/gpu/drm/panfrost/panfrost_device.h | 1 +
2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
index 413987038fbfccb..9c0987a3d71c597 100644
--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
@@ -79,6 +79,21 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
struct devfreq *devfreq;
struct thermal_cooling_device *cooling;
+ /* If we have 2 regulator, we need an OPP table with 2 voltages. */
+ if (pfdev->comp->num_supplies > 1) {
+ pfdev->devfreq.dev_opp_table =
+ dev_pm_opp_set_regulators(dev,
+ pfdev->comp->supply_names,
+ pfdev->comp->num_supplies);
+ if (IS_ERR(pfdev->devfreq.dev_opp_table)) {
+ ret = PTR_ERR(pfdev->devfreq.dev_opp_table);
+ pfdev->devfreq.dev_opp_table = NULL;
+ dev_err(dev,
+ "Failed to init devfreq opp table: %d\n", ret);
+ return ret;
+ }
+ }
+
ret = dev_pm_opp_of_add_table(dev);
if (ret == -ENODEV) /* Optional, continue without devfreq */
return 0;
@@ -119,6 +134,8 @@ void panfrost_devfreq_fini(struct panfrost_device *pfdev)
if (pfdev->devfreq.cooling)
devfreq_cooling_unregister(pfdev->devfreq.cooling);
dev_pm_opp_of_remove_table(&pfdev->pdev->dev);
+ if (pfdev->devfreq.dev_opp_table)
+ dev_pm_opp_put_regulators(pfdev->devfreq.dev_opp_table);
}
void panfrost_devfreq_resume(struct panfrost_device *pfdev)
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h
index c30c719a805940a..5009a8b7c853ea1 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.h
+++ b/drivers/gpu/drm/panfrost/panfrost_device.h
@@ -110,6 +110,7 @@ struct panfrost_device {
struct {
struct devfreq *devfreq;
struct thermal_cooling_device *cooling;
+ struct opp_table *dev_opp_table;
ktime_t busy_time;
ktime_t idle_time;
ktime_t time_last_update;
--
2.25.0.341.g760bfbb309-goog
Some GPUs, namely, the bifrost/g72 part on MT8183, have a second
regulator for their SRAM, let's add support for that.
We extend the framework in a generic manner so that we could
support more than 2 regulators, if required.
Signed-off-by: Nicolas Boichat <[email protected]>
---
v4:
- nits: Run through latest version of checkpatch:
- Use WARN instead of BUG_ON.
- Drop braces in single expression for loop.
- *comp not * comp
v3:
- Make this more generic, by allowing any number of regulators
(in practice we fix the maximum number of regulators to 2, but
this could be increased easily).
- We only probe the second regulator if the device tree matching
data asks for it.
- I couldn't find a way to detect the number of regulators in the
device tree, if we wanted to refuse to probe the device if there
are too many regulators, which might be required for safety, see
the thread on v2 [1].
- The discussion also included the idea of a separate device tree
entry for a "soft PDC", or at least a separate driver. I'm not
sure to understand the full picture, and how different vendors
implement this, so I'm still integrating everything in the main
driver. I'd be happy to try to make mt8183 fit into such a
framework after it's created, but I don't think I'm best placed
to implement (and again, the main purpose of this was to test
if the binding is correct).
[1] https://patchwork.kernel.org/patch/11322839/
drivers/gpu/drm/panfrost/panfrost_device.c | 26 +++++++++++++-------
drivers/gpu/drm/panfrost/panfrost_device.h | 15 +++++++++++-
drivers/gpu/drm/panfrost/panfrost_drv.c | 28 +++++++++++++++-------
3 files changed, 51 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/panfrost/panfrost_device.c
index 238fb6d54df4732..3720d50f6d9f965 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.c
+++ b/drivers/gpu/drm/panfrost/panfrost_device.c
@@ -87,18 +87,27 @@ static void panfrost_clk_fini(struct panfrost_device *pfdev)
static int panfrost_regulator_init(struct panfrost_device *pfdev)
{
- int ret;
+ int ret, i;
- pfdev->regulator = devm_regulator_get(pfdev->dev, "mali");
- if (IS_ERR(pfdev->regulator)) {
- ret = PTR_ERR(pfdev->regulator);
- dev_err(pfdev->dev, "failed to get regulator: %d\n", ret);
+ if (WARN(pfdev->comp->num_supplies > ARRAY_SIZE(pfdev->regulators),
+ "Too many supplies in compatible structure.\n"))
+ return -EINVAL;
+
+ for (i = 0; i < pfdev->comp->num_supplies; i++)
+ pfdev->regulators[i].supply = pfdev->comp->supply_names[i];
+
+ ret = devm_regulator_bulk_get(pfdev->dev,
+ pfdev->comp->num_supplies,
+ pfdev->regulators);
+ if (ret < 0) {
+ dev_err(pfdev->dev, "failed to get regulators: %d\n", ret);
return ret;
}
- ret = regulator_enable(pfdev->regulator);
+ ret = regulator_bulk_enable(pfdev->comp->num_supplies,
+ pfdev->regulators);
if (ret < 0) {
- dev_err(pfdev->dev, "failed to enable regulator: %d\n", ret);
+ dev_err(pfdev->dev, "failed to enable regulators: %d\n", ret);
return ret;
}
@@ -107,7 +116,8 @@ static int panfrost_regulator_init(struct panfrost_device *pfdev)
static void panfrost_regulator_fini(struct panfrost_device *pfdev)
{
- regulator_disable(pfdev->regulator);
+ regulator_bulk_disable(pfdev->comp->num_supplies,
+ pfdev->regulators);
}
int panfrost_device_init(struct panfrost_device *pfdev)
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h
index 06713811b92cdf7..c9468bc5573ac9d 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.h
+++ b/drivers/gpu/drm/panfrost/panfrost_device.h
@@ -7,6 +7,7 @@
#include <linux/atomic.h>
#include <linux/io-pgtable.h>
+#include <linux/regulator/consumer.h>
#include <linux/spinlock.h>
#include <drm/drm_device.h>
#include <drm/drm_mm.h>
@@ -19,6 +20,7 @@ struct panfrost_job;
struct panfrost_perfcnt;
#define NUM_JOB_SLOTS 3
+#define MAX_REGULATORS 2
struct panfrost_features {
u16 id;
@@ -51,6 +53,16 @@ struct panfrost_features {
unsigned long hw_issues[64 / BITS_PER_LONG];
};
+/*
+ * Features that cannot be automatically detected and need matching using the
+ * compatible string, typically SoC-specific.
+ */
+struct panfrost_compatible {
+ /* Supplies count and names. */
+ int num_supplies;
+ const char * const *supply_names;
+};
+
struct panfrost_device {
struct device *dev;
struct drm_device *ddev;
@@ -59,10 +71,11 @@ struct panfrost_device {
void __iomem *iomem;
struct clk *clock;
struct clk *bus_clock;
- struct regulator *regulator;
+ struct regulator_bulk_data regulators[MAX_REGULATORS];
struct reset_control *rstc;
struct panfrost_features features;
+ const struct panfrost_compatible *comp;
spinlock_t as_lock;
unsigned long as_in_use_mask;
diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c
index b7a618db3ee223e..4d08507526239f2 100644
--- a/drivers/gpu/drm/panfrost/panfrost_drv.c
+++ b/drivers/gpu/drm/panfrost/panfrost_drv.c
@@ -584,6 +584,10 @@ static int panfrost_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, pfdev);
+ pfdev->comp = of_device_get_match_data(&pdev->dev);
+ if (!pfdev->comp)
+ return -ENODEV;
+
/* Allocate and initialze the DRM device. */
ddev = drm_dev_alloc(&panfrost_drm_driver, &pdev->dev);
if (IS_ERR(ddev))
@@ -655,16 +659,22 @@ static int panfrost_remove(struct platform_device *pdev)
return 0;
}
+const char * const default_supplies[] = { "mali" };
+static const struct panfrost_compatible default_data = {
+ .num_supplies = ARRAY_SIZE(default_supplies),
+ .supply_names = default_supplies,
+};
+
static const struct of_device_id dt_match[] = {
- { .compatible = "arm,mali-t604" },
- { .compatible = "arm,mali-t624" },
- { .compatible = "arm,mali-t628" },
- { .compatible = "arm,mali-t720" },
- { .compatible = "arm,mali-t760" },
- { .compatible = "arm,mali-t820" },
- { .compatible = "arm,mali-t830" },
- { .compatible = "arm,mali-t860" },
- { .compatible = "arm,mali-t880" },
+ { .compatible = "arm,mali-t604", .data = &default_data, },
+ { .compatible = "arm,mali-t624", .data = &default_data, },
+ { .compatible = "arm,mali-t628", .data = &default_data, },
+ { .compatible = "arm,mali-t720", .data = &default_data, },
+ { .compatible = "arm,mali-t760", .data = &default_data, },
+ { .compatible = "arm,mali-t820", .data = &default_data, },
+ { .compatible = "arm,mali-t830", .data = &default_data, },
+ { .compatible = "arm,mali-t860", .data = &default_data, },
+ { .compatible = "arm,mali-t880", .data = &default_data, },
{}
};
MODULE_DEVICE_TABLE(of, dt_match);
--
2.25.0.341.g760bfbb309-goog
For testing only, the driver doesn't really work yet, AFAICT.
Signed-off-by: Nicolas Boichat <[email protected]>
---
v4:
- Add power domain names.
v3:
- Match mt8183-mali instead of bifrost, as we require special
handling for the 2 regulators and 3 power domains.
drivers/gpu/drm/panfrost/panfrost_drv.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c
index a6e162236d67fdf..497c375932ad589 100644
--- a/drivers/gpu/drm/panfrost/panfrost_drv.c
+++ b/drivers/gpu/drm/panfrost/panfrost_drv.c
@@ -667,6 +667,15 @@ static const struct panfrost_compatible default_data = {
.pm_domain_names = NULL,
};
+const char * const mediatek_mt8183_supplies[] = { "mali", "sram" };
+const char * const mediatek_mt8183_pm_domains[] = { "core0", "core1", "2d" };
+static const struct panfrost_compatible mediatek_mt8183_data = {
+ .num_supplies = ARRAY_SIZE(mediatek_mt8183_supplies),
+ .supply_names = mediatek_mt8183_supplies,
+ .num_pm_domains = 3,
+ .pm_domain_names = mediatek_mt8183_pm_domains,
+};
+
static const struct of_device_id dt_match[] = {
{ .compatible = "arm,mali-t604", .data = &default_data, },
{ .compatible = "arm,mali-t624", .data = &default_data, },
@@ -677,6 +686,8 @@ static const struct of_device_id dt_match[] = {
{ .compatible = "arm,mali-t830", .data = &default_data, },
{ .compatible = "arm,mali-t860", .data = &default_data, },
{ .compatible = "arm,mali-t880", .data = &default_data, },
+ { .compatible = "mediatek,mt8183-mali",
+ .data = &mediatek_mt8183_data },
{}
};
MODULE_DEVICE_TABLE(of, dt_match);
--
2.25.0.341.g760bfbb309-goog
When there is a single power domain per device, the core will
ensure the power domain is switched on (so it is technically
equivalent to having not power domain specified at all).
However, when there are multiple domains, as in MT8183 Bifrost
GPU, we need to handle them in driver code.
Signed-off-by: Nicolas Boichat <[email protected]>
---
The downstream driver we use on chromeos-4.19 currently uses 2
additional devices in device tree to accomodate for this [1], but
I believe this solution is cleaner.
[1] https://chromium.googlesource.com/chromiumos/third_party/kernel/+/refs/heads/chromeos-4.19/drivers/gpu/arm/midgard/platform/mediatek/mali_kbase_runtime_pm.c#31
v4:
- Match the exact power domain names as specified in the compatible
struct, instead of just matching the number of power domains.
[Review: Ulf Hansson]
- Dropped print and reordered function [Review: Steven Price]
- nits: Run through latest version of checkpatch:
- Use WARN instead of BUG_ON.
- Drop braces for single expression if block.
v3:
- Use the compatible matching data to specify the number of power
domains. Note that setting 0 or 1 in num_pm_domains is equivalent
as the core will handle these 2 cases in the exact same way
(automatically, without driver intervention), and there should
be no adverse consequence in this case (the concern is about
switching on only some power domains and not others).
drivers/gpu/drm/panfrost/panfrost_device.c | 97 ++++++++++++++++++++--
drivers/gpu/drm/panfrost/panfrost_device.h | 11 +++
drivers/gpu/drm/panfrost/panfrost_drv.c | 2 +
3 files changed, 102 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/panfrost/panfrost_device.c
index 3720d50f6d9f965..8136babd3ba9935 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.c
+++ b/drivers/gpu/drm/panfrost/panfrost_device.c
@@ -5,6 +5,7 @@
#include <linux/clk.h>
#include <linux/reset.h>
#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
#include <linux/regulator/consumer.h>
#include "panfrost_device.h"
@@ -120,6 +121,79 @@ static void panfrost_regulator_fini(struct panfrost_device *pfdev)
pfdev->regulators);
}
+static void panfrost_pm_domain_fini(struct panfrost_device *pfdev)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(pfdev->pm_domain_devs); i++) {
+ if (!pfdev->pm_domain_devs[i])
+ break;
+
+ if (pfdev->pm_domain_links[i])
+ device_link_del(pfdev->pm_domain_links[i]);
+
+ dev_pm_domain_detach(pfdev->pm_domain_devs[i], true);
+ }
+}
+
+static int panfrost_pm_domain_init(struct panfrost_device *pfdev)
+{
+ int err;
+ int i, num_domains;
+
+ num_domains = of_count_phandle_with_args(pfdev->dev->of_node,
+ "power-domains",
+ "#power-domain-cells");
+
+ /*
+ * Single domain is handled by the core, and, if only a single power
+ * the power domain is requested, the property is optional.
+ */
+ if (num_domains < 2 && pfdev->comp->num_pm_domains < 2)
+ return 0;
+
+ if (num_domains != pfdev->comp->num_pm_domains) {
+ dev_err(pfdev->dev,
+ "Incorrect number of power domains: %d provided, %d needed\n",
+ num_domains, pfdev->comp->num_pm_domains);
+ return -EINVAL;
+ }
+
+ if (WARN(num_domains > ARRAY_SIZE(pfdev->pm_domain_devs),
+ "Too many supplies in compatible structure.\n"))
+ return -EINVAL;
+
+ for (i = 0; i < num_domains; i++) {
+ pfdev->pm_domain_devs[i] =
+ dev_pm_domain_attach_by_name(pfdev->dev,
+ pfdev->comp->pm_domain_names[i]);
+ if (IS_ERR_OR_NULL(pfdev->pm_domain_devs[i])) {
+ err = PTR_ERR(pfdev->pm_domain_devs[i]) ? : -ENODATA;
+ pfdev->pm_domain_devs[i] = NULL;
+ dev_err(pfdev->dev,
+ "failed to get pm-domain %s(%d): %d\n",
+ pfdev->comp->pm_domain_names[i], i, err);
+ goto err;
+ }
+
+ pfdev->pm_domain_links[i] = device_link_add(pfdev->dev,
+ pfdev->pm_domain_devs[i], DL_FLAG_PM_RUNTIME |
+ DL_FLAG_STATELESS | DL_FLAG_RPM_ACTIVE);
+ if (!pfdev->pm_domain_links[i]) {
+ dev_err(pfdev->pm_domain_devs[i],
+ "adding device link failed!\n");
+ err = -ENODEV;
+ goto err;
+ }
+ }
+
+ return 0;
+
+err:
+ panfrost_pm_domain_fini(pfdev);
+ return err;
+}
+
int panfrost_device_init(struct panfrost_device *pfdev)
{
int err;
@@ -150,37 +224,43 @@ int panfrost_device_init(struct panfrost_device *pfdev)
goto err_out1;
}
+ err = panfrost_pm_domain_init(pfdev);
+ if (err)
+ goto err_out2;
+
res = platform_get_resource(pfdev->pdev, IORESOURCE_MEM, 0);
pfdev->iomem = devm_ioremap_resource(pfdev->dev, res);
if (IS_ERR(pfdev->iomem)) {
dev_err(pfdev->dev, "failed to ioremap iomem\n");
err = PTR_ERR(pfdev->iomem);
- goto err_out2;
+ goto err_out3;
}
err = panfrost_gpu_init(pfdev);
if (err)
- goto err_out2;
+ goto err_out3;
err = panfrost_mmu_init(pfdev);
if (err)
- goto err_out3;
+ goto err_out4;
err = panfrost_job_init(pfdev);
if (err)
- goto err_out4;
+ goto err_out5;
err = panfrost_perfcnt_init(pfdev);
if (err)
- goto err_out5;
+ goto err_out6;
return 0;
-err_out5:
+err_out6:
panfrost_job_fini(pfdev);
-err_out4:
+err_out5:
panfrost_mmu_fini(pfdev);
-err_out3:
+err_out4:
panfrost_gpu_fini(pfdev);
+err_out3:
+ panfrost_pm_domain_fini(pfdev);
err_out2:
panfrost_reset_fini(pfdev);
err_out1:
@@ -196,6 +276,7 @@ void panfrost_device_fini(struct panfrost_device *pfdev)
panfrost_job_fini(pfdev);
panfrost_mmu_fini(pfdev);
panfrost_gpu_fini(pfdev);
+ panfrost_pm_domain_fini(pfdev);
panfrost_reset_fini(pfdev);
panfrost_regulator_fini(pfdev);
panfrost_clk_fini(pfdev);
diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h
index c9468bc5573ac9d..c30c719a805940a 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.h
+++ b/drivers/gpu/drm/panfrost/panfrost_device.h
@@ -21,6 +21,7 @@ struct panfrost_perfcnt;
#define NUM_JOB_SLOTS 3
#define MAX_REGULATORS 2
+#define MAX_PM_DOMAINS 3
struct panfrost_features {
u16 id;
@@ -61,6 +62,13 @@ struct panfrost_compatible {
/* Supplies count and names. */
int num_supplies;
const char * const *supply_names;
+ /*
+ * Number of power domains required, note that values 0 and 1 are
+ * handled identically, as only values > 1 need special handling.
+ */
+ int num_pm_domains;
+ /* Only required if num_pm_domains > 1. */
+ const char * const *pm_domain_names;
};
struct panfrost_device {
@@ -73,6 +81,9 @@ struct panfrost_device {
struct clk *bus_clock;
struct regulator_bulk_data regulators[MAX_REGULATORS];
struct reset_control *rstc;
+ /* pm_domains for devices with more than one. */
+ struct device *pm_domain_devs[MAX_PM_DOMAINS];
+ struct device_link *pm_domain_links[MAX_PM_DOMAINS];
struct panfrost_features features;
const struct panfrost_compatible *comp;
diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c
index 4d08507526239f2..a6e162236d67fdf 100644
--- a/drivers/gpu/drm/panfrost/panfrost_drv.c
+++ b/drivers/gpu/drm/panfrost/panfrost_drv.c
@@ -663,6 +663,8 @@ const char * const default_supplies[] = { "mali" };
static const struct panfrost_compatible default_data = {
.num_supplies = ARRAY_SIZE(default_supplies),
.supply_names = default_supplies,
+ .num_pm_domains = 1, /* optional */
+ .pm_domain_names = NULL,
};
static const struct of_device_id dt_match[] = {
--
2.25.0.341.g760bfbb309-goog
On 2/7/20 6:26 AM, Nicolas Boichat wrote:
> Hi!
>
> Follow-up on the v3: https://patchwork.kernel.org/cover/11331343/.
>
> The main purpose of this series is to upstream the dts change and the
> binding document, but I wanted to see how far I could probe the GPU, to
> check that the binding is indeed correct. The rest of the patches are
> RFC/work-in-progress, but I think some of them could already be picked up.
>
> So this is tested on MT8183 with a chromeos-4.19 kernel, and a ton of
> backports to get the latest panfrost driver (I should probably try on
> linux-next at some point but this was the path of least resistance).
>
> I tested it as a module as it's more challenging (originally probing would
> work built-in, on boot, but not as a module, as I didn't have the power
> domain changes, and all power domains are on by default during boot).
>
> Probing logs looks like this, currently. They look sane.
> [ 501.319728] panfrost 13040000.gpu: clock rate = 511999970
> [ 501.320041] panfrost 13040000.gpu: Linked as a consumer to regulator.14
> [ 501.320102] panfrost 13040000.gpu: Linked as a consumer to regulator.31
> [ 501.320651] panfrost 13040000.gpu: Linked as a consumer to genpd:0:13040000.gpu
> [ 501.320954] panfrost 13040000.gpu: Linked as a consumer to genpd:1:13040000.gpu
> [ 501.321062] panfrost 13040000.gpu: Linked as a consumer to genpd:2:13040000.gpu
> [ 501.321734] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
> [ 501.321741] panfrost 13040000.gpu: features: 00000000,13de77ff, issues: 00000000,00000400
> [ 501.321747] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
> [ 501.321752] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
> [ 501.324951] [drm] Initialized panfrost 1.1.0 20180908 for 13040000.gpu on minor 2
>
> Some more changes are still required to get devfreq working, and of course
> I do not have a userspace driver to test this with.
Have you tried the Panfrost tests in IGT? They are atm quite basic, but
could be interesting to check that the different HW units are correctly
powered on.
Regards,
Tomeu
> I believe at least patches 1, 2, and 3 can be merged. 4 and 5 are mostly
> useful in conjunction with 6 and 7 (which are not ready yet), so I'll let
> maintainers decide.
>
> Thanks!
>
> Nicolas Boichat (7):
> dt-bindings: gpu: mali-bifrost: Add Mediatek MT8183
> arm64: dts: mt8183: Add node for the Mali GPU
> drm/panfrost: Improve error reporting in panfrost_gpu_power_on
> drm/panfrost: Add support for multiple regulators
> drm/panfrost: Add support for multiple power domains
> RFC: drm/panfrost: Add mt8183-mali compatible string
> RFC: drm/panfrost: devfreq: Add support for 2 regulators
>
> .../bindings/gpu/arm,mali-bifrost.yaml | 25 ++++
> arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 7 +
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 105 +++++++++++++++
> drivers/gpu/drm/panfrost/panfrost_devfreq.c | 17 +++
> drivers/gpu/drm/panfrost/panfrost_device.c | 123 +++++++++++++++---
> drivers/gpu/drm/panfrost/panfrost_device.h | 27 +++-
> drivers/gpu/drm/panfrost/panfrost_drv.c | 41 ++++--
> drivers/gpu/drm/panfrost/panfrost_gpu.c | 11 +-
> 8 files changed, 326 insertions(+), 30 deletions(-)
>
On Fri, Feb 7, 2020 at 2:18 PM Tomeu Vizoso <[email protected]> wrote:
>
> On 2/7/20 6:26 AM, Nicolas Boichat wrote:
> > Hi!
> >
> > Follow-up on the v3: https://patchwork.kernel.org/cover/11331343/.
> >
> > The main purpose of this series is to upstream the dts change and the
> > binding document, but I wanted to see how far I could probe the GPU, to
> > check that the binding is indeed correct. The rest of the patches are
> > RFC/work-in-progress, but I think some of them could already be picked up.
> >
> > So this is tested on MT8183 with a chromeos-4.19 kernel, and a ton of
> > backports to get the latest panfrost driver (I should probably try on
> > linux-next at some point but this was the path of least resistance).
> >
> > I tested it as a module as it's more challenging (originally probing would
> > work built-in, on boot, but not as a module, as I didn't have the power
> > domain changes, and all power domains are on by default during boot).
> >
> > Probing logs looks like this, currently. They look sane.
> > [ 501.319728] panfrost 13040000.gpu: clock rate = 511999970
> > [ 501.320041] panfrost 13040000.gpu: Linked as a consumer to regulator.14
> > [ 501.320102] panfrost 13040000.gpu: Linked as a consumer to regulator.31
> > [ 501.320651] panfrost 13040000.gpu: Linked as a consumer to genpd:0:13040000.gpu
> > [ 501.320954] panfrost 13040000.gpu: Linked as a consumer to genpd:1:13040000.gpu
> > [ 501.321062] panfrost 13040000.gpu: Linked as a consumer to genpd:2:13040000.gpu
> > [ 501.321734] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
> > [ 501.321741] panfrost 13040000.gpu: features: 00000000,13de77ff, issues: 00000000,00000400
> > [ 501.321747] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
> > [ 501.321752] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
> > [ 501.324951] [drm] Initialized panfrost 1.1.0 20180908 for 13040000.gpu on minor 2
> >
> > Some more changes are still required to get devfreq working, and of course
> > I do not have a userspace driver to test this with.
>
> Have you tried the Panfrost tests in IGT? They are atm quite basic, but
> could be interesting to check that the different HW units are correctly
> powered on.
I haven't, you mean this right?
https://gitlab.freedesktop.org/tomeu/igt-gpu-tools/tree/panfrost
Any specific test you have in mind?
Thanks,
> Regards,
>
> Tomeu
>
> > I believe at least patches 1, 2, and 3 can be merged. 4 and 5 are mostly
> > useful in conjunction with 6 and 7 (which are not ready yet), so I'll let
> > maintainers decide.
> >
> > Thanks!
> >
> > Nicolas Boichat (7):
> > dt-bindings: gpu: mali-bifrost: Add Mediatek MT8183
> > arm64: dts: mt8183: Add node for the Mali GPU
> > drm/panfrost: Improve error reporting in panfrost_gpu_power_on
> > drm/panfrost: Add support for multiple regulators
> > drm/panfrost: Add support for multiple power domains
> > RFC: drm/panfrost: Add mt8183-mali compatible string
> > RFC: drm/panfrost: devfreq: Add support for 2 regulators
> >
> > .../bindings/gpu/arm,mali-bifrost.yaml | 25 ++++
> > arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 7 +
> > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 105 +++++++++++++++
> > drivers/gpu/drm/panfrost/panfrost_devfreq.c | 17 +++
> > drivers/gpu/drm/panfrost/panfrost_device.c | 123 +++++++++++++++---
> > drivers/gpu/drm/panfrost/panfrost_device.h | 27 +++-
> > drivers/gpu/drm/panfrost/panfrost_drv.c | 41 ++++--
> > drivers/gpu/drm/panfrost/panfrost_gpu.c | 11 +-
> > 8 files changed, 326 insertions(+), 30 deletions(-)
> >
On 2/7/20 8:42 AM, Nicolas Boichat wrote:
> On Fri, Feb 7, 2020 at 2:18 PM Tomeu Vizoso <[email protected]> wrote:
>>
>> On 2/7/20 6:26 AM, Nicolas Boichat wrote:
>>> Hi!
>>>
>>> Follow-up on the v3: https://patchwork.kernel.org/cover/11331343/.
>>>
>>> The main purpose of this series is to upstream the dts change and the
>>> binding document, but I wanted to see how far I could probe the GPU, to
>>> check that the binding is indeed correct. The rest of the patches are
>>> RFC/work-in-progress, but I think some of them could already be picked up.
>>>
>>> So this is tested on MT8183 with a chromeos-4.19 kernel, and a ton of
>>> backports to get the latest panfrost driver (I should probably try on
>>> linux-next at some point but this was the path of least resistance).
>>>
>>> I tested it as a module as it's more challenging (originally probing would
>>> work built-in, on boot, but not as a module, as I didn't have the power
>>> domain changes, and all power domains are on by default during boot).
>>>
>>> Probing logs looks like this, currently. They look sane.
>>> [ 501.319728] panfrost 13040000.gpu: clock rate = 511999970
>>> [ 501.320041] panfrost 13040000.gpu: Linked as a consumer to regulator.14
>>> [ 501.320102] panfrost 13040000.gpu: Linked as a consumer to regulator.31
>>> [ 501.320651] panfrost 13040000.gpu: Linked as a consumer to genpd:0:13040000.gpu
>>> [ 501.320954] panfrost 13040000.gpu: Linked as a consumer to genpd:1:13040000.gpu
>>> [ 501.321062] panfrost 13040000.gpu: Linked as a consumer to genpd:2:13040000.gpu
>>> [ 501.321734] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
>>> [ 501.321741] panfrost 13040000.gpu: features: 00000000,13de77ff, issues: 00000000,00000400
>>> [ 501.321747] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
>>> [ 501.321752] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
>>> [ 501.324951] [drm] Initialized panfrost 1.1.0 20180908 for 13040000.gpu on minor 2
>>>
>>> Some more changes are still required to get devfreq working, and of course
>>> I do not have a userspace driver to test this with.
>>
>> Have you tried the Panfrost tests in IGT? They are atm quite basic, but
>> could be interesting to check that the different HW units are correctly
>> powered on.
>
> I haven't, you mean this right?
> https://gitlab.freedesktop.org/tomeu/igt-gpu-tools/tree/panfrost
Yes, though may be better to use the upstream repo:
https://gitlab.freedesktop.org/drm/igt-gpu-tools
> Any specific test you have in mind?
All the panfrost ones, but looks like panfrost_prime:gem-prime-import is
failing atm:
https://lava.collabora.co.uk/scheduler/job/2214987
Cheers,
Tomeu
> Thanks,
>
>> Regards,
>>
>> Tomeu
>>
>>> I believe at least patches 1, 2, and 3 can be merged. 4 and 5 are mostly
>>> useful in conjunction with 6 and 7 (which are not ready yet), so I'll let
>>> maintainers decide.
>>>
>>> Thanks!
>>>
>>> Nicolas Boichat (7):
>>> dt-bindings: gpu: mali-bifrost: Add Mediatek MT8183
>>> arm64: dts: mt8183: Add node for the Mali GPU
>>> drm/panfrost: Improve error reporting in panfrost_gpu_power_on
>>> drm/panfrost: Add support for multiple regulators
>>> drm/panfrost: Add support for multiple power domains
>>> RFC: drm/panfrost: Add mt8183-mali compatible string
>>> RFC: drm/panfrost: devfreq: Add support for 2 regulators
>>>
>>> .../bindings/gpu/arm,mali-bifrost.yaml | 25 ++++
>>> arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 7 +
>>> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 105 +++++++++++++++
>>> drivers/gpu/drm/panfrost/panfrost_devfreq.c | 17 +++
>>> drivers/gpu/drm/panfrost/panfrost_device.c | 123 +++++++++++++++---
>>> drivers/gpu/drm/panfrost/panfrost_device.h | 27 +++-
>>> drivers/gpu/drm/panfrost/panfrost_drv.c | 41 ++++--
>>> drivers/gpu/drm/panfrost/panfrost_gpu.c | 11 +-
>>> 8 files changed, 326 insertions(+), 30 deletions(-)
>>>
> + for (i = 0; i < ARRAY_SIZE(pfdev->pm_domain_devs); i++) {
> + if (!pfdev->pm_domain_devs[i])
> + break;
I'm not totally familiar with this code, but should this be a break or
just a continue?
On Fri, 7 Feb 2020 at 06:27, Nicolas Boichat <[email protected]> wrote:
>
> When there is a single power domain per device, the core will
> ensure the power domain is switched on (so it is technically
> equivalent to having not power domain specified at all).
>
> However, when there are multiple domains, as in MT8183 Bifrost
> GPU, we need to handle them in driver code.
>
> Signed-off-by: Nicolas Boichat <[email protected]>
Besides a minor nitpick, feel free to add:
Reviewed-by: Ulf Hansson <[email protected]>
Kind regards
Uffe
>
> ---
>
> The downstream driver we use on chromeos-4.19 currently uses 2
> additional devices in device tree to accomodate for this [1], but
> I believe this solution is cleaner.
>
> [1] https://chromium.googlesource.com/chromiumos/third_party/kernel/+/refs/heads/chromeos-4.19/drivers/gpu/arm/midgard/platform/mediatek/mali_kbase_runtime_pm.c#31
>
> v4:
> - Match the exact power domain names as specified in the compatible
> struct, instead of just matching the number of power domains.
> [Review: Ulf Hansson]
> - Dropped print and reordered function [Review: Steven Price]
> - nits: Run through latest version of checkpatch:
> - Use WARN instead of BUG_ON.
> - Drop braces for single expression if block.
> v3:
> - Use the compatible matching data to specify the number of power
> domains. Note that setting 0 or 1 in num_pm_domains is equivalent
> as the core will handle these 2 cases in the exact same way
> (automatically, without driver intervention), and there should
> be no adverse consequence in this case (the concern is about
> switching on only some power domains and not others).
>
> drivers/gpu/drm/panfrost/panfrost_device.c | 97 ++++++++++++++++++++--
> drivers/gpu/drm/panfrost/panfrost_device.h | 11 +++
> drivers/gpu/drm/panfrost/panfrost_drv.c | 2 +
> 3 files changed, 102 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/panfrost/panfrost_device.c
> index 3720d50f6d9f965..8136babd3ba9935 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_device.c
> +++ b/drivers/gpu/drm/panfrost/panfrost_device.c
> @@ -5,6 +5,7 @@
> #include <linux/clk.h>
> #include <linux/reset.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> #include <linux/regulator/consumer.h>
>
> #include "panfrost_device.h"
> @@ -120,6 +121,79 @@ static void panfrost_regulator_fini(struct panfrost_device *pfdev)
> pfdev->regulators);
> }
>
> +static void panfrost_pm_domain_fini(struct panfrost_device *pfdev)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(pfdev->pm_domain_devs); i++) {
> + if (!pfdev->pm_domain_devs[i])
> + break;
> +
> + if (pfdev->pm_domain_links[i])
> + device_link_del(pfdev->pm_domain_links[i]);
> +
> + dev_pm_domain_detach(pfdev->pm_domain_devs[i], true);
> + }
> +}
> +
> +static int panfrost_pm_domain_init(struct panfrost_device *pfdev)
> +{
> + int err;
> + int i, num_domains;
> +
> + num_domains = of_count_phandle_with_args(pfdev->dev->of_node,
> + "power-domains",
> + "#power-domain-cells");
> +
> + /*
> + * Single domain is handled by the core, and, if only a single power
> + * the power domain is requested, the property is optional.
> + */
> + if (num_domains < 2 && pfdev->comp->num_pm_domains < 2)
> + return 0;
> +
> + if (num_domains != pfdev->comp->num_pm_domains) {
> + dev_err(pfdev->dev,
> + "Incorrect number of power domains: %d provided, %d needed\n",
> + num_domains, pfdev->comp->num_pm_domains);
> + return -EINVAL;
> + }
> +
> + if (WARN(num_domains > ARRAY_SIZE(pfdev->pm_domain_devs),
> + "Too many supplies in compatible structure.\n"))
Nitpick:
Not sure this deserves a WARN. Perhaps a regular dev_err() is sufficient.
> + return -EINVAL;
> +
> + for (i = 0; i < num_domains; i++) {
> + pfdev->pm_domain_devs[i] =
> + dev_pm_domain_attach_by_name(pfdev->dev,
> + pfdev->comp->pm_domain_names[i]);
> + if (IS_ERR_OR_NULL(pfdev->pm_domain_devs[i])) {
> + err = PTR_ERR(pfdev->pm_domain_devs[i]) ? : -ENODATA;
> + pfdev->pm_domain_devs[i] = NULL;
> + dev_err(pfdev->dev,
> + "failed to get pm-domain %s(%d): %d\n",
> + pfdev->comp->pm_domain_names[i], i, err);
> + goto err;
> + }
> +
> + pfdev->pm_domain_links[i] = device_link_add(pfdev->dev,
> + pfdev->pm_domain_devs[i], DL_FLAG_PM_RUNTIME |
> + DL_FLAG_STATELESS | DL_FLAG_RPM_ACTIVE);
> + if (!pfdev->pm_domain_links[i]) {
> + dev_err(pfdev->pm_domain_devs[i],
> + "adding device link failed!\n");
> + err = -ENODEV;
> + goto err;
> + }
> + }
> +
> + return 0;
> +
> +err:
> + panfrost_pm_domain_fini(pfdev);
> + return err;
> +}
> +
> int panfrost_device_init(struct panfrost_device *pfdev)
> {
> int err;
> @@ -150,37 +224,43 @@ int panfrost_device_init(struct panfrost_device *pfdev)
> goto err_out1;
> }
>
> + err = panfrost_pm_domain_init(pfdev);
> + if (err)
> + goto err_out2;
> +
> res = platform_get_resource(pfdev->pdev, IORESOURCE_MEM, 0);
> pfdev->iomem = devm_ioremap_resource(pfdev->dev, res);
> if (IS_ERR(pfdev->iomem)) {
> dev_err(pfdev->dev, "failed to ioremap iomem\n");
> err = PTR_ERR(pfdev->iomem);
> - goto err_out2;
> + goto err_out3;
> }
>
> err = panfrost_gpu_init(pfdev);
> if (err)
> - goto err_out2;
> + goto err_out3;
>
> err = panfrost_mmu_init(pfdev);
> if (err)
> - goto err_out3;
> + goto err_out4;
>
> err = panfrost_job_init(pfdev);
> if (err)
> - goto err_out4;
> + goto err_out5;
>
> err = panfrost_perfcnt_init(pfdev);
> if (err)
> - goto err_out5;
> + goto err_out6;
>
> return 0;
> -err_out5:
> +err_out6:
> panfrost_job_fini(pfdev);
> -err_out4:
> +err_out5:
> panfrost_mmu_fini(pfdev);
> -err_out3:
> +err_out4:
> panfrost_gpu_fini(pfdev);
> +err_out3:
> + panfrost_pm_domain_fini(pfdev);
> err_out2:
> panfrost_reset_fini(pfdev);
> err_out1:
> @@ -196,6 +276,7 @@ void panfrost_device_fini(struct panfrost_device *pfdev)
> panfrost_job_fini(pfdev);
> panfrost_mmu_fini(pfdev);
> panfrost_gpu_fini(pfdev);
> + panfrost_pm_domain_fini(pfdev);
> panfrost_reset_fini(pfdev);
> panfrost_regulator_fini(pfdev);
> panfrost_clk_fini(pfdev);
> diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h
> index c9468bc5573ac9d..c30c719a805940a 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_device.h
> +++ b/drivers/gpu/drm/panfrost/panfrost_device.h
> @@ -21,6 +21,7 @@ struct panfrost_perfcnt;
>
> #define NUM_JOB_SLOTS 3
> #define MAX_REGULATORS 2
> +#define MAX_PM_DOMAINS 3
>
> struct panfrost_features {
> u16 id;
> @@ -61,6 +62,13 @@ struct panfrost_compatible {
> /* Supplies count and names. */
> int num_supplies;
> const char * const *supply_names;
> + /*
> + * Number of power domains required, note that values 0 and 1 are
> + * handled identically, as only values > 1 need special handling.
> + */
> + int num_pm_domains;
> + /* Only required if num_pm_domains > 1. */
> + const char * const *pm_domain_names;
> };
>
> struct panfrost_device {
> @@ -73,6 +81,9 @@ struct panfrost_device {
> struct clk *bus_clock;
> struct regulator_bulk_data regulators[MAX_REGULATORS];
> struct reset_control *rstc;
> + /* pm_domains for devices with more than one. */
> + struct device *pm_domain_devs[MAX_PM_DOMAINS];
> + struct device_link *pm_domain_links[MAX_PM_DOMAINS];
>
> struct panfrost_features features;
> const struct panfrost_compatible *comp;
> diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c
> index 4d08507526239f2..a6e162236d67fdf 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_drv.c
> +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c
> @@ -663,6 +663,8 @@ const char * const default_supplies[] = { "mali" };
> static const struct panfrost_compatible default_data = {
> .num_supplies = ARRAY_SIZE(default_supplies),
> .supply_names = default_supplies,
> + .num_pm_domains = 1, /* optional */
> + .pm_domain_names = NULL,
> };
>
> static const struct of_device_id dt_match[] = {
> --
> 2.25.0.341.g760bfbb309-goog
>
On Fri, Feb 7, 2020 at 9:52 PM Alyssa Rosenzweig
<[email protected]> wrote:
>
> > + for (i = 0; i < ARRAY_SIZE(pfdev->pm_domain_devs); i++) {
> > + if (!pfdev->pm_domain_devs[i])
> > + break;
(next time, please provide a tiny bit more context when quoting, I had
to look up to see where this comes from)
So this comes from panfrost_pm_domain_fini.
> I'm not totally familiar with this code, but should this be a break or
> just a continue?
Check how the domains are initialized in panfrost_pm_domain_init, they
are guaranteed to be "packed" at the beginning of the array, so there
can't be any holes, so break is safe.
On Fri, Feb 7, 2020 at 10:26 PM Ulf Hansson <[email protected]> wrote:
>
> On Fri, 7 Feb 2020 at 06:27, Nicolas Boichat <[email protected]> wrote:
> >
> > When there is a single power domain per device, the core will
> > ensure the power domain is switched on (so it is technically
> > equivalent to having not power domain specified at all).
> >
> > However, when there are multiple domains, as in MT8183 Bifrost
> > GPU, we need to handle them in driver code.
> >
> > Signed-off-by: Nicolas Boichat <[email protected]>
>
> Besides a minor nitpick, feel free to add:
>
> Reviewed-by: Ulf Hansson <[email protected]>
>
> Kind regards
> Uffe
>
> [snip]
> > +static int panfrost_pm_domain_init(struct panfrost_device *pfdev)
> > +{
> > + int err;
> > + int i, num_domains;
> > +
> > + num_domains = of_count_phandle_with_args(pfdev->dev->of_node,
> > + "power-domains",
> > + "#power-domain-cells");
> > +
> > + /*
> > + * Single domain is handled by the core, and, if only a single power
> > + * the power domain is requested, the property is optional.
> > + */
> > + if (num_domains < 2 && pfdev->comp->num_pm_domains < 2)
> > + return 0;
> > +
> > + if (num_domains != pfdev->comp->num_pm_domains) {
> > + dev_err(pfdev->dev,
> > + "Incorrect number of power domains: %d provided, %d needed\n",
> > + num_domains, pfdev->comp->num_pm_domains);
> > + return -EINVAL;
> > + }
> > +
> > + if (WARN(num_domains > ARRAY_SIZE(pfdev->pm_domain_devs),
> > + "Too many supplies in compatible structure.\n"))
>
> Nitpick:
> Not sure this deserves a WARN. Perhaps a regular dev_err() is sufficient.
Ah well I had a BUG_ON before so presumably this is already a little better ,-)
You can only reach there if you set pfdev->comp->num_pm_domains >
MAX_PM_DOMAINS in the currently matched struct panfrost_compatible
(pfdev->comp->num_pm_domains == num_domains, and see below too), so
the kernel code would actually be actually broken (not the device
tree, nor anything that could be probed). So I'm wondering if the
loudness of a WARN is better in this case? Arguable ,-)
> > + return -EINVAL;
> [snip]
> > --- a/drivers/gpu/drm/panfrost/panfrost_device.h
> > +++ b/drivers/gpu/drm/panfrost/panfrost_device.h
> > @@ -21,6 +21,7 @@ struct panfrost_perfcnt;
> >
> > #define NUM_JOB_SLOTS 3
> > #define MAX_REGULATORS 2
> > +#define MAX_PM_DOMAINS 3
> >
> > struct panfrost_features {
> > u16 id;
> > @@ -61,6 +62,13 @@ struct panfrost_compatible {
> > /* Supplies count and names. */
> > int num_supplies;
> > const char * const *supply_names;
> > + /*
> > + * Number of power domains required, note that values 0 and 1 are
> > + * handled identically, as only values > 1 need special handling.
> > + */
> > + int num_pm_domains;
> > + /* Only required if num_pm_domains > 1. */
> > + const char * const *pm_domain_names;
> > };
> >
> > struct panfrost_device {
> > @@ -73,6 +81,9 @@ struct panfrost_device {
> > struct clk *bus_clock;
> > struct regulator_bulk_data regulators[MAX_REGULATORS];
> > struct reset_control *rstc;
> > + /* pm_domains for devices with more than one. */
> > + struct device *pm_domain_devs[MAX_PM_DOMAINS];
> > + struct device_link *pm_domain_links[MAX_PM_DOMAINS];
> >
> > struct panfrost_features features;
> > const struct panfrost_compatible *comp;
> > diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c
> > index 4d08507526239f2..a6e162236d67fdf 100644
> > --- a/drivers/gpu/drm/panfrost/panfrost_drv.c
> > +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c
> > @@ -663,6 +663,8 @@ const char * const default_supplies[] = { "mali" };
> > static const struct panfrost_compatible default_data = {
> > .num_supplies = ARRAY_SIZE(default_supplies),
> > .supply_names = default_supplies,
> > + .num_pm_domains = 1, /* optional */
> > + .pm_domain_names = NULL,
> > };
> >
> > static const struct of_device_id dt_match[] = {
> > --
> > 2.25.0.341.g760bfbb309-goog
> >
On Fri, Feb 7, 2020 at 4:13 PM Tomeu Vizoso <[email protected]> wrote:
>
> On 2/7/20 8:42 AM, Nicolas Boichat wrote:
> > On Fri, Feb 7, 2020 at 2:18 PM Tomeu Vizoso <[email protected]> wrote:
> >>
> >>> Some more changes are still required to get devfreq working, and of course
> >>> I do not have a userspace driver to test this with.
> >>
> >> Have you tried the Panfrost tests in IGT? They are atm quite basic, but
> >> could be interesting to check that the different HW units are correctly
> >> powered on.
> >
> > I haven't, you mean this right?
> > https://gitlab.freedesktop.org/tomeu/igt-gpu-tools/tree/panfrost
>
> Yes, though may be better to use the upstream repo:
>
> https://gitlab.freedesktop.org/drm/igt-gpu-tools
>
> > Any specific test you have in mind?
>
> All the panfrost ones, but looks like panfrost_prime:gem-prime-import is
> failing atm:
>
> https://lava.collabora.co.uk/scheduler/job/2214987
(I first removed opp table from device tree to avoid constant spew
about devfreq not supporting 2 regulators, I should get around to fix
that...)
# /usr/libexec/igt-gpu-tools/panfrost_gem_new
IGT-Version: 1.24-gd4d574a4 (arm) (Linux: 4.19.99 aarch64)
Starting subtest: gem-new-4096
Subtest gem-new-4096: SUCCESS (0.000s)
Starting subtest: gem-new-0
Subtest gem-new-0: SUCCESS (0.000s)
Starting subtest: gem-new-zeroed
Subtest gem-new-zeroed: SUCCESS (0.001s)
# /usr/libexec/igt-gpu-tools/panfrost_get_param
IGT-Version: 1.24-gd4d574a4 (arm) (Linux: 4.19.99 aarch64)
Starting subtest: base-params
Subtest base-params: SUCCESS (0.000s)
Starting subtest: get-bad-param
Subtest get-bad-param: SUCCESS (0.000s)
Starting subtest: get-bad-padding
Subtest get-bad-padding: SUCCESS (0.000s)
# /usr/libexec/igt-gpu-tools/panfrost_prime
IGT-Version: 1.24-gd4d574a4 (arm) (Linux: 4.19.99 aarch64)
Starting subtest: gem-prime-import
(panfrost_prime:1527) ioctl_wrappers-CRITICAL: Test assertion failure
function prime_fd_to_handle, file
../igt-gpu-tools-9999/lib/ioctl_wrappers.c:1336:
(panfrost_prime:1527) ioctl_wrappers-CRITICAL: Failed assertion:
igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) |
(((0x2e)) << 0) | ((((sizeof(struct drm_prime_handle)))) <<
((0+8)+8)))), (&args)) == 0
(panfrost_prime:1527) ioctl_wrappers-CRITICAL: Last errno: 95,
Operation not supported
(panfrost_prime:1527) ioctl_wrappers-CRITICAL: error: -1 != 0
Stack trace:
Subtest gem-prime-import failed.
Subtest gem-prime-import: FAIL (0.004s)
(but that looks expected?)
Now the trickier ones, I guess we're either missing something, or my
dirty 4.19 backport is very broken:
# /usr/libexec/igt-gpu-tools/panfrost_submit
IGT-Version: 1.24-gd4d574a4 (arm) (Linux: 4.19.99 aarch64)
Starting subtest: pan-submit
(panfrost_submit:1643) CRITICAL: Test assertion failure function
__real_main86, file ../igt-gpu-tools-9999/tests/panfrost_submit.c:103:
(panfrost_submit:1643) CRITICAL: Failed assertion: syncobj_wait(fd,
&submit->args->out_sync, 1, abs_timeout(SHORT_TIME_NSEC), 0, NULL)
Stack trace:
Subtest pan-submit failed.
**** DEBUG ****
(panfrost_submit:1643) CRITICAL: Test assertion failure function
__real_main86, file ../igt-gpu-tools-9999/tests/panfrost_submit.c:103:
(panfrost_submit:1643) CRITICAL: Failed assertion: syncobj_wait(fd,
&submit->args->out_sync, 1, abs_timeout(SHORT_TIME_NSEC), 0, NULL)
(panfrost_submit:1643) igt_core-INFO: Stack trace:
**** END ****
Subtest pan-submit: FAIL (0.119s)
Starting subtest: pan-submit-error-no-jc
Subtest pan-submit-error-no-jc: SUCCESS (0.000s)
Starting subtest: pan-submit-error-bad-in-syncs
Subtest pan-submit-error-bad-in-syncs: SUCCESS (0.012s)
Starting subtest: pan-submit-error-bad-bo-handles
Subtest pan-submit-error-bad-bo-handles: SUCCESS (0.012s)
Starting subtest: pan-submit-error-bad-requirements
Subtest pan-submit-error-bad-requirements: SUCCESS (0.012s)
Starting subtest: pan-submit-error-bad-out-sync
Subtest pan-submit-error-bad-out-sync: SUCCESS (0.012s)
Starting subtest: pan-reset
(panfrost_submit:1643) CRITICAL: Test assertion failure function
__real_main86, file ../igt-gpu-tools-9999/tests/panfrost_submit.c:173:
(panfrost_submit:1643) CRITICAL: Failed assertion: syncobj_wait(fd,
&submit->args->out_sync, 1, abs_timeout(BAD_JOB_TIME_NSEC), 0, NULL)
Stack trace:
Subtest pan-reset failed.
**** DEBUG ****
(panfrost_submit:1643) CRITICAL: Test assertion failure function
__real_main86, file ../igt-gpu-tools-9999/tests/panfrost_submit.c:173:
(panfrost_submit:1643) CRITICAL: Failed assertion: syncobj_wait(fd,
&submit->args->out_sync, 1, abs_timeout(BAD_JOB_TIME_NSEC), 0, NULL)
(panfrost_submit:1643) igt_core-INFO: Stack trace:
**** END ****
Subtest pan-reset: FAIL (0.840s)
The pan-submit case causes an MMU fault:
(full log: https://gist.github.com/drinkcat/1ae36cb1b1b71f30cc4fc29759612d76)
[ 1215.234937] [IGT] panfrost_submit: executing
[ 1215.318446] [IGT] panfrost_submit: starting subtest pan-submit
...
[ 1215.338644] panfrost 13040000.gpu: Unhandled Page fault in AS0 at
VA 0x000000FF00000000
Reason: TODO
raw fault status: 0xA002C0
decoded fault status: SLAVE FAULT
exception type 0xC0: UNKNOWN
access type 0x2: READ
source id 0xA0
[ 1215.444504] [IGT] panfrost_submit: exiting, ret=98
...
[ 1215.446902] panfrost 13040000.gpu: js fault, js=0,
status=JOB_BUS_FAULT, head=0x300b000, tail=0x300b000
[ 1215.446935] panfrost 13040000.gpu: Unhandled Page fault in AS0 at
VA 0x000000FF00000000
Reason: TODO
raw fault status: 0xA002C0
decoded fault status: SLAVE FAULT
exception type 0xC0: UNKNOWN
access type 0x2: READ
source id 0xA0
pan-reset failure looks similar:
https://gist.github.com/drinkcat/2d336d57e6b95262d83e7a28a409bc5b
Thanks,
> Cheers,
>
> Tomeu
>
> > Thanks,
> >
> >> Regards,
> >>
> >> Tomeu
> >>
> >>> I believe at least patches 1, 2, and 3 can be merged. 4 and 5 are mostly
> >>> useful in conjunction with 6 and 7 (which are not ready yet), so I'll let
> >>> maintainers decide.
> >>>
> >>> Thanks!
> >>>
> >>> Nicolas Boichat (7):
> >>> dt-bindings: gpu: mali-bifrost: Add Mediatek MT8183
> >>> arm64: dts: mt8183: Add node for the Mali GPU
> >>> drm/panfrost: Improve error reporting in panfrost_gpu_power_on
> >>> drm/panfrost: Add support for multiple regulators
> >>> drm/panfrost: Add support for multiple power domains
> >>> RFC: drm/panfrost: Add mt8183-mali compatible string
> >>> RFC: drm/panfrost: devfreq: Add support for 2 regulators
> >>>
> >>> .../bindings/gpu/arm,mali-bifrost.yaml | 25 ++++
> >>> arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 7 +
> >>> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 105 +++++++++++++++
> >>> drivers/gpu/drm/panfrost/panfrost_devfreq.c | 17 +++
> >>> drivers/gpu/drm/panfrost/panfrost_device.c | 123 +++++++++++++++---
> >>> drivers/gpu/drm/panfrost/panfrost_device.h | 27 +++-
> >>> drivers/gpu/drm/panfrost/panfrost_drv.c | 41 ++++--
> >>> drivers/gpu/drm/panfrost/panfrost_gpu.c | 11 +-
> >>> 8 files changed, 326 insertions(+), 30 deletions(-)
> >>>
On Sun, 9 Feb 2020 at 13:50, Nicolas Boichat <[email protected]> wrote:
>
> On Fri, Feb 7, 2020 at 10:26 PM Ulf Hansson <[email protected]> wrote:
> >
> > On Fri, 7 Feb 2020 at 06:27, Nicolas Boichat <[email protected]> wrote:
> > >
> > > When there is a single power domain per device, the core will
> > > ensure the power domain is switched on (so it is technically
> > > equivalent to having not power domain specified at all).
> > >
> > > However, when there are multiple domains, as in MT8183 Bifrost
> > > GPU, we need to handle them in driver code.
> > >
> > > Signed-off-by: Nicolas Boichat <[email protected]>
> >
> > Besides a minor nitpick, feel free to add:
> >
> > Reviewed-by: Ulf Hansson <[email protected]>
> >
> > Kind regards
> > Uffe
> >
> > [snip]
> > > +static int panfrost_pm_domain_init(struct panfrost_device *pfdev)
> > > +{
> > > + int err;
> > > + int i, num_domains;
> > > +
> > > + num_domains = of_count_phandle_with_args(pfdev->dev->of_node,
> > > + "power-domains",
> > > + "#power-domain-cells");
> > > +
> > > + /*
> > > + * Single domain is handled by the core, and, if only a single power
> > > + * the power domain is requested, the property is optional.
> > > + */
> > > + if (num_domains < 2 && pfdev->comp->num_pm_domains < 2)
> > > + return 0;
> > > +
> > > + if (num_domains != pfdev->comp->num_pm_domains) {
> > > + dev_err(pfdev->dev,
> > > + "Incorrect number of power domains: %d provided, %d needed\n",
> > > + num_domains, pfdev->comp->num_pm_domains);
> > > + return -EINVAL;
> > > + }
> > > +
> > > + if (WARN(num_domains > ARRAY_SIZE(pfdev->pm_domain_devs),
> > > + "Too many supplies in compatible structure.\n"))
> >
> > Nitpick:
> > Not sure this deserves a WARN. Perhaps a regular dev_err() is sufficient.
>
> Ah well I had a BUG_ON before so presumably this is already a little better ,-)
>
> You can only reach there if you set pfdev->comp->num_pm_domains >
> MAX_PM_DOMAINS in the currently matched struct panfrost_compatible
> (pfdev->comp->num_pm_domains == num_domains, and see below too), so
> the kernel code would actually be actually broken (not the device
> tree, nor anything that could be probed). So I'm wondering if the
> loudness of a WARN is better in this case? Arguable ,-)
I see. It's not a big a deal, so feel free to keep as is.
[...]
Kind regards
Uffe
On 2/10/20 4:39 AM, Nicolas Boichat wrote:
> On Fri, Feb 7, 2020 at 4:13 PM Tomeu Vizoso <[email protected]> wrote:
>>
>> On 2/7/20 8:42 AM, Nicolas Boichat wrote:
>>> On Fri, Feb 7, 2020 at 2:18 PM Tomeu Vizoso <[email protected]> wrote:
>>>>
>>>>> Some more changes are still required to get devfreq working, and of course
>>>>> I do not have a userspace driver to test this with.
>>>>
>>>> Have you tried the Panfrost tests in IGT? They are atm quite basic, but
>>>> could be interesting to check that the different HW units are correctly
>>>> powered on.
>>>
>>> I haven't, you mean this right?
>>> https://gitlab.freedesktop.org/tomeu/igt-gpu-tools/tree/panfrost
>>
>> Yes, though may be better to use the upstream repo:
>>
>> https://gitlab.freedesktop.org/drm/igt-gpu-tools
>>
>>> Any specific test you have in mind?
>>
>> All the panfrost ones, but looks like panfrost_prime:gem-prime-import is
>> failing atm:
>>
>> https://lava.collabora.co.uk/scheduler/job/2214987
>
> (I first removed opp table from device tree to avoid constant spew
> about devfreq not supporting 2 regulators, I should get around to fix
> that...)
>
> # /usr/libexec/igt-gpu-tools/panfrost_gem_new
> IGT-Version: 1.24-gd4d574a4 (arm) (Linux: 4.19.99 aarch64)
> Starting subtest: gem-new-4096
> Subtest gem-new-4096: SUCCESS (0.000s)
> Starting subtest: gem-new-0
> Subtest gem-new-0: SUCCESS (0.000s)
> Starting subtest: gem-new-zeroed
> Subtest gem-new-zeroed: SUCCESS (0.001s)
> # /usr/libexec/igt-gpu-tools/panfrost_get_param
> IGT-Version: 1.24-gd4d574a4 (arm) (Linux: 4.19.99 aarch64)
> Starting subtest: base-params
> Subtest base-params: SUCCESS (0.000s)
> Starting subtest: get-bad-param
> Subtest get-bad-param: SUCCESS (0.000s)
> Starting subtest: get-bad-padding
> Subtest get-bad-padding: SUCCESS (0.000s)
> # /usr/libexec/igt-gpu-tools/panfrost_prime
> IGT-Version: 1.24-gd4d574a4 (arm) (Linux: 4.19.99 aarch64)
> Starting subtest: gem-prime-import
> (panfrost_prime:1527) ioctl_wrappers-CRITICAL: Test assertion failure
> function prime_fd_to_handle, file
> ../igt-gpu-tools-9999/lib/ioctl_wrappers.c:1336:
> (panfrost_prime:1527) ioctl_wrappers-CRITICAL: Failed assertion:
> igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) |
> (((0x2e)) << 0) | ((((sizeof(struct drm_prime_handle)))) <<
> ((0+8)+8)))), (&args)) == 0
> (panfrost_prime:1527) ioctl_wrappers-CRITICAL: Last errno: 95,
> Operation not supported
> (panfrost_prime:1527) ioctl_wrappers-CRITICAL: error: -1 != 0
> Stack trace:
> Subtest gem-prime-import failed.
> Subtest gem-prime-import: FAIL (0.004s)
> (but that looks expected?)
Yep, haven't gotten to investigate yet.
> Now the trickier ones, I guess we're either missing something, or my
> dirty 4.19 backport is very broken:
Damn, looks like the simple job we use to test submits doesn't work as-is
on your GPU.
But things seem to work otherwise, so probably the kernel driver is fully
functional with your changes.
Cheers,
Tomeu
> # /usr/libexec/igt-gpu-tools/panfrost_submit
> IGT-Version: 1.24-gd4d574a4 (arm) (Linux: 4.19.99 aarch64)
> Starting subtest: pan-submit
> (panfrost_submit:1643) CRITICAL: Test assertion failure function
> __real_main86, file ../igt-gpu-tools-9999/tests/panfrost_submit.c:103:
> (panfrost_submit:1643) CRITICAL: Failed assertion: syncobj_wait(fd,
> &submit->args->out_sync, 1, abs_timeout(SHORT_TIME_NSEC), 0, NULL)
> Stack trace:
> Subtest pan-submit failed.
> **** DEBUG ****
> (panfrost_submit:1643) CRITICAL: Test assertion failure function
> __real_main86, file ../igt-gpu-tools-9999/tests/panfrost_submit.c:103:
> (panfrost_submit:1643) CRITICAL: Failed assertion: syncobj_wait(fd,
> &submit->args->out_sync, 1, abs_timeout(SHORT_TIME_NSEC), 0, NULL)
> (panfrost_submit:1643) igt_core-INFO: Stack trace:
> **** END ****
> Subtest pan-submit: FAIL (0.119s)
> Starting subtest: pan-submit-error-no-jc
> Subtest pan-submit-error-no-jc: SUCCESS (0.000s)
> Starting subtest: pan-submit-error-bad-in-syncs
> Subtest pan-submit-error-bad-in-syncs: SUCCESS (0.012s)
> Starting subtest: pan-submit-error-bad-bo-handles
> Subtest pan-submit-error-bad-bo-handles: SUCCESS (0.012s)
> Starting subtest: pan-submit-error-bad-requirements
> Subtest pan-submit-error-bad-requirements: SUCCESS (0.012s)
> Starting subtest: pan-submit-error-bad-out-sync
> Subtest pan-submit-error-bad-out-sync: SUCCESS (0.012s)
> Starting subtest: pan-reset
> (panfrost_submit:1643) CRITICAL: Test assertion failure function
> __real_main86, file ../igt-gpu-tools-9999/tests/panfrost_submit.c:173:
> (panfrost_submit:1643) CRITICAL: Failed assertion: syncobj_wait(fd,
> &submit->args->out_sync, 1, abs_timeout(BAD_JOB_TIME_NSEC), 0, NULL)
> Stack trace:
> Subtest pan-reset failed.
> **** DEBUG ****
> (panfrost_submit:1643) CRITICAL: Test assertion failure function
> __real_main86, file ../igt-gpu-tools-9999/tests/panfrost_submit.c:173:
> (panfrost_submit:1643) CRITICAL: Failed assertion: syncobj_wait(fd,
> &submit->args->out_sync, 1, abs_timeout(BAD_JOB_TIME_NSEC), 0, NULL)
> (panfrost_submit:1643) igt_core-INFO: Stack trace:
> **** END ****
> Subtest pan-reset: FAIL (0.840s)
>
> The pan-submit case causes an MMU fault:
> (full log: https://gist.github.com/drinkcat/1ae36cb1b1b71f30cc4fc29759612d76)
>
> [ 1215.234937] [IGT] panfrost_submit: executing
> [ 1215.318446] [IGT] panfrost_submit: starting subtest pan-submit
> ...
> [ 1215.338644] panfrost 13040000.gpu: Unhandled Page fault in AS0 at
> VA 0x000000FF00000000
> Reason: TODO
> raw fault status: 0xA002C0
> decoded fault status: SLAVE FAULT
> exception type 0xC0: UNKNOWN
> access type 0x2: READ
> source id 0xA0
> [ 1215.444504] [IGT] panfrost_submit: exiting, ret=98
> ...
> [ 1215.446902] panfrost 13040000.gpu: js fault, js=0,
> status=JOB_BUS_FAULT, head=0x300b000, tail=0x300b000
> [ 1215.446935] panfrost 13040000.gpu: Unhandled Page fault in AS0 at
> VA 0x000000FF00000000
> Reason: TODO
> raw fault status: 0xA002C0
> decoded fault status: SLAVE FAULT
> exception type 0xC0: UNKNOWN
> access type 0x2: READ
> source id 0xA0
>
> pan-reset failure looks similar:
> https://gist.github.com/drinkcat/2d336d57e6b95262d83e7a28a409bc5b
>
> Thanks,
>
>> Cheers,
>>
>> Tomeu
>>
>>> Thanks,
>>>
>>>> Regards,
>>>>
>>>> Tomeu
>>>>
>>>>> I believe at least patches 1, 2, and 3 can be merged. 4 and 5 are mostly
>>>>> useful in conjunction with 6 and 7 (which are not ready yet), so I'll let
>>>>> maintainers decide.
>>>>>
>>>>> Thanks!
>>>>>
>>>>> Nicolas Boichat (7):
>>>>> dt-bindings: gpu: mali-bifrost: Add Mediatek MT8183
>>>>> arm64: dts: mt8183: Add node for the Mali GPU
>>>>> drm/panfrost: Improve error reporting in panfrost_gpu_power_on
>>>>> drm/panfrost: Add support for multiple regulators
>>>>> drm/panfrost: Add support for multiple power domains
>>>>> RFC: drm/panfrost: Add mt8183-mali compatible string
>>>>> RFC: drm/panfrost: devfreq: Add support for 2 regulators
>>>>>
>>>>> .../bindings/gpu/arm,mali-bifrost.yaml | 25 ++++
>>>>> arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 7 +
>>>>> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 105 +++++++++++++++
>>>>> drivers/gpu/drm/panfrost/panfrost_devfreq.c | 17 +++
>>>>> drivers/gpu/drm/panfrost/panfrost_device.c | 123 +++++++++++++++---
>>>>> drivers/gpu/drm/panfrost/panfrost_device.h | 27 +++-
>>>>> drivers/gpu/drm/panfrost/panfrost_drv.c | 41 ++++--
>>>>> drivers/gpu/drm/panfrost/panfrost_gpu.c | 11 +-
>>>>> 8 files changed, 326 insertions(+), 30 deletions(-)
>>>>>
On 07/02/2020 05:26, Nicolas Boichat wrote:
> Some GPUs, namely, the bifrost/g72 part on MT8183, have a second
> regulator for their SRAM, let's add support for that.
>
> We extend the framework in a generic manner so that we could
> support more than 2 regulators, if required.
>
> Signed-off-by: Nicolas Boichat <[email protected]>
Reviewed-by: Steven Price <[email protected]>
Thanks,
Steve
>
> ---
>
> v4:
> - nits: Run through latest version of checkpatch:
> - Use WARN instead of BUG_ON.
> - Drop braces in single expression for loop.
> - *comp not * comp
> v3:
> - Make this more generic, by allowing any number of regulators
> (in practice we fix the maximum number of regulators to 2, but
> this could be increased easily).
> - We only probe the second regulator if the device tree matching
> data asks for it.
> - I couldn't find a way to detect the number of regulators in the
> device tree, if we wanted to refuse to probe the device if there
> are too many regulators, which might be required for safety, see
> the thread on v2 [1].
> - The discussion also included the idea of a separate device tree
> entry for a "soft PDC", or at least a separate driver. I'm not
> sure to understand the full picture, and how different vendors
> implement this, so I'm still integrating everything in the main
> driver. I'd be happy to try to make mt8183 fit into such a
> framework after it's created, but I don't think I'm best placed
> to implement (and again, the main purpose of this was to test
> if the binding is correct).
>
> [1] https://patchwork.kernel.org/patch/11322839/
>
> drivers/gpu/drm/panfrost/panfrost_device.c | 26 +++++++++++++-------
> drivers/gpu/drm/panfrost/panfrost_device.h | 15 +++++++++++-
> drivers/gpu/drm/panfrost/panfrost_drv.c | 28 +++++++++++++++-------
> 3 files changed, 51 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/panfrost/panfrost_device.c
> index 238fb6d54df4732..3720d50f6d9f965 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_device.c
> +++ b/drivers/gpu/drm/panfrost/panfrost_device.c
> @@ -87,18 +87,27 @@ static void panfrost_clk_fini(struct panfrost_device *pfdev)
>
> static int panfrost_regulator_init(struct panfrost_device *pfdev)
> {
> - int ret;
> + int ret, i;
>
> - pfdev->regulator = devm_regulator_get(pfdev->dev, "mali");
> - if (IS_ERR(pfdev->regulator)) {
> - ret = PTR_ERR(pfdev->regulator);
> - dev_err(pfdev->dev, "failed to get regulator: %d\n", ret);
> + if (WARN(pfdev->comp->num_supplies > ARRAY_SIZE(pfdev->regulators),
> + "Too many supplies in compatible structure.\n"))
> + return -EINVAL;
> +
> + for (i = 0; i < pfdev->comp->num_supplies; i++)
> + pfdev->regulators[i].supply = pfdev->comp->supply_names[i];
> +
> + ret = devm_regulator_bulk_get(pfdev->dev,
> + pfdev->comp->num_supplies,
> + pfdev->regulators);
> + if (ret < 0) {
> + dev_err(pfdev->dev, "failed to get regulators: %d\n", ret);
> return ret;
> }
>
> - ret = regulator_enable(pfdev->regulator);
> + ret = regulator_bulk_enable(pfdev->comp->num_supplies,
> + pfdev->regulators);
> if (ret < 0) {
> - dev_err(pfdev->dev, "failed to enable regulator: %d\n", ret);
> + dev_err(pfdev->dev, "failed to enable regulators: %d\n", ret);
> return ret;
> }
>
> @@ -107,7 +116,8 @@ static int panfrost_regulator_init(struct panfrost_device *pfdev)
>
> static void panfrost_regulator_fini(struct panfrost_device *pfdev)
> {
> - regulator_disable(pfdev->regulator);
> + regulator_bulk_disable(pfdev->comp->num_supplies,
> + pfdev->regulators);
> }
>
> int panfrost_device_init(struct panfrost_device *pfdev)
> diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h
> index 06713811b92cdf7..c9468bc5573ac9d 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_device.h
> +++ b/drivers/gpu/drm/panfrost/panfrost_device.h
> @@ -7,6 +7,7 @@
>
> #include <linux/atomic.h>
> #include <linux/io-pgtable.h>
> +#include <linux/regulator/consumer.h>
> #include <linux/spinlock.h>
> #include <drm/drm_device.h>
> #include <drm/drm_mm.h>
> @@ -19,6 +20,7 @@ struct panfrost_job;
> struct panfrost_perfcnt;
>
> #define NUM_JOB_SLOTS 3
> +#define MAX_REGULATORS 2
>
> struct panfrost_features {
> u16 id;
> @@ -51,6 +53,16 @@ struct panfrost_features {
> unsigned long hw_issues[64 / BITS_PER_LONG];
> };
>
> +/*
> + * Features that cannot be automatically detected and need matching using the
> + * compatible string, typically SoC-specific.
> + */
> +struct panfrost_compatible {
> + /* Supplies count and names. */
> + int num_supplies;
> + const char * const *supply_names;
> +};
> +
> struct panfrost_device {
> struct device *dev;
> struct drm_device *ddev;
> @@ -59,10 +71,11 @@ struct panfrost_device {
> void __iomem *iomem;
> struct clk *clock;
> struct clk *bus_clock;
> - struct regulator *regulator;
> + struct regulator_bulk_data regulators[MAX_REGULATORS];
> struct reset_control *rstc;
>
> struct panfrost_features features;
> + const struct panfrost_compatible *comp;
>
> spinlock_t as_lock;
> unsigned long as_in_use_mask;
> diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c
> index b7a618db3ee223e..4d08507526239f2 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_drv.c
> +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c
> @@ -584,6 +584,10 @@ static int panfrost_probe(struct platform_device *pdev)
>
> platform_set_drvdata(pdev, pfdev);
>
> + pfdev->comp = of_device_get_match_data(&pdev->dev);
> + if (!pfdev->comp)
> + return -ENODEV;
> +
> /* Allocate and initialze the DRM device. */
> ddev = drm_dev_alloc(&panfrost_drm_driver, &pdev->dev);
> if (IS_ERR(ddev))
> @@ -655,16 +659,22 @@ static int panfrost_remove(struct platform_device *pdev)
> return 0;
> }
>
> +const char * const default_supplies[] = { "mali" };
> +static const struct panfrost_compatible default_data = {
> + .num_supplies = ARRAY_SIZE(default_supplies),
> + .supply_names = default_supplies,
> +};
> +
> static const struct of_device_id dt_match[] = {
> - { .compatible = "arm,mali-t604" },
> - { .compatible = "arm,mali-t624" },
> - { .compatible = "arm,mali-t628" },
> - { .compatible = "arm,mali-t720" },
> - { .compatible = "arm,mali-t760" },
> - { .compatible = "arm,mali-t820" },
> - { .compatible = "arm,mali-t830" },
> - { .compatible = "arm,mali-t860" },
> - { .compatible = "arm,mali-t880" },
> + { .compatible = "arm,mali-t604", .data = &default_data, },
> + { .compatible = "arm,mali-t624", .data = &default_data, },
> + { .compatible = "arm,mali-t628", .data = &default_data, },
> + { .compatible = "arm,mali-t720", .data = &default_data, },
> + { .compatible = "arm,mali-t760", .data = &default_data, },
> + { .compatible = "arm,mali-t820", .data = &default_data, },
> + { .compatible = "arm,mali-t830", .data = &default_data, },
> + { .compatible = "arm,mali-t860", .data = &default_data, },
> + { .compatible = "arm,mali-t880", .data = &default_data, },
> {}
> };
> MODULE_DEVICE_TABLE(of, dt_match);
>
On 07/02/2020 05:26, Nicolas Boichat wrote:
> When there is a single power domain per device, the core will
> ensure the power domain is switched on (so it is technically
> equivalent to having not power domain specified at all).
>
> However, when there are multiple domains, as in MT8183 Bifrost
> GPU, we need to handle them in driver code.
>
> Signed-off-by: Nicolas Boichat <[email protected]>
LGTM!
Reviewed-by: Steven Price <[email protected]>
Thanks,
Steve
>
> ---
>
> The downstream driver we use on chromeos-4.19 currently uses 2
> additional devices in device tree to accomodate for this [1], but
> I believe this solution is cleaner.
>
> [1] https://chromium.googlesource.com/chromiumos/third_party/kernel/+/refs/heads/chromeos-4.19/drivers/gpu/arm/midgard/platform/mediatek/mali_kbase_runtime_pm.c#31
>
> v4:
> - Match the exact power domain names as specified in the compatible
> struct, instead of just matching the number of power domains.
> [Review: Ulf Hansson]
> - Dropped print and reordered function [Review: Steven Price]
> - nits: Run through latest version of checkpatch:
> - Use WARN instead of BUG_ON.
> - Drop braces for single expression if block.
> v3:
> - Use the compatible matching data to specify the number of power
> domains. Note that setting 0 or 1 in num_pm_domains is equivalent
> as the core will handle these 2 cases in the exact same way
> (automatically, without driver intervention), and there should
> be no adverse consequence in this case (the concern is about
> switching on only some power domains and not others).
>
> drivers/gpu/drm/panfrost/panfrost_device.c | 97 ++++++++++++++++++++--
> drivers/gpu/drm/panfrost/panfrost_device.h | 11 +++
> drivers/gpu/drm/panfrost/panfrost_drv.c | 2 +
> 3 files changed, 102 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/panfrost/panfrost_device.c
> index 3720d50f6d9f965..8136babd3ba9935 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_device.c
> +++ b/drivers/gpu/drm/panfrost/panfrost_device.c
> @@ -5,6 +5,7 @@
> #include <linux/clk.h>
> #include <linux/reset.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> #include <linux/regulator/consumer.h>
>
> #include "panfrost_device.h"
> @@ -120,6 +121,79 @@ static void panfrost_regulator_fini(struct panfrost_device *pfdev)
> pfdev->regulators);
> }
>
> +static void panfrost_pm_domain_fini(struct panfrost_device *pfdev)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(pfdev->pm_domain_devs); i++) {
> + if (!pfdev->pm_domain_devs[i])
> + break;
> +
> + if (pfdev->pm_domain_links[i])
> + device_link_del(pfdev->pm_domain_links[i]);
> +
> + dev_pm_domain_detach(pfdev->pm_domain_devs[i], true);
> + }
> +}
> +
> +static int panfrost_pm_domain_init(struct panfrost_device *pfdev)
> +{
> + int err;
> + int i, num_domains;
> +
> + num_domains = of_count_phandle_with_args(pfdev->dev->of_node,
> + "power-domains",
> + "#power-domain-cells");
> +
> + /*
> + * Single domain is handled by the core, and, if only a single power
> + * the power domain is requested, the property is optional.
> + */
> + if (num_domains < 2 && pfdev->comp->num_pm_domains < 2)
> + return 0;
> +
> + if (num_domains != pfdev->comp->num_pm_domains) {
> + dev_err(pfdev->dev,
> + "Incorrect number of power domains: %d provided, %d needed\n",
> + num_domains, pfdev->comp->num_pm_domains);
> + return -EINVAL;
> + }
> +
> + if (WARN(num_domains > ARRAY_SIZE(pfdev->pm_domain_devs),
> + "Too many supplies in compatible structure.\n"))
> + return -EINVAL;
> +
> + for (i = 0; i < num_domains; i++) {
> + pfdev->pm_domain_devs[i] =
> + dev_pm_domain_attach_by_name(pfdev->dev,
> + pfdev->comp->pm_domain_names[i]);
> + if (IS_ERR_OR_NULL(pfdev->pm_domain_devs[i])) {
> + err = PTR_ERR(pfdev->pm_domain_devs[i]) ? : -ENODATA;
> + pfdev->pm_domain_devs[i] = NULL;
> + dev_err(pfdev->dev,
> + "failed to get pm-domain %s(%d): %d\n",
> + pfdev->comp->pm_domain_names[i], i, err);
> + goto err;
> + }
> +
> + pfdev->pm_domain_links[i] = device_link_add(pfdev->dev,
> + pfdev->pm_domain_devs[i], DL_FLAG_PM_RUNTIME |
> + DL_FLAG_STATELESS | DL_FLAG_RPM_ACTIVE);
> + if (!pfdev->pm_domain_links[i]) {
> + dev_err(pfdev->pm_domain_devs[i],
> + "adding device link failed!\n");
> + err = -ENODEV;
> + goto err;
> + }
> + }
> +
> + return 0;
> +
> +err:
> + panfrost_pm_domain_fini(pfdev);
> + return err;
> +}
> +
> int panfrost_device_init(struct panfrost_device *pfdev)
> {
> int err;
> @@ -150,37 +224,43 @@ int panfrost_device_init(struct panfrost_device *pfdev)
> goto err_out1;
> }
>
> + err = panfrost_pm_domain_init(pfdev);
> + if (err)
> + goto err_out2;
> +
> res = platform_get_resource(pfdev->pdev, IORESOURCE_MEM, 0);
> pfdev->iomem = devm_ioremap_resource(pfdev->dev, res);
> if (IS_ERR(pfdev->iomem)) {
> dev_err(pfdev->dev, "failed to ioremap iomem\n");
> err = PTR_ERR(pfdev->iomem);
> - goto err_out2;
> + goto err_out3;
> }
>
> err = panfrost_gpu_init(pfdev);
> if (err)
> - goto err_out2;
> + goto err_out3;
>
> err = panfrost_mmu_init(pfdev);
> if (err)
> - goto err_out3;
> + goto err_out4;
>
> err = panfrost_job_init(pfdev);
> if (err)
> - goto err_out4;
> + goto err_out5;
>
> err = panfrost_perfcnt_init(pfdev);
> if (err)
> - goto err_out5;
> + goto err_out6;
>
> return 0;
> -err_out5:
> +err_out6:
> panfrost_job_fini(pfdev);
> -err_out4:
> +err_out5:
> panfrost_mmu_fini(pfdev);
> -err_out3:
> +err_out4:
> panfrost_gpu_fini(pfdev);
> +err_out3:
> + panfrost_pm_domain_fini(pfdev);
> err_out2:
> panfrost_reset_fini(pfdev);
> err_out1:
> @@ -196,6 +276,7 @@ void panfrost_device_fini(struct panfrost_device *pfdev)
> panfrost_job_fini(pfdev);
> panfrost_mmu_fini(pfdev);
> panfrost_gpu_fini(pfdev);
> + panfrost_pm_domain_fini(pfdev);
> panfrost_reset_fini(pfdev);
> panfrost_regulator_fini(pfdev);
> panfrost_clk_fini(pfdev);
> diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h
> index c9468bc5573ac9d..c30c719a805940a 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_device.h
> +++ b/drivers/gpu/drm/panfrost/panfrost_device.h
> @@ -21,6 +21,7 @@ struct panfrost_perfcnt;
>
> #define NUM_JOB_SLOTS 3
> #define MAX_REGULATORS 2
> +#define MAX_PM_DOMAINS 3
>
> struct panfrost_features {
> u16 id;
> @@ -61,6 +62,13 @@ struct panfrost_compatible {
> /* Supplies count and names. */
> int num_supplies;
> const char * const *supply_names;
> + /*
> + * Number of power domains required, note that values 0 and 1 are
> + * handled identically, as only values > 1 need special handling.
> + */
> + int num_pm_domains;
> + /* Only required if num_pm_domains > 1. */
> + const char * const *pm_domain_names;
> };
>
> struct panfrost_device {
> @@ -73,6 +81,9 @@ struct panfrost_device {
> struct clk *bus_clock;
> struct regulator_bulk_data regulators[MAX_REGULATORS];
> struct reset_control *rstc;
> + /* pm_domains for devices with more than one. */
> + struct device *pm_domain_devs[MAX_PM_DOMAINS];
> + struct device_link *pm_domain_links[MAX_PM_DOMAINS];
>
> struct panfrost_features features;
> const struct panfrost_compatible *comp;
> diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c
> index 4d08507526239f2..a6e162236d67fdf 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_drv.c
> +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c
> @@ -663,6 +663,8 @@ const char * const default_supplies[] = { "mali" };
> static const struct panfrost_compatible default_data = {
> .num_supplies = ARRAY_SIZE(default_supplies),
> .supply_names = default_supplies,
> + .num_pm_domains = 1, /* optional */
> + .pm_domain_names = NULL,
> };
>
> static const struct of_device_id dt_match[] = {
>
On Fri, Feb 07, 2020 at 01:26:24PM +0800, Nicolas Boichat wrote:
> Some GPUs, namely, the bifrost/g72 part on MT8183, have a second
> regulator for their SRAM, let's add support for that.
Reviwed-by: Mark Brown <[email protected]>
+Saravana
On Thu, Feb 6, 2020 at 11:27 PM Nicolas Boichat <[email protected]> wrote:
>
> When there is a single power domain per device, the core will
> ensure the power domain is switched on (so it is technically
> equivalent to having not power domain specified at all).
>
> However, when there are multiple domains, as in MT8183 Bifrost
> GPU, we need to handle them in driver code.
>
> Signed-off-by: Nicolas Boichat <[email protected]>
>
> ---
>
> The downstream driver we use on chromeos-4.19 currently uses 2
> additional devices in device tree to accomodate for this [1], but
> I believe this solution is cleaner.
>
> [1] https://chromium.googlesource.com/chromiumos/third_party/kernel/+/refs/heads/chromeos-4.19/drivers/gpu/arm/midgard/platform/mediatek/mali_kbase_runtime_pm.c#31
>
> v4:
> - Match the exact power domain names as specified in the compatible
> struct, instead of just matching the number of power domains.
> [Review: Ulf Hansson]
> - Dropped print and reordered function [Review: Steven Price]
> - nits: Run through latest version of checkpatch:
> - Use WARN instead of BUG_ON.
> - Drop braces for single expression if block.
> v3:
> - Use the compatible matching data to specify the number of power
> domains. Note that setting 0 or 1 in num_pm_domains is equivalent
> as the core will handle these 2 cases in the exact same way
> (automatically, without driver intervention), and there should
> be no adverse consequence in this case (the concern is about
> switching on only some power domains and not others).
>
> drivers/gpu/drm/panfrost/panfrost_device.c | 97 ++++++++++++++++++++--
> drivers/gpu/drm/panfrost/panfrost_device.h | 11 +++
> drivers/gpu/drm/panfrost/panfrost_drv.c | 2 +
> 3 files changed, 102 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/panfrost/panfrost_device.c
> index 3720d50f6d9f965..8136babd3ba9935 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_device.c
> +++ b/drivers/gpu/drm/panfrost/panfrost_device.c
> @@ -5,6 +5,7 @@
> #include <linux/clk.h>
> #include <linux/reset.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> #include <linux/regulator/consumer.h>
>
> #include "panfrost_device.h"
> @@ -120,6 +121,79 @@ static void panfrost_regulator_fini(struct panfrost_device *pfdev)
> pfdev->regulators);
> }
>
> +static void panfrost_pm_domain_fini(struct panfrost_device *pfdev)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(pfdev->pm_domain_devs); i++) {
> + if (!pfdev->pm_domain_devs[i])
> + break;
> +
> + if (pfdev->pm_domain_links[i])
> + device_link_del(pfdev->pm_domain_links[i]);
> +
> + dev_pm_domain_detach(pfdev->pm_domain_devs[i], true);
> + }
> +}
> +
> +static int panfrost_pm_domain_init(struct panfrost_device *pfdev)
> +{
> + int err;
> + int i, num_domains;
> +
> + num_domains = of_count_phandle_with_args(pfdev->dev->of_node,
> + "power-domains",
> + "#power-domain-cells");
> +
> + /*
> + * Single domain is handled by the core, and, if only a single power
> + * the power domain is requested, the property is optional.
> + */
> + if (num_domains < 2 && pfdev->comp->num_pm_domains < 2)
> + return 0;
> +
> + if (num_domains != pfdev->comp->num_pm_domains) {
> + dev_err(pfdev->dev,
> + "Incorrect number of power domains: %d provided, %d needed\n",
> + num_domains, pfdev->comp->num_pm_domains);
> + return -EINVAL;
> + }
> +
> + if (WARN(num_domains > ARRAY_SIZE(pfdev->pm_domain_devs),
> + "Too many supplies in compatible structure.\n"))
> + return -EINVAL;
> +
> + for (i = 0; i < num_domains; i++) {
> + pfdev->pm_domain_devs[i] =
> + dev_pm_domain_attach_by_name(pfdev->dev,
> + pfdev->comp->pm_domain_names[i]);
> + if (IS_ERR_OR_NULL(pfdev->pm_domain_devs[i])) {
> + err = PTR_ERR(pfdev->pm_domain_devs[i]) ? : -ENODATA;
> + pfdev->pm_domain_devs[i] = NULL;
> + dev_err(pfdev->dev,
> + "failed to get pm-domain %s(%d): %d\n",
> + pfdev->comp->pm_domain_names[i], i, err);
> + goto err;
> + }
> +
> + pfdev->pm_domain_links[i] = device_link_add(pfdev->dev,
> + pfdev->pm_domain_devs[i], DL_FLAG_PM_RUNTIME |
> + DL_FLAG_STATELESS | DL_FLAG_RPM_ACTIVE);
We're in the process of adding device links based on DT properties.
Shouldn't we add power domains to that? See drivers/of/property.c for
what's handled.
Rob
On Tue, Feb 11, 2020 at 11:44 AM Rob Herring <[email protected]> wrote:
>
> +Saravana
>
> On Thu, Feb 6, 2020 at 11:27 PM Nicolas Boichat <[email protected]> wrote:
> >
> > When there is a single power domain per device, the core will
> > ensure the power domain is switched on (so it is technically
> > equivalent to having not power domain specified at all).
> >
> > However, when there are multiple domains, as in MT8183 Bifrost
> > GPU, we need to handle them in driver code.
> >
> > Signed-off-by: Nicolas Boichat <[email protected]>
> >
> > ---
> >
> > The downstream driver we use on chromeos-4.19 currently uses 2
> > additional devices in device tree to accomodate for this [1], but
> > I believe this solution is cleaner.
> >
> > [1] https://chromium.googlesource.com/chromiumos/third_party/kernel/+/refs/heads/chromeos-4.19/drivers/gpu/arm/midgard/platform/mediatek/mali_kbase_runtime_pm.c#31
> >
> > v4:
> > - Match the exact power domain names as specified in the compatible
> > struct, instead of just matching the number of power domains.
> > [Review: Ulf Hansson]
> > - Dropped print and reordered function [Review: Steven Price]
> > - nits: Run through latest version of checkpatch:
> > - Use WARN instead of BUG_ON.
> > - Drop braces for single expression if block.
> > v3:
> > - Use the compatible matching data to specify the number of power
> > domains. Note that setting 0 or 1 in num_pm_domains is equivalent
> > as the core will handle these 2 cases in the exact same way
> > (automatically, without driver intervention), and there should
> > be no adverse consequence in this case (the concern is about
> > switching on only some power domains and not others).
> >
> > drivers/gpu/drm/panfrost/panfrost_device.c | 97 ++++++++++++++++++++--
> > drivers/gpu/drm/panfrost/panfrost_device.h | 11 +++
> > drivers/gpu/drm/panfrost/panfrost_drv.c | 2 +
> > 3 files changed, 102 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/panfrost/panfrost_device.c
> > index 3720d50f6d9f965..8136babd3ba9935 100644
> > --- a/drivers/gpu/drm/panfrost/panfrost_device.c
> > +++ b/drivers/gpu/drm/panfrost/panfrost_device.c
> > @@ -5,6 +5,7 @@
> > #include <linux/clk.h>
> > #include <linux/reset.h>
> > #include <linux/platform_device.h>
> > +#include <linux/pm_domain.h>
> > #include <linux/regulator/consumer.h>
> >
> > #include "panfrost_device.h"
> > @@ -120,6 +121,79 @@ static void panfrost_regulator_fini(struct panfrost_device *pfdev)
> > pfdev->regulators);
> > }
> >
> > +static void panfrost_pm_domain_fini(struct panfrost_device *pfdev)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(pfdev->pm_domain_devs); i++) {
> > + if (!pfdev->pm_domain_devs[i])
> > + break;
> > +
> > + if (pfdev->pm_domain_links[i])
> > + device_link_del(pfdev->pm_domain_links[i]);
> > +
> > + dev_pm_domain_detach(pfdev->pm_domain_devs[i], true);
> > + }
> > +}
> > +
> > +static int panfrost_pm_domain_init(struct panfrost_device *pfdev)
> > +{
> > + int err;
> > + int i, num_domains;
> > +
> > + num_domains = of_count_phandle_with_args(pfdev->dev->of_node,
> > + "power-domains",
> > + "#power-domain-cells");
> > +
> > + /*
> > + * Single domain is handled by the core, and, if only a single power
> > + * the power domain is requested, the property is optional.
> > + */
> > + if (num_domains < 2 && pfdev->comp->num_pm_domains < 2)
> > + return 0;
> > +
> > + if (num_domains != pfdev->comp->num_pm_domains) {
> > + dev_err(pfdev->dev,
> > + "Incorrect number of power domains: %d provided, %d needed\n",
> > + num_domains, pfdev->comp->num_pm_domains);
> > + return -EINVAL;
> > + }
> > +
> > + if (WARN(num_domains > ARRAY_SIZE(pfdev->pm_domain_devs),
> > + "Too many supplies in compatible structure.\n"))
> > + return -EINVAL;
> > +
> > + for (i = 0; i < num_domains; i++) {
> > + pfdev->pm_domain_devs[i] =
> > + dev_pm_domain_attach_by_name(pfdev->dev,
> > + pfdev->comp->pm_domain_names[i]);
> > + if (IS_ERR_OR_NULL(pfdev->pm_domain_devs[i])) {
> > + err = PTR_ERR(pfdev->pm_domain_devs[i]) ? : -ENODATA;
> > + pfdev->pm_domain_devs[i] = NULL;
> > + dev_err(pfdev->dev,
> > + "failed to get pm-domain %s(%d): %d\n",
> > + pfdev->comp->pm_domain_names[i], i, err);
> > + goto err;
> > + }
> > +
> > + pfdev->pm_domain_links[i] = device_link_add(pfdev->dev,
> > + pfdev->pm_domain_devs[i], DL_FLAG_PM_RUNTIME |
> > + DL_FLAG_STATELESS | DL_FLAG_RPM_ACTIVE);
>
> We're in the process of adding device links based on DT properties.
> Shouldn't we add power domains to that? See drivers/of/property.c for
> what's handled.
Rob,
drivers/of/property.c doesn't enable the RPM_ACTIVE AND PM_RUNTIME
flags. Wanted to start off conservative. But adding command line ops
to change the default flags shouldn't be difficult. But before I do
that, I want to change of_devlink to
fw_devlink=<disabled|permissive|enabled>. May be I can extend that to
"disabled, permissive, suspend, runtime".
Nicholas,
And the adding and removing of device links for power domains will be
a 2 line change. I've been meaning to add a few more bindings like
hwspinlocks and pinctrl. I can roll power domains support into that if
you want.
-Saravana
On Tue, Feb 11, 2020 at 2:09 PM Saravana Kannan <[email protected]> wrote:
>
> On Tue, Feb 11, 2020 at 11:44 AM Rob Herring <[email protected]> wrote:
> >
> > +Saravana
> >
> > On Thu, Feb 6, 2020 at 11:27 PM Nicolas Boichat <[email protected]> wrote:
> > >
> > > When there is a single power domain per device, the core will
> > > ensure the power domain is switched on (so it is technically
> > > equivalent to having not power domain specified at all).
> > >
> > > However, when there are multiple domains, as in MT8183 Bifrost
> > > GPU, we need to handle them in driver code.
> > >
> > > Signed-off-by: Nicolas Boichat <[email protected]>
> > >
> > > ---
> > >
> > > The downstream driver we use on chromeos-4.19 currently uses 2
> > > additional devices in device tree to accomodate for this [1], but
> > > I believe this solution is cleaner.
> > >
> > > [1] https://chromium.googlesource.com/chromiumos/third_party/kernel/+/refs/heads/chromeos-4.19/drivers/gpu/arm/midgard/platform/mediatek/mali_kbase_runtime_pm.c#31
> > >
> > > v4:
> > > - Match the exact power domain names as specified in the compatible
> > > struct, instead of just matching the number of power domains.
> > > [Review: Ulf Hansson]
> > > - Dropped print and reordered function [Review: Steven Price]
> > > - nits: Run through latest version of checkpatch:
> > > - Use WARN instead of BUG_ON.
> > > - Drop braces for single expression if block.
> > > v3:
> > > - Use the compatible matching data to specify the number of power
> > > domains. Note that setting 0 or 1 in num_pm_domains is equivalent
> > > as the core will handle these 2 cases in the exact same way
> > > (automatically, without driver intervention), and there should
> > > be no adverse consequence in this case (the concern is about
> > > switching on only some power domains and not others).
> > >
> > > drivers/gpu/drm/panfrost/panfrost_device.c | 97 ++++++++++++++++++++--
> > > drivers/gpu/drm/panfrost/panfrost_device.h | 11 +++
> > > drivers/gpu/drm/panfrost/panfrost_drv.c | 2 +
> > > 3 files changed, 102 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/panfrost/panfrost_device.c
> > > index 3720d50f6d9f965..8136babd3ba9935 100644
> > > --- a/drivers/gpu/drm/panfrost/panfrost_device.c
> > > +++ b/drivers/gpu/drm/panfrost/panfrost_device.c
> > > @@ -5,6 +5,7 @@
> > > #include <linux/clk.h>
> > > #include <linux/reset.h>
> > > #include <linux/platform_device.h>
> > > +#include <linux/pm_domain.h>
> > > #include <linux/regulator/consumer.h>
> > >
> > > #include "panfrost_device.h"
> > > @@ -120,6 +121,79 @@ static void panfrost_regulator_fini(struct panfrost_device *pfdev)
> > > pfdev->regulators);
> > > }
> > >
> > > +static void panfrost_pm_domain_fini(struct panfrost_device *pfdev)
> > > +{
> > > + int i;
> > > +
> > > + for (i = 0; i < ARRAY_SIZE(pfdev->pm_domain_devs); i++) {
> > > + if (!pfdev->pm_domain_devs[i])
> > > + break;
> > > +
> > > + if (pfdev->pm_domain_links[i])
> > > + device_link_del(pfdev->pm_domain_links[i]);
> > > +
> > > + dev_pm_domain_detach(pfdev->pm_domain_devs[i], true);
> > > + }
> > > +}
> > > +
> > > +static int panfrost_pm_domain_init(struct panfrost_device *pfdev)
> > > +{
> > > + int err;
> > > + int i, num_domains;
> > > +
> > > + num_domains = of_count_phandle_with_args(pfdev->dev->of_node,
> > > + "power-domains",
> > > + "#power-domain-cells");
> > > +
> > > + /*
> > > + * Single domain is handled by the core, and, if only a single power
> > > + * the power domain is requested, the property is optional.
> > > + */
> > > + if (num_domains < 2 && pfdev->comp->num_pm_domains < 2)
> > > + return 0;
> > > +
> > > + if (num_domains != pfdev->comp->num_pm_domains) {
> > > + dev_err(pfdev->dev,
> > > + "Incorrect number of power domains: %d provided, %d needed\n",
> > > + num_domains, pfdev->comp->num_pm_domains);
> > > + return -EINVAL;
> > > + }
> > > +
> > > + if (WARN(num_domains > ARRAY_SIZE(pfdev->pm_domain_devs),
> > > + "Too many supplies in compatible structure.\n"))
> > > + return -EINVAL;
> > > +
> > > + for (i = 0; i < num_domains; i++) {
> > > + pfdev->pm_domain_devs[i] =
> > > + dev_pm_domain_attach_by_name(pfdev->dev,
> > > + pfdev->comp->pm_domain_names[i]);
> > > + if (IS_ERR_OR_NULL(pfdev->pm_domain_devs[i])) {
> > > + err = PTR_ERR(pfdev->pm_domain_devs[i]) ? : -ENODATA;
> > > + pfdev->pm_domain_devs[i] = NULL;
> > > + dev_err(pfdev->dev,
> > > + "failed to get pm-domain %s(%d): %d\n",
> > > + pfdev->comp->pm_domain_names[i], i, err);
> > > + goto err;
> > > + }
> > > +
> > > + pfdev->pm_domain_links[i] = device_link_add(pfdev->dev,
> > > + pfdev->pm_domain_devs[i], DL_FLAG_PM_RUNTIME |
> > > + DL_FLAG_STATELESS | DL_FLAG_RPM_ACTIVE);
> >
> > We're in the process of adding device links based on DT properties.
> > Shouldn't we add power domains to that? See drivers/of/property.c for
> > what's handled.
>
> Rob,
>
> drivers/of/property.c doesn't enable the RPM_ACTIVE AND PM_RUNTIME
> flags. Wanted to start off conservative.
I worry that you can't add it later without potentially breaking platforms.
I haven't checked, but I assume these flags make runtime PM honor
device links? That seems like the more conservative option (more
reasons why a device can't suspend).
> But adding command line ops
> to change the default flags shouldn't be difficult. But before I do
> that, I want to change of_devlink to
> fw_devlink=<disabled|permissive|enabled>. May be I can extend that to
> "disabled, permissive, suspend, runtime".
I think any command line option should be debug primarily. It's kind
of a big hammer.
Can drivers adjust the flags themselves? Just modify the flags rather
than trying to create new links?
Rob
On Wed, Feb 12, 2020 at 4:09 AM Saravana Kannan <[email protected]> wrote:
>
> On Tue, Feb 11, 2020 at 11:44 AM Rob Herring <[email protected]> wrote:
> >
> > +Saravana
> >
> > On Thu, Feb 6, 2020 at 11:27 PM Nicolas Boichat <[email protected]> wrote:
> > >
> > > When there is a single power domain per device, the core will
> > > ensure the power domain is switched on (so it is technically
> > > equivalent to having not power domain specified at all).
> > >
> > > However, when there are multiple domains, as in MT8183 Bifrost
> > > GPU, we need to handle them in driver code.
> > >
> > > Signed-off-by: Nicolas Boichat <[email protected]>
> > >
> > > ---
> > > [snip]
> > > + pfdev->pm_domain_links[i] = device_link_add(pfdev->dev,
> > > + pfdev->pm_domain_devs[i], DL_FLAG_PM_RUNTIME |
> > > + DL_FLAG_STATELESS | DL_FLAG_RPM_ACTIVE);
> >
> > We're in the process of adding device links based on DT properties.
> > Shouldn't we add power domains to that? See drivers/of/property.c for
> > what's handled.
>
> Rob,
>
> drivers/of/property.c doesn't enable the RPM_ACTIVE AND PM_RUNTIME
> flags. Wanted to start off conservative. But adding command line ops
> to change the default flags shouldn't be difficult. But before I do
> that, I want to change of_devlink to
> fw_devlink=<disabled|permissive|enabled>. May be I can extend that to
> "disabled, permissive, suspend, runtime".
>
> Nicholas,
>
> And the adding and removing of device links for power domains will be
> a 2 line change. I've been meaning to add a few more bindings like
> hwspinlocks and pinctrl. I can roll power domains support into that if
> you want.
Adding power domains makes sense to me, as there are a bunch of other
users (git grep dev_pm_domain_attach_by_name).
This seems to be a bit orthogonal to this patch though. If your
solution lands before this (and not something that is behind a command
line option), then I'm happy to make use of it. Either way, happy to
test things.
On Tue, Feb 11, 2020 at 5:58 PM Rob Herring <[email protected]> wrote:
>
> On Tue, Feb 11, 2020 at 2:09 PM Saravana Kannan <[email protected]> wrote:
> >
> > On Tue, Feb 11, 2020 at 11:44 AM Rob Herring <[email protected]> wrote:
> > >
> > > +Saravana
> > >
> > > On Thu, Feb 6, 2020 at 11:27 PM Nicolas Boichat <[email protected]> wrote:
> > > >
> > > > When there is a single power domain per device, the core will
> > > > ensure the power domain is switched on (so it is technically
> > > > equivalent to having not power domain specified at all).
> > > >
> > > > However, when there are multiple domains, as in MT8183 Bifrost
> > > > GPU, we need to handle them in driver code.
> > > >
> > > > Signed-off-by: Nicolas Boichat <[email protected]>
> > > >
> > > > ---
> > > >
> > > > The downstream driver we use on chromeos-4.19 currently uses 2
> > > > additional devices in device tree to accomodate for this [1], but
> > > > I believe this solution is cleaner.
> > > >
> > > > [1] https://chromium.googlesource.com/chromiumos/third_party/kernel/+/refs/heads/chromeos-4.19/drivers/gpu/arm/midgard/platform/mediatek/mali_kbase_runtime_pm.c#31
> > > >
> > > > v4:
> > > > - Match the exact power domain names as specified in the compatible
> > > > struct, instead of just matching the number of power domains.
> > > > [Review: Ulf Hansson]
> > > > - Dropped print and reordered function [Review: Steven Price]
> > > > - nits: Run through latest version of checkpatch:
> > > > - Use WARN instead of BUG_ON.
> > > > - Drop braces for single expression if block.
> > > > v3:
> > > > - Use the compatible matching data to specify the number of power
> > > > domains. Note that setting 0 or 1 in num_pm_domains is equivalent
> > > > as the core will handle these 2 cases in the exact same way
> > > > (automatically, without driver intervention), and there should
> > > > be no adverse consequence in this case (the concern is about
> > > > switching on only some power domains and not others).
> > > >
> > > > drivers/gpu/drm/panfrost/panfrost_device.c | 97 ++++++++++++++++++++--
> > > > drivers/gpu/drm/panfrost/panfrost_device.h | 11 +++
> > > > drivers/gpu/drm/panfrost/panfrost_drv.c | 2 +
> > > > 3 files changed, 102 insertions(+), 8 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/panfrost/panfrost_device.c
> > > > index 3720d50f6d9f965..8136babd3ba9935 100644
> > > > --- a/drivers/gpu/drm/panfrost/panfrost_device.c
> > > > +++ b/drivers/gpu/drm/panfrost/panfrost_device.c
> > > > @@ -5,6 +5,7 @@
> > > > #include <linux/clk.h>
> > > > #include <linux/reset.h>
> > > > #include <linux/platform_device.h>
> > > > +#include <linux/pm_domain.h>
> > > > #include <linux/regulator/consumer.h>
> > > >
> > > > #include "panfrost_device.h"
> > > > @@ -120,6 +121,79 @@ static void panfrost_regulator_fini(struct panfrost_device *pfdev)
> > > > pfdev->regulators);
> > > > }
> > > >
> > > > +static void panfrost_pm_domain_fini(struct panfrost_device *pfdev)
> > > > +{
> > > > + int i;
> > > > +
> > > > + for (i = 0; i < ARRAY_SIZE(pfdev->pm_domain_devs); i++) {
> > > > + if (!pfdev->pm_domain_devs[i])
> > > > + break;
> > > > +
> > > > + if (pfdev->pm_domain_links[i])
> > > > + device_link_del(pfdev->pm_domain_links[i]);
> > > > +
> > > > + dev_pm_domain_detach(pfdev->pm_domain_devs[i], true);
> > > > + }
> > > > +}
> > > > +
> > > > +static int panfrost_pm_domain_init(struct panfrost_device *pfdev)
> > > > +{
> > > > + int err;
> > > > + int i, num_domains;
> > > > +
> > > > + num_domains = of_count_phandle_with_args(pfdev->dev->of_node,
> > > > + "power-domains",
> > > > + "#power-domain-cells");
> > > > +
> > > > + /*
> > > > + * Single domain is handled by the core, and, if only a single power
> > > > + * the power domain is requested, the property is optional.
> > > > + */
> > > > + if (num_domains < 2 && pfdev->comp->num_pm_domains < 2)
> > > > + return 0;
> > > > +
> > > > + if (num_domains != pfdev->comp->num_pm_domains) {
> > > > + dev_err(pfdev->dev,
> > > > + "Incorrect number of power domains: %d provided, %d needed\n",
> > > > + num_domains, pfdev->comp->num_pm_domains);
> > > > + return -EINVAL;
> > > > + }
> > > > +
> > > > + if (WARN(num_domains > ARRAY_SIZE(pfdev->pm_domain_devs),
> > > > + "Too many supplies in compatible structure.\n"))
> > > > + return -EINVAL;
> > > > +
> > > > + for (i = 0; i < num_domains; i++) {
> > > > + pfdev->pm_domain_devs[i] =
> > > > + dev_pm_domain_attach_by_name(pfdev->dev,
> > > > + pfdev->comp->pm_domain_names[i]);
> > > > + if (IS_ERR_OR_NULL(pfdev->pm_domain_devs[i])) {
> > > > + err = PTR_ERR(pfdev->pm_domain_devs[i]) ? : -ENODATA;
> > > > + pfdev->pm_domain_devs[i] = NULL;
> > > > + dev_err(pfdev->dev,
> > > > + "failed to get pm-domain %s(%d): %d\n",
> > > > + pfdev->comp->pm_domain_names[i], i, err);
> > > > + goto err;
> > > > + }
> > > > +
> > > > + pfdev->pm_domain_links[i] = device_link_add(pfdev->dev,
> > > > + pfdev->pm_domain_devs[i], DL_FLAG_PM_RUNTIME |
> > > > + DL_FLAG_STATELESS | DL_FLAG_RPM_ACTIVE);
> > >
> > > We're in the process of adding device links based on DT properties.
> > > Shouldn't we add power domains to that? See drivers/of/property.c for
> > > what's handled.
> >
> > Rob,
> >
> > drivers/of/property.c doesn't enable the RPM_ACTIVE AND PM_RUNTIME
> > flags. Wanted to start off conservative.
>
> I worry that you can't add it later without potentially breaking platforms.
>
> I haven't checked, but I assume these flags make runtime PM honor
> device links? That seems like the more conservative option (more
> reasons why a device can't suspend).
Conservative as in, if of_devlink adds the RPM_ACTIVE flag, the
drivers can't remove it.
> > But adding command line ops
> > to change the default flags shouldn't be difficult. But before I do
> > that, I want to change of_devlink to
> > fw_devlink=<disabled|permissive|enabled>. May be I can extend that to
> > "disabled, permissive, suspend, runtime".
>
> I think any command line option should be debug primarily. It's kind
> of a big hammer.
It is a big hammer. But it's better than disabling of_devlink
altogether. There is always going to be weird hardware that won't work
with of_devlink if all the device link flags are set. They'll need
some fix up of drivers and/or clean up of DT. And having different
of_devlink command line options would at least let those hardware to
run with as much of_devlink enabled as possible while working to get
more fixes into the kernel. That way, we can make sure we don't
regress further while trying to improve the support.
> Can drivers adjust the flags themselves? Just modify the flags rather
> than trying to create new links?
They can, but only in an additive manner. And the way to do it would
be to add a device link like usual and the framework takes care of
combining the flags. That's why I don't set most of the flags by
default.
-Saravana
+Viresh Kumar +Stephen Boyd for clock advice.
On Fri, Feb 7, 2020 at 1:27 PM Nicolas Boichat <[email protected]> wrote:
>
> The Bifrost GPU on MT8183 uses 2 regulators (core and SRAM) for
> devfreq, and provides OPP table with 2 sets of voltages.
>
> TODO: This is incomplete as we'll need add support for setting
> a pair of voltages as well.
So all we need for this to work (at least apparently, that is, I can
change frequency) is this:
https://lore.kernel.org/patchwork/patch/1192945/
(ah well, Viresh just replied, so, probably not, I'll check that out
and use the correct API)
But then there's a slight problem: panfrost_devfreq uses a bunch of
clk_get_rate calls, and the clock PLLs (at least on MTK platform) are
never fully precise, so we get back 299999955 for 300 Mhz and
799999878 for 800 Mhz. That means that the kernel is unable to keep
devfreq stats as neither of these values are in the table:
[ 4802.470952] devfreq devfreq1: Couldn't update frequency transition
information.
The kbase driver fixes this by remembering the last set frequency, and
reporting that to devfreq. Should we do that as well or is there a
better fix?
Another thing that I'm not implementing is the dance that Mediatek
does in their kbase driver when changing the clock (described in patch
2/7):
""
The binding we use with out-of-tree Mali drivers includes more
clocks, this is used for devfreq: the out-of-tree driver switches
clk_mux to clk_sub_parent (26Mhz), adjusts clk_main_parent, then
switches clk_mux back to clk_main_parent:
(see https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-4.19/drivers/gpu/arm/midgard/platform/mediatek/mali_kbase_runtime_pm.c#423)
clocks =
<&topckgen CLK_TOP_MFGPLL_CK>,
<&topckgen CLK_TOP_MUX_MFG>,
<&clk26m>,
<&mfgcfg CLK_MFG_BG3D>;
clock-names =
"clk_main_parent",
"clk_mux",
"clk_sub_parent",
"subsys_mfg_cg";
""
Is there a clean/simple way to implement this in the clock
framework/device tree? Or should we implement something in the
panfrost driver?
Thanks!
>
> Signed-off-by: Nicolas Boichat <[email protected]>
>
> ---
> drivers/gpu/drm/panfrost/panfrost_devfreq.c | 17 +++++++++++++++++
> drivers/gpu/drm/panfrost/panfrost_device.h | 1 +
> 2 files changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> index 413987038fbfccb..9c0987a3d71c597 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> +++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
> @@ -79,6 +79,21 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
> struct devfreq *devfreq;
> struct thermal_cooling_device *cooling;
>
> + /* If we have 2 regulator, we need an OPP table with 2 voltages. */
> + if (pfdev->comp->num_supplies > 1) {
> + pfdev->devfreq.dev_opp_table =
> + dev_pm_opp_set_regulators(dev,
> + pfdev->comp->supply_names,
> + pfdev->comp->num_supplies);
> + if (IS_ERR(pfdev->devfreq.dev_opp_table)) {
> + ret = PTR_ERR(pfdev->devfreq.dev_opp_table);
> + pfdev->devfreq.dev_opp_table = NULL;
> + dev_err(dev,
> + "Failed to init devfreq opp table: %d\n", ret);
> + return ret;
> + }
> + }
> +
> ret = dev_pm_opp_of_add_table(dev);
> if (ret == -ENODEV) /* Optional, continue without devfreq */
> return 0;
> @@ -119,6 +134,8 @@ void panfrost_devfreq_fini(struct panfrost_device *pfdev)
> if (pfdev->devfreq.cooling)
> devfreq_cooling_unregister(pfdev->devfreq.cooling);
> dev_pm_opp_of_remove_table(&pfdev->pdev->dev);
> + if (pfdev->devfreq.dev_opp_table)
> + dev_pm_opp_put_regulators(pfdev->devfreq.dev_opp_table);
> }
>
> void panfrost_devfreq_resume(struct panfrost_device *pfdev)
> diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h
> index c30c719a805940a..5009a8b7c853ea1 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_device.h
> +++ b/drivers/gpu/drm/panfrost/panfrost_device.h
> @@ -110,6 +110,7 @@ struct panfrost_device {
> struct {
> struct devfreq *devfreq;
> struct thermal_cooling_device *cooling;
> + struct opp_table *dev_opp_table;
> ktime_t busy_time;
> ktime_t idle_time;
> ktime_t time_last_update;
> --
> 2.25.0.341.g760bfbb309-goog
>
On Wed, Feb 12, 2020 at 2:19 PM Nicolas Boichat <[email protected]> wrote:
>
> +Viresh Kumar +Stephen Boyd for clock advice.
You missed adding us in the cc list of the email, fixed that now :)
On 07/02/2020 06:26, Nicolas Boichat wrote:
> It is useful to know which component cannot be powered on.
>
> Signed-off-by: Nicolas Boichat <[email protected]>
> Reviewed-by: Steven Price <[email protected]>
> Reviewed-by: Alyssa Rosenzweig <[email protected]>
Reviewed-by: Matthias Brugger <[email protected]>
> ---
>
> Was useful when trying to probe Bifrost GPU, to understand what
> issue we are facing.
>
> v4:
> - No change
> v3:
> - Rebased on https://patchwork.kernel.org/patch/11325689/
>
> drivers/gpu/drm/panfrost/panfrost_gpu.c | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panfrost/panfrost_gpu.c
> index 460fc190de6e815..856f2fd1fa8ed27 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_gpu.c
> +++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c
> @@ -308,17 +308,20 @@ void panfrost_gpu_power_on(struct panfrost_device *pfdev)
> gpu_write(pfdev, L2_PWRON_LO, pfdev->features.l2_present);
> ret = readl_relaxed_poll_timeout(pfdev->iomem + L2_READY_LO,
> val, val == pfdev->features.l2_present, 100, 1000);
> + if (ret)
> + dev_err(pfdev->dev, "error powering up gpu L2");
>
> gpu_write(pfdev, SHADER_PWRON_LO, pfdev->features.shader_present);
> - ret |= readl_relaxed_poll_timeout(pfdev->iomem + SHADER_READY_LO,
> + ret = readl_relaxed_poll_timeout(pfdev->iomem + SHADER_READY_LO,
> val, val == pfdev->features.shader_present, 100, 1000);
> + if (ret)
> + dev_err(pfdev->dev, "error powering up gpu shader");
>
> gpu_write(pfdev, TILER_PWRON_LO, pfdev->features.tiler_present);
> - ret |= readl_relaxed_poll_timeout(pfdev->iomem + TILER_READY_LO,
> + ret = readl_relaxed_poll_timeout(pfdev->iomem + TILER_READY_LO,
> val, val == pfdev->features.tiler_present, 100, 1000);
> -
> if (ret)
> - dev_err(pfdev->dev, "error powering up gpu");
> + dev_err(pfdev->dev, "error powering up gpu tiler");
> }
>
> void panfrost_gpu_power_off(struct panfrost_device *pfdev)
>
On Wed, Feb 12, 2020 at 2:49 AM Nicolas Boichat <[email protected]> wrote:
>
> +Viresh Kumar +Stephen Boyd for clock advice.
>
> On Fri, Feb 7, 2020 at 1:27 PM Nicolas Boichat <[email protected]> wrote:
> >
> > The Bifrost GPU on MT8183 uses 2 regulators (core and SRAM) for
> > devfreq, and provides OPP table with 2 sets of voltages.
> >
> > TODO: This is incomplete as we'll need add support for setting
> > a pair of voltages as well.
>
> So all we need for this to work (at least apparently, that is, I can
> change frequency) is this:
> https://lore.kernel.org/patchwork/patch/1192945/
> (ah well, Viresh just replied, so, probably not, I'll check that out
> and use the correct API)
>
> But then there's a slight problem: panfrost_devfreq uses a bunch of
> clk_get_rate calls, and the clock PLLs (at least on MTK platform) are
> never fully precise, so we get back 299999955 for 300 Mhz and
> 799999878 for 800 Mhz. That means that the kernel is unable to keep
> devfreq stats as neither of these values are in the table:
> [ 4802.470952] devfreq devfreq1: Couldn't update frequency transition
> information.
> The kbase driver fixes this by remembering the last set frequency, and
> reporting that to devfreq. Should we do that as well or is there a
> better fix?
>
> Another thing that I'm not implementing is the dance that Mediatek
> does in their kbase driver when changing the clock (described in patch
> 2/7):
> ""
> The binding we use with out-of-tree Mali drivers includes more
> clocks, this is used for devfreq: the out-of-tree driver switches
> clk_mux to clk_sub_parent (26Mhz), adjusts clk_main_parent, then
> switches clk_mux back to clk_main_parent:
> (see https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-4.19/drivers/gpu/arm/midgard/platform/mediatek/mali_kbase_runtime_pm.c#423)
> clocks =
> <&topckgen CLK_TOP_MFGPLL_CK>,
> <&topckgen CLK_TOP_MUX_MFG>,
> <&clk26m>,
> <&mfgcfg CLK_MFG_BG3D>;
> clock-names =
> "clk_main_parent",
> "clk_mux",
> "clk_sub_parent",
> "subsys_mfg_cg";
> ""
> Is there a clean/simple way to implement this in the clock
> framework/device tree? Or should we implement something in the
> panfrost driver?
Putting parent clocks into 'clocks' for a device is a pretty common
abuse. The 'assigned-clocks' binding is what's used for parent clock
setup. Not sure that's going to help here though. Is this dance
because the parent clock frequency can't be changed cleanly? If up to
me, I'd put that dance in the clock driver. The GPU shouldn't have to
care.
Rob
+Weiyi Lu +Nick Fan @MTK who may have more ideas.
On Thu, Feb 13, 2020 at 2:14 AM Rob Herring <[email protected]> wrote:
>
> On Wed, Feb 12, 2020 at 2:49 AM Nicolas Boichat <[email protected]> wrote:
> >
> > +Viresh Kumar +Stephen Boyd for clock advice.
> >
> > On Fri, Feb 7, 2020 at 1:27 PM Nicolas Boichat <[email protected]> wrote:
> > >
> > > The Bifrost GPU on MT8183 uses 2 regulators (core and SRAM) for
> > > devfreq, and provides OPP table with 2 sets of voltages.
> > >
> > > TODO: This is incomplete as we'll need add support for setting
> > > a pair of voltages as well.
> >
> > So all we need for this to work (at least apparently, that is, I can
> > change frequency) is this:
> > https://lore.kernel.org/patchwork/patch/1192945/
> > (ah well, Viresh just replied, so, probably not, I'll check that out
> > and use the correct API)
> >
> > But then there's a slight problem: panfrost_devfreq uses a bunch of
> > clk_get_rate calls, and the clock PLLs (at least on MTK platform) are
> > never fully precise, so we get back 299999955 for 300 Mhz and
> > 799999878 for 800 Mhz. That means that the kernel is unable to keep
> > devfreq stats as neither of these values are in the table:
> > [ 4802.470952] devfreq devfreq1: Couldn't update frequency transition
> > information.
> > The kbase driver fixes this by remembering the last set frequency, and
> > reporting that to devfreq. Should we do that as well or is there a
> > better fix?
> >
> > Another thing that I'm not implementing is the dance that Mediatek
> > does in their kbase driver when changing the clock (described in patch
> > 2/7):
> > ""
> > The binding we use with out-of-tree Mali drivers includes more
> > clocks, this is used for devfreq: the out-of-tree driver switches
> > clk_mux to clk_sub_parent (26Mhz), adjusts clk_main_parent, then
> > switches clk_mux back to clk_main_parent:
> > (see https://chromium.googlesource.com/chromiumos/third_party/kernel/+/chromeos-4.19/drivers/gpu/arm/midgard/platform/mediatek/mali_kbase_runtime_pm.c#423)
> > clocks =
> > <&topckgen CLK_TOP_MFGPLL_CK>,
> > <&topckgen CLK_TOP_MUX_MFG>,
> > <&clk26m>,
> > <&mfgcfg CLK_MFG_BG3D>;
> > clock-names =
> > "clk_main_parent",
> > "clk_mux",
> > "clk_sub_parent",
> > "subsys_mfg_cg";
> > ""
> > Is there a clean/simple way to implement this in the clock
> > framework/device tree? Or should we implement something in the
> > panfrost driver?
>
> Putting parent clocks into 'clocks' for a device is a pretty common
> abuse. The 'assigned-clocks' binding is what's used for parent clock
> setup. Not sure that's going to help here though. Is this dance
> because the parent clock frequency can't be changed cleanly?
Nick/Weiyi, any idea why we do that dance in the first place? (maybe
the PLL clock is unstable while it's being changed?)
If we really need it, can we move that logic to the clock core?
> If up to
> me, I'd put that dance in the clock driver. The GPU shouldn't have to
> care.
>
> Rob
On Thu, Feb 13, 2020 at 3:57 PM Nicolas Boichat <[email protected]> wrote:
> > > [snip]
> > > But then there's a slight problem: panfrost_devfreq uses a bunch of
> > > clk_get_rate calls, and the clock PLLs (at least on MTK platform) are
> > > never fully precise, so we get back 299999955 for 300 Mhz and
> > > 799999878 for 800 Mhz. That means that the kernel is unable to keep
> > > devfreq stats as neither of these values are in the table:
> > > [ 4802.470952] devfreq devfreq1: Couldn't update frequency transition
> > > information.
> > > The kbase driver fixes this by remembering the last set frequency, and
> > > reporting that to devfreq. Should we do that as well or is there a
> > > better fix?
This one is my bad, I was missing this patch in my forklift to 4.19:
22bd4df9dadf46f drm/panfrost: devfreq: Round frequencies to OPPs
(should really try to boot that board on linux-next, but that's for
another time)
+JB and SJ for info sync
Hi Nicolas,
Please see my inline reply.
Thanks
Hi Weiyi,
Could you please help to comment on the second question?
Thanks
Warmest regards,
Nick Fan 范哲維
-----Original Message-----
From: Nicolas Boichat [mailto:[email protected]]
Sent: Thursday, February 13, 2020 3:58 PM
To: Rob Herring <[email protected]>; Weiyi Lu (呂威儀) <[email protected]>; Nick Fan (范哲維) <[email protected]>
Cc: David Airlie <[email protected]>; Daniel Vetter <[email protected]>; Mark Rutland <[email protected]>; Matthias Brugger <[email protected]>; Tomeu Vizoso <[email protected]>; Steven Price <[email protected]>; Alyssa Rosenzweig <[email protected]>; Liam Girdwood <[email protected]>; Mark Brown <[email protected]>; dri-devel <[email protected]>; Devicetree List <[email protected]>; lkml <[email protected]>; linux-arm Mailing List <[email protected]>; moderated list:ARM/Mediatek SoC support <[email protected]>; Hsin-Yi Wang <[email protected]>; Ulf Hansson <[email protected]>; Viresh Kumar <[email protected]>; Stephen Boyd <[email protected]>
Subject: Re: [PATCH v4 7/7] RFC: drm/panfrost: devfreq: Add support for 2 regulators
+Weiyi Lu +Nick Fan @MTK who may have more ideas.
On Thu, Feb 13, 2020 at 2:14 AM Rob Herring <[email protected]> wrote:
>
> On Wed, Feb 12, 2020 at 2:49 AM Nicolas Boichat <[email protected]> wrote:
> >
> > +Viresh Kumar +Stephen Boyd for clock advice.
> >
> > On Fri, Feb 7, 2020 at 1:27 PM Nicolas Boichat <[email protected]> wrote:
> > >
> > > The Bifrost GPU on MT8183 uses 2 regulators (core and SRAM) for
> > > devfreq, and provides OPP table with 2 sets of voltages.
> > >
> > > TODO: This is incomplete as we'll need add support for setting a
> > > pair of voltages as well.
> >
> > So all we need for this to work (at least apparently, that is, I can
> > change frequency) is this:
> > https://lore.kernel.org/patchwork/patch/1192945/
> > (ah well, Viresh just replied, so, probably not, I'll check that out
> > and use the correct API)
> >
> > But then there's a slight problem: panfrost_devfreq uses a bunch of
> > clk_get_rate calls, and the clock PLLs (at least on MTK platform)
> > are never fully precise, so we get back 299999955 for 300 Mhz and
> > 799999878 for 800 Mhz. That means that the kernel is unable to keep
> > devfreq stats as neither of these values are in the table:
> > [ 4802.470952] devfreq devfreq1: Couldn't update frequency
> > transition information.
> > The kbase driver fixes this by remembering the last set frequency,
> > and reporting that to devfreq. Should we do that as well or is there
> > a better fix?
> >
> > Another thing that I'm not implementing is the dance that Mediatek
> > does in their kbase driver when changing the clock (described in
> > patch
> > 2/7):
> > ""
> > The binding we use with out-of-tree Mali drivers includes more
> > clocks, this is used for devfreq: the out-of-tree driver switches
> > clk_mux to clk_sub_parent (26Mhz), adjusts clk_main_parent, then
> > switches clk_mux back to clk_main_parent:
> > (see
> > https://chromium.googlesource.com/chromiumos/third_party/kernel/+/ch
> > romeos-4.19/drivers/gpu/arm/midgard/platform/mediatek/mali_kbase_run
> > time_pm.c#423)
> > clocks =
> > <&topckgen CLK_TOP_MFGPLL_CK>,
> > <&topckgen CLK_TOP_MUX_MFG>,
> > <&clk26m>,
> > <&mfgcfg CLK_MFG_BG3D>;
> > clock-names =
> > "clk_main_parent",
> > "clk_mux",
> > "clk_sub_parent",
> > "subsys_mfg_cg";
> > ""
> > Is there a clean/simple way to implement this in the clock
> > framework/device tree? Or should we implement something in the
> > panfrost driver?
>
> Putting parent clocks into 'clocks' for a device is a pretty common
> abuse. The 'assigned-clocks' binding is what's used for parent clock
> setup. Not sure that's going to help here though. Is this dance
> because the parent clock frequency can't be changed cleanly?
Nick/Weiyi, any idea why we do that dance in the first place? (maybe the PLL clock is unstable while it's being changed?)
Clock source may become unstable during clock frequency changes, so it is always safer to switch to a more reliable clock source.
Otherwise, it may cause some problem in some corner case.
I would suggest to keep it.
If we really need it, can we move that logic to the clock core?
> If up to
> me, I'd put that dance in the clock driver. The GPU shouldn't have to
> care.
>
> Rob
On Thu, Feb 6, 2020 at 11:26 PM Nicolas Boichat <[email protected]> wrote:
>
> Hi!
>
> Follow-up on the v3: https://patchwork.kernel.org/cover/11331343/.
>
> The main purpose of this series is to upstream the dts change and the
> binding document, but I wanted to see how far I could probe the GPU, to
> check that the binding is indeed correct. The rest of the patches are
> RFC/work-in-progress, but I think some of them could already be picked up.
>
> So this is tested on MT8183 with a chromeos-4.19 kernel, and a ton of
> backports to get the latest panfrost driver (I should probably try on
> linux-next at some point but this was the path of least resistance).
>
> I tested it as a module as it's more challenging (originally probing would
> work built-in, on boot, but not as a module, as I didn't have the power
> domain changes, and all power domains are on by default during boot).
>
> Probing logs looks like this, currently. They look sane.
> [ 501.319728] panfrost 13040000.gpu: clock rate = 511999970
> [ 501.320041] panfrost 13040000.gpu: Linked as a consumer to regulator.14
> [ 501.320102] panfrost 13040000.gpu: Linked as a consumer to regulator.31
> [ 501.320651] panfrost 13040000.gpu: Linked as a consumer to genpd:0:13040000.gpu
> [ 501.320954] panfrost 13040000.gpu: Linked as a consumer to genpd:1:13040000.gpu
> [ 501.321062] panfrost 13040000.gpu: Linked as a consumer to genpd:2:13040000.gpu
> [ 501.321734] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
> [ 501.321741] panfrost 13040000.gpu: features: 00000000,13de77ff, issues: 00000000,00000400
> [ 501.321747] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
> [ 501.321752] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
> [ 501.324951] [drm] Initialized panfrost 1.1.0 20180908 for 13040000.gpu on minor 2
>
> Some more changes are still required to get devfreq working, and of course
> I do not have a userspace driver to test this with.
>
> I believe at least patches 1, 2, and 3 can be merged. 4 and 5 are mostly
> useful in conjunction with 6 and 7 (which are not ready yet), so I'll let
> maintainers decide.
I've applied 3, 4, and 5 to drm-misc-next. Patch 2 should go via Mediatek tree.
Rob
Looping back on this, after digging a bit deeper...
On Fri, Feb 14, 2020 at 9:38 AM Nick Fan (范哲維) <[email protected]> wrote:
> [snip]
> > > Another thing that I'm not implementing is the dance that Mediatek
> > > does in their kbase driver when changing the clock (described in
> > > patch
> > > 2/7):
> > > ""
> > > The binding we use with out-of-tree Mali drivers includes more
> > > clocks, this is used for devfreq: the out-of-tree driver switches
> > > clk_mux to clk_sub_parent (26Mhz), adjusts clk_main_parent, then
> > > switches clk_mux back to clk_main_parent:
> > > (see
> > > https://chromium.googlesource.com/chromiumos/third_party/kernel/+/ch
> > > romeos-4.19/drivers/gpu/arm/midgard/platform/mediatek/mali_kbase_run
> > > time_pm.c#423)
> > > clocks =
> > > <&topckgen CLK_TOP_MFGPLL_CK>,
> > > <&topckgen CLK_TOP_MUX_MFG>,
> > > <&clk26m>,
> > > <&mfgcfg CLK_MFG_BG3D>;
> > > clock-names =
> > > "clk_main_parent",
> > > "clk_mux",
> > > "clk_sub_parent",
> > > "subsys_mfg_cg";
> > > ""
> > > Is there a clean/simple way to implement this in the clock
> > > framework/device tree? Or should we implement something in the
> > > panfrost driver?
> >
> > Putting parent clocks into 'clocks' for a device is a pretty common
> > abuse. The 'assigned-clocks' binding is what's used for parent clock
> > setup. Not sure that's going to help here though. Is this dance
> > because the parent clock frequency can't be changed cleanly?
>
> Nick/Weiyi, any idea why we do that dance in the first place? (maybe the PLL clock is unstable while it's being changed?)
>
> Clock source may become unstable during clock frequency changes, so it is always safer to switch to a more reliable clock source.
> Otherwise, it may cause some problem in some corner case.
> I would suggest to keep it.
The Mediatek CPUfreq driver actually does a very similar dance:
https://github.com/torvalds/linux/blob/master/drivers/cpufreq/mediatek-cpufreq.c#L249
What they have in the device tree is the main clock, and the
"intermediate" clock that is required during switching:
clocks = <&mcucfg CLK_MCU_MP0_SEL>, <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
clock-names = "cpu", "intermediate";
The topology looks like this:
clk26m 15 15 1 26000000
0 0 50000
armpll_ll 1 1 0 1417000000
0 0 50000
mcu_mp0_sel 0 0 0 1417000000
0 0 50000
And device tree provides mcu_mp0_sel as "cpu", and the armpll_div_pll1
as "intermediate".
The driver looks up armpll_ll by calling get_parent, then:
- set_parent(mcu_mp0_sel, armpll_div_pll1)
- set_rate(armpll_ll, new_rate)
- set_parent(mcu_mp0_sel, armpll_ll)
On MT8183's GPU, the topology is a little bit more complicated (but I
think there should be a way to merge mfg_bg3d an mfg_sel in the clock
core)
clk26m 15 15 1 26000000
0 0 50000
mfgpll 1 1 0 419999817
0 0 50000
mfgpll_ck 2 2 0 419999817
0 0 50000
mfg_sel 3 3 0 419999817
0 0 50000
mfg_bg3d 1 1 0 419999817
0 0 50000
We're going to need a special panfrost devfreq driver for mt8183
anyway (to handle the 2 regulators), so it would be easy to take a
similar approach:
- Add "intermediate" clock in the device tree (clk26m)
- Find mfg_sel/mfgpll_ck using 1/2 clk_get_parent calls.
- Switch mfg_sel to clk26m, set mfgpll_ck rate, switch mfg_sel back
to mfgpll_ck.
(BTW, I tried to look, and couldn't find examples or reparenting
during clock changes in drivers/clk, are there existing drivers doing
similar things? Or this would be new?).