Change in v4:
* Cleaned up kona_smp.c and associated DT file.
* Corrected documentation for DT bindings.
* Corrected secondary-boot-reg entry for bcm4708 DT file.
Change in v3:
* Fixed patch subject from RESEND PATCH to PATCH
* Deleted arch/arm/mach-bcm/bcm_nsp.h file
* Removed inclusion of header file bcm_nsp.h in platsmp.c
* Removed unused variable 'timeout' in nsp_boot_secondary()
Changes in v2:
Removed the pen_holding method of SMP bringup for NSP SoC and
replaced it with simple wakeup of secondary core using ARM IPI.
This series adds SMP support for Broadcom's Northstar Plus SoC.
There are similar SMP enablement methods for many ARMv7 bsed SoCs.
BCM NSP SoC, has a typical such mechanism - after power-on, the
secondary core is held in a standby state, primary core provides a
startup address for the secondary core and wakes it up. Booting of
the secondary core is serialized using pen_release global variable.
The startup address is programmed at a special register location
which is defined in the device tree using a "secondary-boot-reg"
property in a node whose "enable-method" property matches.
The first patch adds cpu-enable-method in the device tree bindings
documentation. It also updates ARM CPU device tree documentation
with Broadcom Northstar Plus CPU details.
The second patch adds SMP support to the BCM NSP device tree file.
The third patch, enables SMP on BCM NSP. It also consolidates
common SMP handling between BCM NSP and BCM Kona.
The final patch, enables SMP on BCM 4708 and this patch is pulled
in from Jon Mason's patch from the mailing list.
This patch series is constructed based on Linux v4.4-rc1.
The source code is available at GITHUB:
https://github.com/Broadcom/cygnus-linux/tree/nsp-smp-v2
Jon Mason (1):
ARM: BCM: Add SMP support for Broadcom 4708
Kapil Hali (4):
dt-bindings: add SMP enable-method for Broadcom NSP
ARM: BCM: Clean up SMP support for Broadcom Kona
ARM: dts: Add SMP support for Broadcom NSP
ARM: BCM: Add SMP support for Broadcom NSP
.../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 39 ++++++
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
arch/arm/boot/dts/bcm-nsp.dtsi | 33 +++--
arch/arm/boot/dts/bcm11351.dtsi | 2 +-
arch/arm/boot/dts/bcm21664.dtsi | 2 +-
arch/arm/boot/dts/bcm4708.dtsi | 2 +
arch/arm/mach-bcm/Kconfig | 3 +
arch/arm/mach-bcm/Makefile | 11 +-
arch/arm/mach-bcm/{kona_smp.c => platsmp.c} | 144 +++++++++++++++++----
9 files changed, 193 insertions(+), 44 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
rename arch/arm/mach-bcm/{kona_smp.c => platsmp.c} (63%)
--
2.1.0
Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
Northstar Plus CPU to the 32-bit ARM CPU device tree binding
documentation file and create a new binding documentation for
Northstar Plus CPU.
Signed-off-by: Kapil Hali <[email protected]>
---
.../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 39 ++++++++++++++++++++++
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
2 files changed, 40 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
new file mode 100644
index 0000000..bf08872
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
@@ -0,0 +1,39 @@
+Broadcom Northstar Plus SoC CPU Enable Method
+---------------------------------------------
+This binding defines the enable method used for starting secondary
+CPUs in the following Broadcom SoCs:
+ BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
+
+The enable method is specified by defining the following required
+properties in the "cpus" device tree node:
+ - enable-method = "brcm,bcm-nsp-smp";
+ - secondary-boot-reg = <...>;
+
+The secondary-boot-reg property is a u32 value that specifies the
+physical address of the register which should hold the common
+entry point for a secondary CPU. This entry is cpu node specific
+and should be added per cpu. E.g., in case of NSP (BCM58625) which
+is a dual core CPU SoC, this entry should be added to cpu1 node.
+
+
+Example:
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "brcm,bcm-nsp-smp";
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ next-level-cache = <&L2>;
+ reg = <0>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ next-level-cache = <&L2>;
+ reg = <1>;
+ secondary-boot-reg = <0xffff042c>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 3a07a87..d191554 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -190,6 +190,7 @@ nodes to be present and contain the properties described below.
"allwinner,sun6i-a31"
"allwinner,sun8i-a23"
"arm,psci"
+ "brcm,bcm-nsp-smp"
"brcm,brahma-b15"
"marvell,armada-375-smp"
"marvell,armada-380-smp"
--
2.1.0
These changes cleans up SMP implementaion for Broadcom's
Kona SoC which are required for handling SMP for iProc
family of SoCs at a single place for BCM NSP and BCM Kona.
Signed-off-by: Kapil Hali <[email protected]>
---
arch/arm/boot/dts/bcm11351.dtsi | 2 +-
arch/arm/boot/dts/bcm21664.dtsi | 2 +-
arch/arm/mach-bcm/kona_smp.c | 82 +++++++++++++++++++++++++++--------------
3 files changed, 56 insertions(+), 30 deletions(-)
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index 2ddaa51..3dc7a8c 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -31,7 +31,6 @@
#address-cells = <1>;
#size-cells = <0>;
enable-method = "brcm,bcm11351-cpu-method";
- secondary-boot-reg = <0x3500417c>;
cpu0: cpu@0 {
device_type = "cpu";
@@ -42,6 +41,7 @@
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
+ secondary-boot-reg = <0x3500417c>;
reg = <1>;
};
};
diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi
index 2016b72..3f525be 100644
--- a/arch/arm/boot/dts/bcm21664.dtsi
+++ b/arch/arm/boot/dts/bcm21664.dtsi
@@ -31,7 +31,6 @@
#address-cells = <1>;
#size-cells = <0>;
enable-method = "brcm,bcm11351-cpu-method";
- secondary-boot-reg = <0x35004178>;
cpu0: cpu@0 {
device_type = "cpu";
@@ -42,6 +41,7 @@
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
+ secondary-boot-reg = <0x35004178>;
reg = <1>;
};
};
diff --git a/arch/arm/mach-bcm/kona_smp.c b/arch/arm/mach-bcm/kona_smp.c
index 66a0465..15af781 100644
--- a/arch/arm/mach-bcm/kona_smp.c
+++ b/arch/arm/mach-bcm/kona_smp.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2014 Broadcom Corporation
+ * Copyright (C) 2014-2015 Broadcom Corporation
* Copyright 2014 Linaro Limited
*
* This program is free software; you can redistribute it and/or
@@ -30,9 +30,10 @@
/* Name of device node property defining secondary boot register location */
#define OF_SECONDARY_BOOT "secondary-boot-reg"
+#define MPIDR_CPUID_BITMASK 0x3
/* I/O address of register used to coordinate secondary core startup */
-static u32 secondary_boot;
+static u32 secondary_boot_addr;
/*
* Enable the Cortex A9 Snoop Control Unit
@@ -78,44 +79,68 @@ static int __init scu_a9_enable(void)
static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
{
static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
- struct device_node *node;
+ struct device_node *cpus_node = NULL;
+ struct device_node *cpu_node = NULL;
int ret;
- BUG_ON(secondary_boot); /* We're called only once */
-
/*
* This function is only called via smp_ops->smp_prepare_cpu().
* That only happens if a "/cpus" device tree node exists
* and has an "enable-method" property that selects the SMP
* operations defined herein.
*/
- node = of_find_node_by_path("/cpus");
- BUG_ON(!node);
-
- /*
- * Our secondary enable method requires a "secondary-boot-reg"
- * property to specify a register address used to request the
- * ROM code boot a secondary code. If we have any trouble
- * getting this we fall back to uniprocessor mode.
- */
- if (of_property_read_u32(node, OF_SECONDARY_BOOT, &secondary_boot)) {
- pr_err("%s: missing/invalid " OF_SECONDARY_BOOT " property\n",
- node->name);
- ret = -ENOENT; /* Arrange to disable SMP */
- goto out;
+ cpus_node = of_find_node_by_path("/cpus");
+ if (!cpus_node)
+ return;
+
+ for_each_child_of_node(cpus_node, cpu_node) {
+ u32 cpuid;
+
+ if (of_node_cmp(cpu_node->type, "cpu"))
+ continue;
+
+ if (of_property_read_u32(cpu_node, "reg", &cpuid)) {
+ pr_debug("%s: missing reg property\n",
+ cpu_node->full_name);
+ ret = -ENOENT;
+ goto out;
+ }
+
+ /*
+ * "secondary-boot-reg" property should be defined only
+ * for secondary cpu
+ */
+ if ((cpuid & MPIDR_CPUID_BITMASK) == 1) {
+ /*
+ * Our secondary enable method requires a
+ * "secondary-boot-reg" property to specify a register
+ * address used to request the ROM code boot a secondary
+ * core. If we have any trouble getting this we fall
+ * back to uniprocessor mode.
+ */
+ if (of_property_read_u32(cpu_node,
+ OF_SECONDARY_BOOT,
+ &secondary_boot_addr)) {
+ pr_warn("%s: no" OF_SECONDARY_BOOT "property\n",
+ cpu_node->name);
+ ret = -ENOENT;
+ goto out;
+ }
+ }
}
/*
- * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is
+ * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is
* returned, the SoC reported a uniprocessor configuration.
* We bail on any other error.
*/
ret = scu_a9_enable();
out:
- of_node_put(node);
+ of_node_put(cpu_node);
+ of_node_put(cpus_node);
+
if (ret) {
/* Update the CPU present map to reflect uniprocessor mode */
- BUG_ON(ret != -ENOENT);
pr_warn("disabling SMP\n");
init_cpu_present(&only_cpu_0);
}
@@ -139,7 +164,7 @@ out:
* - Wait for the secondary boot register to be re-written, which
* indicates the secondary core has started.
*/
-static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
void __iomem *boot_reg;
phys_addr_t boot_func;
@@ -154,15 +179,16 @@ static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle)
return -EINVAL;
}
- if (!secondary_boot) {
+ if (!secondary_boot_addr) {
pr_err("required secondary boot register not specified\n");
return -EINVAL;
}
- boot_reg = ioremap_nocache((phys_addr_t)secondary_boot, sizeof(u32));
+ boot_reg = ioremap_nocache(
+ (phys_addr_t)secondary_boot_addr, sizeof(u32));
if (!boot_reg) {
pr_err("unable to map boot register for cpu %u\n", cpu_id);
- return -ENOSYS;
+ return -ENOMEM;
}
/*
@@ -191,12 +217,12 @@ static int bcm_boot_secondary(unsigned int cpu, struct task_struct *idle)
pr_err("timeout waiting for cpu %u to start\n", cpu_id);
- return -ENOSYS;
+ return -ENXIO;
}
static struct smp_operations bcm_smp_ops __initdata = {
.smp_prepare_cpus = bcm_smp_prepare_cpus,
- .smp_boot_secondary = bcm_boot_secondary,
+ .smp_boot_secondary = kona_boot_secondary,
};
CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
&bcm_smp_ops);
--
2.1.0
Add device tree changes required for providing SMP support
for Broadcom Northstar Plus SoC.
Signed-off-by: Kapil Hali <[email protected]>
---
arch/arm/boot/dts/bcm-nsp.dtsi | 33 +++++++++++++++++++++------------
1 file changed, 21 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 58aca27..4c52417 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -40,24 +40,33 @@
model = "Broadcom Northstar Plus SoC";
interrupt-parent = <&gic>;
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "brcm,bcm-nsp-smp";
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ next-level-cache = <&L2>;
+ reg = <0x0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ next-level-cache = <&L2>;
+ secondary-boot-reg = <0xffff042c>;
+ reg = <0x1>;
+ };
+ };
+
mpcore {
compatible = "simple-bus";
ranges = <0x00000000 0x19020000 0x00003000>;
#address-cells = <1>;
#size-cells = <1>;
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- next-level-cache = <&L2>;
- reg = <0x0>;
- };
- };
-
L2: l2-cache {
compatible = "arm,pl310-cache";
reg = <0x2000 0x1000>;
--
2.1.0
Add SMP support for Broadcom's Northstar Plus SoC
cpu enable method. This changes also consolidates
iProc family's - BCM NSP and BCM Kona, platform
SMP handling in a common file.
Northstar Plus SoC is based on ARM Cortex-A9
revision r3p0 which requires configuration for ARM
Errata 764369 for SMP. This change adds the needed
configuration option.
Signed-off-by: Kapil Hali <[email protected]>
---
arch/arm/mach-bcm/Kconfig | 2 +
arch/arm/mach-bcm/Makefile | 8 +++-
arch/arm/mach-bcm/{kona_smp.c => platsmp.c} | 64 ++++++++++++++++++++++++++++-
3 files changed, 71 insertions(+), 3 deletions(-)
rename arch/arm/mach-bcm/{kona_smp.c => platsmp.c} (81%)
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 8c53c55..83765a0 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -40,6 +40,8 @@ config ARCH_BCM_NSP
select ARCH_BCM_IPROC
select ARM_ERRATA_754322
select ARM_ERRATA_775420
+ select ARM_ERRATA_764369 if SMP
+ select HAVE_SMP
help
Support for Broadcom Northstar Plus SoC.
Broadcom Northstar Plus family of SoCs are used for switching control
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 892261f..5193a25 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -14,7 +14,11 @@
obj-$(CONFIG_ARCH_BCM_CYGNUS) += bcm_cygnus.o
# Northstar Plus
-obj-$(CONFIG_ARCH_BCM_NSP) += bcm_nsp.o
+obj-$(CONFIG_ARCH_BCM_NSP) += bcm_nsp.o
+
+ifeq ($(CONFIG_ARCH_BCM_NSP),y)
+obj-$(CONFIG_SMP) += platsmp.o
+endif
# BCM281XX
obj-$(CONFIG_ARCH_BCM_281XX) += board_bcm281xx.o
@@ -23,7 +27,7 @@ obj-$(CONFIG_ARCH_BCM_281XX) += board_bcm281xx.o
obj-$(CONFIG_ARCH_BCM_21664) += board_bcm21664.o
# BCM281XX and BCM21664 SMP support
-obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += kona_smp.o
+obj-$(CONFIG_ARCH_BCM_MOBILE_SMP) += platsmp.o
# BCM281XX and BCM21664 L2 cache control
obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o
diff --git a/arch/arm/mach-bcm/kona_smp.c b/arch/arm/mach-bcm/platsmp.c
similarity index 81%
rename from arch/arm/mach-bcm/kona_smp.c
rename to arch/arm/mach-bcm/platsmp.c
index 15af781..ea4201e 100644
--- a/arch/arm/mach-bcm/kona_smp.c
+++ b/arch/arm/mach-bcm/platsmp.c
@@ -12,12 +12,17 @@
* GNU General Public License for more details.
*/
-#include <linux/init.h>
+#include <linux/cpumask.h>
+#include <linux/delay.h>
#include <linux/errno.h>
+#include <linux/init.h>
#include <linux/io.h>
+#include <linux/jiffies.h>
#include <linux/of.h>
#include <linux/sched.h>
+#include <linux/smp.h>
+#include <asm/cacheflush.h>
#include <asm/smp.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
@@ -76,6 +81,36 @@ static int __init scu_a9_enable(void)
return 0;
}
+static int nsp_write_lut(void)
+{
+ void __iomem *sku_rom_lut;
+ phys_addr_t secondary_startup_phy;
+
+ if (!secondary_boot_addr) {
+ pr_warn("required secondary boot register not specified\n");
+ return -EINVAL;
+ }
+
+ sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot_addr,
+ sizeof(secondary_boot_addr));
+ if (!sku_rom_lut) {
+ pr_warn("unable to ioremap SKU-ROM LUT register\n");
+ return -ENOMEM;
+ }
+
+ secondary_startup_phy = virt_to_phys(secondary_startup);
+ BUG_ON(secondary_startup_phy > (phys_addr_t)U32_MAX);
+
+ writel_relaxed(secondary_startup_phy, sku_rom_lut);
+
+ /* Ensure the write is visible to the secondary core */
+ smp_wmb();
+
+ iounmap(sku_rom_lut);
+
+ return 0;
+}
+
static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
{
static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
@@ -220,9 +255,36 @@ static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
return -ENXIO;
}
+static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ int ret;
+
+ /*
+ * After wake up, secondary core branches to the startup
+ * address programmed at SKU ROM LUT location.
+ */
+ ret = nsp_write_lut();
+ if (ret) {
+ pr_err("unable to write startup addr to SKU ROM LUT\n");
+ goto out;
+ }
+
+ /* Send a CPU wakeup interrupt to the secondary core */
+ arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+out:
+ return ret;
+}
+
static struct smp_operations bcm_smp_ops __initdata = {
.smp_prepare_cpus = bcm_smp_prepare_cpus,
.smp_boot_secondary = kona_boot_secondary,
};
CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
&bcm_smp_ops);
+
+struct smp_operations nsp_smp_ops __initdata = {
+ .smp_prepare_cpus = bcm_smp_prepare_cpus,
+ .smp_boot_secondary = nsp_boot_secondary,
+};
+CPU_METHOD_OF_DECLARE(bcm_smp_nsp, "brcm,bcm-nsp-smp", &nsp_smp_ops);
--
2.1.0
From: Jon Mason <[email protected]>
Add SMP support for Broadcom's 4708 SoCs.
Signed-off-by: Jon Mason <[email protected]>
Acked-by: Hauke Mehrtens <[email protected]>
Tested-by: Hauke Mehrtens <[email protected]>
Signed-off-by: Kapil Hali <[email protected]>
---
arch/arm/boot/dts/bcm4708.dtsi | 2 ++
arch/arm/mach-bcm/Kconfig | 1 +
arch/arm/mach-bcm/Makefile | 3 +++
3 files changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/bcm4708.dtsi b/arch/arm/boot/dts/bcm4708.dtsi
index 31141e8..eed4dd1 100644
--- a/arch/arm/boot/dts/bcm4708.dtsi
+++ b/arch/arm/boot/dts/bcm4708.dtsi
@@ -15,6 +15,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "brcm,bcm-nsp-smp";
cpu@0 {
device_type = "cpu";
@@ -27,6 +28,7 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
+ secondary-boot-reg = <0xffff0400>;
reg = <0x1>;
};
};
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 83765a0..e85246f 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -54,6 +54,7 @@ config ARCH_BCM_NSP
config ARCH_BCM_5301X
bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
select ARCH_BCM_IPROC
+ select HAVE_SMP
help
Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 5193a25..7d66515 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -43,6 +43,9 @@ obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o
# BCM5301X
obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o
+ifeq ($(CONFIG_ARCH_BCM_5301X),y)
+obj-$(CONFIG_SMP) += platsmp.o
+endif
# BCM63XXx
ifeq ($(CONFIG_ARCH_BCM_63XX),y)
--
2.1.0
On 01/12/15 08:24, Kapil Hali wrote:
> Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
> Northstar Plus CPU to the 32-bit ARM CPU device tree binding
> documentation file and create a new binding documentation for
> Northstar Plus CPU.
>
> Signed-off-by: Kapil Hali <[email protected]>
Applied to devicetree/next, thanks!
--
Florian
On 01/12/15 08:24, Kapil Hali wrote:
> Add device tree changes required for providing SMP support
> for Broadcom Northstar Plus SoC.
>
> Signed-off-by: Kapil Hali <[email protected]>
Applied to devicetree/next, thanks!
--
Florian
On 01/12/15 08:24, Kapil Hali wrote:
> These changes cleans up SMP implementaion for Broadcom's
> Kona SoC which are required for handling SMP for iProc
> family of SoCs at a single place for BCM NSP and BCM Kona.
>
> Signed-off-by: Kapil Hali <[email protected]>
Applied to soc/next, thanks!
--
Florian
On 01/12/15 08:24, Kapil Hali wrote:
> Add SMP support for Broadcom's Northstar Plus SoC
> cpu enable method. This changes also consolidates
> iProc family's - BCM NSP and BCM Kona, platform
> SMP handling in a common file.
>
> Northstar Plus SoC is based on ARM Cortex-A9
> revision r3p0 which requires configuration for ARM
> Errata 764369 for SMP. This change adds the needed
> configuration option.
>
> Signed-off-by: Kapil Hali <[email protected]>
Applied to soc/next, thanks!
--
Florian
On 01/12/15 08:24, Kapil Hali wrote:
> From: Jon Mason <[email protected]>
>
> Add SMP support for Broadcom's 4708 SoCs.
>
> Signed-off-by: Jon Mason <[email protected]>
> Acked-by: Hauke Mehrtens <[email protected]>
> Tested-by: Hauke Mehrtens <[email protected]>
> Signed-off-by: Kapil Hali <[email protected]>
Applied to soc/next, thanks!
--
Florian
On 01/12/15 08:24, Kapil Hali wrote:
> These changes cleans up SMP implementaion for Broadcom's
> Kona SoC which are required for handling SMP for iProc
> family of SoCs at a single place for BCM NSP and BCM Kona.
FWIW, I gave this patch a try on a Capri board, and this still brings-up
the two CPUs successfully:
MMC read: dev # 0, block # 114688, count 32768 ...
100% (32768/32768 blocks)
32768 blocks read: OK
## Starting application at 0x80008000 ...
Uncompressing Linux... done, booting the kernel.
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.4.0-rc1-00005-ge49c96ed573e
(fainelli@fainelli-desktop) (gcc version 4.
8.5 (Broadcom stbgcc-4.8-1.4) ) #605 SMP Tue Dec 1 17:53:02 PST 2015
[ 0.000000] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7),
cr=10c5387d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing
instruction cache
[ 0.000000] Machine model: BCM28155 AP board
[ 0.000000] cma: Reserved 16 MiB at 0xbf000000
[ 0.000000] Memory policy: Data cache writealloc
[ 0.000000] PERCPU: Embedded 12 pages/cpu @ef7d3000 s18752 r8192
d22208 u49152
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on.
Total pages: 260608
[ 0.000000] Kernel command line: console=ttyS0,115200n8
[ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288
bytes)
[ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144
bytes)
[ 0.000000] Memory: 1009696K/1048576K available (6384K kernel code,
279K rwdata, 2268K rodata, 4152
K init, 218K bss, 22496K reserved, 16384K cma-reserved, 245760K highmem)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xffc00000 - 0xfff00000 (3072 kB)
[ 0.000000] vmalloc : 0xf0800000 - 0xff800000 ( 240 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xf0000000 ( 768 MB)
[ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
[ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB)
[ 0.000000] .text : 0xc0008000 - 0xc087b694 (8654 kB)
[ 0.000000] .init : 0xc087c000 - 0xc0c8a000 (4152 kB)
[ 0.000000] .data : 0xc0c8a000 - 0xc0ccfdf8 ( 280 kB)
[ 0.000000] .bss : 0xc0cd2000 - 0xc0d08bac ( 219 kB)
[ 0.000000] Hierarchical RCU implementation.
[ 0.000000] Build-time adjustment of leaf fanout to 32.
[ 0.000000] RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=32,
nr_cpu_ids=2
[ 0.000000] NR_IRQS:16 nr_irqs:16 16
[ 0.000000] __ccu_wait_bit: slave_ccu/0x0484 bit 18 was never set
[ 0.000000] __peri_clk_init: error initializing gate for bsc3
[ 0.000000] Broadcom slave_ccu initialization had errors
[ 0.000000] sched_clock: 32 bits at 1kHz, resolution 1000000ns, wraps
every 2147483647500000ns
[ 0.000000] Console: colour dummy device 80x30
[ 0.006000] Calibrating delay loop... 2383.87 BogoMIPS (lpj=1191936)
[ 0.006000] pid_max: default: 32768 minimum: 301
[ 0.006000] Mount-cache hash table entries: 2048 (order: 1, 8192
bytes)
[ 0.006000] Mountpoint-cache hash table entries: 2048 (order: 1, 8192
bytes)
[ 0.006000] CPU: Testing write buffer coherency: ok
[ 0.006000] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.006000] Setting up static identity map for 0x800082c0 -
0x80008318
[ 0.015000] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[ 0.015000] Brought up 2 CPUs
[ 0.015000] SMP: Total of 2 processors activated (7200.76 BogoMIPS).
[ 0.015000] CPU: All CPU(s) started in SVC mode.
[ 0.015000] devtmpfs: initialized
[ 0.016000] VFP support v0.3: implementor 41 architecture 3 part 30
variant 9 rev 4
[ 0.016000] clocksource: jiffies: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 19112604462
75000 ns
[ 0.016000] pinctrl core: initialized pinctrl subsystem
[ 0.017000] NET: Registered protocol family 16
[ 0.017000] DMA: preallocated 256 KiB pool for atomic coherent
allocations
[ 0.023000] cpuidle: using governor ladder
[ 0.025000] cpuidle: using governor menu
[ 0.026000] Kona Secure API initialized
[ 0.026000] BCM-L2C-310 cache controller enabled, 16 ways, 512 kB
[ 0.026000] BCM-L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x1e050000
[ 0.026000] hw-breakpoint: found 5 (+1 reserved) breakpoint and 1
watchpoint registers.
[ 0.026000] hw-breakpoint: maximum watchpoint size is 4 bytes.
[ 0.033000] SCSI subsystem initialized
[ 0.033000] usbcore: registered new interface driver usbfs
[ 0.033000] usbcore: registered new interface driver hub
[ 0.033000] usbcore: registered new device driver usb
[ 0.033000] Linux video capture interface: v2.00
[ 0.033000] pps_core: LinuxPPS API ver. 1 registered
[ 0.033000] pps_core: Software ver. 5.3.6 - Copyright 2005-2007
Rodolfo Giometti <[email protected]
>
[ 0.033000] PTP clock support registered
[ 0.034000] Advanced Linux Sound Architecture Driver Initialized.
[ 0.037000] NET: Registered protocol family 2
[ 0.037000] TCP established hash table entries: 8192 (order: 3, 32768
bytes)
[ 0.038000] TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
[ 0.038000] TCP: Hash tables configured (established 8192 bind 8192)
[ 0.038000] UDP hash table entries: 512 (order: 2, 16384 bytes)
[ 0.038000] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
[ 0.038000] NET: Registered protocol family 1
[ 0.038000] RPC: Registered named UNIX socket transport module.
[ 0.038000] RPC: Registered udp transport module.
[ 0.038000] RPC: Registered tcp transport module.
[ 0.038000] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 0.114000] futex hash table entries: 512 (order: 3, 32768 bytes)
[ 0.114000] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[ 0.114000] NFS: Registering the id_resolver key type
[ 0.114000] Key type id_resolver registered
[ 0.114000] Key type id_legacy registered
[ 0.114000] nfs4filelayout_init: NFSv4 File Layout Driver
Registering...
[ 0.114000] jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
[ 0.114000] fuse init (API version 7.23)
[ 0.115000] bounce: pool size: 64 pages
[ 0.115000] Block layer SCSI generic (bsg) driver version 0.4 loaded
(major 252)
[ 0.115000] io scheduler noop registered
[ 0.115000] io scheduler deadline registered
[ 0.115000] io scheduler cfq registered (default)
[ 0.115000] bcm-kona-gpio 35003000.gpio: Setting up Kona GPIO
[ 0.138000] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 0.139000] console [ttyS0] disabled
[ 0.139000] 3e000000.uart: ttyS0 at MMIO 0x3e000000 (irq = 17,
base_baud = 808290) is a 16550A
[ 0.415000] console [ttyS0] enabled
[ 0.421000] brd: module loaded
[ 0.423000] loop: module loaded
[ 0.424000] libphy: Fixed MDIO Bus: probed
[ 0.425000] cnic: QLogic cnicDriver v2.5.22 (July 20, 2015)
[ 0.426000] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
[ 0.427000] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
[ 0.428000] pegasus: v0.9.3 (2013/04/25), Pegasus/Pegasus II USB
Ethernet driver
[ 0.429000] usbcore: registered new interface driver pegasus
[ 0.430000] usbcore: registered new interface driver asix
[ 0.431000] usbcore: registered new interface driver ax88179_178a
[ 0.432000] usbcore: registered new interface driver cdc_ether
[ 0.433000] usbcore: registered new interface driver cdc_ncm
[ 0.434000] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI)
Driver
[ 0.435000] ehci-pci: EHCI PCI platform driver
[ 0.436000] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[ 0.437000] ohci-pci: OHCI PCI platform driver
[ 0.438000] usbcore: registered new interface driver usb-storage
[ 0.439000] mousedev: PS/2 mouse device common for all mice
[ 0.440000] i2c /dev entries driver
[ 0.441000] bcm-kona-i2c 3e016000.i2c: device registered successfully
[ 0.442000] bcm-kona-i2c 3e017000.i2c: device registered successfully
[ 0.443000] bcm-kona-i2c 3e018000.i2c: device registered successfully
[ 0.444000] bcm-kona-i2c 3500d000.i2c: device registered successfully
[ 0.445000] gspca_main: v2.14.0 registered
[ 0.446000] sdhci: Secure Digital Host Controller Interface driver
[ 0.447000] sdhci: Copyright(c) Pierre Ossman
[ 0.448000] sdhci-pltfm: SDHCI platform and OF driver helper
[ 0.452000] sdhci-kona 3f190000.sdio: No vmmc regulator found
[ 0.453000] sdhci-kona 3f190000.sdio: No vqmmc regulator found
[ 0.483000] mmc0: SDHCI controller on 3f190000.sdio [3f190000.sdio]
using ADMA
[ 0.485000] sdhci-kona 3f1b0000.sdio: Got CD GPIO
[ 0.489000] sdhci-kona 3f1b0000.sdio: No vmmc regulator found
[ 0.490000] sdhci-kona 3f1b0000.sdio: No vqmmc regulator found
[ 0.519000] mmc1: SDHCI controller on 3f1b0000.sdio [3f1b0000.sdio]
using ADMA
[ 0.520000] usbcore: registered new interface driver usbhid
[ 0.521000] usbhid: USB HID core driver
[ 0.522000] NET: Registered protocol family 17
[ 0.523000] bridge: automatic filtering via arp/ip/ip6tables has been
deprecated. Update your scrip
ts to load br_netfilter if you need this.
[ 0.524000] 8021q: 802.1Q VLAN Support v1.8
[ 0.525000] Key type dns_resolver registered
[ 0.526000] Registering SWP/SWPB emulation handler
[ 0.527000] ALSA device list:
[ 0.528000] No soundcards found.
[ 0.529000] ttyS0 - failed to request DMA
[ 0.531000] Freeing unused kernel memory: 4152K (c087c000 - c0c8a000)
starting pid 1114, tty '': '/etc/init.d/rcS'
Mounting virtual filesystems
[ 0.548000] mmc0: MAN_BKOPS_EN bit is not set
[ 0.554000] mmc0: new high speed MMC card at address 0001
[ 0.557000] mmcblk0: mmc0:0001 016G4A 14.8 GiB
[ 0.560000] mmcblk0boot0: mmc0:0001 016G4A partition 1 2.00 MiB
* WARNING: THIS STB CONTAINS GPLv3 SOFTWARE[ 0.564000] mmcblk0boot1:
mmc0:0001 016G4A partition 2 2
.00 MiB
* GPLv3 programs must be removed in order to enable security.
* See: http://www.gnu.org/licenses/gpl-faq.html#Tivoization
[ 0.570000] mmcblk0rpmb: mmc0:0001 016G4A partition 3 256 KiB
Configuring lo interface
[ 0.577000] Alternate GPT is invalid, using primary GPT.
[ 0.580000] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14
p15
Starting network services
starting pid 1211, tty '': '/bin/cttyhack /bin/sh -l'
#
# ps awwux
USER PID %CPU %MEM VSZ RSS TTY STAT START TIME COMMAND
root 1 22.0 0.1 1928 1244 ? Ss 00:00 0:00 init
root 2 0.0 0.0 0 0 ? S 00:00 0:00
[kthreadd]
root 3 0.0 0.0 0 0 ? S 00:00 0:00
[ksoftirqd/0]
root 4 0.0 0.0 0 0 ? S 00:00 0:00
[kworker/0:0]
root 5 0.0 0.0 0 0 ? S< 00:00 0:00
[kworker/0:0H]
root 6 0.0 0.0 0 0 ? S 00:00 0:00
[kworker/u4:0]
root 7 0.0 0.0 0 0 ? S 00:00 0:00
[rcu_sched]
root 8 0.0 0.0 0 0 ? S 00:00 0:00
[rcu_bh]
root 9 0.0 0.0 0 0 ? S 00:00 0:00
[migration/0]
root 10 0.0 0.0 0 0 ? S 00:00 0:00
[watchdog/0]
root 11 0.0 0.0 0 0 ? S 00:00 0:00
[watchdog/1]
root 12 0.0 0.0 0 0 ? S 00:00 0:00
[migration/1]
root 13 0.0 0.0 0 0 ? S 00:00 0:00
[ksoftirqd/1]
root 14 0.0 0.0 0 0 ? S 00:00 0:00
[kworker/1:0]
root 15 0.0 0.0 0 0 ? S< 00:00 0:00
[kworker/1:0H]
root 16 0.0 0.0 0 0 ? S 00:00 0:00
[kdevtmpfs]
root 17 2.0 0.0 0 0 ? S 00:00 0:00
[kworker/u4:1]
root 18 0.0 0.0 0 0 ? S< 00:00 0:00 [perf]
root 24 0.0 0.0 0 0 ? S 00:00 0:00
[kworker/u4:2]
root 248 0.0 0.0 0 0 ? S 00:00 0:00
[khungtaskd]
root 249 0.0 0.0 0 0 ? S< 00:00 0:00
[writeback]
root 250 0.0 0.0 0 0 ? S< 00:00 0:00
[crypto]
root 252 0.0 0.0 0 0 ? S< 00:00 0:00
[bioset]
root 253 0.0 0.0 0 0 ? S 00:00 0:00
[kworker/0:1]
root 254 0.0 0.0 0 0 ? S< 00:00 0:00
[kblockd]
root 256 0.0 0.0 0 0 ? S< 00:00 0:00
[ata_sff]
root 376 0.0 0.0 0 0 ? S< 00:00 0:00
[rpciod]
root 389 0.0 0.0 0 0 ? S 00:00 0:00 [kswapd0]
root 390 0.0 0.0 0 0 ? S 00:00 0:00
[fsnotify_mark]
root 391 0.0 0.0 0 0 ? S< 00:00 0:00 [nfsiod]
root 943 0.0 0.0 0 0 ? S 00:00 0:00
[kworker/1:1]
root 947 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 950 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 951 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 952 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 953 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 954 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 955 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 956 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 957 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 958 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 959 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 960 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 961 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 962 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 963 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 964 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 998 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 1001 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 1004 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 1007 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 1010 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 1013 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 1016 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 1019 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 1051 0.0 0.0 0 0 ? S< 00:00 0:00 [cnic_wq]
root 1074 0.0 0.0 0 0 ? S< 00:00 0:00 [kpsmoused]
root 1092 0.0 0.0 0 0 ? S 00:00 0:00
[irq/24-mmc0]
root 1094 0.0 0.0 0 0 ? S 00:00 0:00
[irq/25-mmc1]
root 1096 0.0 0.0 0 0 ? S 00:00 0:00
[irq/31-3f1b0000]
root 1111 0.0 0.0 0 0 ? S< 00:00 0:00 [deferwq]
root 1127 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 1130 0.0 0.0 0 0 ? S 00:00 0:00 [mmcqd/0]
root 1131 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 1133 0.0 0.0 0 0 ? S 00:00 0:00
[mmcqd/0boot0]
root 1134 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 1137 0.0 0.0 0 0 ? S 00:00 0:00
[mmcqd/0boot1]
root 1138 0.0 0.0 0 0 ? S< 00:00 0:00 [bioset]
root 1140 0.0 0.0 0 0 ? S 00:00 0:00
[mmcqd/0rpmb]
bin 1174 0.0 0.1 1452 1072 ? Ss 00:00 0:00 portmap
root 1210 0.0 0.0 1928 56 ? Ss 00:00 0:00 telnetd
root 1211 0.0 0.1 1968 1632 ttyS0 Ss 00:00 0:00 /bin/sh -l
root 1219 0.0 0.1 1948 1124 ttyS0 R+ 00:00 0:00 ps awwux
c# cat /proc/cpuinfo
processor : 0
model name : ARMv7 Processor rev 0 (v7l)
BogoMIPS : 2383.87
Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpd32
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x3
CPU part : 0xc09
CPU revision : 0
processor : 1
model name : ARMv7 Processor rev 0 (v7l)
BogoMIPS : 4816.89
Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpd32
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x3
CPU part : 0xc09
CPU revision : 0
Hardware : BCM281xx Broadcom Application Processor
Revision : 0000
Serial : 0000000000000000
#
--
Florian
On 12/01/2015 05:24 PM, Kapil Hali wrote:
> From: Jon Mason <[email protected]>
>
> Add SMP support for Broadcom's 4708 SoCs.
>
> Signed-off-by: Jon Mason <[email protected]>
> Acked-by: Hauke Mehrtens <[email protected]>
> Tested-by: Hauke Mehrtens <[email protected]>
> Signed-off-by: Kapil Hali <[email protected]>
> ---
> arch/arm/boot/dts/bcm4708.dtsi | 2 ++
> arch/arm/mach-bcm/Kconfig | 1 +
> arch/arm/mach-bcm/Makefile | 3 +++
> 3 files changed, 6 insertions(+)
>
> diff --git a/arch/arm/boot/dts/bcm4708.dtsi b/arch/arm/boot/dts/bcm4708.dtsi
> index 31141e8..eed4dd1 100644
> --- a/arch/arm/boot/dts/bcm4708.dtsi
> +++ b/arch/arm/boot/dts/bcm4708.dtsi
> @@ -15,6 +15,7 @@
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> + enable-method = "brcm,bcm-nsp-smp";
>
> cpu@0 {
> device_type = "cpu";
> @@ -27,6 +28,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a9";
> next-level-cache = <&L2>;
> + secondary-boot-reg = <0xffff0400>;
> reg = <0x1>;
> };
> };
> diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
> index 83765a0..e85246f 100644
> --- a/arch/arm/mach-bcm/Kconfig
> +++ b/arch/arm/mach-bcm/Kconfig
> @@ -54,6 +54,7 @@ config ARCH_BCM_NSP
> config ARCH_BCM_5301X
> bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
> select ARCH_BCM_IPROC
> + select HAVE_SMP
> help
> Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
>
When applying this patch please make sure it is correctly applied this
patch causes some problems here:
http://www.spinics.net/lists/arm-kernel/msg462137.html
> diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
> index 5193a25..7d66515 100644
> --- a/arch/arm/mach-bcm/Makefile
> +++ b/arch/arm/mach-bcm/Makefile
> @@ -43,6 +43,9 @@ obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o
>
> # BCM5301X
> obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o
> +ifeq ($(CONFIG_ARCH_BCM_5301X),y)
> +obj-$(CONFIG_SMP) += platsmp.o
> +endif
>
> # BCM63XXx
> ifeq ($(CONFIG_ARCH_BCM_63XX),y)
>
I am getting this on a Northstar 1 / BCM4708:
[ 0.137634] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.143643] Setting up static identity map for 0x82a0 - 0x82d4
[ 0.189772] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[ 0.189861] Brought up 2 CPUs
[ 0.198845] SMP: Total of 2 processors activated (3188.32 BogoMIPS).
[ 0.205446] CPU: WARNING: CPU(s) started in wrong/inconsistent modes
(primary CPU mode 0x13)
[ 0.214167] CPU: This may indicate a broken bootloader or firmware.
I assume that this is correct and the bootloader is just broken, it uses
this bootloader: "CFE for Foxconn Router version: v1.0.14", I haven't
noticed any problems, so it is ok for me.
Hauke
On Tue, Dec 01, 2015 at 11:24:05AM -0500, Kapil Hali wrote:
> Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
> Northstar Plus CPU to the 32-bit ARM CPU device tree binding
> documentation file and create a new binding documentation for
> Northstar Plus CPU.
>
> Signed-off-by: Kapil Hali <[email protected]>
> ---
> .../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 39 ++++++++++++++++++++++
> Documentation/devicetree/bindings/arm/cpus.txt | 1 +
> 2 files changed, 40 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> new file mode 100644
> index 0000000..bf08872
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
> @@ -0,0 +1,39 @@
> +Broadcom Northstar Plus SoC CPU Enable Method
> +---------------------------------------------
> +This binding defines the enable method used for starting secondary
> +CPUs in the following Broadcom SoCs:
> + BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
> +
> +The enable method is specified by defining the following required
> +properties in the "cpus" device tree node:
> + - enable-method = "brcm,bcm-nsp-smp";
> + - secondary-boot-reg = <...>;
Both of these are supposed to be per cpu core.
Rob
> +
> +The secondary-boot-reg property is a u32 value that specifies the
> +physical address of the register which should hold the common
> +entry point for a secondary CPU. This entry is cpu node specific
> +and should be added per cpu. E.g., in case of NSP (BCM58625) which
> +is a dual core CPU SoC, this entry should be added to cpu1 node.
> +
> +
> +Example:
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + enable-method = "brcm,bcm-nsp-smp";
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a9";
> + next-level-cache = <&L2>;
> + reg = <0>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a9";
> + next-level-cache = <&L2>;
> + reg = <1>;
> + secondary-boot-reg = <0xffff042c>;
> + };
> + };
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index 3a07a87..d191554 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -190,6 +190,7 @@ nodes to be present and contain the properties described below.
> "allwinner,sun6i-a31"
> "allwinner,sun8i-a23"
> "arm,psci"
> + "brcm,bcm-nsp-smp"
> "brcm,brahma-b15"
> "marvell,armada-375-smp"
> "marvell,armada-380-smp"
> --
> 2.1.0
>
Hi Rob,
On 12/2/2015 8:56 PM, Rob Herring wrote:
> On Tue, Dec 01, 2015 at 11:24:05AM -0500, Kapil Hali wrote:
>> Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
>> Northstar Plus CPU to the 32-bit ARM CPU device tree binding
>> documentation file and create a new binding documentation for
>> Northstar Plus CPU.
>>
>> Signed-off-by: Kapil Hali <[email protected]>
>> ---
>> .../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 39 ++++++++++++++++++++++
>> Documentation/devicetree/bindings/arm/cpus.txt | 1 +
>> 2 files changed, 40 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>>
>> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>> new file mode 100644
>> index 0000000..bf08872
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>> @@ -0,0 +1,39 @@
>> +Broadcom Northstar Plus SoC CPU Enable Method
>> +---------------------------------------------
>> +This binding defines the enable method used for starting secondary
>> +CPUs in the following Broadcom SoCs:
>> + BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
>> +
>> +The enable method is specified by defining the following required
>> +properties in the "cpus" device tree node:
>> + - enable-method = "brcm,bcm-nsp-smp";
>> + - secondary-boot-reg = <...>;
>
> Both of these are supposed to be per cpu core.
'enable-method' if not found in 'cpu' node is looked at in the 'cpus'
node. Except for two-three SoC families, 'enable-method' is within
'cpus' node. Is my interpretation incorrect? Did I miss anything here?
>
> Rob
>
>> +
>> +The secondary-boot-reg property is a u32 value that specifies the
>> +physical address of the register which should hold the common
>> +entry point for a secondary CPU. This entry is cpu node specific
>> +and should be added per cpu. E.g., in case of NSP (BCM58625) which
>> +is a dual core CPU SoC, this entry should be added to cpu1 node.
>> +
>> +
>> +Example:
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + enable-method = "brcm,bcm-nsp-smp";
>> +
>> + cpu0: cpu@0 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a9";
>> + next-level-cache = <&L2>;
>> + reg = <0>;
>> + };
>> +
>> + cpu1: cpu@1 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a9";
>> + next-level-cache = <&L2>;
>> + reg = <1>;
>> + secondary-boot-reg = <0xffff042c>;
>> + };
>> + };
>> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
>> index 3a07a87..d191554 100644
>> --- a/Documentation/devicetree/bindings/arm/cpus.txt
>> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
>> @@ -190,6 +190,7 @@ nodes to be present and contain the properties described below.
>> "allwinner,sun6i-a31"
>> "allwinner,sun8i-a23"
>> "arm,psci"
>> + "brcm,bcm-nsp-smp"
>> "brcm,brahma-b15"
>> "marvell,armada-375-smp"
>> "marvell,armada-380-smp"
>> --
>> 2.1.0
>>
>
Thanks,
Kapil
On Wed, Dec 02, 2015 at 04:03:03PM +0100, Hauke Mehrtens wrote:
> On 12/01/2015 05:24 PM, Kapil Hali wrote:
> > From: Jon Mason <[email protected]>
> >
> > Add SMP support for Broadcom's 4708 SoCs.
> >
> > Signed-off-by: Jon Mason <[email protected]>
> > Acked-by: Hauke Mehrtens <[email protected]>
> > Tested-by: Hauke Mehrtens <[email protected]>
> > Signed-off-by: Kapil Hali <[email protected]>
> > ---
> > arch/arm/boot/dts/bcm4708.dtsi | 2 ++
> > arch/arm/mach-bcm/Kconfig | 1 +
> > arch/arm/mach-bcm/Makefile | 3 +++
> > 3 files changed, 6 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/bcm4708.dtsi b/arch/arm/boot/dts/bcm4708.dtsi
> > index 31141e8..eed4dd1 100644
> > --- a/arch/arm/boot/dts/bcm4708.dtsi
> > +++ b/arch/arm/boot/dts/bcm4708.dtsi
> > @@ -15,6 +15,7 @@
> > cpus {
> > #address-cells = <1>;
> > #size-cells = <0>;
> > + enable-method = "brcm,bcm-nsp-smp";
> >
> > cpu@0 {
> > device_type = "cpu";
> > @@ -27,6 +28,7 @@
> > device_type = "cpu";
> > compatible = "arm,cortex-a9";
> > next-level-cache = <&L2>;
> > + secondary-boot-reg = <0xffff0400>;
> > reg = <0x1>;
> > };
> > };
> > diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
> > index 83765a0..e85246f 100644
> > --- a/arch/arm/mach-bcm/Kconfig
> > +++ b/arch/arm/mach-bcm/Kconfig
> > @@ -54,6 +54,7 @@ config ARCH_BCM_NSP
> > config ARCH_BCM_5301X
> > bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
> > select ARCH_BCM_IPROC
> > + select HAVE_SMP
> > help
> > Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
> >
>
> When applying this patch please make sure it is correctly applied this
> patch causes some problems here:
>
> http://www.spinics.net/lists/arm-kernel/msg462137.html
>
> > diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
> > index 5193a25..7d66515 100644
> > --- a/arch/arm/mach-bcm/Makefile
> > +++ b/arch/arm/mach-bcm/Makefile
> > @@ -43,6 +43,9 @@ obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o
> >
> > # BCM5301X
> > obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o
> > +ifeq ($(CONFIG_ARCH_BCM_5301X),y)
> > +obj-$(CONFIG_SMP) += platsmp.o
> > +endif
> >
> > # BCM63XXx
> > ifeq ($(CONFIG_ARCH_BCM_63XX),y)
> >
>
> I am getting this on a Northstar 1 / BCM4708:
>
> [ 0.137634] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
> [ 0.143643] Setting up static identity map for 0x82a0 - 0x82d4
> [ 0.189772] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
> [ 0.189861] Brought up 2 CPUs
> [ 0.198845] SMP: Total of 2 processors activated (3188.32 BogoMIPS).
> [ 0.205446] CPU: WARNING: CPU(s) started in wrong/inconsistent modes
> (primary CPU mode 0x13)
> [ 0.214167] CPU: This may indicate a broken bootloader or firmware.
>
> I assume that this is correct and the bootloader is just broken, it uses
> this bootloader: "CFE for Foxconn Router version: v1.0.14", I haven't
> noticed any problems, so it is ok for me.
On my 4708 SVK, I see the same issue
[ 0.090877] CPU: Testing write buffer coherency: ok
[ 0.091231] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.091377] Setting up static identity map for 0x82a0 - 0x82f8
[ 0.130146] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[ 0.130251] Brought up 2 CPUs
[ 0.130323] SMP: Total of 2 processors activated (3188.32 BogoMIPS).
[ 0.130345] CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x13)
[ 0.130374] CPU: This may indicate a broken bootloader or firmware.
I'll investigate it more and see if I can bottom out on the cause.
Thanks,
Jon
>
> Hauke
On 02/12/15 08:06, Kapil Hali wrote:
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>>> @@ -0,0 +1,39 @@
>>> +Broadcom Northstar Plus SoC CPU Enable Method
>>> +---------------------------------------------
>>> +This binding defines the enable method used for starting secondary
>>> +CPUs in the following Broadcom SoCs:
>>> + BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
>>> +
>>> +The enable method is specified by defining the following required
>>> +properties in the "cpus" device tree node:
>>> + - enable-method = "brcm,bcm-nsp-smp";
>>> + - secondary-boot-reg = <...>;
>>
>> Both of these are supposed to be per cpu core.
>
> 'enable-method' if not found in 'cpu' node is looked at in the 'cpus'
> node. Except for two-three SoC families, 'enable-method' is within
> 'cpus' node. Is my interpretation incorrect? Did I miss anything here?
So, what do we do from here? I would appreciate a timely answer from the
DT maintainers here so we can decide on the fate of this patch series
for 4.5.
Thank you
--
Florian
On Thu, Dec 03, 2015 at 04:08:36PM -0500, Jon Mason wrote:
> On Wed, Dec 02, 2015 at 04:03:03PM +0100, Hauke Mehrtens wrote:
> > On 12/01/2015 05:24 PM, Kapil Hali wrote:
> > > From: Jon Mason <[email protected]>
> > >
> > > Add SMP support for Broadcom's 4708 SoCs.
> > >
> > > Signed-off-by: Jon Mason <[email protected]>
> > > Acked-by: Hauke Mehrtens <[email protected]>
> > > Tested-by: Hauke Mehrtens <[email protected]>
> > > Signed-off-by: Kapil Hali <[email protected]>
> > > ---
> > > arch/arm/boot/dts/bcm4708.dtsi | 2 ++
> > > arch/arm/mach-bcm/Kconfig | 1 +
> > > arch/arm/mach-bcm/Makefile | 3 +++
> > > 3 files changed, 6 insertions(+)
> > >
> > > diff --git a/arch/arm/boot/dts/bcm4708.dtsi b/arch/arm/boot/dts/bcm4708.dtsi
> > > index 31141e8..eed4dd1 100644
> > > --- a/arch/arm/boot/dts/bcm4708.dtsi
> > > +++ b/arch/arm/boot/dts/bcm4708.dtsi
> > > @@ -15,6 +15,7 @@
> > > cpus {
> > > #address-cells = <1>;
> > > #size-cells = <0>;
> > > + enable-method = "brcm,bcm-nsp-smp";
> > >
> > > cpu@0 {
> > > device_type = "cpu";
> > > @@ -27,6 +28,7 @@
> > > device_type = "cpu";
> > > compatible = "arm,cortex-a9";
> > > next-level-cache = <&L2>;
> > > + secondary-boot-reg = <0xffff0400>;
> > > reg = <0x1>;
> > > };
> > > };
> > > diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
> > > index 83765a0..e85246f 100644
> > > --- a/arch/arm/mach-bcm/Kconfig
> > > +++ b/arch/arm/mach-bcm/Kconfig
> > > @@ -54,6 +54,7 @@ config ARCH_BCM_NSP
> > > config ARCH_BCM_5301X
> > > bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
> > > select ARCH_BCM_IPROC
> > > + select HAVE_SMP
> > > help
> > > Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
> > >
> >
> > When applying this patch please make sure it is correctly applied this
> > patch causes some problems here:
> >
> > http://www.spinics.net/lists/arm-kernel/msg462137.html
> >
> > > diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
> > > index 5193a25..7d66515 100644
> > > --- a/arch/arm/mach-bcm/Makefile
> > > +++ b/arch/arm/mach-bcm/Makefile
> > > @@ -43,6 +43,9 @@ obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o
> > >
> > > # BCM5301X
> > > obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o
> > > +ifeq ($(CONFIG_ARCH_BCM_5301X),y)
> > > +obj-$(CONFIG_SMP) += platsmp.o
> > > +endif
> > >
> > > # BCM63XXx
> > > ifeq ($(CONFIG_ARCH_BCM_63XX),y)
> > >
> >
> > I am getting this on a Northstar 1 / BCM4708:
> >
> > [ 0.137634] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
> > [ 0.143643] Setting up static identity map for 0x82a0 - 0x82d4
> > [ 0.189772] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
> > [ 0.189861] Brought up 2 CPUs
> > [ 0.198845] SMP: Total of 2 processors activated (3188.32 BogoMIPS).
> > [ 0.205446] CPU: WARNING: CPU(s) started in wrong/inconsistent modes
> > (primary CPU mode 0x13)
> > [ 0.214167] CPU: This may indicate a broken bootloader or firmware.
> >
> > I assume that this is correct and the bootloader is just broken, it uses
> > this bootloader: "CFE for Foxconn Router version: v1.0.14", I haven't
> > noticed any problems, so it is ok for me.
>
> On my 4708 SVK, I see the same issue
>
> [ 0.090877] CPU: Testing write buffer coherency: ok
> [ 0.091231] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
> [ 0.091377] Setting up static identity map for 0x82a0 - 0x82f8
> [ 0.130146] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
> [ 0.130251] Brought up 2 CPUs
> [ 0.130323] SMP: Total of 2 processors activated (3188.32 BogoMIPS).
> [ 0.130345] CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x13)
> [ 0.130374] CPU: This may indicate a broken bootloader or firmware.
>
> I'll investigate it more and see if I can bottom out on the cause.
I looked at previous versions of this patch, and the issue appears to
be present there as well. I'm not sure why I didn't notice it before.
I don't think "fixing" CFE is an option. Should we investigate the
possibility of setting the CPU mode of CPU1 in the early_boot of
Linux?
Thanks,
Jon
>
> Thanks,
> Jon
>
>
> >
> > Hauke
On Wed, Dec 2, 2015 at 10:06 AM, Kapil Hali <[email protected]> wrote:
> Hi Rob,
>
> On 12/2/2015 8:56 PM, Rob Herring wrote:
>> On Tue, Dec 01, 2015 at 11:24:05AM -0500, Kapil Hali wrote:
>>> Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
>>> Northstar Plus CPU to the 32-bit ARM CPU device tree binding
>>> documentation file and create a new binding documentation for
>>> Northstar Plus CPU.
>>>
>>> Signed-off-by: Kapil Hali <[email protected]>
>>> ---
>>> .../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 39 ++++++++++++++++++++++
>>> Documentation/devicetree/bindings/arm/cpus.txt | 1 +
>>> 2 files changed, 40 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>>> new file mode 100644
>>> index 0000000..bf08872
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>>> @@ -0,0 +1,39 @@
>>> +Broadcom Northstar Plus SoC CPU Enable Method
>>> +---------------------------------------------
>>> +This binding defines the enable method used for starting secondary
>>> +CPUs in the following Broadcom SoCs:
>>> + BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
>>> +
>>> +The enable method is specified by defining the following required
>>> +properties in the "cpus" device tree node:
>>> + - enable-method = "brcm,bcm-nsp-smp";
>>> + - secondary-boot-reg = <...>;
>>
>> Both of these are supposed to be per cpu core.
>
> 'enable-method' if not found in 'cpu' node is looked at in the 'cpus'
> node. Except for two-three SoC families, 'enable-method' is within
> 'cpus' node. Is my interpretation incorrect? Did I miss anything here?
I'm not sure how you counted, but it is much more than 2-3 that are
correct (including all of PPC). It is quite mixed in dts files, but it
is documented to be per cpu node, so lets follow the documentation
please.
Rob
Hi Rob,
On 12/6/2015 6:22 AM, Rob Herring wrote:
> On Wed, Dec 2, 2015 at 10:06 AM, Kapil Hali <[email protected]> wrote:
>> Hi Rob,
>>
>> On 12/2/2015 8:56 PM, Rob Herring wrote:
>>> On Tue, Dec 01, 2015 at 11:24:05AM -0500, Kapil Hali wrote:
>>>> Add a compatible string "brcm,bcm-nsp-smp" for Broadcom's
>>>> Northstar Plus CPU to the 32-bit ARM CPU device tree binding
>>>> documentation file and create a new binding documentation for
>>>> Northstar Plus CPU.
>>>>
>>>> Signed-off-by: Kapil Hali <[email protected]>
>>>> ---
>>>> .../bindings/arm/bcm/brcm,nsp-cpu-method.txt | 39 ++++++++++++++++++++++
>>>> Documentation/devicetree/bindings/arm/cpus.txt | 1 +
>>>> 2 files changed, 40 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>>>> new file mode 100644
>>>> index 0000000..bf08872
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,nsp-cpu-method.txt
>>>> @@ -0,0 +1,39 @@
>>>> +Broadcom Northstar Plus SoC CPU Enable Method
>>>> +---------------------------------------------
>>>> +This binding defines the enable method used for starting secondary
>>>> +CPUs in the following Broadcom SoCs:
>>>> + BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
>>>> +
>>>> +The enable method is specified by defining the following required
>>>> +properties in the "cpus" device tree node:
>>>> + - enable-method = "brcm,bcm-nsp-smp";
>>>> + - secondary-boot-reg = <...>;
>>>
>>> Both of these are supposed to be per cpu core.
>>
>> 'enable-method' if not found in 'cpu' node is looked at in the 'cpus'
>> node. Except for two-three SoC families, 'enable-method' is within
>> 'cpus' node. Is my interpretation incorrect? Did I miss anything here?
>
> I'm not sure how you counted, but it is much more than 2-3 that are
> correct (including all of PPC). It is quite mixed in dts files, but it
> is documented to be per cpu node, so lets follow the documentation
> please.
>
> Rob
>
I looked at arch/arm/* and not other arch types. But, as you said, let
us keep it how it is in documentation and I have already updated latest
patch set reflecting this change.
Thanks,
Kapil