The current bridge driver always forced us to use 24 bits per pixel
over the DP link. This is a waste if you are hooked up to a panel
that only supports 6 bits per color or fewer, since in that case you
ran run at 18 bits per pixel and thus end up at a lower DP clock rate.
Let's support this.
While at it, let's clean up the math in the function to avoid rounding
errors (and round in the correct direction when we have to round).
Numbers are sufficiently small (because mode->clock is in kHz) that we
don't need to worry about integer overflow.
Signed-off-by: Douglas Anderson <[email protected]>
Tested-by: Rob Clark <[email protected]>
Reviewed-by: Rob Clark <[email protected]>
---
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/bridge/ti-sn65dsi86.c | 27 ++++++++++++++++++---------
1 file changed, 18 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
index 0fc9e97b2d98..d5990a0947b9 100644
--- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
@@ -51,6 +51,7 @@
#define SN_ENH_FRAME_REG 0x5A
#define VSTREAM_ENABLE BIT(3)
#define SN_DATA_FORMAT_REG 0x5B
+#define BPP_18_RGB BIT(0)
#define SN_HPD_DISABLE_REG 0x5C
#define HPD_DISABLE BIT(0)
#define SN_AUX_WDATA_REG(x) (0x64 + (x))
@@ -436,6 +437,14 @@ static void ti_sn_bridge_set_dsi_rate(struct ti_sn_bridge *pdata)
regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
}
+static unsigned int ti_sn_bridge_get_bpp(struct ti_sn_bridge *pdata)
+{
+ if (pdata->connector.display_info.bpc <= 6)
+ return 18;
+ else
+ return 24;
+}
+
/**
* LUT index corresponds to register value and
* LUT values corresponds to dp data rate supported
@@ -447,21 +456,17 @@ static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
static void ti_sn_bridge_set_dp_rate(struct ti_sn_bridge *pdata)
{
- unsigned int bit_rate_mhz, dp_rate_mhz;
+ unsigned int bit_rate_khz, dp_rate_mhz;
unsigned int i;
struct drm_display_mode *mode =
&pdata->bridge.encoder->crtc->state->adjusted_mode;
- /*
- * Calculate minimum bit rate based on our pixel clock. At
- * the moment this driver never sets the DP_18BPP_EN bit in
- * register 0x5b so we hardcode 24bpp.
- */
- bit_rate_mhz = (mode->clock / 1000) * 24;
+ /* Calculate minimum bit rate based on our pixel clock. */
+ bit_rate_khz = mode->clock * ti_sn_bridge_get_bpp(pdata);
/* Calculate minimum DP data rate, taking 80% as per DP spec */
- dp_rate_mhz = ((bit_rate_mhz / pdata->dp_lanes) * DP_CLK_FUDGE_NUM) /
- DP_CLK_FUDGE_DEN;
+ dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM,
+ 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN);
for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
if (ti_sn_bridge_dp_rate_lut[i] > dp_rate_mhz)
@@ -550,6 +555,10 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge)
regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
CHA_DSI_LANES_MASK, val);
+ /* Set the DP output format (18 bpp or 24 bpp) */
+ val = (ti_sn_bridge_get_bpp(pdata) == 18) ? BPP_18_RGB : 0;
+ regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val);
+
/* DP lane config */
val = DP_NUM_LANES(min(pdata->dp_lanes, 3));
regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
--
2.24.1.735.g03f4e72817-goog
On Wed 18 Dec 14:35 PST 2019, Douglas Anderson wrote:
> The current bridge driver always forced us to use 24 bits per pixel
> over the DP link. This is a waste if you are hooked up to a panel
> that only supports 6 bits per color or fewer, since in that case you
> ran run at 18 bits per pixel and thus end up at a lower DP clock rate.
s/ran/can/
>
> Let's support this.
>
> While at it, let's clean up the math in the function to avoid rounding
> errors (and round in the correct direction when we have to round).
> Numbers are sufficiently small (because mode->clock is in kHz) that we
> don't need to worry about integer overflow.
>
> Signed-off-by: Douglas Anderson <[email protected]>
> Tested-by: Rob Clark <[email protected]>
> Reviewed-by: Rob Clark <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> drivers/gpu/drm/bridge/ti-sn65dsi86.c | 27 ++++++++++++++++++---------
> 1 file changed, 18 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> index 0fc9e97b2d98..d5990a0947b9 100644
> --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> @@ -51,6 +51,7 @@
> #define SN_ENH_FRAME_REG 0x5A
> #define VSTREAM_ENABLE BIT(3)
> #define SN_DATA_FORMAT_REG 0x5B
> +#define BPP_18_RGB BIT(0)
> #define SN_HPD_DISABLE_REG 0x5C
> #define HPD_DISABLE BIT(0)
> #define SN_AUX_WDATA_REG(x) (0x64 + (x))
> @@ -436,6 +437,14 @@ static void ti_sn_bridge_set_dsi_rate(struct ti_sn_bridge *pdata)
> regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
> }
>
> +static unsigned int ti_sn_bridge_get_bpp(struct ti_sn_bridge *pdata)
> +{
> + if (pdata->connector.display_info.bpc <= 6)
> + return 18;
> + else
> + return 24;
> +}
> +
> /**
> * LUT index corresponds to register value and
> * LUT values corresponds to dp data rate supported
> @@ -447,21 +456,17 @@ static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
>
> static void ti_sn_bridge_set_dp_rate(struct ti_sn_bridge *pdata)
> {
> - unsigned int bit_rate_mhz, dp_rate_mhz;
> + unsigned int bit_rate_khz, dp_rate_mhz;
> unsigned int i;
> struct drm_display_mode *mode =
> &pdata->bridge.encoder->crtc->state->adjusted_mode;
>
> - /*
> - * Calculate minimum bit rate based on our pixel clock. At
> - * the moment this driver never sets the DP_18BPP_EN bit in
> - * register 0x5b so we hardcode 24bpp.
> - */
> - bit_rate_mhz = (mode->clock / 1000) * 24;
> + /* Calculate minimum bit rate based on our pixel clock. */
> + bit_rate_khz = mode->clock * ti_sn_bridge_get_bpp(pdata);
>
> /* Calculate minimum DP data rate, taking 80% as per DP spec */
> - dp_rate_mhz = ((bit_rate_mhz / pdata->dp_lanes) * DP_CLK_FUDGE_NUM) /
> - DP_CLK_FUDGE_DEN;
> + dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM,
> + 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN);
>
> for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
> if (ti_sn_bridge_dp_rate_lut[i] > dp_rate_mhz)
> @@ -550,6 +555,10 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge)
> regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
> CHA_DSI_LANES_MASK, val);
>
> + /* Set the DP output format (18 bpp or 24 bpp) */
> + val = (ti_sn_bridge_get_bpp(pdata) == 18) ? BPP_18_RGB : 0;
> + regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val);
> +
> /* DP lane config */
> val = DP_NUM_LANES(min(pdata->dp_lanes, 3));
> regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
> --
> 2.24.1.735.g03f4e72817-goog
>
Andrzej / Neil,
On Mon, Feb 3, 2020 at 3:37 PM Bjorn Andersson
<[email protected]> wrote:
>
> On Wed 18 Dec 14:35 PST 2019, Douglas Anderson wrote:
>
> > The current bridge driver always forced us to use 24 bits per pixel
> > over the DP link. This is a waste if you are hooked up to a panel
> > that only supports 6 bits per color or fewer, since in that case you
> > ran run at 18 bits per pixel and thus end up at a lower DP clock rate.
>
> s/ran/can/
I'm going to make the assumption that you can fix this typo when
applying the patch and I'm not planning to send a v4. If that's not a
good assumption then please yell.
Thanks!
-Doug
Andrzej / Neil,
On Mon, Feb 3, 2020 at 4:21 PM Doug Anderson <[email protected]> wrote:
>
> Andrzej / Neil,
>
> On Mon, Feb 3, 2020 at 3:37 PM Bjorn Andersson
> <[email protected]> wrote:
> >
> > On Wed 18 Dec 14:35 PST 2019, Douglas Anderson wrote:
> >
> > > The current bridge driver always forced us to use 24 bits per pixel
> > > over the DP link. This is a waste if you are hooked up to a panel
> > > that only supports 6 bits per color or fewer, since in that case you
> > > ran run at 18 bits per pixel and thus end up at a lower DP clock rate.
> >
> > s/ran/can/
>
> I'm going to make the assumption that you can fix this typo when
> applying the patch and I'm not planning to send a v4. If that's not a
> good assumption then please yell.
With -rc1 released, it seems like it might be a nice time to land this
series. Do you happen to know if there is anything outstanding? Is
one of you two the right person to land this series, or should I be
asking someone else? I can see if I can find someone to take them
through drm-misc if there's nobody else?
It's not massively crazy urgent or anything, but the patches have been
floating for quite some time now and it'd be nice to know what the
plan was. I also have another patch I'd like to post up but was
hoping to get this series resolved first.
Thanks much!
-Doug
Hi,
On 13/02/2020 00:04, Doug Anderson wrote:
> Andrzej / Neil,
>
> On Mon, Feb 3, 2020 at 4:21 PM Doug Anderson <[email protected]> wrote:
>>
>> Andrzej / Neil,
>>
>> On Mon, Feb 3, 2020 at 3:37 PM Bjorn Andersson
>> <[email protected]> wrote:
>>>
>>> On Wed 18 Dec 14:35 PST 2019, Douglas Anderson wrote:
>>>
>>>> The current bridge driver always forced us to use 24 bits per pixel
>>>> over the DP link. This is a waste if you are hooked up to a panel
>>>> that only supports 6 bits per color or fewer, since in that case you
>>>> ran run at 18 bits per pixel and thus end up at a lower DP clock rate.
>>>
>>> s/ran/can/
>>
>> I'm going to make the assumption that you can fix this typo when
>> applying the patch and I'm not planning to send a v4. If that's not a
>> good assumption then please yell.
>
> With -rc1 released, it seems like it might be a nice time to land this
> series. Do you happen to know if there is anything outstanding? Is
> one of you two the right person to land this series, or should I be
> asking someone else? I can see if I can find someone to take them
> through drm-misc if there's nobody else?
>
> It's not massively crazy urgent or anything, but the patches have been
> floating for quite some time now and it'd be nice to know what the
> plan was. I also have another patch I'd like to post up but was
> hoping to get this series resolved first.
>
> Thanks much!
>
> -Doug
>
I will push it shortly, seems everything is fine and reviewed.
Neil
Hi,
On Thu, Jul 9, 2020 at 6:19 PM Steev Klimaszewski <[email protected]> wrote:
>
> Hi Doug,
>
> I've been testing 5.8 and linux-next on the Lenovo Yoga C630, and with this patch applied, there is really bad banding on the display.
>
> I'm really bad at explaining it, but you can see the differences in the following:
>
> 24bit (pre-5.8) - https://dev.gentoo.org/~steev/files/image0.jpg
>
> 18bit (5.8/linux-next) - https://dev.gentoo.org/~steev/files/image1.jpg
Presumably this means that your panel is defined improperly? If the
panel reports that it's a 6 bits per pixel panel but it's actually an
8 bits per pixel panel then you'll run into this problem.
I would have to assume you have a bunch of out of tree patches to
support your hardware since I don't see any device trees in linuxnext
(other than cheza) that use this bridge chip. Otherwise I could try
to check and confirm that was the problem.
-Doug
Hi,
On Thu, Jul 9, 2020 at 6:38 PM Doug Anderson <[email protected]> wrote:
>
> Hi,
>
> On Thu, Jul 9, 2020 at 6:19 PM Steev Klimaszewski <[email protected]> wrote:
> >
> > Hi Doug,
> >
> > I've been testing 5.8 and linux-next on the Lenovo Yoga C630, and with this patch applied, there is really bad banding on the display.
> >
> > I'm really bad at explaining it, but you can see the differences in the following:
> >
> > 24bit (pre-5.8) - https://dev.gentoo.org/~steev/files/image0.jpg
> >
> > 18bit (5.8/linux-next) - https://dev.gentoo.org/~steev/files/image1.jpg
>
> Presumably this means that your panel is defined improperly? If the
> panel reports that it's a 6 bits per pixel panel but it's actually an
> 8 bits per pixel panel then you'll run into this problem.
>
> I would have to assume you have a bunch of out of tree patches to
> support your hardware since I don't see any device trees in linuxnext
> (other than cheza) that use this bridge chip. Otherwise I could try
> to check and confirm that was the problem.
Ah, interesting. Maybe you have the panel:
boe,nv133fhm-n61
As far as I can tell from the datasheet (I have the similar
boe,nv133fhm-n62) this is a 6bpp panel. ...but if you feed it 8bpp
the banding goes away! Maybe the panel itself knows how to dither???
...or maybe the datasheet / edid are wrong and this is actually an
8bpp panel. Seems unlikely...
In any case, one fix is to pick
<https://lore.kernel.org/dri-devel/[email protected]/>,
though right now that patch is only enabled for sc7180. Maybe you
could figure out how to apply it to your hardware?
...another fix would be to pretend that your panel is 8bpp even though
it's actually 6bpp. Ironically if anyone ever tried to configure BPP
from the EDID they'd go back to 6bpp. You can read the EDID of your
panel with this:
bus=$(i2cdetect -l | grep sn65 | sed 's/i2c-\([0-9]*\).*$/\1/')
i2cdump ${bus} 0x50 i
When I do that and then decode it on the "boe,nv133fhm-n62" panel, I find:
6 bits per primary color channel
-Doug
On 7/9/20 9:14 PM, Doug Anderson wrote:
> Hi,
>
> On Thu, Jul 9, 2020 at 6:38 PM Doug Anderson <[email protected]> wrote:
>> Hi,
>>
>> On Thu, Jul 9, 2020 at 6:19 PM Steev Klimaszewski <[email protected]> wrote:
>>> Hi Doug,
>>>
>>> I've been testing 5.8 and linux-next on the Lenovo Yoga C630, and with this patch applied, there is really bad banding on the display.
>>>
>>> I'm really bad at explaining it, but you can see the differences in the following:
>>>
>>> 24bit (pre-5.8) - https://dev.gentoo.org/~steev/files/image0.jpg
>>>
>>> 18bit (5.8/linux-next) - https://dev.gentoo.org/~steev/files/image1.jpg
>> Presumably this means that your panel is defined improperly? If the
>> panel reports that it's a 6 bits per pixel panel but it's actually an
>> 8 bits per pixel panel then you'll run into this problem.
>>
>> I would have to assume you have a bunch of out of tree patches to
>> support your hardware since I don't see any device trees in linuxnext
>> (other than cheza) that use this bridge chip. Otherwise I could try
>> to check and confirm that was the problem.
> Ah, interesting. Maybe you have the panel:
>
> boe,nv133fhm-n61
>
> As far as I can tell from the datasheet (I have the similar
> boe,nv133fhm-n62) this is a 6bpp panel. ...but if you feed it 8bpp
> the banding goes away! Maybe the panel itself knows how to dither???
> ...or maybe the datasheet / edid are wrong and this is actually an
> 8bpp panel. Seems unlikely...
>
> In any case, one fix is to pick
> <https://lore.kernel.org/dri-devel/[email protected]/>,
> though right now that patch is only enabled for sc7180. Maybe you
> could figure out how to apply it to your hardware?
>
> ...another fix would be to pretend that your panel is 8bpp even though
> it's actually 6bpp. Ironically if anyone ever tried to configure BPP
> from the EDID they'd go back to 6bpp. You can read the EDID of your
> panel with this:
>
> bus=$(i2cdetect -l | grep sn65 | sed 's/i2c-\([0-9]*\).*$/\1/')
> i2cdump ${bus} 0x50 i
>
> When I do that and then decode it on the "boe,nv133fhm-n62" panel, I find:
>
> 6 bits per primary color channel
>
> -Doug
Hi Doug,
Decoding it does show be to boe,nv133fhm-n61 - and yeah it does say it's
6-bit according to panelook's specs for it.
I'll take a look at the patch and see what I can come up with... at the
moment, I'm forcing it to be 8bit and that does "work fine" but I'd like
it to be fixed properly instead of my hack.
Thanks for your time and work!
-- Steev
On 7/9/20 10:12 PM, Steev Klimaszewski wrote:
>
> On 7/9/20 9:14 PM, Doug Anderson wrote:
>> Hi,
>>
>> On Thu, Jul 9, 2020 at 6:38 PM Doug Anderson <[email protected]>
>> wrote:
>>> Hi,
>>>
>>> On Thu, Jul 9, 2020 at 6:19 PM Steev Klimaszewski <[email protected]>
>>> wrote:
>>>> Hi Doug,
>>>>
>>>> I've been testing 5.8 and linux-next on the Lenovo Yoga C630, and
>>>> with this patch applied, there is really bad banding on the display.
>>>>
>>>> I'm really bad at explaining it, but you can see the differences in
>>>> the following:
>>>>
>>>> 24bit (pre-5.8) - https://dev.gentoo.org/~steev/files/image0.jpg
>>>>
>>>> 18bit (5.8/linux-next) -
>>>> https://dev.gentoo.org/~steev/files/image1.jpg
>>> Presumably this means that your panel is defined improperly? If the
>>> panel reports that it's a 6 bits per pixel panel but it's actually an
>>> 8 bits per pixel panel then you'll run into this problem.
>>>
>>> I would have to assume you have a bunch of out of tree patches to
>>> support your hardware since I don't see any device trees in linuxnext
>>> (other than cheza) that use this bridge chip. Otherwise I could try
>>> to check and confirm that was the problem.
>> Ah, interesting. Maybe you have the panel:
>>
>> boe,nv133fhm-n61
>>
>> As far as I can tell from the datasheet (I have the similar
>> boe,nv133fhm-n62) this is a 6bpp panel. ...but if you feed it 8bpp
>> the banding goes away! Maybe the panel itself knows how to dither???
>> ...or maybe the datasheet / edid are wrong and this is actually an
>> 8bpp panel. Seems unlikely...
>>
>> In any case, one fix is to pick
>> <https://lore.kernel.org/dri-devel/[email protected]/>,
>>
>> though right now that patch is only enabled for sc7180. Maybe you
>> could figure out how to apply it to your hardware?
>>
>> ...another fix would be to pretend that your panel is 8bpp even though
>> it's actually 6bpp. Ironically if anyone ever tried to configure BPP
>> from the EDID they'd go back to 6bpp. You can read the EDID of your
>> panel with this:
>>
>> bus=$(i2cdetect -l | grep sn65 | sed 's/i2c-\([0-9]*\).*$/\1/')
>> i2cdump ${bus} 0x50 i
>>
>> When I do that and then decode it on the "boe,nv133fhm-n62" panel, I
>> find:
>>
>> 6 bits per primary color channel
>>
>> -Doug
>
>
> Hi Doug,
>
> Decoding it does show be to boe,nv133fhm-n61 - and yeah it does say
> it's 6-bit according to panelook's specs for it.
>
>
> I'll take a look at the patch and see what I can come up with... at
> the moment, I'm forcing it to be 8bit and that does "work fine" but
> I'd like it to be fixed properly instead of my hack.
>
> Thanks for your time and work!
>
> -- Steev
>
For what it's worth - the 5.8 that I'm testing is at
https://github.com/steev/linux/commits/c630-5.8-rc4-inline-encryption
On 7/9/20 10:17 PM, Steev Klimaszewski wrote:
>
> On 7/9/20 10:12 PM, Steev Klimaszewski wrote:
>>
>> On 7/9/20 9:14 PM, Doug Anderson wrote:
>>> Hi,
>>>
>>> On Thu, Jul 9, 2020 at 6:38 PM Doug Anderson <[email protected]>
>>> wrote:
>>>> Hi,
>>>>
>>>> On Thu, Jul 9, 2020 at 6:19 PM Steev Klimaszewski
>>>> <[email protected]> wrote:
>>>>> Hi Doug,
>>>>>
>>>>> I've been testing 5.8 and linux-next on the Lenovo Yoga C630, and
>>>>> with this patch applied, there is really bad banding on the display.
>>>>>
>>>>> I'm really bad at explaining it, but you can see the differences
>>>>> in the following:
>>>>>
>>>>> 24bit (pre-5.8) - https://dev.gentoo.org/~steev/files/image0.jpg
>>>>>
>>>>> 18bit (5.8/linux-next) -
>>>>> https://dev.gentoo.org/~steev/files/image1.jpg
>>>> Presumably this means that your panel is defined improperly? If the
>>>> panel reports that it's a 6 bits per pixel panel but it's actually an
>>>> 8 bits per pixel panel then you'll run into this problem.
>>>>
>>>> I would have to assume you have a bunch of out of tree patches to
>>>> support your hardware since I don't see any device trees in linuxnext
>>>> (other than cheza) that use this bridge chip. Otherwise I could try
>>>> to check and confirm that was the problem.
>>> Ah, interesting. Maybe you have the panel:
>>>
>>> boe,nv133fhm-n61
>>>
>>> As far as I can tell from the datasheet (I have the similar
>>> boe,nv133fhm-n62) this is a 6bpp panel. ...but if you feed it 8bpp
>>> the banding goes away! Maybe the panel itself knows how to dither???
>>> ...or maybe the datasheet / edid are wrong and this is actually an
>>> 8bpp panel. Seems unlikely...
>>>
>>> In any case, one fix is to pick
>>> <https://lore.kernel.org/dri-devel/[email protected]/>,
>>>
>>> though right now that patch is only enabled for sc7180. Maybe you
>>> could figure out how to apply it to your hardware?
>>>
>>> ...another fix would be to pretend that your panel is 8bpp even though
>>> it's actually 6bpp. Ironically if anyone ever tried to configure BPP
>>> from the EDID they'd go back to 6bpp. You can read the EDID of your
>>> panel with this:
>>>
>>> bus=$(i2cdetect -l | grep sn65 | sed 's/i2c-\([0-9]*\).*$/\1/')
>>> i2cdump ${bus} 0x50 i
>>>
>>> When I do that and then decode it on the "boe,nv133fhm-n62" panel, I
>>> find:
>>>
>>> 6 bits per primary color channel
>>>
>>> -Doug
>>
>>
>> Hi Doug,
>>
>> Decoding it does show be to boe,nv133fhm-n61 - and yeah it does say
>> it's 6-bit according to panelook's specs for it.
I derped again...
root@c630:~# bus=$(i2cdetect -l | grep sn65 | sed 's/i2c-\([0-9]*\).*$/\1/')
root@c630:~# i2cdump ${bus} 0x50 i > edid
WARNING! This program can confuse your I2C bus, cause data loss and worse!
I will probe file /dev/i2c-16, address 0x50, mode i2c block
Continue? [Y/n]
root@c630:~# edid-decode edid
edid-decode (hex):
00 ff ff ff ff ff ff 00 09 e5 d1 07 00 00 00 00
01 1c 01 04 a5 1d 11 78 0a 1d b0 a6 58 54 9e 26
0f 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
01 01 01 01 01 01 c0 39 80 18 71 38 28 40 30 20
36 00 26 a5 10 00 00 1a 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 1a 00 00 00 fe 00 42
4f 45 20 43 51 0a 20 20 20 20 20 20 00 00 00 fe
00 4e 56 31 33 33 46 48 4d 2d 4e 36 31 0a 00 9a
03 26 0a 77 ab 1c 05 71 6f 1d 8c f1 43 ce 6a bb
fb d3 11 20 39 07 22 6e 65 68 77 70 d3 05 34 73
44 21 8b fd f5 6d 11 62 94 2a 7c fa 93 ba 6a 61
92 da 15 53 4c 39 eb f7 86 23 97 48 e9 39 09 d2
66 02 70 bb e2 77 0f 4a a3 a0 4c 72 6e 5d 47 70
43 c2 13 f3 b2 d9 b9 78 02 be 41 82 15 6a 28 dc
45 0f 9d eb 0f 2a cc e8 35 8d 34 7f 3e 84 5e a3
30 5e 1e 29 0a 48 0c d1 0a c4 08 31 03 a9 3b 29
----------------
EDID version: 1.4
Manufacturer: BOE Model 2001 Serial Number 0
Made in week 1 of 2018
Digital display
8 bits per primary color channel
DisplayPort interface
Maximum image size: 29 cm x 17 cm
Gamma: 2.20
Supported color formats: RGB 4:4:4, YCrCb 4:4:4
First detailed timing includes the native pixel format and preferred
refresh rate
Color Characteristics
Red: 0.6484, 0.3447
Green: 0.3310, 0.6181
Blue: 0.1503, 0.0615
White: 0.3125, 0.3281
Established Timings I & II: none
Standard Timings: none
Detailed mode: Clock 147.840 MHz, 294 mm x 165 mm
1920 1968 2000 2200 ( 48 32 200)
1080 1083 1089 1120 ( 3 6 31)
+hsync -vsync
VertFreq: 60.000 Hz, HorFreq: 67.200 kHz
Manufacturer-Specified Display Descriptor (0x00): 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 1a ................
Alphanumeric Data String: BOE CQ
Alphanumeric Data String: NV133FHM-N61
Checksum: 0x9a
----------------
Unknown EDID Extension Block 0x03
03 26 0a 77 ab 1c 05 71 6f 1d 8c f1 43 ce 6a bb .&.w...qo...C.j.
fb d3 11 20 39 07 22 6e 65 68 77 70 d3 05 34 73 ... 9."nehwp..4s
44 21 8b fd f5 6d 11 62 94 2a 7c fa 93 ba 6a 61 D!...m.b.*|...ja
92 da 15 53 4c 39 eb f7 86 23 97 48 e9 39 09 d2 ...SL9...#.H.9..
66 02 70 bb e2 77 0f 4a a3 a0 4c 72 6e 5d 47 70 f.p..w.J..Lrn]Gp
43 c2 13 f3 b2 d9 b9 78 02 be 41 82 15 6a 28 dc C......x..A..j(.
45 0f 9d eb 0f 2a cc e8 35 8d 34 7f 3e 84 5e a3 E....*..5.4.>.^.
30 5e 1e 29 0a 48 0c d1 0a c4 08 31 03 a9 3b 29 0^.).H.....1..;)
Checksum: 0x29 (should be 0x82)
- My edid does in fact say it's 8bit
Hi,
On Thu, Jul 9, 2020 at 8:43 PM Steev Klimaszewski <[email protected]> wrote:
>
>
> On 7/9/20 10:17 PM, Steev Klimaszewski wrote:
> >
> > On 7/9/20 10:12 PM, Steev Klimaszewski wrote:
> >>
> >> On 7/9/20 9:14 PM, Doug Anderson wrote:
> >>> Hi,
> >>>
> >>> On Thu, Jul 9, 2020 at 6:38 PM Doug Anderson <[email protected]>
> >>> wrote:
> >>>> Hi,
> >>>>
> >>>> On Thu, Jul 9, 2020 at 6:19 PM Steev Klimaszewski
> >>>> <[email protected]> wrote:
> >>>>> Hi Doug,
> >>>>>
> >>>>> I've been testing 5.8 and linux-next on the Lenovo Yoga C630, and
> >>>>> with this patch applied, there is really bad banding on the display.
> >>>>>
> >>>>> I'm really bad at explaining it, but you can see the differences
> >>>>> in the following:
> >>>>>
> >>>>> 24bit (pre-5.8) - https://dev.gentoo.org/~steev/files/image0.jpg
> >>>>>
> >>>>> 18bit (5.8/linux-next) -
> >>>>> https://dev.gentoo.org/~steev/files/image1.jpg
> >>>> Presumably this means that your panel is defined improperly? If the
> >>>> panel reports that it's a 6 bits per pixel panel but it's actually an
> >>>> 8 bits per pixel panel then you'll run into this problem.
> >>>>
> >>>> I would have to assume you have a bunch of out of tree patches to
> >>>> support your hardware since I don't see any device trees in linuxnext
> >>>> (other than cheza) that use this bridge chip. Otherwise I could try
> >>>> to check and confirm that was the problem.
> >>> Ah, interesting. Maybe you have the panel:
> >>>
> >>> boe,nv133fhm-n61
> >>>
> >>> As far as I can tell from the datasheet (I have the similar
> >>> boe,nv133fhm-n62) this is a 6bpp panel. ...but if you feed it 8bpp
> >>> the banding goes away! Maybe the panel itself knows how to dither???
> >>> ...or maybe the datasheet / edid are wrong and this is actually an
> >>> 8bpp panel. Seems unlikely...
> >>>
> >>> In any case, one fix is to pick
> >>> <https://lore.kernel.org/dri-devel/[email protected]/>,
> >>>
> >>> though right now that patch is only enabled for sc7180. Maybe you
> >>> could figure out how to apply it to your hardware?
> >>>
> >>> ...another fix would be to pretend that your panel is 8bpp even though
> >>> it's actually 6bpp. Ironically if anyone ever tried to configure BPP
> >>> from the EDID they'd go back to 6bpp. You can read the EDID of your
> >>> panel with this:
> >>>
> >>> bus=$(i2cdetect -l | grep sn65 | sed 's/i2c-\([0-9]*\).*$/\1/')
> >>> i2cdump ${bus} 0x50 i
> >>>
> >>> When I do that and then decode it on the "boe,nv133fhm-n62" panel, I
> >>> find:
> >>>
> >>> 6 bits per primary color channel
> >>>
> >>> -Doug
> >>
> >>
> >> Hi Doug,
> >>
> >> Decoding it does show be to boe,nv133fhm-n61 - and yeah it does say
> >> it's 6-bit according to panelook's specs for it.
>
>
> I derped again...
>
> root@c630:~# bus=$(i2cdetect -l | grep sn65 | sed 's/i2c-\([0-9]*\).*$/\1/')
> root@c630:~# i2cdump ${bus} 0x50 i > edid
> WARNING! This program can confuse your I2C bus, cause data loss and worse!
> I will probe file /dev/i2c-16, address 0x50, mode i2c block
> Continue? [Y/n]
> root@c630:~# edid-decode edid
> edid-decode (hex):
>
> 00 ff ff ff ff ff ff 00 09 e5 d1 07 00 00 00 00
> 01 1c 01 04 a5 1d 11 78 0a 1d b0 a6 58 54 9e 26
> 0f 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
> 01 01 01 01 01 01 c0 39 80 18 71 38 28 40 30 20
> 36 00 26 a5 10 00 00 1a 00 00 00 00 00 00 00 00
> 00 00 00 00 00 00 00 00 00 1a 00 00 00 fe 00 42
> 4f 45 20 43 51 0a 20 20 20 20 20 20 00 00 00 fe
> 00 4e 56 31 33 33 46 48 4d 2d 4e 36 31 0a 00 9a
>
> 03 26 0a 77 ab 1c 05 71 6f 1d 8c f1 43 ce 6a bb
> fb d3 11 20 39 07 22 6e 65 68 77 70 d3 05 34 73
> 44 21 8b fd f5 6d 11 62 94 2a 7c fa 93 ba 6a 61
> 92 da 15 53 4c 39 eb f7 86 23 97 48 e9 39 09 d2
> 66 02 70 bb e2 77 0f 4a a3 a0 4c 72 6e 5d 47 70
> 43 c2 13 f3 b2 d9 b9 78 02 be 41 82 15 6a 28 dc
> 45 0f 9d eb 0f 2a cc e8 35 8d 34 7f 3e 84 5e a3
> 30 5e 1e 29 0a 48 0c d1 0a c4 08 31 03 a9 3b 29
>
> ----------------
>
> EDID version: 1.4
> Manufacturer: BOE Model 2001 Serial Number 0
> Made in week 1 of 2018
> Digital display
> 8 bits per primary color channel
> DisplayPort interface
> Maximum image size: 29 cm x 17 cm
> Gamma: 2.20
> Supported color formats: RGB 4:4:4, YCrCb 4:4:4
> First detailed timing includes the native pixel format and preferred
> refresh rate
> Color Characteristics
> Red: 0.6484, 0.3447
> Green: 0.3310, 0.6181
> Blue: 0.1503, 0.0615
> White: 0.3125, 0.3281
> Established Timings I & II: none
> Standard Timings: none
> Detailed mode: Clock 147.840 MHz, 294 mm x 165 mm
> 1920 1968 2000 2200 ( 48 32 200)
> 1080 1083 1089 1120 ( 3 6 31)
> +hsync -vsync
> VertFreq: 60.000 Hz, HorFreq: 67.200 kHz
> Manufacturer-Specified Display Descriptor (0x00): 00 00 00 00 00 00 00
> 00 00 00 00 00 00 00 00 1a ................
> Alphanumeric Data String: BOE CQ
> Alphanumeric Data String: NV133FHM-N61
> Checksum: 0x9a
>
> ----------------
>
> Unknown EDID Extension Block 0x03
> 03 26 0a 77 ab 1c 05 71 6f 1d 8c f1 43 ce 6a bb .&.w...qo...C.j.
> fb d3 11 20 39 07 22 6e 65 68 77 70 d3 05 34 73 ... 9."nehwp..4s
> 44 21 8b fd f5 6d 11 62 94 2a 7c fa 93 ba 6a 61 D!...m.b.*|...ja
> 92 da 15 53 4c 39 eb f7 86 23 97 48 e9 39 09 d2 ...SL9...#.H.9..
> 66 02 70 bb e2 77 0f 4a a3 a0 4c 72 6e 5d 47 70 f.p..w.J..Lrn]Gp
> 43 c2 13 f3 b2 d9 b9 78 02 be 41 82 15 6a 28 dc C......x..A..j(.
> 45 0f 9d eb 0f 2a cc e8 35 8d 34 7f 3e 84 5e a3 E....*..5.4.>.^.
> 30 5e 1e 29 0a 48 0c d1 0a c4 08 31 03 a9 3b 29 0^.).H.....1..;)
> Checksum: 0x29 (should be 0x82)
>
>
> - My edid does in fact say it's 8bit
Crazy! Mine:
Extracted contents:
header: 00 ff ff ff ff ff ff 00
serial number: 09 e5 2d 08 00 00 00 00 23 1c
version: 01 04
basic params: 95 1d 11 78 02
chroma info: d5 00 a6 58 54 9f 27 0f 4f 57
established: 00 00 00
standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
descriptor 1: c0 39 80 18 71 38 28 40 30 20 36 00 26 a5 10 00 00 1a
descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
descriptor 3: 00 00 00 fe 00 42 4f 45 20 43 51 0a 20 20 20 20 20 20
descriptor 4: 00 00 00 fe 00 4e 56 31 33 33 46 48 4d 2d 4e 36 32 0a
extensions: 00
checksum: 40
Manufacturer: BOE Model 82d Serial Number 0
Made week 35 of 2018
EDID version: 1.4
Digital display
6 bits per primary color channel
DisplayPort interface
Maximum image size: 29 cm x 17 cm
Gamma: 2.20
Supported color formats: RGB 4:4:4
First detailed timing is preferred timing
Established timings supported:
Standard timings supported:
Detailed mode: Clock 147.840 MHz, 294 mm x 165 mm
1920 1968 2000 2200 hborder 0
1080 1083 1089 1120 vborder 0
+hsync -vsync
Manufacturer-specified data, tag 0
ASCII string: BOE
ASCII string: NV133FHM-N62
Checksum: 0x40 (valid)
Unknown extension block
EDID block does NOT conform to EDID 1.3!
Missing name descriptor
Missing monitor ranges
Detailed block string not properly terminated
EDID block does not conform at all!
Has 128 nonconformant extension block(s)
Hi,
On 7/9/20 11:12 PM, Doug Anderson wrote:
>> root@c630:~# bus=$(i2cdetect -l | grep sn65 | sed 's/i2c-\([0-9]*\).*$/\1/')
>> root@c630:~# i2cdump ${bus} 0x50 i > edid
>> WARNING! This program can confuse your I2C bus, cause data loss and worse!
>> I will probe file /dev/i2c-16, address 0x50, mode i2c block
>> Continue? [Y/n]
>> root@c630:~# edid-decode edid
>> edid-decode (hex):
>>
>> 00 ff ff ff ff ff ff 00 09 e5 d1 07 00 00 00 00
>> 01 1c 01 04 a5 1d 11 78 0a 1d b0 a6 58 54 9e 26
>> 0f 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
>> 01 01 01 01 01 01 c0 39 80 18 71 38 28 40 30 20
>> 36 00 26 a5 10 00 00 1a 00 00 00 00 00 00 00 00
>> 00 00 00 00 00 00 00 00 00 1a 00 00 00 fe 00 42
>> 4f 45 20 43 51 0a 20 20 20 20 20 20 00 00 00 fe
>> 00 4e 56 31 33 33 46 48 4d 2d 4e 36 31 0a 00 9a
>>
>> 03 26 0a 77 ab 1c 05 71 6f 1d 8c f1 43 ce 6a bb
>> fb d3 11 20 39 07 22 6e 65 68 77 70 d3 05 34 73
>> 44 21 8b fd f5 6d 11 62 94 2a 7c fa 93 ba 6a 61
>> 92 da 15 53 4c 39 eb f7 86 23 97 48 e9 39 09 d2
>> 66 02 70 bb e2 77 0f 4a a3 a0 4c 72 6e 5d 47 70
>> 43 c2 13 f3 b2 d9 b9 78 02 be 41 82 15 6a 28 dc
>> 45 0f 9d eb 0f 2a cc e8 35 8d 34 7f 3e 84 5e a3
>> 30 5e 1e 29 0a 48 0c d1 0a c4 08 31 03 a9 3b 29
>>
>> ----------------
>>
>> EDID version: 1.4
>> Manufacturer: BOE Model 2001 Serial Number 0
>> Made in week 1 of 2018
>> Digital display
>> 8 bits per primary color channel
>> DisplayPort interface
>> Maximum image size: 29 cm x 17 cm
>> Gamma: 2.20
>> Supported color formats: RGB 4:4:4, YCrCb 4:4:4
>> First detailed timing includes the native pixel format and preferred
>> refresh rate
>> Color Characteristics
>> Red: 0.6484, 0.3447
>> Green: 0.3310, 0.6181
>> Blue: 0.1503, 0.0615
>> White: 0.3125, 0.3281
>> Established Timings I & II: none
>> Standard Timings: none
>> Detailed mode: Clock 147.840 MHz, 294 mm x 165 mm
>> 1920 1968 2000 2200 ( 48 32 200)
>> 1080 1083 1089 1120 ( 3 6 31)
>> +hsync -vsync
>> VertFreq: 60.000 Hz, HorFreq: 67.200 kHz
>> Manufacturer-Specified Display Descriptor (0x00): 00 00 00 00 00 00 00
>> 00 00 00 00 00 00 00 00 1a ................
>> Alphanumeric Data String: BOE CQ
>> Alphanumeric Data String: NV133FHM-N61
>> Checksum: 0x9a
>>
>> ----------------
>>
>> Unknown EDID Extension Block 0x03
>> 03 26 0a 77 ab 1c 05 71 6f 1d 8c f1 43 ce 6a bb .&.w...qo...C.j.
>> fb d3 11 20 39 07 22 6e 65 68 77 70 d3 05 34 73 ... 9."nehwp..4s
>> 44 21 8b fd f5 6d 11 62 94 2a 7c fa 93 ba 6a 61 D!...m.b.*|...ja
>> 92 da 15 53 4c 39 eb f7 86 23 97 48 e9 39 09 d2 ...SL9...#.H.9..
>> 66 02 70 bb e2 77 0f 4a a3 a0 4c 72 6e 5d 47 70 f.p..w.J..Lrn]Gp
>> 43 c2 13 f3 b2 d9 b9 78 02 be 41 82 15 6a 28 dc C......x..A..j(.
>> 45 0f 9d eb 0f 2a cc e8 35 8d 34 7f 3e 84 5e a3 E....*..5.4.>.^.
>> 30 5e 1e 29 0a 48 0c d1 0a c4 08 31 03 a9 3b 29 0^.).H.....1..;)
>> Checksum: 0x29 (should be 0x82)
>>
>>
>> - My edid does in fact say it's 8bit
> Crazy! Mine:
>
> Extracted contents:
> header: 00 ff ff ff ff ff ff 00
> serial number: 09 e5 2d 08 00 00 00 00 23 1c
> version: 01 04
> basic params: 95 1d 11 78 02
> chroma info: d5 00 a6 58 54 9f 27 0f 4f 57
> established: 00 00 00
> standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
> descriptor 1: c0 39 80 18 71 38 28 40 30 20 36 00 26 a5 10 00 00 1a
> descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> descriptor 3: 00 00 00 fe 00 42 4f 45 20 43 51 0a 20 20 20 20 20 20
> descriptor 4: 00 00 00 fe 00 4e 56 31 33 33 46 48 4d 2d 4e 36 32 0a
> extensions: 00
> checksum: 40
>
> Manufacturer: BOE Model 82d Serial Number 0
> Made week 35 of 2018
> EDID version: 1.4
> Digital display
> 6 bits per primary color channel
> DisplayPort interface
> Maximum image size: 29 cm x 17 cm
> Gamma: 2.20
> Supported color formats: RGB 4:4:4
> First detailed timing is preferred timing
> Established timings supported:
> Standard timings supported:
> Detailed mode: Clock 147.840 MHz, 294 mm x 165 mm
> 1920 1968 2000 2200 hborder 0
> 1080 1083 1089 1120 vborder 0
> +hsync -vsync
> Manufacturer-specified data, tag 0
> ASCII string: BOE
> ASCII string: NV133FHM-N62
> Checksum: 0x40 (valid)
>
> Unknown extension block
>
> EDID block does NOT conform to EDID 1.3!
> Missing name descriptor
> Missing monitor ranges
> Detailed block string not properly terminated
> EDID block does not conform at all!
> Has 128 nonconformant extension block(s)
I did attempt to modify the patch, and I don't think I did it correctly
Around line 232, I changed
IS_SC7180_TARGET(c->hw.hwversion))
to
IS_SC7180_TARGET(c->hw.hwversion) ||
IS_SDM845_TARGET(c->hw.hwversion))
But it would seem that only gets us 1/2 way there...
https://dev.gentoo.org/~steev/files/image2.jpg
But should I continue on this path, or should we be finding others who
have an N61 and see what their EDID reports?
I have another c630, but unfortunately, it appears to have the IVO
screen in it, instead of another N61. I asked another user and he also
had the IVO.
-- steev
On Thu, Jul 9, 2020 at 11:15 PM Steev Klimaszewski <[email protected]> wrote:
>
> Hi,
>
> On 7/9/20 11:12 PM, Doug Anderson wrote:
> >> root@c630:~# bus=$(i2cdetect -l | grep sn65 | sed 's/i2c-\([0-9]*\).*$/\1/')
> >> root@c630:~# i2cdump ${bus} 0x50 i > edid
> >> WARNING! This program can confuse your I2C bus, cause data loss and worse!
> >> I will probe file /dev/i2c-16, address 0x50, mode i2c block
> >> Continue? [Y/n]
> >> root@c630:~# edid-decode edid
> >> edid-decode (hex):
> >>
> >> 00 ff ff ff ff ff ff 00 09 e5 d1 07 00 00 00 00
> >> 01 1c 01 04 a5 1d 11 78 0a 1d b0 a6 58 54 9e 26
> >> 0f 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
> >> 01 01 01 01 01 01 c0 39 80 18 71 38 28 40 30 20
> >> 36 00 26 a5 10 00 00 1a 00 00 00 00 00 00 00 00
> >> 00 00 00 00 00 00 00 00 00 1a 00 00 00 fe 00 42
> >> 4f 45 20 43 51 0a 20 20 20 20 20 20 00 00 00 fe
> >> 00 4e 56 31 33 33 46 48 4d 2d 4e 36 31 0a 00 9a
> >>
> >> 03 26 0a 77 ab 1c 05 71 6f 1d 8c f1 43 ce 6a bb
> >> fb d3 11 20 39 07 22 6e 65 68 77 70 d3 05 34 73
> >> 44 21 8b fd f5 6d 11 62 94 2a 7c fa 93 ba 6a 61
> >> 92 da 15 53 4c 39 eb f7 86 23 97 48 e9 39 09 d2
> >> 66 02 70 bb e2 77 0f 4a a3 a0 4c 72 6e 5d 47 70
> >> 43 c2 13 f3 b2 d9 b9 78 02 be 41 82 15 6a 28 dc
> >> 45 0f 9d eb 0f 2a cc e8 35 8d 34 7f 3e 84 5e a3
> >> 30 5e 1e 29 0a 48 0c d1 0a c4 08 31 03 a9 3b 29
> >>
> >> ----------------
> >>
> >> EDID version: 1.4
> >> Manufacturer: BOE Model 2001 Serial Number 0
> >> Made in week 1 of 2018
> >> Digital display
> >> 8 bits per primary color channel
> >> DisplayPort interface
> >> Maximum image size: 29 cm x 17 cm
> >> Gamma: 2.20
> >> Supported color formats: RGB 4:4:4, YCrCb 4:4:4
> >> First detailed timing includes the native pixel format and preferred
> >> refresh rate
> >> Color Characteristics
> >> Red: 0.6484, 0.3447
> >> Green: 0.3310, 0.6181
> >> Blue: 0.1503, 0.0615
> >> White: 0.3125, 0.3281
> >> Established Timings I & II: none
> >> Standard Timings: none
> >> Detailed mode: Clock 147.840 MHz, 294 mm x 165 mm
> >> 1920 1968 2000 2200 ( 48 32 200)
> >> 1080 1083 1089 1120 ( 3 6 31)
> >> +hsync -vsync
> >> VertFreq: 60.000 Hz, HorFreq: 67.200 kHz
> >> Manufacturer-Specified Display Descriptor (0x00): 00 00 00 00 00 00 00
> >> 00 00 00 00 00 00 00 00 1a ................
> >> Alphanumeric Data String: BOE CQ
> >> Alphanumeric Data String: NV133FHM-N61
> >> Checksum: 0x9a
> >>
> >> ----------------
> >>
> >> Unknown EDID Extension Block 0x03
> >> 03 26 0a 77 ab 1c 05 71 6f 1d 8c f1 43 ce 6a bb .&.w...qo...C.j.
> >> fb d3 11 20 39 07 22 6e 65 68 77 70 d3 05 34 73 ... 9."nehwp..4s
> >> 44 21 8b fd f5 6d 11 62 94 2a 7c fa 93 ba 6a 61 D!...m.b.*|...ja
> >> 92 da 15 53 4c 39 eb f7 86 23 97 48 e9 39 09 d2 ...SL9...#.H.9..
> >> 66 02 70 bb e2 77 0f 4a a3 a0 4c 72 6e 5d 47 70 f.p..w.J..Lrn]Gp
> >> 43 c2 13 f3 b2 d9 b9 78 02 be 41 82 15 6a 28 dc C......x..A..j(.
> >> 45 0f 9d eb 0f 2a cc e8 35 8d 34 7f 3e 84 5e a3 E....*..5.4.>.^.
> >> 30 5e 1e 29 0a 48 0c d1 0a c4 08 31 03 a9 3b 29 0^.).H.....1..;)
> >> Checksum: 0x29 (should be 0x82)
> >>
> >>
> >> - My edid does in fact say it's 8bit
> > Crazy! Mine:
> >
> > Extracted contents:
> > header: 00 ff ff ff ff ff ff 00
> > serial number: 09 e5 2d 08 00 00 00 00 23 1c
> > version: 01 04
> > basic params: 95 1d 11 78 02
> > chroma info: d5 00 a6 58 54 9f 27 0f 4f 57
> > established: 00 00 00
> > standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
> > descriptor 1: c0 39 80 18 71 38 28 40 30 20 36 00 26 a5 10 00 00 1a
> > descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> > descriptor 3: 00 00 00 fe 00 42 4f 45 20 43 51 0a 20 20 20 20 20 20
> > descriptor 4: 00 00 00 fe 00 4e 56 31 33 33 46 48 4d 2d 4e 36 32 0a
> > extensions: 00
> > checksum: 40
> >
> > Manufacturer: BOE Model 82d Serial Number 0
> > Made week 35 of 2018
> > EDID version: 1.4
> > Digital display
> > 6 bits per primary color channel
> > DisplayPort interface
> > Maximum image size: 29 cm x 17 cm
> > Gamma: 2.20
> > Supported color formats: RGB 4:4:4
> > First detailed timing is preferred timing
> > Established timings supported:
> > Standard timings supported:
> > Detailed mode: Clock 147.840 MHz, 294 mm x 165 mm
> > 1920 1968 2000 2200 hborder 0
> > 1080 1083 1089 1120 vborder 0
> > +hsync -vsync
> > Manufacturer-specified data, tag 0
> > ASCII string: BOE
> > ASCII string: NV133FHM-N62
> > Checksum: 0x40 (valid)
> >
> > Unknown extension block
> >
> > EDID block does NOT conform to EDID 1.3!
> > Missing name descriptor
> > Missing monitor ranges
> > Detailed block string not properly terminated
> > EDID block does not conform at all!
> > Has 128 nonconformant extension block(s)
>
> I did attempt to modify the patch, and I don't think I did it correctly
>
> Around line 232, I changed
>
> IS_SC7180_TARGET(c->hw.hwversion))
>
> to
>
> IS_SC7180_TARGET(c->hw.hwversion) ||
>
> IS_SDM845_TARGET(c->hw.hwversion))
>
>
> But it would seem that only gets us 1/2 way there...
>
> https://dev.gentoo.org/~steev/files/image2.jpg
>
neat.. I guess this is because 845/850 supports split-lm (layer
mixer), and uses it for horiz resolution above 1080
(MAX_HDISPLAY_SPLIT)
I *think* you could probably increase MAX_HDISPLAY_SPLIT to 1920 and
it will "work". (Or at least I think our reasons for using a lower
value are power, on older gens we only used split mode above 2k
width.)
BR,
-R
>
> But should I continue on this path, or should we be finding others who
> have an N61 and see what their EDID reports?
>
> I have another c630, but unfortunately, it appears to have the IVO
> screen in it, instead of another N61. I asked another user and he also
> had the IVO.
>
> -- steev
>
Hi,
On Thu, Jul 9, 2020 at 11:15 PM Steev Klimaszewski <[email protected]> wrote:
>
> Hi,
>
> On 7/9/20 11:12 PM, Doug Anderson wrote:
> >> root@c630:~# bus=$(i2cdetect -l | grep sn65 | sed 's/i2c-\([0-9]*\).*$/\1/')
> >> root@c630:~# i2cdump ${bus} 0x50 i > edid
> >> WARNING! This program can confuse your I2C bus, cause data loss and worse!
> >> I will probe file /dev/i2c-16, address 0x50, mode i2c block
> >> Continue? [Y/n]
> >> root@c630:~# edid-decode edid
> >> edid-decode (hex):
> >>
> >> 00 ff ff ff ff ff ff 00 09 e5 d1 07 00 00 00 00
> >> 01 1c 01 04 a5 1d 11 78 0a 1d b0 a6 58 54 9e 26
> >> 0f 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
> >> 01 01 01 01 01 01 c0 39 80 18 71 38 28 40 30 20
> >> 36 00 26 a5 10 00 00 1a 00 00 00 00 00 00 00 00
> >> 00 00 00 00 00 00 00 00 00 1a 00 00 00 fe 00 42
> >> 4f 45 20 43 51 0a 20 20 20 20 20 20 00 00 00 fe
> >> 00 4e 56 31 33 33 46 48 4d 2d 4e 36 31 0a 00 9a
> >>
> >> 03 26 0a 77 ab 1c 05 71 6f 1d 8c f1 43 ce 6a bb
> >> fb d3 11 20 39 07 22 6e 65 68 77 70 d3 05 34 73
> >> 44 21 8b fd f5 6d 11 62 94 2a 7c fa 93 ba 6a 61
> >> 92 da 15 53 4c 39 eb f7 86 23 97 48 e9 39 09 d2
> >> 66 02 70 bb e2 77 0f 4a a3 a0 4c 72 6e 5d 47 70
> >> 43 c2 13 f3 b2 d9 b9 78 02 be 41 82 15 6a 28 dc
> >> 45 0f 9d eb 0f 2a cc e8 35 8d 34 7f 3e 84 5e a3
> >> 30 5e 1e 29 0a 48 0c d1 0a c4 08 31 03 a9 3b 29
> >>
> >> ----------------
> >>
> >> EDID version: 1.4
> >> Manufacturer: BOE Model 2001 Serial Number 0
> >> Made in week 1 of 2018
> >> Digital display
> >> 8 bits per primary color channel
> >> DisplayPort interface
> >> Maximum image size: 29 cm x 17 cm
> >> Gamma: 2.20
> >> Supported color formats: RGB 4:4:4, YCrCb 4:4:4
> >> First detailed timing includes the native pixel format and preferred
> >> refresh rate
> >> Color Characteristics
> >> Red: 0.6484, 0.3447
> >> Green: 0.3310, 0.6181
> >> Blue: 0.1503, 0.0615
> >> White: 0.3125, 0.3281
> >> Established Timings I & II: none
> >> Standard Timings: none
> >> Detailed mode: Clock 147.840 MHz, 294 mm x 165 mm
> >> 1920 1968 2000 2200 ( 48 32 200)
> >> 1080 1083 1089 1120 ( 3 6 31)
> >> +hsync -vsync
> >> VertFreq: 60.000 Hz, HorFreq: 67.200 kHz
> >> Manufacturer-Specified Display Descriptor (0x00): 00 00 00 00 00 00 00
> >> 00 00 00 00 00 00 00 00 1a ................
> >> Alphanumeric Data String: BOE CQ
> >> Alphanumeric Data String: NV133FHM-N61
> >> Checksum: 0x9a
> >>
> >> ----------------
> >>
> >> Unknown EDID Extension Block 0x03
> >> 03 26 0a 77 ab 1c 05 71 6f 1d 8c f1 43 ce 6a bb .&.w...qo...C.j.
> >> fb d3 11 20 39 07 22 6e 65 68 77 70 d3 05 34 73 ... 9."nehwp..4s
> >> 44 21 8b fd f5 6d 11 62 94 2a 7c fa 93 ba 6a 61 D!...m.b.*|...ja
> >> 92 da 15 53 4c 39 eb f7 86 23 97 48 e9 39 09 d2 ...SL9...#.H.9..
> >> 66 02 70 bb e2 77 0f 4a a3 a0 4c 72 6e 5d 47 70 f.p..w.J..Lrn]Gp
> >> 43 c2 13 f3 b2 d9 b9 78 02 be 41 82 15 6a 28 dc C......x..A..j(.
> >> 45 0f 9d eb 0f 2a cc e8 35 8d 34 7f 3e 84 5e a3 E....*..5.4.>.^.
> >> 30 5e 1e 29 0a 48 0c d1 0a c4 08 31 03 a9 3b 29 0^.).H.....1..;)
> >> Checksum: 0x29 (should be 0x82)
> >>
> >>
> >> - My edid does in fact say it's 8bit
> > Crazy! Mine:
> >
> > Extracted contents:
> > header: 00 ff ff ff ff ff ff 00
> > serial number: 09 e5 2d 08 00 00 00 00 23 1c
> > version: 01 04
> > basic params: 95 1d 11 78 02
> > chroma info: d5 00 a6 58 54 9f 27 0f 4f 57
> > established: 00 00 00
> > standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
> > descriptor 1: c0 39 80 18 71 38 28 40 30 20 36 00 26 a5 10 00 00 1a
> > descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> > descriptor 3: 00 00 00 fe 00 42 4f 45 20 43 51 0a 20 20 20 20 20 20
> > descriptor 4: 00 00 00 fe 00 4e 56 31 33 33 46 48 4d 2d 4e 36 32 0a
> > extensions: 00
> > checksum: 40
> >
> > Manufacturer: BOE Model 82d Serial Number 0
> > Made week 35 of 2018
> > EDID version: 1.4
> > Digital display
> > 6 bits per primary color channel
> > DisplayPort interface
> > Maximum image size: 29 cm x 17 cm
> > Gamma: 2.20
> > Supported color formats: RGB 4:4:4
> > First detailed timing is preferred timing
> > Established timings supported:
> > Standard timings supported:
> > Detailed mode: Clock 147.840 MHz, 294 mm x 165 mm
> > 1920 1968 2000 2200 hborder 0
> > 1080 1083 1089 1120 vborder 0
> > +hsync -vsync
> > Manufacturer-specified data, tag 0
> > ASCII string: BOE
> > ASCII string: NV133FHM-N62
> > Checksum: 0x40 (valid)
> >
> > Unknown extension block
> >
> > EDID block does NOT conform to EDID 1.3!
> > Missing name descriptor
> > Missing monitor ranges
> > Detailed block string not properly terminated
> > EDID block does not conform at all!
> > Has 128 nonconformant extension block(s)
>
> I did attempt to modify the patch, and I don't think I did it correctly
>
> Around line 232, I changed
>
> IS_SC7180_TARGET(c->hw.hwversion))
>
> to
>
> IS_SC7180_TARGET(c->hw.hwversion) ||
>
> IS_SDM845_TARGET(c->hw.hwversion))
>
>
> But it would seem that only gets us 1/2 way there...
>
> https://dev.gentoo.org/~steev/files/image2.jpg
>
>
> But should I continue on this path,
It's probably worth getting dithering working on your sdm845 anyway in
case anyone actually does put a 6bpp panel on this SoC.
> or should we be finding others who
> have an N61 and see what their EDID reports?
I have an email out to BOE, but it might take a little while to get a
response. I'll see what they say. If they say that the panel
actually supports 8bpp then it's a no-brainer and we should just
switch to 8bpp and be done.
...but if they say it's a 6bpp panel that has its own dither logic
then it gets more complicated. Initially one would think there should
be very little downside in defining the panel as an 8bpp panel and
calling it done. ...except that it conflicts with some other work
that I have in progress. :-P Specifically if you treat the panel as
6bpp and then reduce the blanking a tiny bit you can actually save 75
mW of total system power on my board (probably similar on your board
since you have the same bridge chip). You can see a patch to do that
here:
https://crrev.com/c/2276384
...so I'm hoping to get some clarity from BOE both on the true bits
per pixel and whether my proposed timings are valid before moving
forward. Is that OK?
-Doug
On 7/10/20 9:47 AM, Doug Anderson wrote:
> Hi,
>
>
> But should I continue on this path,
> It's probably worth getting dithering working on your sdm845 anyway in
> case anyone actually does put a 6bpp panel on this SoC.
>
>
>> or should we be finding others who
>> have an N61 and see what their EDID reports?
> I have an email out to BOE, but it might take a little while to get a
> response. I'll see what they say. If they say that the panel
> actually supports 8bpp then it's a no-brainer and we should just
> switch to 8bpp and be done.
>
> ...but if they say it's a 6bpp panel that has its own dither logic
> then it gets more complicated. Initially one would think there should
> be very little downside in defining the panel as an 8bpp panel and
> calling it done. ...except that it conflicts with some other work
> that I have in progress. :-P Specifically if you treat the panel as
> 6bpp and then reduce the blanking a tiny bit you can actually save 75
> mW of total system power on my board (probably similar on your board
> since you have the same bridge chip). You can see a patch to do that
> here:
>
> https://crrev.com/c/2276384
>
> ...so I'm hoping to get some clarity from BOE both on the true bits
> per pixel and whether my proposed timings are valid before moving
> forward. Is that OK?
>
>
> -Doug
It's fine by me - testing Rob's suggestion of changing
MAX_HDISPLAY_SPLIT 1080->1920 along with the change to adding IS_SDM845
does give me a full screen that looks nicer, I'm fine with using the
hack locally until a proper solution is found. And I'm always a fan of
using less power on a laptop.
I'll give the patch a spin here if you want as well.
Hopefully BOE gets back to you soon, and there's no rush, I'm just an
end user who is extremely appreciative of all the work everyone on the
list and the kernel in general put in to make my machines usable.
Hi,
On Fri, Jul 10, 2020 at 10:11 AM Steev Klimaszewski <[email protected]> wrote:
>
>
> On 7/10/20 9:47 AM, Doug Anderson wrote:
> > Hi,
> >
> >
> > But should I continue on this path,
> > It's probably worth getting dithering working on your sdm845 anyway in
> > case anyone actually does put a 6bpp panel on this SoC.
> >
> >
> >> or should we be finding others who
> >> have an N61 and see what their EDID reports?
> > I have an email out to BOE, but it might take a little while to get a
> > response. I'll see what they say. If they say that the panel
> > actually supports 8bpp then it's a no-brainer and we should just
> > switch to 8bpp and be done.
> >
> > ...but if they say it's a 6bpp panel that has its own dither logic
> > then it gets more complicated. Initially one would think there should
> > be very little downside in defining the panel as an 8bpp panel and
> > calling it done. ...except that it conflicts with some other work
> > that I have in progress. :-P Specifically if you treat the panel as
> > 6bpp and then reduce the blanking a tiny bit you can actually save 75
> > mW of total system power on my board (probably similar on your board
> > since you have the same bridge chip). You can see a patch to do that
> > here:
> >
> > https://crrev.com/c/2276384
> >
> > ...so I'm hoping to get some clarity from BOE both on the true bits
> > per pixel and whether my proposed timings are valid before moving
> > forward. Is that OK?
> >
> >
> > -Doug
>
>
> It's fine by me - testing Rob's suggestion of changing
> MAX_HDISPLAY_SPLIT 1080->1920 along with the change to adding IS_SDM845
> does give me a full screen that looks nicer, I'm fine with using the
> hack locally until a proper solution is found. And I'm always a fan of
> using less power on a laptop.
>
>
> I'll give the patch a spin here if you want as well.
>
>
> Hopefully BOE gets back to you soon, and there's no rush, I'm just an
> end user who is extremely appreciative of all the work everyone on the
> list and the kernel in general put in to make my machines usable.
Just FYI that I got confirmation that the panel is truly 6 bpp but it
will do FRC dithering if given an 8 bpp input. That means that you
should be getting just as good picture quality (and possibly more
tunable) by using the dithering in the display pipeline and leaving
the panel as 6bpp. Thus I'm going to assume that's the route we'll go
down. If ever we find someone that wants to use this panel on a
display controller that can't do its own dithering then I guess we'll
have to figure out what to do then...
In terms of the more optimal pixel clock for saving power, my proposal
is still being analyzed and I'll report back when I hear more. I'm
seeing if BOE can confirm that my proposal will work both for my panel
(the -n62 variant) and the one you have (the -n61 variant).
-Doug
Hi,
On Tue, Jul 14, 2020 at 8:31 AM Doug Anderson <[email protected]> wrote:
>
> > Hopefully BOE gets back to you soon, and there's no rush, I'm just an
> > end user who is extremely appreciative of all the work everyone on the
> > list and the kernel in general put in to make my machines usable.
>
> Just FYI that I got confirmation that the panel is truly 6 bpp but it
> will do FRC dithering if given an 8 bpp input. That means that you
> should be getting just as good picture quality (and possibly more
> tunable) by using the dithering in the display pipeline and leaving
> the panel as 6bpp. Thus I'm going to assume that's the route we'll go
> down. If ever we find someone that wants to use this panel on a
> display controller that can't do its own dithering then I guess we'll
> have to figure out what to do then...
>
> In terms of the more optimal pixel clock for saving power, my proposal
> is still being analyzed and I'll report back when I hear more. I'm
> seeing if BOE can confirm that my proposal will work both for my panel
> (the -n62 variant) and the one you have (the -n61 variant).
To close the loop here: we finally got back an official word that we
shouldn't use my proposed timings that would have allowed us to move
down to a 1.62 GHz pixel clock. Though they work most of the time,
there are apparently some corner cases where they cause problems /
flickering. :( While you could certainly use the timings on your own
system if they happen to work for you, I don't think it'd be a good
idea to switch the default over to them or anything. I'm told that
hardware makers will take this type of thing into consideration for
future hardware.
-Doug
