LinuxLists.cc - [PATCH 1/6] arm64: dts: qcom: sm8150: describe all PCI MSI interrupts

2024-01-25 13:09:13

Subject: [PATCH 1/6] arm64: dts: qcom: sm8150: describe all PCI MSI interrupts

Each group of MSI interrupts is mapped to the separate host interrupt.
Describe each of interrupts in the device tree for PCIe hosts. Not
tested on hardware.

Signed-off-by: Krzysztof Kozlowski <[email protected]>

---

Bindings now expect 8 interrupts:
https://lore.kernel.org/linux-devicetree/[email protected]/T/#t
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 24 ++++++++++++++++++++----
1 file changed, 20 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 761a6757dc26..26cf8459f74f 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -1843,8 +1843,16 @@ pcie0: pcie@1c00000 {
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;

- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
@@ -1934,8 +1942,16 @@ pcie1: pcie@1c08000 {
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;

- interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
--
2.34.1

2024-01-25 13:09:57

by Krzysztof Kozlowski

[permalink] [raw]

Subject: [PATCH 5/6] arm64: dts: qcom: sm8550: describe all PCI MSI interrupts

Each group of MSI interrupts is mapped to the separate host interrupt.
Describe each of interrupts in the device tree for PCIe hosts. Only
boot tested on hardware.

Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 24 ++++++++++++++++++++----
1 file changed, 20 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index ee1ba5a8c8fc..80e31fb21055 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1713,8 +1713,16 @@ pcie0: pcie@1c00000 {
linux,pci-domain = <0>;
num-lanes = <2>;

- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7";

#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
@@ -1804,8 +1812,16 @@ pcie1: pcie@1c08000 {
linux,pci-domain = <1>;
num-lanes = <2>;

- interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7";

#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
--
2.34.1

2024-01-25 13:10:15

by Krzysztof Kozlowski

[permalink] [raw]

Subject: [PATCH 6/6] arm64: dts: qcom: sm8650: describe all PCI MSI interrupts

Each group of MSI interrupts is mapped to the separate host interrupt.
Describe each of interrupts in the device tree for PCIe hosts. Not
tested on hardware.

Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8650.dtsi | 24 ++++++++++++++++++++----
1 file changed, 20 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 2df77123a8c7..9fc4f3e37a8c 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -2213,8 +2213,16 @@ pcie0: pci@1c00000 {
<0 0x60100000 0 0x100000>;
reg-names = "parf", "dbi", "elbi", "atu", "config";

- interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7";

clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
@@ -2317,8 +2325,16 @@ pcie1: pci@1c08000 {
"atu",
"config";

- interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7";

clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
--
2.34.1

2024-01-25 13:12:24

by Krzysztof Kozlowski

[permalink] [raw]

Subject: [PATCH 2/6] arm64: dts: qcom: sm8250: describe all PCI MSI interrupts

Each group of MSI interrupts is mapped to the separate host interrupt.
Describe each of interrupts in the device tree for PCIe hosts. Not
tested on hardware.

PCIe0 was done already in commit f2819650aab5 ("arm64: dts: qcom:
sm8250: provide additional MSI interrupts").

Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 24 ++++++++++++++++++++----
1 file changed, 20 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 760501c1301a..41f5e6eb2f6b 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2248,8 +2248,16 @@ pcie1: pcie@1c08000 {
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;

- interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
@@ -2349,8 +2357,16 @@ pcie2: pcie@1c10000 {
ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
<0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;

- interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
--
2.34.1

2024-01-25 13:19:17

by Dmitry Baryshkov

[permalink] [raw]

Subject: Re: [PATCH 2/6] arm64: dts: qcom: sm8250: describe all PCI MSI interrupts

On Thu, 25 Jan 2024 at 15:07, Krzysztof Kozlowski
<[email protected]> wrote:
>
> Each group of MSI interrupts is mapped to the separate host interrupt.
> Describe each of interrupts in the device tree for PCIe hosts. Not
> tested on hardware.
>
> PCIe0 was done already in commit f2819650aab5 ("arm64: dts: qcom:
> sm8250: provide additional MSI interrupts").
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 24 ++++++++++++++++++++----
> 1 file changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index 760501c1301a..41f5e6eb2f6b 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -2248,8 +2248,16 @@ pcie1: pcie@1c08000 {
> ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
> <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
>
> - interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "msi";
> + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi0", "msi1", "msi2", "msi3",
> + "msi4", "msi5", "msi6", "msi7";
> #interrupt-cells = <1>;
> interrupt-map-mask = <0 0 0 0x7>;
> interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> @@ -2349,8 +2357,16 @@ pcie2: pcie@1c10000 {
> ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
> <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
>
> - interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "msi";
> + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi0", "msi1", "msi2", "msi3",
> + "msi4", "msi5", "msi6", "msi7";

This part looks a bit suspicious. All other platforms have these
interrupts in a continuous range.

Other than that, LGTM

> #interrupt-cells = <1>;
> interrupt-map-mask = <0 0 0 0x7>;
> interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> --
> 2.34.1
>
>

--
With best wishes
Dmitry

2024-01-25 13:20:28

by Dmitry Baryshkov

[permalink] [raw]

Subject: Re: [PATCH 1/6] arm64: dts: qcom: sm8150: describe all PCI MSI interrupts

On Thu, 25 Jan 2024 at 15:07, Krzysztof Kozlowski
<[email protected]> wrote:
>
> Each group of MSI interrupts is mapped to the separate host interrupt.
> Describe each of interrupts in the device tree for PCIe hosts. Not
> tested on hardware.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>
> ---
>
> Bindings now expect 8 interrupts:
> https://lore.kernel.org/linux-devicetree/[email protected]/T/#t
> ---
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 24 ++++++++++++++++++++----
> 1 file changed, 20 insertions(+), 4 deletions(-)

Reviewed-by: Dmitry Baryshkov <[email protected]>

--
With best wishes
Dmitry

2024-01-25 13:26:24

by Dmitry Baryshkov

[permalink] [raw]

Subject: Re: [PATCH 5/6] arm64: dts: qcom: sm8550: describe all PCI MSI interrupts

On Thu, 25 Jan 2024 at 15:08, Krzysztof Kozlowski
<[email protected]> wrote:
>
> Each group of MSI interrupts is mapped to the separate host interrupt.
> Describe each of interrupts in the device tree for PCIe hosts. Only
> boot tested on hardware.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 24 ++++++++++++++++++++----
> 1 file changed, 20 insertions(+), 4 deletions(-)
>

Reviewed-by: Dmitry Baryshkov <[email protected]>

--
With best wishes
Dmitry

2024-01-25 13:26:41

by Dmitry Baryshkov

[permalink] [raw]

Subject: Re: [PATCH 6/6] arm64: dts: qcom: sm8650: describe all PCI MSI interrupts

On Thu, 25 Jan 2024 at 15:08, Krzysztof Kozlowski
<[email protected]> wrote:
>
> Each group of MSI interrupts is mapped to the separate host interrupt.
> Describe each of interrupts in the device tree for PCIe hosts. Not
> tested on hardware.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8650.dtsi | 24 ++++++++++++++++++++----
> 1 file changed, 20 insertions(+), 4 deletions(-)
>

Reviewed-by: Dmitry Baryshkov <[email protected]>

--
With best wishes
Dmitry

2024-01-25 13:30:40

by Dmitry Baryshkov

[permalink] [raw]

Subject: Re: [PATCH 2/6] arm64: dts: qcom: sm8250: describe all PCI MSI interrupts

On Thu, 25 Jan 2024 at 15:18, Dmitry Baryshkov
<[email protected]> wrote:
>
> On Thu, 25 Jan 2024 at 15:07, Krzysztof Kozlowski
> <[email protected]> wrote:
> >
> > Each group of MSI interrupts is mapped to the separate host interrupt.
> > Describe each of interrupts in the device tree for PCIe hosts. Not
> > tested on hardware.
> >
> > PCIe0 was done already in commit f2819650aab5 ("arm64: dts: qcom:
> > sm8250: provide additional MSI interrupts").
> >
> > Signed-off-by: Krzysztof Kozlowski <[email protected]>
> > ---
> > arch/arm64/boot/dts/qcom/sm8250.dtsi | 24 ++++++++++++++++++++----
> > 1 file changed, 20 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> > index 760501c1301a..41f5e6eb2f6b 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> > @@ -2248,8 +2248,16 @@ pcie1: pcie@1c08000 {
> > ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
> > <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
> >
> > - interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
> > - interrupt-names = "msi";
> > + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "msi0", "msi1", "msi2", "msi3",
> > + "msi4", "msi5", "msi6", "msi7";
> > #interrupt-cells = <1>;
> > interrupt-map-mask = <0 0 0 0x7>;
> > interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> > @@ -2349,8 +2357,16 @@ pcie2: pcie@1c10000 {
> > ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
> > <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
> >
> > - interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
> > - interrupt-names = "msi";
> > + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "msi0", "msi1", "msi2", "msi3",
> > + "msi4", "msi5", "msi6", "msi7";
>
> This part looks a bit suspicious. All other platforms have these
> interrupts in a continuous range.

Hmm, pcie1 interrupts are also not contiguous. Okay, fine then:

Reviewed-by: Dmitry Baryshkov <[email protected]>

--
With best wishes
Dmitry

2024-01-25 13:41:43

by Neil Armstrong

[permalink] [raw]

Subject: Re: [PATCH 5/6] arm64: dts: qcom: sm8550: describe all PCI MSI interrupts

On 25/01/2024 14:06, Krzysztof Kozlowski wrote:
> Each group of MSI interrupts is mapped to the separate host interrupt.
> Describe each of interrupts in the device tree for PCIe hosts. Only
> boot tested on hardware.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 24 ++++++++++++++++++++----
> 1 file changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index ee1ba5a8c8fc..80e31fb21055 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -1713,8 +1713,16 @@ pcie0: pcie@1c00000 {
> linux,pci-domain = <0>;
> num-lanes = <2>;
>
> - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "msi";
> + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi0", "msi1", "msi2", "msi3",
> + "msi4", "msi5", "msi6", "msi7";
>
> #interrupt-cells = <1>;
> interrupt-map-mask = <0 0 0 0x7>;
> @@ -1804,8 +1812,16 @@ pcie1: pcie@1c08000 {
> linux,pci-domain = <1>;
> num-lanes = <2>;
>
> - interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "msi";
> + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi0", "msi1", "msi2", "msi3",
> + "msi4", "msi5", "msi6", "msi7";
>
> #interrupt-cells = <1>;
> interrupt-map-mask = <0 0 0 0x7>;

230: 22 0 0 0 0 0 0 0 PCI-MSI 134742016 Edge nvme0q0
232: 0 0 0 0 0 0 0 0 PCI-MSI 134742017 Edge nvme0q1
233: 1 0 0 0 0 0 0 0 PCI-MSI 134742018 Edge nvme0q2
234: 0 0 0 0 0 0 0 0 PCI-MSI 134742019 Edge nvme0q3
235: 1 0 0 0 0 0 0 0 PCI-MSI 134742020 Edge nvme0q4
236: 1 0 0 0 0 0 0 0 PCI-MSI 134742021 Edge nvme0q5
237: 23 0 0 0 0 0 0 0 PCI-MSI 134742022 Edge nvme0q6
238: 18 0 0 0 0 0 0 0 PCI-MSI 134742023 Edge nvme0q7
239: 0 0 0 0 0 0 0 0 PCI-MSI 134742024 Edge nvme0q8
258: 4 0 0 0 0 0 0 0 PCI-MSI 524288 Edge bhi
259: 5 0 0 0 0 0 0 0 PCI-MSI 524289 Edge mhi
260: 33 0 0 0 0 0 0 0 PCI-MSI 524290 Edge mhi
261: 3 0 0 0 0 0 0 0 PCI-MSI 524291 Edge ce0
262: 2 0 0 0 0 0 0 0 PCI-MSI 524292 Edge ce1
263: 41 0 0 0 0 0 0 0 PCI-MSI 524293 Edge ce2
264: 28 0 0 0 0 0 0 0 PCI-MSI 524294 Edge ce3
265: 0 0 0 0 0 0 0 0 PCI-MSI 524295 Edge ce5
266: 0 0 0 0 0 0 0 0 PCI-MSI 524296 Edge DP_EXT_IRQ
267: 0 0 0 0 0 0 0 0 PCI-MSI 524297 Edge DP_EXT_IRQ
268: 0 0 0 0 0 0 0 0 PCI-MSI 524298 Edge DP_EXT_IRQ
269: 0 0 0 0 0 0 0 0 PCI-MSI 524299 Edge DP_EXT_IRQ
270: 0 0 0 0 0 0 0 0 PCI-MSI 524300 Edge DP_EXT_IRQ
271: 0 0 0 0 0 0 0 0 PCI-MSI 524301 Edge DP_EXT_IRQ
272: 0 0 0 0 0 0 0 0 PCI-MSI 524302 Edge DP_EXT_IRQ

Tested-by: Neil Armstrong <[email protected]> # on SM8550-HDK

235: 4 0 0 0 0 0 0 0 PCI-MSI 524288 Edge bhi
236: 5 0 0 0 0 0 0 0 PCI-MSI 524289 Edge mhi
237: 33 0 0 0 0 0 0 0 PCI-MSI 524290 Edge mhi
238: 3 0 0 0 0 0 0 0 PCI-MSI 524291 Edge ce0
239: 2 0 0 0 0 0 0 0 PCI-MSI 524292 Edge ce1
240: 40 0 0 0 0 0 0 0 PCI-MSI 524293 Edge ce2
241: 29 0 0 0 0 0 0 0 PCI-MSI 524294 Edge ce3
242: 0 0 0 0 0 0 0 0 PCI-MSI 524295 Edge ce5
243: 0 0 0 0 0 0 0 0 PCI-MSI 524296 Edge DP_EXT_IRQ
244: 0 0 0 0 0 0 0 0 PCI-MSI 524297 Edge DP_EXT_IRQ
245: 0 0 0 0 0 0 0 0 PCI-MSI 524298 Edge DP_EXT_IRQ
246: 0 0 0 0 0 0 0 0 PCI-MSI 524299 Edge DP_EXT_IRQ
247: 0 0 0 0 0 0 0 0 PCI-MSI 524300 Edge DP_EXT_IRQ
248: 0 0 0 0 0 0 0 0 PCI-MSI 524301 Edge DP_EXT_IRQ
249: 0 0 0 0 0 0 0 0 PCI-MSI 524302 Edge DP_EXT_IRQ

Tested-by: Neil Armstrong <[email protected]> # on SM8550-QRD

2024-01-25 13:43:17

by Neil Armstrong

[permalink] [raw]

Subject: Re: [PATCH 6/6] arm64: dts: qcom: sm8650: describe all PCI MSI interrupts

2024-01-25 14:47:14

by Krzysztof Kozlowski

[permalink] [raw]

Subject: Re: [PATCH 2/6] arm64: dts: qcom: sm8250: describe all PCI MSI interrupts

On 25/01/2024 14:25, Dmitry Baryshkov wrote:
>>> interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
>>> @@ -2349,8 +2357,16 @@ pcie2: pcie@1c10000 {
>>> ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>,
>>> <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
>>>
>>> - interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
>>> - interrupt-names = "msi";
>>> + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
>>> + interrupt-names = "msi0", "msi1", "msi2", "msi3",
>>> + "msi4", "msi5", "msi6", "msi7";
>>
>> This part looks a bit suspicious. All other platforms have these
>> interrupts in a continuous range.
>
> Hmm, pcie1 interrupts are also not contiguous. Okay, fine then:
>

Yeah, the other case has even two gaps.

Best regards,
Krzysztof

2024-01-25 16:33:35

by Konrad Dybcio

[permalink] [raw]

Subject: Re: [PATCH 1/6] arm64: dts: qcom: sm8150: describe all PCI MSI interrupts

On 1/25/24 14:06, Krzysztof Kozlowski wrote:
> Each group of MSI interrupts is mapped to the separate host interrupt.
> Describe each of interrupts in the device tree for PCIe hosts. Not
> tested on hardware.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>
> ---

There's no cover letter, so I can't batch a-b..

Could you please resend, turning interrupt-names into a vertical
list?

Konrad

2024-01-26 10:11:48

by Krzysztof Kozlowski

[permalink] [raw]

Subject: Re: [PATCH 1/6] arm64: dts: qcom: sm8150: describe all PCI MSI interrupts

On 25/01/2024 17:33, Konrad Dybcio wrote:
>
>
> On 1/25/24 14:06, Krzysztof Kozlowski wrote:
>> Each group of MSI interrupts is mapped to the separate host interrupt.
>> Describe each of interrupts in the device tree for PCIe hosts. Not
>> tested on hardware.
>>
>> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>>
>> ---
>
> There's no cover letter, so I can't batch a-b..

Sorry for that. I'll fix it for next version.

>
> Could you please resend, turning interrupt-names into a vertical
> list?

One "msiX" per line? Sure, I can.

Best regards,
Krzysztof