Allwinner A64 has display engine pipeline like other Allwinner SOC's A83T/H3/H5.
A64 behaviour similar to Allwinner A83T where
Mixer0 => TCON0 => LVDS/RGB/MIPI-DSI
Mixer1 => TCON1 => HDMI
as per Display System Block Diagram from the A64 user manual.
This patchset adds support for the two display pipelines, and enables
the HDMI output on several boards. The first pipeline is not enabled in
this patchset yet, although it's added.
Icenowy Zheng (2):
clk: sunxi-ng: a64: Add max. rate constraint to video PLLs
dt-bindings: sun4i-drm: add HDMI VCC supply property for sun8i-dw-hdmi
Jagan Teki (8):
clk: sunxi-ng: a64: Add minimal rate for video PLLs
dt-bindings: display: Add compatible for A64 DE2 display pipeline
drm/sun4i: Add support for A64 mixers
drm/sun4i: Add support for A64 display engine
dt-bindings: display: Add compatible for A64 HDMI
dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO0 macro
arm64: dts: allwinner: a64: Add display pipeline
arm64: dts: allwinner: a64: Enable HDMI output on A64 boards w/ HDMI
Jernej Skrabec (1):
drm/sun4i: Add support for HDMI voltage regulator
.../bindings/display/sunxi/sun4i-drm.txt | 9 +
.../dts/allwinner/sun50i-a64-bananapi-m64.dts | 34 ++++
.../dts/allwinner/sun50i-a64-nanopi-a64.dts | 34 ++++
.../dts/allwinner/sun50i-a64-olinuxino.dts | 34 ++++
.../dts/allwinner/sun50i-a64-orangepi-win.dts | 34 ++++
.../boot/dts/allwinner/sun50i-a64-pine64.dts | 34 ++++
.../allwinner/sun50i-a64-sopine-baseboard.dts | 34 ++++
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 170 ++++++++++++++++++
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 48 ++---
drivers/clk/sunxi-ng/ccu-sun50i-a64.h | 4 +-
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 17 +-
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 2 +
drivers/gpu/drm/sun4i/sun8i_mixer.c | 24 +++
include/dt-bindings/clock/sun50i-a64-ccu.h | 1 +
15 files changed, 456 insertions(+), 24 deletions(-)
--
2.18.0
From: Jagan Teki <[email protected]>
According to documentation and experience with other similar SoCs, video
PLLs don't work stable if their output frequency is set below 192 MHz.
Because of that, set minimal rate to both A64 video PLLs to 192 MHz.
Signed-off-by: Jagan Teki <[email protected]>
Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
---
Changes for v3..v4:
- none
Changes for v2:
- New patch
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 46 ++++++++++++++-------------
1 file changed, 24 insertions(+), 22 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index ee9c12cf3f08..d0e30192f0cf 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -64,17 +64,18 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
- "osc24M", 0x010,
- 8, 7, /* N */
- 0, 4, /* M */
- BIT(24), /* frac enable */
- BIT(25), /* frac select */
- 270000000, /* frac rate 0 */
- 297000000, /* frac rate 1 */
- BIT(31), /* gate */
- BIT(28), /* lock */
- CLK_SET_RATE_UNGATE);
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video0_clk, "pll-video0",
+ "osc24M", 0x010,
+ 192000000, /* Minimum rate */
+ 8, 7, /* N */
+ 0, 4, /* M */
+ BIT(24), /* frac enable */
+ BIT(25), /* frac select */
+ 270000000, /* frac rate 0 */
+ 297000000, /* frac rate 1 */
+ BIT(31), /* gate */
+ BIT(28), /* lock */
+ CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
"osc24M", 0x018,
@@ -125,17 +126,18 @@ static struct ccu_nk pll_periph1_clk = {
},
};
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
- "osc24M", 0x030,
- 8, 7, /* N */
- 0, 4, /* M */
- BIT(24), /* frac enable */
- BIT(25), /* frac select */
- 270000000, /* frac rate 0 */
- 297000000, /* frac rate 1 */
- BIT(31), /* gate */
- BIT(28), /* lock */
- CLK_SET_RATE_UNGATE);
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video1_clk, "pll-video1",
+ "osc24M", 0x030,
+ 192000000, /* Minimum rate */
+ 8, 7, /* N */
+ 0, 4, /* M */
+ BIT(24), /* frac enable */
+ BIT(25), /* frac select */
+ 270000000, /* frac rate 0 */
+ 297000000, /* frac rate 1 */
+ BIT(31), /* gate */
+ BIT(28), /* lock */
+ CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
"osc24M", 0x038,
--
2.18.0
Video PLLs on A64 can be set to higher rate that it is actually
supported by HW.
Limit maximum rate to 1008 MHz. This is the maximum allowed rate by BSP
clock driver. Interestengly, user manual specifies maximum frequency to
be 600 MHz. Historically, this data was wrong in some user manuals for
other SoCs, so more faith is put in BSP clock driver.
Signed-off-by: Icenowy Zheng <[email protected]>
---
New patch in v4.
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 50 ++++++++++++++-------------
1 file changed, 26 insertions(+), 24 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index d0e30192f0cf..5f80eb018014 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -64,18 +64,19 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video0_clk, "pll-video0",
- "osc24M", 0x010,
- 192000000, /* Minimum rate */
- 8, 7, /* N */
- 0, 4, /* M */
- BIT(24), /* frac enable */
- BIT(25), /* frac select */
- 270000000, /* frac rate 0 */
- 297000000, /* frac rate 1 */
- BIT(31), /* gate */
- BIT(28), /* lock */
- CLK_SET_RATE_UNGATE);
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
+ "osc24M", 0x010,
+ 192000000, /* Minimum rate */
+ 1008000000, /* Maximum rate */
+ 8, 7, /* N */
+ 0, 4, /* M */
+ BIT(24), /* frac enable */
+ BIT(25), /* frac select */
+ 270000000, /* frac rate 0 */
+ 297000000, /* frac rate 1 */
+ BIT(31), /* gate */
+ BIT(28), /* lock */
+ CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
"osc24M", 0x018,
@@ -126,18 +127,19 @@ static struct ccu_nk pll_periph1_clk = {
},
};
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video1_clk, "pll-video1",
- "osc24M", 0x030,
- 192000000, /* Minimum rate */
- 8, 7, /* N */
- 0, 4, /* M */
- BIT(24), /* frac enable */
- BIT(25), /* frac select */
- 270000000, /* frac rate 0 */
- 297000000, /* frac rate 1 */
- BIT(31), /* gate */
- BIT(28), /* lock */
- CLK_SET_RATE_UNGATE);
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",
+ "osc24M", 0x030,
+ 192000000, /* Minimum rate */
+ 1008000000, /* Maximum rate */
+ 8, 7, /* N */
+ 0, 4, /* M */
+ BIT(24), /* frac enable */
+ BIT(25), /* frac select */
+ 270000000, /* frac rate 0 */
+ 297000000, /* frac rate 1 */
+ BIT(31), /* gate */
+ BIT(28), /* lock */
+ CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
"osc24M", 0x038,
--
2.18.0
From: Jagan Teki <[email protected]>
Allwinner A64 has a DE2 display pipeline. The TCONs are similar to the
ones in A83T, but the mixers are new (similar to the later R40 SoC).
This patch adds dt-binding documentation for A64 DE2 display pipeline.
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
[Icenowy: Refactor and also cover TCON1]
Signed-off-by: Icenowy Zheng <[email protected]>
---
Changes for v4:
- none
Changes for v3.1:
- added mixer0 and TCON0
Changes for v3:
- collect Rob r-w-b tag
Changes for v2:
- Add fallback compatible for tcon1
- Add separate compatible for mixer1
.../devicetree/bindings/display/sunxi/sun4i-drm.txt | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index f8773ecb7525..7b79c5e3dffc 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -151,6 +151,8 @@ Required properties:
* allwinner,sun8i-v3s-tcon
* allwinner,sun9i-a80-tcon-lcd
* allwinner,sun9i-a80-tcon-tv
+ * "allwinner,sun50i-a64-tcon-lcd", "allwinner,sun8i-a83t-tcon-lcd"
+ * "allwinner,sun50i-a64-tcon-tv", "allwinner,sun8i-a83t-tcon-tv"
- reg: base address and size of memory-mapped region
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the TCON.
@@ -370,6 +372,8 @@ Required properties:
* allwinner,sun8i-a83t-de2-mixer-1
* allwinner,sun8i-h3-de2-mixer-0
* allwinner,sun8i-v3s-de2-mixer
+ * allwinner,sun50i-a64-de2-mixer-0
+ * allwinner,sun50i-a64-de2-mixer-1
- reg: base address and size of the memory-mapped region.
- clocks: phandles to the clocks feeding the mixer
* bus: the mixer interface clock
@@ -403,6 +407,7 @@ Required properties:
* allwinner,sun8i-r40-display-engine
* allwinner,sun8i-v3s-display-engine
* allwinner,sun9i-a80-display-engine
+ * allwinner,sun50i-a64-display-engine
- allwinner,pipelines: list of phandle to the display engine
frontends (DE 1.0) or mixers (DE 2.0) available.
--
2.18.0
From: Jagan Teki <[email protected]>
Display Engine(DE2) in Allwinner A64 has two mixers and tcons.
The routing for mixer0 is through tcon0 and connected to
LVDS/RGB/MIPI-DSI controller.
The routing for mixer1 is through tcon1 and connected to HDMI.
Signed-off-by: Jagan Teki <[email protected]>
Signed-off-by: Icenowy Zheng <[email protected]>
---
Changes for v4, v3.1, v3, v2:
- none
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 8b0cd08034e0..fbd5a3d44d11 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -420,6 +420,7 @@ static const struct of_device_id sun4i_drv_of_table[] = {
{ .compatible = "allwinner,sun8i-h3-display-engine" },
{ .compatible = "allwinner,sun8i-v3s-display-engine" },
{ .compatible = "allwinner,sun9i-a80-display-engine" },
+ { .compatible = "allwinner,sun50i-a64-display-engine" },
{ }
};
MODULE_DEVICE_TABLE(of, sun4i_drv_of_table);
--
2.18.0
From: Jagan Teki <[email protected]>
Mixers in Allwinner have similar capabilities as others SoCs with DE2.
Add support for them.
Signed-off-by: Jagan Teki <[email protected]>
[Icenowy: Add mixer1]
Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Jernej Skrabec <[email protected]>
---
Changes for v4:
- none
Changes for v3.1:
- Add mixer0
Changes for v3:
- none
Changes for v2:
- New patch
drivers/gpu/drm/sun4i/sun8i_mixer.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index cb65b0ed53fd..091f6cf40353 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -553,6 +553,22 @@ static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {
.mod_rate = 150000000,
};
+static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = {
+ .ccsc = 0,
+ .mod_rate = 297000000,
+ .scaler_mask = 0xf,
+ .ui_num = 3,
+ .vi_num = 1,
+};
+
+static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = {
+ .ccsc = 1,
+ .mod_rate = 297000000,
+ .scaler_mask = 0x3,
+ .ui_num = 1,
+ .vi_num = 1,
+};
+
static const struct of_device_id sun8i_mixer_of_table[] = {
{
.compatible = "allwinner,sun8i-a83t-de2-mixer-0",
@@ -570,6 +586,14 @@ static const struct of_device_id sun8i_mixer_of_table[] = {
.compatible = "allwinner,sun8i-v3s-de2-mixer",
.data = &sun8i_v3s_mixer_cfg,
},
+ {
+ .compatible = "allwinner,sun50i-a64-de2-mixer-0",
+ .data = &sun50i_a64_mixer0_cfg,
+ },
+ {
+ .compatible = "allwinner,sun50i-a64-de2-mixer-1",
+ .data = &sun50i_a64_mixer1_cfg,
+ },
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_mixer_of_table);
--
2.18.0
From: Jagan Teki <[email protected]>
Allwinner A64 have a display pipeline with 2 mixers/TCONs, the first
TCON is connected to LCD and the second is to HDMI.
The HDMI controller/PHY pair is similar to the one on H3/H5.
Add all required device tree nodes of the display pipeline, including
the TCON0 LCD one and the TCON1 HDMI one.
Signed-off-by: Jagan Teki <[email protected]>
[Icenowy: refactor commit message and add 1st pipeline]
Signed-off-by: Icenowy Zheng <[email protected]>
---
Changes for v4:
- Misc fixes
- Dropped second PLL from HDMI PHY clock
Changes for v3.1:
- Refactor commit message to make it more clear.
- Added first pipeline (mixer0 -> tcon0)
Changes for v3:
- Squash all pipeline components in one patch
- Add status for mixer1 and tcon1
Changes for v2:
- Change compatibles and other based on previous patch changes
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 170 ++++++++++++++++++
1 file changed, 170 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index b73f9287c3f0..8c7bcae0b8ec 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -121,6 +121,13 @@
};
};
+ de: display-engine {
+ compatible = "allwinner,sun50i-a64-display-engine";
+ allwinner,pipelines = <&mixer0>,
+ <&mixer1>;
+ status = "disabled";
+ };
+
osc24M: osc24M_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -203,6 +210,52 @@
#clock-cells = <1>;
#reset-cells = <1>;
};
+
+ mixer0: mixer@100000 {
+ compatible = "allwinner,sun50i-a64-de2-mixer-0";
+ reg = <0x100000 0x100000>;
+ clocks = <&display_clocks CLK_BUS_MIXER0>,
+ <&display_clocks CLK_MIXER0>;
+ clock-names = "bus",
+ "mod";
+ resets = <&display_clocks RST_MIXER0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer0_out: port@1 {
+ reg = <1>;
+
+ mixer0_out_tcon0: endpoint {
+ remote-endpoint = <&tcon0_in_mixer0>;
+ };
+ };
+ };
+ };
+
+ mixer1: mixer@200000 {
+ compatible = "allwinner,sun50i-a64-de2-mixer-1";
+ reg = <0x200000 0x100000>;
+ clocks = <&display_clocks CLK_BUS_MIXER1>,
+ <&display_clocks CLK_MIXER1>;
+ clock-names = "bus",
+ "mod";
+ resets = <&display_clocks RST_MIXER1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer1_out: port@1 {
+ reg = <1>;
+
+ mixer1_out_tcon1: endpoint {
+ remote-endpoint = <&tcon1_in_mixer1>;
+ };
+ };
+ };
+ };
};
syscon: syscon@1c00000 {
@@ -237,6 +290,75 @@
#dma-cells = <1>;
};
+ tcon0: lcd-controller@1c0c000 {
+ compatible = "allwinner,sun50i-a64-tcon-lcd",
+ "allwinner,sun8i-a83t-tcon-lcd";
+ reg = <0x01c0c000 0x1000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
+ clock-names = "ahb", "tcon-ch0";
+ clock-output-names = "tcon-pixel-clock";
+ resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
+ reset-names = "lcd", "lvds";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon0_in_mixer0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mixer0_out_tcon0>;
+ };
+ };
+
+ tcon0_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+
+ tcon1: lcd-controller@1c0d000 {
+ compatible = "allwinner,sun50i-a64-tcon-tv",
+ "allwinner,sun8i-a83t-tcon-tv";
+ reg = <0x01c0d000 0x1000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
+ clock-names = "ahb", "tcon-ch1";
+ resets = <&ccu RST_BUS_TCON1>;
+ reset-names = "lcd";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon1_in: port@0 {
+ reg = <0>;
+
+ tcon1_in_mixer1: endpoint {
+ remote-endpoint = <&mixer1_out_tcon1>;
+ };
+ };
+
+ tcon1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon1_out_hdmi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&hdmi_in_tcon1>;
+ };
+ };
+ };
+ };
+
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun50i-a64-mmc";
reg = <0x01c0f000 0x1000>;
@@ -700,6 +826,50 @@
status = "disabled";
};
+ hdmi: hdmi@1ee0000 {
+ compatible = "allwinner,sun50i-a64-dw-hdmi",
+ "allwinner,sun8i-a83t-dw-hdmi";
+ reg = <0x01ee0000 0x10000>;
+ reg-io-width = <1>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
+ <&ccu CLK_HDMI>;
+ clock-names = "iahb", "isfr", "tmds";
+ resets = <&ccu RST_BUS_HDMI1>;
+ reset-names = "ctrl";
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi-phy";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port@0 {
+ reg = <0>;
+
+ hdmi_in_tcon1: endpoint {
+ remote-endpoint = <&tcon1_out_hdmi>;
+ };
+ };
+
+ hdmi_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ hdmi_phy: hdmi-phy@1ef0000 {
+ compatible = "allwinner,sun8i-h3-hdmi-phy";
+ reg = <0x01ef0000 0x10000>;
+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
+ <&ccu 7>;
+ clock-names = "bus", "mod", "pll-0";
+ resets = <&ccu RST_BUS_HDMI0>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ };
+
rtc: rtc@1f00000 {
compatible = "allwinner,sun6i-a31-rtc";
reg = <0x01f00000 0x54>;
--
2.18.0
From: Jernej Skrabec <[email protected]>
Some boards have HDMI VCC pin connected to voltage regulator which may
not be turned on by default.
Add support for such boards by adding voltage regulator handling code to
HDMI driver.
Signed-off-by: Jernej Skrabec <[email protected]>
[Icenowy: change supply name to "hvcc"]
Signed-off-by: Icenowy Zheng <[email protected]>
---
Changes in v4:
- Rename the supply name to "hvcc".
Changes in v3.1:
- New patch. (Replaced "drm: sun4i: add support for HVCC regulator
for DWC HDMI glue" by Icenowy.)
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 17 ++++++++++++++++-
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 2 ++
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
index 31875b636434..ed2983770e9c 100644
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
@@ -125,10 +125,22 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
return PTR_ERR(hdmi->clk_tmds);
}
+ hdmi->regulator = devm_regulator_get(dev, "hvcc");
+ if (IS_ERR(hdmi->regulator)) {
+ dev_err(dev, "Couldn't get regulator\n");
+ return PTR_ERR(hdmi->regulator);
+ }
+
+ ret = regulator_enable(hdmi->regulator);
+ if (ret) {
+ dev_err(dev, "Failed to enable regulator\n");
+ return ret;
+ }
+
ret = reset_control_deassert(hdmi->rst_ctrl);
if (ret) {
dev_err(dev, "Could not deassert ctrl reset control\n");
- return ret;
+ goto err_disable_regulator;
}
ret = clk_prepare_enable(hdmi->clk_tmds);
@@ -183,6 +195,8 @@ static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
clk_disable_unprepare(hdmi->clk_tmds);
err_assert_ctrl_reset:
reset_control_assert(hdmi->rst_ctrl);
+err_disable_regulator:
+ regulator_disable(hdmi->regulator);
return ret;
}
@@ -196,6 +210,7 @@ static void sun8i_dw_hdmi_unbind(struct device *dev, struct device *master,
sun8i_hdmi_phy_remove(hdmi);
clk_disable_unprepare(hdmi->clk_tmds);
reset_control_assert(hdmi->rst_ctrl);
+ regulator_disable(hdmi->regulator);
}
static const struct component_ops sun8i_dw_hdmi_ops = {
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
index aadbe0a10b0c..7fdc1ecd2892 100644
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
@@ -10,6 +10,7 @@
#include <drm/drm_encoder.h>
#include <linux/clk.h>
#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#define SUN8I_HDMI_PHY_DBG_CTRL_REG 0x0000
@@ -176,6 +177,7 @@ struct sun8i_dw_hdmi {
struct drm_encoder encoder;
struct sun8i_hdmi_phy *phy;
struct dw_hdmi_plat_data plat_data;
+ struct regulator *regulator;
struct reset_control *rst_ctrl;
};
--
2.18.0
From: Jagan Teki <[email protected]>
Allwinner A64 HDMI PHY clock has PLL_VIDEO0 as a parent.
Include the macro on dt-bindings so-that the same can be used
while defining CCU clock phandles.
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Icenowy Zheng <[email protected]>
---
Changes for v4:
- Dropped PLL_VIDEO1
Changes for v3.1:
- none
Changes for v3:
- collect Rob r-w-b tag
Changes for v2:
- new patch
drivers/clk/sunxi-ng/ccu-sun50i-a64.h | 4 +++-
include/dt-bindings/clock/sun50i-a64-ccu.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h
index 061b6fbb4f95..a83951cf0224 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.h
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.h
@@ -27,7 +27,9 @@
#define CLK_PLL_AUDIO_2X 4
#define CLK_PLL_AUDIO_4X 5
#define CLK_PLL_AUDIO_8X 6
-#define CLK_PLL_VIDEO0 7
+
+/* PLL_VIDEO0 exported for HDMI PHY */
+
#define CLK_PLL_VIDEO0_2X 8
#define CLK_PLL_VE 9
#define CLK_PLL_DDR0 10
diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h
index d66432c6e675..a8ac4cfcdcbc 100644
--- a/include/dt-bindings/clock/sun50i-a64-ccu.h
+++ b/include/dt-bindings/clock/sun50i-a64-ccu.h
@@ -43,6 +43,7 @@
#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_
#define _DT_BINDINGS_CLK_SUN50I_A64_H_
+#define CLK_PLL_VIDEO0 7
#define CLK_PLL_PERIPH0 11
#define CLK_BUS_MIPI_DSI 28
--
2.18.0
Allwiner SoCs with DesignWare HDMI controller all come with a "HVCC"
pin, which is the VCC of HDMI part.
Add a supply property to specify HVCC's regulator in the device tree.
Signed-off-by: Icenowy Zheng <[email protected]>
---
Changes in v4:
- Rename the supply name to "hvcc".
Changes in v3.1:
- New patch.
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index fdb8fb29033f..0bbb5d47f228 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -97,6 +97,9 @@ Required properties:
first port should be the input endpoint. The second should be the
output, usually to an HDMI connector.
+Optional properties:
+ - hvcc-supply: the VCC power supply of the controller
+
DWC HDMI PHY
------------
--
2.18.0
From: Jagan Teki <[email protected]>
Enable all necessary device tree nodes and add connector node to device
trees for all supported A64 boards with HDMI.
Signed-off-by: Jagan Teki <[email protected]>
[Icenowy: squash all board patches altogether and change supply name]
Signed-off-by: Icenowy Zheng <[email protected]>
---
Changes in v4:
- Rebase some device trees.
Changes in v3,1:
- Squash all enablement patches altogether.
- Change supply name to match DT binding & driver change.
Changes for v3:
- Enable all pipeline components
Changes for v2:
- none
.../dts/allwinner/sun50i-a64-bananapi-m64.dts | 34 +++++++++++++++++++
.../dts/allwinner/sun50i-a64-nanopi-a64.dts | 34 +++++++++++++++++++
.../dts/allwinner/sun50i-a64-olinuxino.dts | 34 +++++++++++++++++++
.../dts/allwinner/sun50i-a64-orangepi-win.dts | 34 +++++++++++++++++++
.../boot/dts/allwinner/sun50i-a64-pine64.dts | 34 +++++++++++++++++++
.../allwinner/sun50i-a64-sopine-baseboard.dts | 34 +++++++++++++++++++
6 files changed, 204 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index 094cfed13df9..cdd03d1145f3 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
@@ -60,6 +60,17 @@
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
@@ -86,6 +97,10 @@
};
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
@@ -103,6 +118,17 @@
status = "okay";
};
+&hdmi {
+ hvcc-supply = <®_dldo1>;
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
index 0ee915d8eb24..22cd5223ede3 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
@@ -59,6 +59,17 @@
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
@@ -76,6 +87,10 @@
};
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
@@ -93,6 +108,17 @@
status = "okay";
};
+&hdmi {
+ hvcc-supply = <®_dldo1>;
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
/* i2c1 connected with gpio headers like pine64, bananapi */
&i2c1 {
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
index a1c2f06ed474..3c18a2f27538 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
@@ -59,6 +59,17 @@
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
reg_usb1_vbus: usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1-vbus";
@@ -76,6 +87,10 @@
};
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
@@ -93,6 +108,17 @@
status = "okay";
};
+&hdmi {
+ hvcc-supply = <®_dldo1>;
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
index c879aa8d8d1b..6109074e3613 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
@@ -64,6 +64,17 @@
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
@@ -101,6 +112,10 @@
};
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
@@ -118,6 +133,17 @@
status = "okay";
};
+&hdmi {
+ hvcc-supply = <®_dldo1>;
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index 1b9b92e541d2..93a7455347a7 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -62,6 +62,21 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+};
+
+&de {
+ status = "okay";
};
&ehci0 {
@@ -82,6 +97,17 @@
};
+&hdmi {
+ hvcc-supply = <®_dldo1>;
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
index c21f2331add6..c09c131ae077 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
@@ -61,6 +61,17 @@
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
reg_vcc1v8: vcc1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8";
@@ -69,6 +80,10 @@
};
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
@@ -86,6 +101,17 @@
status = "okay";
};
+&hdmi {
+ hvcc-supply = <®_dldo1>;
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&mdio {
ext_rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
--
2.18.0
From: Jagan Teki <[email protected]>
The HDMI controller on Allwinner A64 is similar on the one on
H3/H5/A83T (although the PHY is different with A83T).
Add A64 compatible and append A83T compatible as fallback.
Signed-off-by: Jagan Teki <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
[Icenowy: refactor commit log]
Signed-off-by: Icenowy Zheng <[email protected]>
---
Changes for v4:
- none
Changes for v3.1:
- Refactor commit log to make it more clear.
Changes for v3:
- collect Rob r-w-b tag
Changes for v2:
- Add fallback compatible
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 7b79c5e3dffc..fdb8fb29033f 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -78,6 +78,7 @@ Required properties:
- compatible: value must be one of:
* "allwinner,sun8i-a83t-dw-hdmi"
+ * "allwinner,sun50i-a64-dw-hdmi", "allwinner,sun8i-a83t-dw-hdmi"
- reg: base address and size of memory-mapped region
- reg-io-width: See dw_hdmi.txt. Shall be 1.
- interrupts: HDMI interrupt number
--
2.18.0
On Tue, Sep 04, 2018 at 12:40:43PM +0800, Icenowy Zheng wrote:
> From: Jagan Teki <[email protected]>
>
> According to documentation and experience with other similar SoCs, video
> PLLs don't work stable if their output frequency is set below 192 MHz.
>
> Because of that, set minimal rate to both A64 video PLLs to 192 MHz.
>
> Signed-off-by: Jagan Teki <[email protected]>
> Signed-off-by: Icenowy Zheng <[email protected]>
> Reviewed-by: Jernej Skrabec <[email protected]>
Applied, thanks
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
On Tue, Sep 04, 2018 at 12:40:44PM +0800, Icenowy Zheng wrote:
> Video PLLs on A64 can be set to higher rate that it is actually
> supported by HW.
>
> Limit maximum rate to 1008 MHz. This is the maximum allowed rate by BSP
> clock driver. Interestengly, user manual specifies maximum frequency to
> be 600 MHz. Historically, this data was wrong in some user manuals for
> other SoCs, so more faith is put in BSP clock driver.
>
> Signed-off-by: Icenowy Zheng <[email protected]>
Applied, thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
On Tue, Sep 04, 2018 at 12:40:45PM +0800, Icenowy Zheng wrote:
> From: Jagan Teki <[email protected]>
>
> Allwinner A64 has a DE2 display pipeline. The TCONs are similar to the
> ones in A83T, but the mixers are new (similar to the later R40 SoC).
>
> This patch adds dt-binding documentation for A64 DE2 display pipeline.
>
> Signed-off-by: Jagan Teki <[email protected]>
> Reviewed-by: Rob Herring <[email protected]>
> [Icenowy: Refactor and also cover TCON1]
> Signed-off-by: Icenowy Zheng <[email protected]>
Applied, thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
On Tue, Sep 04, 2018 at 12:40:46PM +0800, Icenowy Zheng wrote:
> From: Jagan Teki <[email protected]>
>
> Mixers in Allwinner have similar capabilities as others SoCs with DE2.
>
> Add support for them.
>
> Signed-off-by: Jagan Teki <[email protected]>
> [Icenowy: Add mixer1]
> Signed-off-by: Icenowy Zheng <[email protected]>
> Reviewed-by: Jernej Skrabec <[email protected]>
Applied, thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
On Tue, Sep 04, 2018 at 12:40:48PM +0800, Icenowy Zheng wrote:
> From: Jagan Teki <[email protected]>
>
> The HDMI controller on Allwinner A64 is similar on the one on
> H3/H5/A83T (although the PHY is different with A83T).
>
> Add A64 compatible and append A83T compatible as fallback.
>
> Signed-off-by: Jagan Teki <[email protected]>
> Reviewed-by: Rob Herring <[email protected]>
> [Icenowy: refactor commit log]
> Signed-off-by: Icenowy Zheng <[email protected]>
Applied, thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
On Tue, Sep 04, 2018 at 12:40:47PM +0800, Icenowy Zheng wrote:
> From: Jagan Teki <[email protected]>
>
> Display Engine(DE2) in Allwinner A64 has two mixers and tcons.
>
> The routing for mixer0 is through tcon0 and connected to
> LVDS/RGB/MIPI-DSI controller.
>
> The routing for mixer1 is through tcon1 and connected to HDMI.
>
> Signed-off-by: Jagan Teki <[email protected]>
> Signed-off-by: Icenowy Zheng <[email protected]>
Applied, thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
On Tue, Sep 04, 2018 at 12:40:49PM +0800, Icenowy Zheng wrote:
> From: Jagan Teki <[email protected]>
>
> Allwinner A64 HDMI PHY clock has PLL_VIDEO0 as a parent.
>
> Include the macro on dt-bindings so-that the same can be used
> while defining CCU clock phandles.
>
> Signed-off-by: Jagan Teki <[email protected]>
> Reviewed-by: Rob Herring <[email protected]>
> Signed-off-by: Icenowy Zheng <[email protected]>
Applied, thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
On Tue, Sep 04, 2018 at 12:40:51PM +0800, Icenowy Zheng wrote:
> Allwiner SoCs with DesignWare HDMI controller all come with a "HVCC"
> pin, which is the VCC of HDMI part.
>
> Add a supply property to specify HVCC's regulator in the device tree.
>
> Signed-off-by: Icenowy Zheng <[email protected]>
Applied, thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
On Tue, Sep 04, 2018 at 12:40:52PM +0800, Icenowy Zheng wrote:
> From: Jernej Skrabec <[email protected]>
>
> Some boards have HDMI VCC pin connected to voltage regulator which may
> not be turned on by default.
>
> Add support for such boards by adding voltage regulator handling code to
> HDMI driver.
>
> Signed-off-by: Jernej Skrabec <[email protected]>
> [Icenowy: change supply name to "hvcc"]
> Signed-off-by: Icenowy Zheng <[email protected]>
Applied, thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
On Tue, Sep 4, 2018 at 10:10 AM, Icenowy Zheng <[email protected]> wrote:
> From: Jagan Teki <[email protected]>
>
> Enable all necessary device tree nodes and add connector node to device
> trees for all supported A64 boards with HDMI.
>
> Signed-off-by: Jagan Teki <[email protected]>
> [Icenowy: squash all board patches altogether and change supply name]
> Signed-off-by: Icenowy Zheng <[email protected]>
> ---
> Changes in v4:
> - Rebase some device trees.
> Changes in v3,1:
> - Squash all enablement patches altogether.
> - Change supply name to match DT binding & driver change.
> Changes for v3:
> - Enable all pipeline components
> Changes for v2:
> - none
>
> .../dts/allwinner/sun50i-a64-bananapi-m64.dts | 34 +++++++++++++++++++
> .../dts/allwinner/sun50i-a64-nanopi-a64.dts | 34 +++++++++++++++++++
> .../dts/allwinner/sun50i-a64-olinuxino.dts | 34 +++++++++++++++++++
> .../dts/allwinner/sun50i-a64-orangepi-win.dts | 34 +++++++++++++++++++
> .../boot/dts/allwinner/sun50i-a64-pine64.dts | 34 +++++++++++++++++++
> .../allwinner/sun50i-a64-sopine-baseboard.dts | 34 +++++++++++++++++++
> 6 files changed, 204 insertions(+)
Tested-by: Jagan Teki <[email protected]> # BPI-M64, OPI-Win,
A64-Olinuxino, NPI-A64
Pine64 boards look unable by saying
[drm] Cannot find any crtc or sizes
May be someone can confirm, it.
On Tue, Sep 04, 2018 at 12:40:50PM +0800, Icenowy Zheng wrote:
> + hdmi_phy: hdmi-phy@1ef0000 {
> + compatible = "allwinner,sun8i-h3-hdmi-phy";
> + reg = <0x01ef0000 0x10000>;
> + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
> + <&ccu 7>;
> + clock-names = "bus", "mod", "pll-0";
> + resets = <&ccu RST_BUS_HDMI0>;
> + reset-names = "phy";
> + #phy-cells = <0>;
> + };
This needs to use the bindings we have for that phy.
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
On Wed, Sep 05, 2018 at 12:56:03PM +0530, Jagan Teki wrote:
> On Tue, Sep 4, 2018 at 10:10 AM, Icenowy Zheng <[email protected]> wrote:
> > From: Jagan Teki <[email protected]>
> >
> > Enable all necessary device tree nodes and add connector node to device
> > trees for all supported A64 boards with HDMI.
> >
> > Signed-off-by: Jagan Teki <[email protected]>
> > [Icenowy: squash all board patches altogether and change supply name]
> > Signed-off-by: Icenowy Zheng <[email protected]>
> > ---
> > Changes in v4:
> > - Rebase some device trees.
> > Changes in v3,1:
> > - Squash all enablement patches altogether.
> > - Change supply name to match DT binding & driver change.
> > Changes for v3:
> > - Enable all pipeline components
> > Changes for v2:
> > - none
> >
> > .../dts/allwinner/sun50i-a64-bananapi-m64.dts | 34 +++++++++++++++++++
> > .../dts/allwinner/sun50i-a64-nanopi-a64.dts | 34 +++++++++++++++++++
> > .../dts/allwinner/sun50i-a64-olinuxino.dts | 34 +++++++++++++++++++
> > .../dts/allwinner/sun50i-a64-orangepi-win.dts | 34 +++++++++++++++++++
> > .../boot/dts/allwinner/sun50i-a64-pine64.dts | 34 +++++++++++++++++++
> > .../allwinner/sun50i-a64-sopine-baseboard.dts | 34 +++++++++++++++++++
> > 6 files changed, 204 insertions(+)
>
> Tested-by: Jagan Teki <[email protected]> # BPI-M64, OPI-Win,
> A64-Olinuxino, NPI-A64
>
> Pine64 boards look unable by saying
> [drm] Cannot find any crtc or sizes
>
> May be someone can confirm, it.
Then we should drop the pine64 additions until someone figures it out,
as it has been already discussed.
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
On Wed, Sep 5, 2018 at 1:21 PM, Maxime Ripard <[email protected]> wrote:
> On Wed, Sep 05, 2018 at 12:56:03PM +0530, Jagan Teki wrote:
>> On Tue, Sep 4, 2018 at 10:10 AM, Icenowy Zheng <[email protected]> wrote:
>> > From: Jagan Teki <[email protected]>
>> >
>> > Enable all necessary device tree nodes and add connector node to device
>> > trees for all supported A64 boards with HDMI.
>> >
>> > Signed-off-by: Jagan Teki <[email protected]>
>> > [Icenowy: squash all board patches altogether and change supply name]
>> > Signed-off-by: Icenowy Zheng <[email protected]>
>> > ---
>> > Changes in v4:
>> > - Rebase some device trees.
>> > Changes in v3,1:
>> > - Squash all enablement patches altogether.
>> > - Change supply name to match DT binding & driver change.
>> > Changes for v3:
>> > - Enable all pipeline components
>> > Changes for v2:
>> > - none
>> >
>> > .../dts/allwinner/sun50i-a64-bananapi-m64.dts | 34 +++++++++++++++++++
>> > .../dts/allwinner/sun50i-a64-nanopi-a64.dts | 34 +++++++++++++++++++
>> > .../dts/allwinner/sun50i-a64-olinuxino.dts | 34 +++++++++++++++++++
>> > .../dts/allwinner/sun50i-a64-orangepi-win.dts | 34 +++++++++++++++++++
>> > .../boot/dts/allwinner/sun50i-a64-pine64.dts | 34 +++++++++++++++++++
>> > .../allwinner/sun50i-a64-sopine-baseboard.dts | 34 +++++++++++++++++++
>> > 6 files changed, 204 insertions(+)
>>
>> Tested-by: Jagan Teki <[email protected]> # BPI-M64, OPI-Win,
>> A64-Olinuxino, NPI-A64
>>
>> Pine64 boards look unable by saying
>> [drm] Cannot find any crtc or sizes
>>
>> May be someone can confirm, it.
>
> Then we should drop the pine64 additions until someone figures it out,
> as it has been already discussed.
That is fine, but If anyone have pine64 can confirm this.
Hi,
On 09/05/2018 10:16 AM, Maxime Ripard wrote:
> On Tue, Sep 04, 2018 at 12:40:44PM +0800, Icenowy Zheng wrote:
>> Video PLLs on A64 can be set to higher rate that it is actually
>> supported by HW.
>>
>> Limit maximum rate to 1008 MHz. This is the maximum allowed rate by BSP
>> clock driver. Interestengly, user manual specifies maximum frequency to
>> be 600 MHz. Historically, this data was wrong in some user manuals for
>> other SoCs, so more faith is put in BSP clock driver.
>>
>> Signed-off-by: Icenowy Zheng <[email protected]>
> Applied, thanks!
> Maxime
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
what source tree this patch is supposed to apply for ?
I can't find? the SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX declaration
in 4.19
Thank you
Sergey
I can test it tonight.
On Wed, Sep 5, 2018 at 12:57 AM, Jagan Teki <[email protected]> wrote:
> On Wed, Sep 5, 2018 at 1:21 PM, Maxime Ripard <[email protected]> wrote:
>> On Wed, Sep 05, 2018 at 12:56:03PM +0530, Jagan Teki wrote:
>>> On Tue, Sep 4, 2018 at 10:10 AM, Icenowy Zheng <[email protected]> wrote:
>>> > From: Jagan Teki <[email protected]>
>>> >
>>> > Enable all necessary device tree nodes and add connector node to device
>>> > trees for all supported A64 boards with HDMI.
>>> >
>>> > Signed-off-by: Jagan Teki <[email protected]>
>>> > [Icenowy: squash all board patches altogether and change supply name]
>>> > Signed-off-by: Icenowy Zheng <[email protected]>
>>> > ---
>>> > Changes in v4:
>>> > - Rebase some device trees.
>>> > Changes in v3,1:
>>> > - Squash all enablement patches altogether.
>>> > - Change supply name to match DT binding & driver change.
>>> > Changes for v3:
>>> > - Enable all pipeline components
>>> > Changes for v2:
>>> > - none
>>> >
>>> > .../dts/allwinner/sun50i-a64-bananapi-m64.dts | 34 +++++++++++++++++++
>>> > .../dts/allwinner/sun50i-a64-nanopi-a64.dts | 34 +++++++++++++++++++
>>> > .../dts/allwinner/sun50i-a64-olinuxino.dts | 34 +++++++++++++++++++
>>> > .../dts/allwinner/sun50i-a64-orangepi-win.dts | 34 +++++++++++++++++++
>>> > .../boot/dts/allwinner/sun50i-a64-pine64.dts | 34 +++++++++++++++++++
>>> > .../allwinner/sun50i-a64-sopine-baseboard.dts | 34 +++++++++++++++++++
>>> > 6 files changed, 204 insertions(+)
>>>
>>> Tested-by: Jagan Teki <[email protected]> # BPI-M64, OPI-Win,
>>> A64-Olinuxino, NPI-A64
>>>
>>> Pine64 boards look unable by saying
>>> [drm] Cannot find any crtc or sizes
>>>
>>> May be someone can confirm, it.
>>
>> Then we should drop the pine64 additions until someone figures it out,
>> as it has been already discussed.
>
> That is fine, but If anyone have pine64 can confirm this.
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Wed, Sep 5, 2018 at 3:53 PM, Vasily Khoruzhick <[email protected]> wrote:
> I can test it tonight.
It works fine for me on pine64-lts with HDMI monitor:
[ 1.969772] sun4i-drm display-engine: bound 1100000.mixer (ops
sun8i_mixer_ops)
[ 1.979302] sun4i-drm display-engine: bound 1200000.mixer (ops
sun8i_mixer_ops)
[ 1.979738] sun4i-drm display-engine: No panel or bridge found...
RGB output disabled
[ 1.979755] sun4i-drm display-engine: bound 1c0c000.lcd-controller
(ops sun4i_tcon_ops)
[ 1.979935] sun4i-drm display-engine: bound 1c0d000.lcd-controller
(ops sun4i_tcon_ops)
[ 1.980017] sun4i-drm display-engine: failed to bind 1ee0000.hdmi
(ops sun8i_dw_hdmi_ops): -517
[ 1.980306] sun4i-drm display-engine: Couldn't bind all pipelines components
[ 1.980446] sun4i-drm display-engine: master bind failed: -517
[ 4.230997] sun4i-drm display-engine: bound 1100000.mixer (ops
sun8i_mixer_ops)
[ 4.247886] sun4i-drm display-engine: bound 1200000.mixer (ops
sun8i_mixer_ops)
[ 4.255639] sun4i-drm display-engine: No panel or bridge found...
RGB output disabled
[ 4.263482] sun4i-drm display-engine: bound 1c0c000.lcd-controller
(ops sun4i_tcon_ops)
[ 4.283255] sun4i-drm display-engine: bound 1c0d000.lcd-controller
(ops sun4i_tcon_ops)
[ 4.322055] sun4i-drm display-engine: bound 1ee0000.hdmi (ops
sun8i_dw_hdmi_ops)
[ 4.342115] fb: switching to sun4i-drm-fb from simple
[ 5.001434] sun4i-drm display-engine: fb0: DRM emulated frame buffer device
[ 5.008933] [drm] Initialized sun4i-drm 1.0.0 20150629 for
display-engine on minor 0
I tested non-applied patches from this series on top of
git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git
sunxi/for-next
Tested-by: Vasily Khoruzhick <[email protected]>
>
> On Wed, Sep 5, 2018 at 12:57 AM, Jagan Teki <[email protected]> wrote:
>> On Wed, Sep 5, 2018 at 1:21 PM, Maxime Ripard <[email protected]> wrote:
>>> On Wed, Sep 05, 2018 at 12:56:03PM +0530, Jagan Teki wrote:
>>>> On Tue, Sep 4, 2018 at 10:10 AM, Icenowy Zheng <[email protected]> wrote:
>>>> > From: Jagan Teki <[email protected]>
>>>> >
>>>> > Enable all necessary device tree nodes and add connector node to device
>>>> > trees for all supported A64 boards with HDMI.
>>>> >
>>>> > Signed-off-by: Jagan Teki <[email protected]>
>>>> > [Icenowy: squash all board patches altogether and change supply name]
>>>> > Signed-off-by: Icenowy Zheng <[email protected]>
>>>> > ---
>>>> > Changes in v4:
>>>> > - Rebase some device trees.
>>>> > Changes in v3,1:
>>>> > - Squash all enablement patches altogether.
>>>> > - Change supply name to match DT binding & driver change.
>>>> > Changes for v3:
>>>> > - Enable all pipeline components
>>>> > Changes for v2:
>>>> > - none
>>>> >
>>>> > .../dts/allwinner/sun50i-a64-bananapi-m64.dts | 34 +++++++++++++++++++
>>>> > .../dts/allwinner/sun50i-a64-nanopi-a64.dts | 34 +++++++++++++++++++
>>>> > .../dts/allwinner/sun50i-a64-olinuxino.dts | 34 +++++++++++++++++++
>>>> > .../dts/allwinner/sun50i-a64-orangepi-win.dts | 34 +++++++++++++++++++
>>>> > .../boot/dts/allwinner/sun50i-a64-pine64.dts | 34 +++++++++++++++++++
>>>> > .../allwinner/sun50i-a64-sopine-baseboard.dts | 34 +++++++++++++++++++
>>>> > 6 files changed, 204 insertions(+)
>>>>
>>>> Tested-by: Jagan Teki <[email protected]> # BPI-M64, OPI-Win,
>>>> A64-Olinuxino, NPI-A64
>>>>
>>>> Pine64 boards look unable by saying
>>>> [drm] Cannot find any crtc or sizes
>>>>
>>>> May be someone can confirm, it.
>>>
>>> Then we should drop the pine64 additions until someone figures it out,
>>> as it has been already discussed.
>>
>> That is fine, but If anyone have pine64 can confirm this.
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> [email protected]
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Hi Jagan,
Dne sreda, 05. september 2018 ob 09:57:54 CEST je Jagan Teki napisal(a):
> On Wed, Sep 5, 2018 at 1:21 PM, Maxime Ripard <[email protected]>
wrote:
> > On Wed, Sep 05, 2018 at 12:56:03PM +0530, Jagan Teki wrote:
> >> On Tue, Sep 4, 2018 at 10:10 AM, Icenowy Zheng <[email protected]> wrote:
> >> > From: Jagan Teki <[email protected]>
> >> >
> >> > Enable all necessary device tree nodes and add connector node to device
> >> > trees for all supported A64 boards with HDMI.
> >> >
> >> > Signed-off-by: Jagan Teki <[email protected]>
> >> > [Icenowy: squash all board patches altogether and change supply name]
> >> > Signed-off-by: Icenowy Zheng <[email protected]>
> >> > ---
> >> > Changes in v4:
> >> > - Rebase some device trees.
> >> > Changes in v3,1:
> >> > - Squash all enablement patches altogether.
> >> > - Change supply name to match DT binding & driver change.
> >> > Changes for v3:
> >> > - Enable all pipeline components
> >> > Changes for v2:
> >> > - none
> >> >
> >> > .../dts/allwinner/sun50i-a64-bananapi-m64.dts | 34 +++++++++++++++++++
> >> > .../dts/allwinner/sun50i-a64-nanopi-a64.dts | 34 +++++++++++++++++++
> >> > .../dts/allwinner/sun50i-a64-olinuxino.dts | 34 +++++++++++++++++++
> >> > .../dts/allwinner/sun50i-a64-orangepi-win.dts | 34 +++++++++++++++++++
> >> > .../boot/dts/allwinner/sun50i-a64-pine64.dts | 34 +++++++++++++++++++
> >> > .../allwinner/sun50i-a64-sopine-baseboard.dts | 34 +++++++++++++++++++
> >> > 6 files changed, 204 insertions(+)
> >>
> >> Tested-by: Jagan Teki <[email protected]> # BPI-M64, OPI-Win,
> >> A64-Olinuxino, NPI-A64
> >>
> >> Pine64 boards look unable by saying
> >> [drm] Cannot find any crtc or sizes
> >>
> >> May be someone can confirm, it.
> >
> > Then we should drop the pine64 additions until someone figures it out,
> > as it has been already discussed.
>
> That is fine, but If anyone have pine64 can confirm this.
What is your monitor default resolution and more importantly, what is it's
pixel clock?
Pine64 has U-Boot support for DE2/HDMI, which has some pixel clock issues
which can influence Linux, unfortunately. At the time, there wasn't enough
knowledge to do it properly. I plan to update it after A64 DE2/HDMI support is
finished in kernel.
Meanwhile, can you test if it works for you either with disabled DE2/HDMI in
U-Boot or if you apply this patch to Linux:
https://github.com/jernejsk/linux-1/commit/
019121f953229ca2d624ac39300289a24e5389a1
Best regards,
Jernej
On Tue, Sep 4, 2018 at 10:10 AM, Icenowy Zheng <[email protected]> wrote:
> From: Jagan Teki <[email protected]>
>
> Allwinner A64 have a display pipeline with 2 mixers/TCONs, the first
> TCON is connected to LCD and the second is to HDMI.
>
> The HDMI controller/PHY pair is similar to the one on H3/H5.
>
> Add all required device tree nodes of the display pipeline, including
> the TCON0 LCD one and the TCON1 HDMI one.
>
> Signed-off-by: Jagan Teki <[email protected]>
> [Icenowy: refactor commit message and add 1st pipeline]
> Signed-off-by: Icenowy Zheng <[email protected]>
> ---
> Changes for v4:
> - Misc fixes
> - Dropped second PLL from HDMI PHY clock
Why? it was there in previous versions.
于 2018年9月6日 GMT+08:00 下午2:18:13, Jagan Teki <[email protected]> 写到:
>On Tue, Sep 4, 2018 at 10:10 AM, Icenowy Zheng <[email protected]> wrote:
>> From: Jagan Teki <[email protected]>
>>
>> Allwinner A64 have a display pipeline with 2 mixers/TCONs, the first
>> TCON is connected to LCD and the second is to HDMI.
>>
>> The HDMI controller/PHY pair is similar to the one on H3/H5.
>>
>> Add all required device tree nodes of the display pipeline, including
>> the TCON0 LCD one and the TCON1 HDMI one.
>>
>> Signed-off-by: Jagan Teki <[email protected]>
>> [Icenowy: refactor commit message and add 1st pipeline]
>> Signed-off-by: Icenowy Zheng <[email protected]>
>> ---
>> Changes for v4:
>> - Misc fixes
>> - Dropped second PLL from HDMI PHY clock
>
>Why? it was there in previous versions.
Based on my experiments, the bit has no effect on A64, and the parent
is always PLL-VIDEO0.
On Wed, Sep 5, 2018 at 1:20 PM, Maxime Ripard <[email protected]> wrote:
> On Tue, Sep 04, 2018 at 12:40:50PM +0800, Icenowy Zheng wrote:
>> + hdmi_phy: hdmi-phy@1ef0000 {
>> + compatible = "allwinner,sun8i-h3-hdmi-phy";
>> + reg = <0x01ef0000 0x10000>;
>> + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
>> + <&ccu 7>;
>> + clock-names = "bus", "mod", "pll-0";
>> + resets = <&ccu RST_BUS_HDMI0>;
>> + reset-names = "phy";
>> + #phy-cells = <0>;
>> + };
>
> This needs to use the bindings we have for that phy.
You mean allwinner,sun50i-a64-hdmi-phy ?
On Fri, Sep 07, 2018 at 09:43:29AM +0530, Jagan Teki wrote:
> On Wed, Sep 5, 2018 at 1:20 PM, Maxime Ripard <[email protected]> wrote:
> > On Tue, Sep 04, 2018 at 12:40:50PM +0800, Icenowy Zheng wrote:
> >> + hdmi_phy: hdmi-phy@1ef0000 {
> >> + compatible = "allwinner,sun8i-h3-hdmi-phy";
> >> + reg = <0x01ef0000 0x10000>;
> >> + clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
> >> + <&ccu 7>;
> >> + clock-names = "bus", "mod", "pll-0";
> >> + resets = <&ccu RST_BUS_HDMI0>;
> >> + reset-names = "phy";
> >> + #phy-cells = <0>;
> >> + };
> >
> > This needs to use the bindings we have for that phy.
>
> You mean allwinner,sun50i-a64-hdmi-phy ?
Yes
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com