From: Qi Hu <[email protected]>
The `vcsr` do not use anymore. Remove this member from `loongarch_fpu`.
Signed-off-by: Qi Hu <[email protected]>
---
arch/loongarch/include/asm/fpregdef.h | 1 -
arch/loongarch/include/asm/processor.h | 2 --
arch/loongarch/kernel/asm-offsets.c | 1 -
arch/loongarch/kernel/fpu.S | 10 ----------
4 files changed, 14 deletions(-)
diff --git a/arch/loongarch/include/asm/fpregdef.h b/arch/loongarch/include/asm/fpregdef.h
index adb16e4b43b0..b6be527831dd 100644
--- a/arch/loongarch/include/asm/fpregdef.h
+++ b/arch/loongarch/include/asm/fpregdef.h
@@ -48,6 +48,5 @@
#define fcsr1 $r1
#define fcsr2 $r2
#define fcsr3 $r3
-#define vcsr16 $r16
#endif /* _ASM_FPREGDEF_H */
diff --git a/arch/loongarch/include/asm/processor.h b/arch/loongarch/include/asm/processor.h
index 1d63c934b289..57ec45aa078e 100644
--- a/arch/loongarch/include/asm/processor.h
+++ b/arch/loongarch/include/asm/processor.h
@@ -80,7 +80,6 @@ BUILD_FPR_ACCESS(64)
struct loongarch_fpu {
unsigned int fcsr;
- unsigned int vcsr;
uint64_t fcc; /* 8x8 */
union fpureg fpr[NUM_FPU_REGS];
};
@@ -161,7 +160,6 @@ struct thread_struct {
*/ \
.fpu = { \
.fcsr = 0, \
- .vcsr = 0, \
.fcc = 0, \
.fpr = {{{0,},},}, \
}, \
diff --git a/arch/loongarch/kernel/asm-offsets.c b/arch/loongarch/kernel/asm-offsets.c
index bfb65eb2844f..20cd9e16a95a 100644
--- a/arch/loongarch/kernel/asm-offsets.c
+++ b/arch/loongarch/kernel/asm-offsets.c
@@ -166,7 +166,6 @@ void output_thread_fpu_defines(void)
OFFSET(THREAD_FCSR, loongarch_fpu, fcsr);
OFFSET(THREAD_FCC, loongarch_fpu, fcc);
- OFFSET(THREAD_VCSR, loongarch_fpu, vcsr);
BLANK();
}
diff --git a/arch/loongarch/kernel/fpu.S b/arch/loongarch/kernel/fpu.S
index 75c6ce0682a2..a631a7137667 100644
--- a/arch/loongarch/kernel/fpu.S
+++ b/arch/loongarch/kernel/fpu.S
@@ -146,16 +146,6 @@
movgr2fcsr fcsr0, \tmp0
.endm
- .macro sc_save_vcsr base, tmp0
- movfcsr2gr \tmp0, vcsr16
- EX st.w \tmp0, \base, 0
- .endm
-
- .macro sc_restore_vcsr base, tmp0
- EX ld.w \tmp0, \base, 0
- movgr2fcsr vcsr16, \tmp0
- .endm
-
/*
* Save a thread's fp context.
*/
--
2.36.1
On 2022/7/4 14:14, huqi wrote:
> From: Qi Hu <[email protected]>
>
> The `vcsr` do not use anymore. Remove this member from `loongarch_fpu`.
"The VCSR is not used any more."
>
> Signed-off-by: Qi Hu <[email protected]>
> ---
> arch/loongarch/include/asm/fpregdef.h | 1 -
> arch/loongarch/include/asm/processor.h | 2 --
> arch/loongarch/kernel/asm-offsets.c | 1 -
> arch/loongarch/kernel/fpu.S | 10 ----------
> 4 files changed, 14 deletions(-)
>
> diff --git a/arch/loongarch/include/asm/fpregdef.h b/arch/loongarch/include/asm/fpregdef.h
> index adb16e4b43b0..b6be527831dd 100644
> --- a/arch/loongarch/include/asm/fpregdef.h
> +++ b/arch/loongarch/include/asm/fpregdef.h
> @@ -48,6 +48,5 @@
> #define fcsr1 $r1
> #define fcsr2 $r2
> #define fcsr3 $r3
> -#define vcsr16 $r16
>
> #endif /* _ASM_FPREGDEF_H */
> diff --git a/arch/loongarch/include/asm/processor.h b/arch/loongarch/include/asm/processor.h
> index 1d63c934b289..57ec45aa078e 100644
> --- a/arch/loongarch/include/asm/processor.h
> +++ b/arch/loongarch/include/asm/processor.h
> @@ -80,7 +80,6 @@ BUILD_FPR_ACCESS(64)
>
> struct loongarch_fpu {
> unsigned int fcsr;
> - unsigned int vcsr;
> uint64_t fcc; /* 8x8 */
> union fpureg fpr[NUM_FPU_REGS];
> };
> @@ -161,7 +160,6 @@ struct thread_struct {
> */ \
> .fpu = { \
> .fcsr = 0, \
> - .vcsr = 0, \
> .fcc = 0, \
> .fpr = {{{0,},},}, \
> }, \
> diff --git a/arch/loongarch/kernel/asm-offsets.c b/arch/loongarch/kernel/asm-offsets.c
> index bfb65eb2844f..20cd9e16a95a 100644
> --- a/arch/loongarch/kernel/asm-offsets.c
> +++ b/arch/loongarch/kernel/asm-offsets.c
> @@ -166,7 +166,6 @@ void output_thread_fpu_defines(void)
>
> OFFSET(THREAD_FCSR, loongarch_fpu, fcsr);
> OFFSET(THREAD_FCC, loongarch_fpu, fcc);
> - OFFSET(THREAD_VCSR, loongarch_fpu, vcsr);
> BLANK();
> }
>
> diff --git a/arch/loongarch/kernel/fpu.S b/arch/loongarch/kernel/fpu.S
> index 75c6ce0682a2..a631a7137667 100644
> --- a/arch/loongarch/kernel/fpu.S
> +++ b/arch/loongarch/kernel/fpu.S
> @@ -146,16 +146,6 @@
> movgr2fcsr fcsr0, \tmp0
> .endm
>
> - .macro sc_save_vcsr base, tmp0
> - movfcsr2gr \tmp0, vcsr16
> - EX st.w \tmp0, \base, 0
> - .endm
> -
> - .macro sc_restore_vcsr base, tmp0
> - EX ld.w \tmp0, \base, 0
> - movgr2fcsr vcsr16, \tmp0
> - .endm
> -
> /*
> * Save a thread's fp context.
> */
The original code was written with future LSX/LASX support in mind; the
code is dead currently, but expected to get utilized Soon (TM).
So, I'd like to confirm if future LoongArch models would *not* feature
LSX/LASX in its current form, and that the Loongson Corporation is not
going to upstream LSX/LASX support, given you are apparently a Loongson
employee with the first-hand information? We'd like to avoid code churn
in general, so if the LSX/LASX support is to be eventually mainlined,
removing them now would only lead to them being introduced later.
On 2022/7/4 15:28, WANG Xuerui wrote:
> On 2022/7/4 14:14, huqi wrote:
>> From: Qi Hu <[email protected]>
>>
>> The `vcsr` do not use anymore. Remove this member from `loongarch_fpu`.
> "The VCSR is not used any more."
Thanks, this is incorrect to use `use`.
>>
>> Signed-off-by: Qi Hu <[email protected]>
>> ---
>> arch/loongarch/include/asm/fpregdef.h | 1 -
>> arch/loongarch/include/asm/processor.h | 2 --
>> arch/loongarch/kernel/asm-offsets.c | 1 -
>> arch/loongarch/kernel/fpu.S | 10 ----------
>> 4 files changed, 14 deletions(-)
>>
>> diff --git a/arch/loongarch/include/asm/fpregdef.h
>> b/arch/loongarch/include/asm/fpregdef.h
>> index adb16e4b43b0..b6be527831dd 100644
>> --- a/arch/loongarch/include/asm/fpregdef.h
>> +++ b/arch/loongarch/include/asm/fpregdef.h
>> @@ -48,6 +48,5 @@
>> #define fcsr1 $r1
>> #define fcsr2 $r2
>> #define fcsr3 $r3
>> -#define vcsr16 $r16
>> #endif /* _ASM_FPREGDEF_H */
>> diff --git a/arch/loongarch/include/asm/processor.h
>> b/arch/loongarch/include/asm/processor.h
>> index 1d63c934b289..57ec45aa078e 100644
>> --- a/arch/loongarch/include/asm/processor.h
>> +++ b/arch/loongarch/include/asm/processor.h
>> @@ -80,7 +80,6 @@ BUILD_FPR_ACCESS(64)
>> struct loongarch_fpu {
>> unsigned int fcsr;
>> - unsigned int vcsr;
>> uint64_t fcc; /* 8x8 */
>> union fpureg fpr[NUM_FPU_REGS];
>> };
>> @@ -161,7 +160,6 @@ struct thread_struct {
>> */ \
>> .fpu = { \
>> .fcsr = 0, \
>> - .vcsr = 0, \
>> .fcc = 0, \
>> .fpr = {{{0,},},}, \
>> }, \
>> diff --git a/arch/loongarch/kernel/asm-offsets.c
>> b/arch/loongarch/kernel/asm-offsets.c
>> index bfb65eb2844f..20cd9e16a95a 100644
>> --- a/arch/loongarch/kernel/asm-offsets.c
>> +++ b/arch/loongarch/kernel/asm-offsets.c
>> @@ -166,7 +166,6 @@ void output_thread_fpu_defines(void)
>> OFFSET(THREAD_FCSR, loongarch_fpu, fcsr);
>> OFFSET(THREAD_FCC, loongarch_fpu, fcc);
>> - OFFSET(THREAD_VCSR, loongarch_fpu, vcsr);
>> BLANK();
>> }
>> diff --git a/arch/loongarch/kernel/fpu.S b/arch/loongarch/kernel/fpu.S
>> index 75c6ce0682a2..a631a7137667 100644
>> --- a/arch/loongarch/kernel/fpu.S
>> +++ b/arch/loongarch/kernel/fpu.S
>> @@ -146,16 +146,6 @@
>> movgr2fcsr fcsr0, \tmp0
>> .endm
>> - .macro sc_save_vcsr base, tmp0
>> - movfcsr2gr \tmp0, vcsr16
>> - EX st.w \tmp0, \base, 0
>> - .endm
>> -
>> - .macro sc_restore_vcsr base, tmp0
>> - EX ld.w \tmp0, \base, 0
>> - movgr2fcsr vcsr16, \tmp0
>> - .endm
>> -
>> /*
>> * Save a thread's fp context.
>> */
>
> The original code was written with future LSX/LASX support in mind;
> the code is dead currently, but expected to get utilized Soon (TM).
>
> So, I'd like to confirm if future LoongArch models would *not* feature
> LSX/LASX in its current form, and that the Loongson Corporation is not
> going to upstream LSX/LASX support, given you are apparently a
> Loongson employee with the first-hand information? We'd like to avoid
> code churn in general, so if the LSX/LASX support is to be eventually
> mainlined, removing them now would only lead to them being introduced
> later.
`vcsr` is removed because it has been removed in hardware. What's more,
it will not be used to support LSX/LASX in the future.
On Mon, 2022-07-04 at 17:27 +0800, huqi wrote:
>
> > The original code was written with future LSX/LASX support in mind;
> > the code is dead currently, but expected to get utilized Soon (TM).
> >
> > So, I'd like to confirm if future LoongArch models would *not* feature
> > LSX/LASX in its current form, and that the Loongson Corporation is not
> > going to upstream LSX/LASX support, given you are apparently a
> > Loongson employee with the first-hand information? We'd like to avoid
> > code churn in general, so if the LSX/LASX support is to be eventually
> > mainlined, removing them now would only lead to them being introduced
> > later.
>
> `vcsr` is removed because it has been removed in hardware. What's more,
> it will not be used to support LSX/LASX in the future.
It would be better to add this information into the commit message. Is
it already removed in 3A5000? On my machine "movfcsr2gr $a0, $r16"
produces SIGILL (but maybe it's because LSX is not enabled via the EUEN
register).
--
Xi Ruoyao <[email protected]>
School of Aerospace Science and Technology, Xidian University
On 2022/7/4 17:58, Xi Ruoyao wrote:
> On Mon, 2022-07-04 at 17:27 +0800, huqi wrote:
>
>>> The original code was written with future LSX/LASX support in mind;
>>> the code is dead currently, but expected to get utilized Soon (TM).
>>>
>>> So, I'd like to confirm if future LoongArch models would *not* feature
>>> LSX/LASX in its current form, and that the Loongson Corporation is not
>>> going to upstream LSX/LASX support, given you are apparently a
>>> Loongson employee with the first-hand information? We'd like to avoid
>>> code churn in general, so if the LSX/LASX support is to be eventually
>>> mainlined, removing them now would only lead to them being introduced
>>> later.
>> `vcsr` is removed because it has been removed in hardware. What's more,
>> it will not be used to support LSX/LASX in the future.
> It would be better to add this information into the commit message. Is
> it already removed in 3A5000? On my machine "movfcsr2gr $a0, $r16"
> produces SIGILL (but maybe it's because LSX is not enabled via the EUEN
> register).
Yes, adding this information to the commit message will be more
reasonable. I will do it later.
It is true that 3A5000 has removed this register. $r16 to $r31 are
reserved for LSX/LASX. So "movfcsr2gr $a0, $r16" will raise SXD/ASXD if
LSX/LASX is not enabled, and kernel will raise SIGILL.