Hi,
This adds more of the DVFS stuff at the SoC .dtsi level. This includes
the CCI and GPU.
Changes since v1:
- Dropped opp-level property from CPU and CCI OPP tables
- Used "opp-supported-hw = <0xff>" for GPU base OPPs to denote "all
variations"
Please have a look and merge for this cycle if possible.
On another note, I'm still cleaning up the MT6366 regulator's binding.
We shouldn't upstream the boards until the PMIC is ready.
ChenYu
Chen-Yu Tsai (4):
arm64: dts: mediatek: mt8186: Add CCI node and CCI OPP table
arm64: dts: mediatek: mt8186: Wire up CPU frequency/voltage scaling
arm64: dts: mediatek: mt8186: Add GPU speed bin NVMEM cells
arm64: dts: mediatek: mt8186: Wire up GPU voltage/frequency scaling
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 490 ++++++++++++++++++++++-
1 file changed, 489 insertions(+), 1 deletion(-)
--
2.41.0.162.gfafddb0af9-goog
On the MT8186, the chip is binned for different GPU voltages at the
highest OPPs. The binning value is stored in the efuse.
Add the NVMEM cell, and tie it to the GPU.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index e2becf2fe79f..3762a70ccafb 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -1519,6 +1519,11 @@ efuse: efuse@11cb0000 {
reg = <0 0x11cb0000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+
+ gpu_speedbin: gpu-speed-bin@59c {
+ reg = <0x59c 0x4>;
+ bits = <0 3>;
+ };
};
mipi_tx0: dsi-phy@11cc0000 {
@@ -1551,6 +1556,8 @@ gpu: gpu@13040000 {
<&spm MT8186_POWER_DOMAIN_MFG3>;
power-domain-names = "core0", "core1";
#cooling-cells = <2>;
+ nvmem-cells = <&gpu_speedbin>;
+ nvmem-cell-names = "speed-bin";
status = "disabled";
};
--
2.41.0.162.gfafddb0af9-goog
On 09/06/2023 09:29, Chen-Yu Tsai wrote:
> Hi,
>
> This adds more of the DVFS stuff at the SoC .dtsi level. This includes
> the CCI and GPU.
>
> Changes since v1:
> - Dropped opp-level property from CPU and CCI OPP tables
> - Used "opp-supported-hw = <0xff>" for GPU base OPPs to denote "all
> variations"
>
> Please have a look and merge for this cycle if possible.
>
> On another note, I'm still cleaning up the MT6366 regulator's binding.
> We shouldn't upstream the boards until the PMIC is ready.
>
> ChenYu
>
> Chen-Yu Tsai (4):
> arm64: dts: mediatek: mt8186: Add CCI node and CCI OPP table
> arm64: dts: mediatek: mt8186: Wire up CPU frequency/voltage scaling
> arm64: dts: mediatek: mt8186: Add GPU speed bin NVMEM cells
> arm64: dts: mediatek: mt8186: Wire up GPU voltage/frequency scaling
>
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 490 ++++++++++++++++++++++-
> 1 file changed, 489 insertions(+), 1 deletion(-)
>
Series applied,
thanks!