This patchset adds the support for PDC interrupt controller found
on sm8150 SoCs from Qualcomm.
Here we add the device-tree bindings, pinctrl driver support
and the dts support for the same.
Cc: Bjorn Andersson <[email protected]>
Cc: Vinod Koul <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Marc Zyngier <[email protected]>
Cc: Linus Walleij <[email protected]>
Bhupesh Sharma (4):
dt-bindings: qcom,pdc: Add compatible for SM8150
pinctrl: qcom: sm8150: Specify PDC map
arm64: dts: qcom: sm8150: Add pdc interrupt controller node
arm64: dts: qcom: sm8150: Add PDC as the interrupt parent for tlmm
.../interrupt-controller/qcom,pdc.txt | 1 +
arch/arm64/boot/dts/qcom/sm8150.dtsi | 11 ++++++++++
drivers/pinctrl/qcom/pinctrl-sm8150.c | 21 +++++++++++++++++++
3 files changed, 33 insertions(+)
--
2.33.1
Add the compatible string for SM8150 SoC from Qualcomm.
Cc: Bjorn Andersson <[email protected]>
Cc: Vinod Koul <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Marc Zyngier <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
---
.../devicetree/bindings/interrupt-controller/qcom,pdc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
index 98d89e53013d..bd3539644d3f 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
@@ -21,6 +21,7 @@ Properties:
- "qcom,sc7180-pdc": For SC7180
- "qcom,sc7280-pdc": For SC7280
- "qcom,sdm845-pdc": For SDM845
+ - "qcom,sdm8150-pdc": For SM8150
- "qcom,sdm8250-pdc": For SM8250
- "qcom,sdm8350-pdc": For SM8350
--
2.33.1
Specify the PDC mapping for SM8150, so that gpio interrupts are
propertly mapped to the wakeup IRQs of the PDC.
Cc: Bjorn Andersson <[email protected]>
Cc: Linus Walleij <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
---
drivers/pinctrl/qcom/pinctrl-sm8150.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8150.c b/drivers/pinctrl/qcom/pinctrl-sm8150.c
index 7359bae68c69..499dd05c3e3d 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8150.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8150.c
@@ -1500,6 +1500,25 @@ static const struct msm_pingroup sm8150_groups[] = {
[178] = SDC_QDSD_PINGROUP(sdc2_data, 0xB2000, 9, 0),
};
+static const struct msm_gpio_wakeirq_map sm8150_pdc_map[] = {
+ { 3, 31 }, { 5, 32 }, { 8, 33 }, { 9, 34 }, { 10, 100 },
+ { 12, 104 }, { 24, 37 }, { 26, 38 }, { 27, 41 }, { 28, 42 },
+ { 30, 39 }, { 36, 43 }, { 37, 44 }, { 38, 30 }, { 39, 118 },
+ { 39, 125 }, { 41, 47 }, { 42, 48 }, { 46, 50 }, { 47, 49 },
+ { 48, 51 }, { 49, 53 }, { 50, 52 }, { 51, 116 }, { 51, 123 },
+ { 53, 54 }, { 54, 55 }, { 55, 56 }, { 56, 57 }, { 58, 58 },
+ { 60, 60 }, { 61, 61 }, { 68, 62 }, { 70, 63 }, { 76, 71 },
+ { 77, 66 }, { 81, 64 }, { 83, 65 }, { 86, 67 }, { 87, 84 },
+ { 88, 117 }, { 88, 124 }, { 90, 69 }, { 91, 70 }, { 93, 75 },
+ { 95, 72 }, { 96, 73 }, { 97, 74 }, { 101, 40 }, { 103, 77 },
+ { 104, 78 }, { 108, 79 }, { 112, 80 }, { 113, 81 }, { 114, 82 },
+ { 117, 85 }, { 118, 101 }, { 119, 87 }, { 120, 88 }, { 121, 89 },
+ { 122, 90 }, { 123, 91 }, { 124, 92 }, { 125, 93 }, { 129, 94 },
+ { 132, 105 }, { 133, 83 }, { 134, 36 }, { 136, 97 }, { 142, 103 },
+ { 144, 115 }, { 144, 122 }, { 147, 102 }, { 150, 107 },
+ { 152, 108 }, { 153, 109 }
+};
+
static const struct msm_pinctrl_soc_data sm8150_pinctrl = {
.pins = sm8150_pins,
.npins = ARRAY_SIZE(sm8150_pins),
@@ -1510,6 +1529,8 @@ static const struct msm_pinctrl_soc_data sm8150_pinctrl = {
.ngpios = 176,
.tiles = sm8150_tiles,
.ntiles = ARRAY_SIZE(sm8150_tiles),
+ .wakeirq_map = sm8150_pdc_map,
+ .nwakeirq_map = ARRAY_SIZE(sm8150_pdc_map),
};
static int sm8150_pinctrl_probe(struct platform_device *pdev)
--
2.33.1
Several wakeup gpios supported by the Top Level Mode Multiplexer (TLMM)
block on sm8150 can be used as interrupt sources and these interrupts
are routed to the PDC interrupt controller.
So, specify PDC as the interrupt parent for the TLMM block.
Cc: Bjorn Andersson <[email protected]>
Cc: Vinod Koul <[email protected]>
Cc: Rob Herring <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index cc4dc11b2585..aa7e949a2bea 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -1937,6 +1937,7 @@ tlmm: pinctrl@3100000 {
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+ wakeup-parent = <&pdc>;
qup_i2c0_default: qup-i2c0-default {
mux {
--
2.33.1
Add pdc interrupt controller for sm8150.
Cc: Bjorn Andersson <[email protected]>
Cc: Vinod Koul <[email protected]>
Cc: Rob Herring <[email protected]>
Signed-off-by: Bhupesh Sharma <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 6012322a5984..cc4dc11b2585 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -1626,6 +1626,16 @@ system-cache-controller@9200000 {
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,sm8150-pdc", "qcom,pdc";
+ reg = <0 0x0b220000 0 0x400>, <0 0x17c000f0 0 0x60>;
+ qcom,pdc-ranges = <0 480 94>, <94 609 31>,
+ <125 63 1>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
--
2.33.1
Hi,
On 1/20/2022 2:01 AM, Bhupesh Sharma wrote:
> Add pdc interrupt controller for sm8150.
>
> Cc: Bjorn Andersson <[email protected]>
> Cc: Vinod Koul <[email protected]>
> Cc: Rob Herring <[email protected]>
> Signed-off-by: Bhupesh Sharma <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index 6012322a5984..cc4dc11b2585 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -1626,6 +1626,16 @@ system-cache-controller@9200000 {
> interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> + pdc: interrupt-controller@b220000 {
> + compatible = "qcom,sm8150-pdc", "qcom,pdc";
> + reg = <0 0x0b220000 0 0x400>, <0 0x17c000f0 0 0x60>;
<0x17c000f0 0x64>;
Remove the second reg, its not used in the driver and also not
documented yet.
Thanks,
Maulik
> + qcom,pdc-ranges = <0 480 94>, <94 609 31>,
> + <125 63 1>;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&intc>;
> + interrupt-controller;
> + };
> +
> ufs_mem_hc: ufshc@1d84000 {
> compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
> "jedec,ufs-2.0";
Hi,
On 1/20/2022 2:01 AM, Bhupesh Sharma wrote:
> Specify the PDC mapping for SM8150, so that gpio interrupts are
> propertly mapped to the wakeup IRQs of the PDC.
s/propertly/properly
>
> Cc: Bjorn Andersson <[email protected]>
> Cc: Linus Walleij <[email protected]>
> Signed-off-by: Bhupesh Sharma <[email protected]>
> ---
> drivers/pinctrl/qcom/pinctrl-sm8150.c | 21 +++++++++++++++++++++
> 1 file changed, 21 insertions(+)
>
> diff --git a/drivers/pinctrl/qcom/pinctrl-sm8150.c b/drivers/pinctrl/qcom/pinctrl-sm8150.c
> index 7359bae68c69..499dd05c3e3d 100644
> --- a/drivers/pinctrl/qcom/pinctrl-sm8150.c
> +++ b/drivers/pinctrl/qcom/pinctrl-sm8150.c
> @@ -1500,6 +1500,25 @@ static const struct msm_pingroup sm8150_groups[] = {
> [178] = SDC_QDSD_PINGROUP(sdc2_data, 0xB2000, 9, 0),
> };
>
> +static const struct msm_gpio_wakeirq_map sm8150_pdc_map[] = {
> + { 3, 31 }, { 5, 32 }, { 8, 33 }, { 9, 34 }, { 10, 100 },
> + { 12, 104 }, { 24, 37 }, { 26, 38 }, { 27, 41 }, { 28, 42 },
> + { 30, 39 }, { 36, 43 }, { 37, 44 }, { 38, 30 }, { 39, 118 },
> + { 39, 125 },
GPIO 39 is duplicated. 39 is used with 118 PDC interrupt in downstream.
so { 39, 125 } can be removed.
> { 41, 47 }, { 42, 48 }, { 46, 50 }, { 47, 49 },
> + { 48, 51 }, { 49, 53 }, { 50, 52 }, { 51, 116 }, { 51, 123 },
GPIO 51 is duplicated. 51 is used with 116 PDC interrupt in downstream
so { 51, 123 } can be removed
> + { 53, 54 }, { 54, 55 }, { 55, 56 }, { 56, 57 }, { 58, 58 },
> + { 60, 60 }, { 61, 61 }, { 68, 62 }, { 70, 63 }, { 76, 71 },
> + { 77, 66 }, { 81, 64 }, { 83, 65 }, { 86, 67 }, { 87, 84 },
> + { 88, 117 }, { 88, 124 }, { 90, 69 }, { 91, 70 }, { 93, 75 },
> + { 95, 72 }, { 96, 73 }, { 97, 74 }, { 101, 40 }, { 103, 77 },
> + { 104, 78 }, { 108, 79 }, { 112, 80 }, { 113, 81 }, { 114, 82 },
> + { 117, 85 }, { 118, 101 }, { 119, 87 }, { 120, 88 }, { 121, 89 },
> + { 122, 90 }, { 123, 91 }, { 124, 92 }, { 125, 93 }, { 129, 94 },
> + { 132, 105 }, { 133, 83 }, { 134, 36 }, { 136, 97 }, { 142, 103 },
> + { 144, 115 }, { 144, 122 }, { 147, 102 }, { 150, 107 },
> + { 152, 108 }, { 153, 109 }
> +};
> +
> static const struct msm_pinctrl_soc_data sm8150_pinctrl = {
> .pins = sm8150_pins,
> .npins = ARRAY_SIZE(sm8150_pins),
> @@ -1510,6 +1529,8 @@ static const struct msm_pinctrl_soc_data sm8150_pinctrl = {
> .ngpios = 176,
> .tiles = sm8150_tiles,
> .ntiles = ARRAY_SIZE(sm8150_tiles),
> + .wakeirq_map = sm8150_pdc_map,
> + .nwakeirq_map = ARRAY_SIZE(sm8150_pdc_map),
On SM8150 need to set .wakeirq_dual_edge_errata = true, similar to sc7180.
Thanks,
Maulik
On Thu, 20 Jan 2022 02:01:30 +0530, Bhupesh Sharma wrote:
> Add the compatible string for SM8150 SoC from Qualcomm.
>
> Cc: Bjorn Andersson <[email protected]>
> Cc: Vinod Koul <[email protected]>
> Cc: Rob Herring <[email protected]>
> Cc: Marc Zyngier <[email protected]>
> Signed-off-by: Bhupesh Sharma <[email protected]>
> ---
> .../devicetree/bindings/interrupt-controller/qcom,pdc.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <[email protected]>
Hi,
Thanks for the review and sorry for the late reply.
On Thu, 20 Jan 2022 at 16:24, Maulik Shah <[email protected]> wrote:
>
> Hi,
>
> On 1/20/2022 2:01 AM, Bhupesh Sharma wrote:
> > Specify the PDC mapping for SM8150, so that gpio interrupts are
> > propertly mapped to the wakeup IRQs of the PDC.
>
> s/propertly/properly
Ok.
> > Cc: Bjorn Andersson <[email protected]>
> > Cc: Linus Walleij <[email protected]>
> > Signed-off-by: Bhupesh Sharma <[email protected]>
> > ---
> > drivers/pinctrl/qcom/pinctrl-sm8150.c | 21 +++++++++++++++++++++
> > 1 file changed, 21 insertions(+)
> >
> > diff --git a/drivers/pinctrl/qcom/pinctrl-sm8150.c b/drivers/pinctrl/qcom/pinctrl-sm8150.c
> > index 7359bae68c69..499dd05c3e3d 100644
> > --- a/drivers/pinctrl/qcom/pinctrl-sm8150.c
> > +++ b/drivers/pinctrl/qcom/pinctrl-sm8150.c
> > @@ -1500,6 +1500,25 @@ static const struct msm_pingroup sm8150_groups[] = {
> > [178] = SDC_QDSD_PINGROUP(sdc2_data, 0xB2000, 9, 0),
> > };
> >
> > +static const struct msm_gpio_wakeirq_map sm8150_pdc_map[] = {
> > + { 3, 31 }, { 5, 32 }, { 8, 33 }, { 9, 34 }, { 10, 100 },
> > + { 12, 104 }, { 24, 37 }, { 26, 38 }, { 27, 41 }, { 28, 42 },
> > + { 30, 39 }, { 36, 43 }, { 37, 44 }, { 38, 30 }, { 39, 118 },
> > + { 39, 125 },
> GPIO 39 is duplicated. 39 is used with 118 PDC interrupt in downstream.
> so { 39, 125 } can be removed.
> > { 41, 47 }, { 42, 48 }, { 46, 50 }, { 47, 49 },
> > + { 48, 51 }, { 49, 53 }, { 50, 52 }, { 51, 116 }, { 51, 123 },
> GPIO 51 is duplicated. 51 is used with 116 PDC interrupt in downstream
> so { 51, 123 } can be removed
> > + { 53, 54 }, { 54, 55 }, { 55, 56 }, { 56, 57 }, { 58, 58 },
> > + { 60, 60 }, { 61, 61 }, { 68, 62 }, { 70, 63 }, { 76, 71 },
> > + { 77, 66 }, { 81, 64 }, { 83, 65 }, { 86, 67 }, { 87, 84 },
> > + { 88, 117 }, { 88, 124 }, { 90, 69 }, { 91, 70 }, { 93, 75 },
> > + { 95, 72 }, { 96, 73 }, { 97, 74 }, { 101, 40 }, { 103, 77 },
> > + { 104, 78 }, { 108, 79 }, { 112, 80 }, { 113, 81 }, { 114, 82 },
> > + { 117, 85 }, { 118, 101 }, { 119, 87 }, { 120, 88 }, { 121, 89 },
> > + { 122, 90 }, { 123, 91 }, { 124, 92 }, { 125, 93 }, { 129, 94 },
> > + { 132, 105 }, { 133, 83 }, { 134, 36 }, { 136, 97 }, { 142, 103 },
> > + { 144, 115 }, { 144, 122 }, { 147, 102 }, { 150, 107 },
> > + { 152, 108 }, { 153, 109 }
> > +};
> > +
> > static const struct msm_pinctrl_soc_data sm8150_pinctrl = {
> > .pins = sm8150_pins,
> > .npins = ARRAY_SIZE(sm8150_pins),
> > @@ -1510,6 +1529,8 @@ static const struct msm_pinctrl_soc_data sm8150_pinctrl = {
> > .ngpios = 176,
> > .tiles = sm8150_tiles,
> > .ntiles = ARRAY_SIZE(sm8150_tiles),
> > + .wakeirq_map = sm8150_pdc_map,
> > + .nwakeirq_map = ARRAY_SIZE(sm8150_pdc_map),
>
> On SM8150 need to set .wakeirq_dual_edge_errata = true, similar to sc7180.
Sure, I will fix this in v2.
Regards,
Bhupesh
Hi,
On Thu, 20 Jan 2022 at 16:24, Maulik Shah <[email protected]> wrote:
>
> Hi,
>
> On 1/20/2022 2:01 AM, Bhupesh Sharma wrote:
> > Add pdc interrupt controller for sm8150.
> >
> > Cc: Bjorn Andersson <[email protected]>
> > Cc: Vinod Koul <[email protected]>
> > Cc: Rob Herring <[email protected]>
> > Signed-off-by: Bhupesh Sharma <[email protected]>
> > ---
> > arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > index 6012322a5984..cc4dc11b2585 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > @@ -1626,6 +1626,16 @@ system-cache-controller@9200000 {
> > interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
> > };
> >
> > + pdc: interrupt-controller@b220000 {
> > + compatible = "qcom,sm8150-pdc", "qcom,pdc";
> > + reg = <0 0x0b220000 0 0x400>, <0 0x17c000f0 0 0x60>;
>
> <0x17c000f0 0x64>;
>
> Remove the second reg, its not used in the driver and also not
> documented yet.
Will do in v2.
Thanks,
Bhupesh
> > + qcom,pdc-ranges = <0 480 94>, <94 609 31>,
> > + <125 63 1>;
> > + #interrupt-cells = <2>;
> > + interrupt-parent = <&intc>;
> > + interrupt-controller;
> > + };
> > +
> > ufs_mem_hc: ufshc@1d84000 {
> > compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
> > "jedec,ufs-2.0";