LinuxLists.cc - [PATCH 00/12] riscv: Allwinner D1 platform support

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Subject: [PATCH 01/12] MAINTAINERS: Match the sun20i family of Allwinner SoCs

Allwinner sunxi SoCs with a RISC-V CPU use the sun20i designator. Match
that pattern in addition to the designators for 32 and 64-bit ARM SoCs.

Signed-off-by: Samuel Holland <[email protected]>
---

MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 8a5012ba6ff9..59bcaa405a6f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1800,7 +1800,7 @@ F: drivers/pinctrl/sunxi/
F: drivers/soc/sunxi/
N: allwinner
N: sun[x456789]i
-N: sun50i
+N: sun[25]0i

ARM/Amlogic Meson SoC CLOCK FRAMEWORK
M: Neil Armstrong <[email protected]>
--
2.35.1

2022-08-15 05:10:45

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Subject: [PATCH 03/12] dt-bindings: vendor-prefixes: Add Allwinner D1 board vendors

Some boards using the Allwinner D1 SoC are made by vendors not
previously documented.

Clockwork Tech LLC (https://www.clockworkpi.com/) manufactures the
ClockworkPi and DevTerm boards.

Beijing Widora Technology Co., Ltd. (https://mangopi.cc/) manufactures
the MangoPi family of boards.

Signed-off-by: Samuel Holland <[email protected]>
---

Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++
1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 2f0151e9f6be..52d076ab6c48 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -258,6 +258,8 @@ patternProperties:
description: Cirrus Logic, Inc.
"^cisco,.*":
description: Cisco Systems, Inc.
+ "^clockwork,.*":
+ description: Clockwork Tech LLC
"^cloudengines,.*":
description: Cloud Engines, Inc.
"^cnm,.*":
@@ -1412,6 +1414,8 @@ patternProperties:
description: Shenzhen whwave Electronics, Inc.
"^wi2wi,.*":
description: Wi2Wi, Inc.
+ "^widora,.*":
+ description: Beijing Widora Technology Co., Ltd.
"^wiligear,.*":
description: Wiligear, Ltd.
"^willsemi,.*":
--
2.35.1

2022-08-15 05:11:15

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Subject: [PATCH 07/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree

"D1 Nezha" is Allwinner's first-party development board for the D1 SoC.
It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard audio,
HDMI, gigabit Ethernet, WiFi and Bluetooth, USB 2.0 host and OTG ports,
plus low-speed I/O from the SoC and a GPIO expander chip.

Most other D1 boards copied the Nezha's power tree, with the 1.8V rail
powered by the SoCs internal LDOA, analog domains powered by ALDO, and
the rest of the board powered by always-on fixed regulators. Some (but
not all) boards also copied the PWM CPU regulator. To avoid duplication,
factor out the out the regulator references that are common across all
known boards.

Signed-off-by: Samuel Holland <[email protected]>
---

arch/riscv/boot/dts/allwinner/Makefile | 1 +
.../sun20i-d1-common-regulators.dtsi | 51 ++++++
.../boot/dts/allwinner/sun20i-d1-nezha.dts | 171 ++++++++++++++++++
3 files changed, 223 insertions(+)
create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts

diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile
index f66554cd5c45..b0a15e8c8d82 100644
--- a/arch/riscv/boot/dts/allwinner/Makefile
+++ b/arch/riscv/boot/dts/allwinner/Makefile
@@ -1 +1,2 @@
# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
new file mode 100644
index 000000000000..143a3e710c3c
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
+
+/ {
+ reg_vcc: vcc {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_vcc_3v3: vcc-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&reg_vcc>;
+ };
+};
+
+&lradc {
+ vref-supply = <&reg_aldo>;
+};
+
+&pio {
+ vcc-pb-supply = <&reg_vcc_3v3>;
+ vcc-pc-supply = <&reg_vcc_3v3>;
+ vcc-pd-supply = <&reg_vcc_3v3>;
+ vcc-pe-supply = <&reg_vcc_3v3>;
+ vcc-pf-supply = <&reg_vcc_3v3>;
+ vcc-pg-supply = <&reg_vcc_3v3>;
+};
+
+&reg_aldo {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vdd33-supply = <&reg_vcc_3v3>;
+};
+
+&reg_hpldo {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ hpldoin-supply = <&reg_vcc_3v3>;
+};
+
+&reg_ldoa {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ ldo-in-supply = <&reg_vcc_3v3>;
+};
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
new file mode 100644
index 000000000000..df865ee15fcf
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "sun20i-d1.dtsi"
+#include "sun20i-d1-common-regulators.dtsi"
+
+/ {
+ model = "Allwinner D1 Nezha";
+ compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1";
+
+ aliases {
+ ethernet0 = &emac;
+ ethernet1 = &xr829;
+ mmc0 = &mmc0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_usbvbus: usbvbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usbvbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
+ enable-active-high;
+ vin-supply = <&reg_vcc>;
+ };
+
+ /*
+ * This regulator is PWM-controlled, but the PWM controller is not
+ * yet supported, so fix the regulator to its default voltage.
+ */
+ reg_vdd_cpu: vdd-cpu {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-cpu";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&reg_vcc>;
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_vdd_cpu>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-0 = <&rgmii_pe_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii-id";
+ phy-supply = <&reg_vcc_3v3>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-0 = <&i2c2_pb0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ pcf8574a: gpio@38 {
+ compatible = "nxp,pcf8574a";
+ reg = <0x38>;
+ interrupt-parent = <&pio>;
+ interrupts = <1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */
+ interrupt-controller;
+ gpio-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+};
+
+&lradc {
+ status = "okay";
+
+ button-160 {
+ label = "OK";
+ linux,code = <KEY_OK>;
+ channel = <0>;
+ voltage = <160000>;
+ };
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ disable-wp;
+ vmmc-supply = <&reg_vcc_3v3>;
+ vqmmc-supply = <&reg_vcc_3v3>;
+ pinctrl-0 = <&mmc0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&mmc1 {
+ bus-width = <4>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ non-removable;
+ vmmc-supply = <&reg_vcc_3v3>;
+ vqmmc-supply = <&reg_vcc_3v3>;
+ pinctrl-0 = <&mmc1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ xr829: wifi@1 {
+ reg = <1>;
+ };
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pb8_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart1 {
+ uart-has-rtscts;
+ pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /* XR829 bluetooth is connected here */
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
+ usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
+ usb0_vbus-supply = <&reg_usbvbus>;
+ usb1_vbus-supply = <&reg_vcc>;
+ status = "okay";
+};
--
2.35.1

2022-08-15 05:11:20

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Subject: [PATCH 08/12] riscv: dts: allwinner: Add Sipeed Lichee RV devicetrees

Sipeed manufactures a "Lichee RV" system-on-module, which provides a
minimal working system on its own, as well as a few carrier boards. The
"Dock" board provides audio, USB, and WiFi. The "86 Panel" additionally
provides 100M Ethernet and a built-in display panel.

The 86 Panel repurposes the USB ID and VBUS detection GPIOs for its RGB
panel interface, since the USB OTG port is inaccessible inside the case.

Co-developed-by: Jisheng Zhang <[email protected]>
Signed-off-by: Jisheng Zhang <[email protected]>
Signed-off-by: Samuel Holland <[email protected]>
---

arch/riscv/boot/dts/allwinner/Makefile | 4 +
.../sun20i-d1-lichee-rv-86-panel-480p.dts | 29 ++++++
.../sun20i-d1-lichee-rv-86-panel-720p.dts | 10 ++
.../sun20i-d1-lichee-rv-86-panel.dtsi | 92 +++++++++++++++++++
.../allwinner/sun20i-d1-lichee-rv-dock.dts | 74 +++++++++++++++
.../dts/allwinner/sun20i-d1-lichee-rv.dts | 84 +++++++++++++++++
6 files changed, 293 insertions(+)
create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts
create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts

diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile
index b0a15e8c8d82..300ada20c735 100644
--- a/arch/riscv/boot/dts/allwinner/Makefile
+++ b/arch/riscv/boot/dts/allwinner/Makefile
@@ -1,2 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-480p.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-dock.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
new file mode 100644
index 000000000000..4df8ffb71561
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Samuel Holland <[email protected]>
+
+#include "sun20i-d1-lichee-rv-86-panel.dtsi"
+
+/ {
+ model = "Sipeed Lichee RV 86 Panel (480p)";
+ compatible = "sipeed,lichee-rv-86-panel-480p", "sipeed,lichee-rv",
+ "allwinner,sun20i-d1";
+};
+
+&i2c2 {
+ pinctrl-0 = <&i2c2_pb0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ touchscreen@48 {
+ compatible = "focaltech,ft6236";
+ reg = <0x48>;
+ interrupt-parent = <&pio>;
+ interrupts = <6 14 IRQ_TYPE_LEVEL_LOW>; /* PG14 */
+ iovcc-supply = <&reg_vcc_3v3>;
+ reset-gpios = <&pio 6 15 GPIO_ACTIVE_LOW>; /* PG15 */
+ touchscreen-size-x = <480>;
+ touchscreen-size-y = <480>;
+ vcc-supply = <&reg_vcc_3v3>;
+ wakeup-source;
+ };
+};
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts
new file mode 100644
index 000000000000..1874fc05359f
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Samuel Holland <[email protected]>
+
+#include "sun20i-d1-lichee-rv-86-panel.dtsi"
+
+/ {
+ model = "Sipeed Lichee RV 86 Panel (720p)";
+ compatible = "sipeed,lichee-rv-86-panel-720p", "sipeed,lichee-rv",
+ "allwinner,sun20i-d1";
+};
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
new file mode 100644
index 000000000000..d89ed8047e80
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Samuel Holland <[email protected]>
+
+#include "sun20i-d1-lichee-rv.dts"
+
+/ {
+ aliases {
+ ethernet0 = &emac;
+ ethernet1 = &xr829;
+ };
+
+ /* PC1 is repurposed as BT_WAKE_AP */
+ /delete-node/ leds;
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&ccu CLK_FANOUT1>;
+ clock-names = "ext_clock";
+ reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
+ assigned-clocks = <&ccu CLK_FANOUT1>;
+ assigned-clock-rates = <32768>;
+ pinctrl-0 = <&clk_pg11_pin>;
+ pinctrl-names = "default";
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-0 = <&rmii_pe_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&ext_rmii_phy>;
+ phy-mode = "rmii";
+ phy-supply = <&reg_vcc_3v3>;
+ status = "okay";
+};
+
+&mdio {
+ ext_rmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */
+ };
+};
+
+&mmc1 {
+ bus-width = <4>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ non-removable;
+ vmmc-supply = <&reg_vcc_3v3>;
+ vqmmc-supply = <&reg_vcc_3v3>;
+ pinctrl-0 = <&mmc1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ xr829: wifi@1 {
+ reg = <1>;
+ };
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ clk_pg11_pin: clk-pg11-pin {
+ pins = "PG11";
+ function = "clk";
+ };
+};
+
+&uart1 {
+ uart-has-rtscts;
+ pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /* XR829 bluetooth is connected here */
+};
+
+&usb_otg {
+ status = "disabled";
+};
+
+&usbphy {
+ /* PD20 and PD21 are repurposed for the LCD panel */
+ /delete-property/ usb0_id_det-gpios;
+ /delete-property/ usb0_vbus_det-gpios;
+ usb1_vbus-supply = <&reg_vcc>;
+};
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
new file mode 100644
index 000000000000..ca36a5d75a7f
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Jisheng Zhang <[email protected]>
+// Copyright (C) 2022 Samuel Holland <[email protected]>
+
+#include <dt-bindings/input/input.h>
+
+#include "sun20i-d1-lichee-rv.dts"
+
+/ {
+ model = "Sipeed Lichee RV Dock";
+ compatible = "sipeed,lichee-rv-dock", "sipeed,lichee-rv",
+ "allwinner,sun20i-d1";
+
+ aliases {
+ ethernet1 = &rtl8723ds;
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&lradc {
+ status = "okay";
+
+ button-220 {
+ label = "OK";
+ linux,code = <KEY_OK>;
+ channel = <0>;
+ voltage = <220000>;
+ };
+};
+
+&mmc1 {
+ bus-width = <4>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ non-removable;
+ vmmc-supply = <&reg_vcc_3v3>;
+ vqmmc-supply = <&reg_vcc_3v3>;
+ pinctrl-0 = <&mmc1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ rtl8723ds: wifi@1 {
+ reg = <1>;
+ };
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&uart1 {
+ uart-has-rtscts;
+ pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ bluetooth {
+ compatible = "realtek,rtl8723ds-bt";
+ device-wake-gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG16 */
+ enable-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */
+ host-wake-gpios = <&pio 6 17 GPIO_ACTIVE_HIGH>; /* PG17 */
+ };
+};
+
+&usbphy {
+ usb1_vbus-supply = <&reg_vcc>;
+};
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
new file mode 100644
index 000000000000..df653111b46c
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Jisheng Zhang <[email protected]>
+// Copyright (C) 2022 Samuel Holland <[email protected]>
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+#include "sun20i-d1.dtsi"
+#include "sun20i-d1-common-regulators.dtsi"
+
+/ {
+ model = "Sipeed Lichee RV";
+ compatible = "sipeed,lichee-rv", "allwinner,sun20i-d1";
+
+ aliases {
+ mmc0 = &mmc0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */
+ };
+ };
+
+ reg_vdd_cpu: vdd-cpu {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-cpu";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ vin-supply = <&reg_vcc>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_vdd_cpu>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&mmc0 {
+ broken-cd;
+ bus-width = <4>;
+ disable-wp;
+ vmmc-supply = <&reg_vcc_3v3>;
+ vqmmc-supply = <&reg_vcc_3v3>;
+ pinctrl-0 = <&mmc0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pb8_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
+ usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
+ usb0_vbus-supply = <&reg_vcc>;
+ status = "okay";
+};
--
2.35.1

2022-08-15 05:23:34

[permalink] [raw]

Subject: [PATCH 05/12] riscv: Add the Allwinner SoC family Kconfig option

Allwinner manufactures the sunxi family of application processors. This
includes the "sun8i" series of ARMv7 SoCs, the "sun50i" series of ARMv8
SoCs, and now the "sun20i" series of 64-bit RISC-V SoCs.

The first SoC in the sun20i series is D1, containing a single T-HEAD
C906 core. D1s is a low-pin-count variant of D1 with co-packaged DRAM.

Most peripherals are shared across the entire chip family. In fact, the
ARMv7 T113 SoC is pin-compatible and almost entirely register-compatible
with the D1s.

This means many existing device drivers can be reused. To facilitate
this reuse, name the symbol ARCH_SUNXI, since that is what the existing
drivers have as their dependency.

Signed-off-by: Samuel Holland <[email protected]>
---

arch/riscv/Kconfig.socs | 9 +++++++++
1 file changed, 9 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 69774bb362d6..1caacbfac1a5 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -1,5 +1,14 @@
menu "SoC selection"

+config ARCH_SUNXI
+ bool "Allwinner sun20i SoCs"
+ select ERRATA_THEAD if MMU && !XIP_KERNEL
+ select SIFIVE_PLIC
+ select SUN4I_TIMER
+ help
+ This enables support for Allwinner sun20i platform hardware,
+ including boards based on the D1 and D1s SoCs.
+
config SOC_MICROCHIP_POLARFIRE
bool "Microchip PolarFire SoCs"
select MCHP_CLK_MPFS
--
2.35.1

2022-08-15 05:32:36

[permalink] [raw]

Subject: [PATCH 02/12] dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles

The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor.
Notably, the C906 core is used in the Allwinner D1 SoC.

Signed-off-by: Samuel Holland <[email protected]>
---

Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++
1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 873dd12f6e89..ce2161d9115a 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -38,6 +38,8 @@ properties:
- sifive,u5
- sifive,u7
- canaan,k210
+ - thead,c906
+ - thead,c910
- const: riscv
- items:
- enum:
--
2.35.1

2022-08-15 05:38:14

[permalink] [raw]

Subject: [PATCH 04/12] dt-bindings: riscv: Add Allwinner D1 board compatibles

Several SoMs and boards are available that feature the Allwinner D1 SoC.
Document their compatible strings.

Signed-off-by: Samuel Holland <[email protected]>
---

.../devicetree/bindings/riscv/sunxi.yaml | 64 +++++++++++++++++++
1 file changed, 64 insertions(+)
create mode 100644 Documentation/devicetree/bindings/riscv/sunxi.yaml

diff --git a/Documentation/devicetree/bindings/riscv/sunxi.yaml b/Documentation/devicetree/bindings/riscv/sunxi.yaml
new file mode 100644
index 000000000000..564a89499894
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/sunxi.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/sunxi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner RISC-V SoC-based boards
+
+maintainers:
+ - Chen-Yu Tsai <[email protected]>
+ - Jernej Skrabec <[email protected]>
+ - Samuel Holland <[email protected]>
+
+description:
+ Allwinner RISC-V SoC-based boards
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: Dongshan Nezha STU SoM
+ items:
+ - const: 100ask,dongshan-nezha-stu
+ - const: allwinner,sun20i-d1
+
+ - description: D1 Nezha board
+ items:
+ - const: allwinner,d1-nezha
+ - const: allwinner,sun20i-d1
+
+ - description: ClockworkPi R-01 SoM and v3.14 board
+ items:
+ - const: clockwork,r-01-clockworkpi-v3.14
+ - const: allwinner,sun20i-d1
+
+ - description: ClockworkPi R-01 SoM, v3.14 board, and DevTerm expansion
+ items:
+ - const: clockwork,r-01-devterm-v3.14
+ - const: clockwork,r-01-clockworkpi-v3.14
+ - const: allwinner,sun20i-d1
+
+ - description: Lichee RV SoM
+ items:
+ - const: sipeed,lichee-rv
+ - const: allwinner,sun20i-d1
+
+ - description: Carrier boards for the Lichee RV SoM
+ items:
+ - enum:
+ - sipeed,lichee-rv-86-panel-480p
+ - sipeed,lichee-rv-86-panel-720p
+ - sipeed,lichee-rv-dock
+ - const: sipeed,lichee-rv
+ - const: allwinner,sun20i-d1
+
+ - description: MangoPi MQ Pro board
+ items:
+ - const: widora,mangopi-mq-pro
+ - const: allwinner,sun20i-d1
+
+additionalProperties: true
+
+...
--
2.35.1

2022-08-15 05:38:25

[permalink] [raw]

Subject: [PATCH 12/12] riscv: defconfig: Enable the Allwinner D1 platform and drivers

Now that several D1-based boards are supported, enable the platform in
our defconfig. Build in the drivers which are necessary to boot, such as
the pinctrl, MMC, RTC (which provides critical clocks), SPI (for flash),
and watchdog (which may be left enabled by the bootloader). Other common
onboard peripherals are enabled as modules.

Signed-off-by: Samuel Holland <[email protected]>
---

arch/riscv/configs/defconfig | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index aed332a9d4ea..8f856982da87 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -25,6 +25,7 @@ CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
# CONFIG_SYSFS_SYSCALL is not set
CONFIG_PROFILING=y
+CONFIG_ARCH_SUNXI=y
CONFIG_SOC_MICROCHIP_POLARFIRE=y
CONFIG_SOC_SIFIVE=y
CONFIG_SOC_STARFIVE=y
@@ -118,22 +119,31 @@ CONFIG_VIRTIO_NET=y
CONFIG_MACB=y
CONFIG_E1000E=y
CONFIG_R8169=y
+CONFIG_STMMAC_ETH=m
CONFIG_MICROSEMI_PHY=y
CONFIG_INPUT_MOUSEDEV=y
+CONFIG_KEYBOARD_SUN4I_LRADC=m
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_I2C_MV64XXX=m
CONFIG_SPI=y
CONFIG_SPI_SIFIVE=y
+CONFIG_SPI_SUN6I=y
# CONFIG_PTP_1588_CLOCK is not set
-CONFIG_GPIOLIB=y
CONFIG_GPIO_SIFIVE=y
+CONFIG_WATCHDOG=y
+CONFIG_SUNXI_WATCHDOG=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_DRM=m
CONFIG_DRM_RADEON=m
CONFIG_DRM_NOUVEAU=m
+CONFIG_DRM_SUN4I=m
CONFIG_DRM_VIRTIO_GPU=m
CONFIG_FB=y
CONFIG_FRAMEBUFFER_CONSOLE=y
@@ -146,19 +156,30 @@ CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_STORAGE=y
CONFIG_USB_UAS=y
+CONFIG_USB_MUSB_HDRC=m
+CONFIG_USB_MUSB_SUNXI=m
+CONFIG_NOP_USB_XCEIV=m
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_CADENCE=y
CONFIG_MMC_SPI=y
+CONFIG_MMC_SUNXI=y
CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_SUN6I=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_SUN6I=m
CONFIG_VIRTIO_PCI=y
CONFIG_VIRTIO_BALLOON=y
CONFIG_VIRTIO_INPUT=y
CONFIG_VIRTIO_MMIO=y
+CONFIG_SUN8I_DE2_CCU=m
+CONFIG_SUN50I_IOMMU=y
CONFIG_RPMSG_CHAR=y
CONFIG_RPMSG_CTRL=y
CONFIG_RPMSG_VIRTIO=y
+CONFIG_PHY_SUN4I_USB=m
+CONFIG_NVMEM_SUNXI_SID=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
--
2.35.1

2022-08-15 05:38:25

[permalink] [raw]

Subject: [PATCH 10/12] riscv: dts: allwinner: Add Dongshan Nezha STU devicetree

The 100ask Dongshan Nezha STU is a system-on-module that can be used
standalone or with a carrier board. The SoM provides gigabit Ethernet,
HDMI, a USB peripheral port, and WiFi/Bluetooth via an RTL8723DS chip.

The "DIY" carrier board exposes almost every pin from the D1 SoC to 0.1"
headers, but contains no digital circuitry, so it does not have its own
devicetree.

Signed-off-by: Samuel Holland <[email protected]>
---

arch/riscv/boot/dts/allwinner/Makefile | 1 +
.../sun20i-d1-dongshan-nezha-stu.dts | 114 ++++++++++++++++++
2 files changed, 115 insertions(+)
create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts

diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile
index bcc304175753..530ef8adb8b0 100644
--- a/arch/riscv/boot/dts/allwinner/Makefile
+++ b/arch/riscv/boot/dts/allwinner/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-dongshan-nezha-stu.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-480p.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-dock.dtb
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
new file mode 100644
index 000000000000..c3d06dfaa7c3
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Samuel Holland <[email protected]>
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+#include "sun20i-d1.dtsi"
+#include "sun20i-d1-common-regulators.dtsi"
+
+/ {
+ model = "Dongshan Nezha STU";
+ compatible = "100ask,dongshan-nezha-stu", "allwinner,sun20i-d1";
+
+ aliases {
+ ethernet0 = &emac;
+ mmc0 = &mmc0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */
+ };
+ };
+
+ reg_usbvbus: usbvbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usbvbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
+ enable-active-high;
+ vin-supply = <&reg_vcc>;
+ };
+
+ /*
+ * This regulator is PWM-controlled, but the PWM controller is not
+ * yet supported, so fix the regulator to its default voltage.
+ */
+ reg_vdd_cpu: vdd-cpu {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-cpu";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&reg_vcc>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_vdd_cpu>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-0 = <&rgmii_pe_pins>;
+ pinctrl-names = "default";
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii-id";
+ phy-supply = <&reg_vcc_3v3>;
+ status = "okay";
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ broken-cd;
+ bus-width = <4>;
+ disable-wp;
+ vmmc-supply = <&reg_vcc_3v3>;
+ vqmmc-supply = <&reg_vcc_3v3>;
+ pinctrl-0 = <&mmc0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pb8_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
+ usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
+ usb0_vbus-supply = <&reg_usbvbus>;
+ status = "okay";
+};
--
2.35.1

2022-08-15 05:38:43

[permalink] [raw]

Subject: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, as well as
one HiFi 4 DSP. The SoC is based on a design that additionally contained
a pair of Cortex A7's. For that reason, some peripherals are duplicated.

This devicetree includes all of the peripherals that already have a
documented binding.

Signed-off-by: Samuel Holland <[email protected]>
---

arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/allwinner/Makefile | 1 +
arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 900 +++++++++++++++++++
3 files changed, 902 insertions(+)
create mode 100644 arch/riscv/boot/dts/allwinner/Makefile
create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi

diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index ff174996cdfd..f292e31bdb2c 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
+subdir-y += allwinner
subdir-y += sifive
subdir-y += starfive
subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile
new file mode 100644
index 000000000000..f66554cd5c45
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/Makefile
@@ -0,0 +1 @@
+# SPDX-License-Identifier: GPL-2.0
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
new file mode 100644
index 000000000000..d1429274f22e
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
@@ -0,0 +1,900 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
+
+#include <dt-bindings/clock/sun6i-rtc.h>
+#include <dt-bindings/clock/sun8i-de2.h>
+#include <dt-bindings/clock/sun8i-tcon-top.h>
+#include <dt-bindings/clock/sun20i-d1-ccu.h>
+#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/reset/sun8i-de2.h>
+#include <dt-bindings/reset/sun20i-d1-ccu.h>
+#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ timebase-frequency = <24000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "thead,c906", "riscv";
+ device_type = "cpu";
+ reg = <0>;
+ clocks = <&ccu CLK_RISCV>;
+ clock-frequency = <24000000>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <256>;
+ d-cache-size = <32768>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ mmu-type = "riscv,sv39";
+ riscv,isa = "rv64imafdc";
+ #cooling-cells = <2>;
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
+ de: display-engine {
+ compatible = "allwinner,sun20i-d1-display-engine";
+ allwinner,pipelines = <&mixer0>, <&mixer1>;
+ status = "disabled";
+ };
+
+ osc24M: osc24M-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ ranges;
+ interrupt-parent = <&plic>;
+ dma-noncoherent;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ dsp_wdt: watchdog@1700400 {
+ compatible = "allwinner,sun20i-d1-wdt";
+ reg = <0x1700400 0x20>;
+ interrupts = <138 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>, <&rtc CLK_OSC32K>;
+ clock-names = "hosc", "losc";
+ status = "reserved";
+ };
+
+ pio: pinctrl@2000000 {
+ compatible = "allwinner,sun20i-d1-pinctrl";
+ reg = <0x2000000 0x800>;
+ interrupts = <85 IRQ_TYPE_LEVEL_HIGH>,
+ <87 IRQ_TYPE_LEVEL_HIGH>,
+ <89 IRQ_TYPE_LEVEL_HIGH>,
+ <91 IRQ_TYPE_LEVEL_HIGH>,
+ <93 IRQ_TYPE_LEVEL_HIGH>,
+ <95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_APB0>,
+ <&osc24M>,
+ <&rtc CLK_OSC32K>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ interrupt-controller;
+ #gpio-cells = <3>;
+ #interrupt-cells = <3>;
+
+ /omit-if-no-ref/
+ i2c0_pb10_pins: i2c0-pb10-pins {
+ pins = "PB10", "PB11";
+ function = "i2c0";
+ };
+
+ /omit-if-no-ref/
+ i2c2_pb0_pins: i2c2-pb0-pins {
+ pins = "PB0", "PB1";
+ function = "i2c2";
+ };
+
+ /omit-if-no-ref/
+ lcd_rgb666_pins: lcd-rgb666-pins {
+ pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
+ "PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
+ "PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
+ "PD18", "PD19", "PD20", "PD21";
+ function = "lcd0";
+ };
+
+ /omit-if-no-ref/
+ mmc0_pins: mmc0-pins {
+ pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
+ function = "mmc0";
+ };
+
+ /omit-if-no-ref/
+ mmc1_pins: mmc1-pins {
+ pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
+ function = "mmc1";
+ };
+
+ /omit-if-no-ref/
+ mmc2_pins: mmc2-pins {
+ pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
+ function = "mmc2";
+ };
+
+ /omit-if-no-ref/
+ rgmii_pe_pins: rgmii-pe-pins {
+ pins = "PE0", "PE1", "PE2", "PE3", "PE4",
+ "PE5", "PE6", "PE7", "PE8", "PE9",
+ "PE11", "PE12", "PE13", "PE14", "PE15";
+ function = "emac";
+ };
+
+ /omit-if-no-ref/
+ rmii_pe_pins: rmii-pe-pins {
+ pins = "PE0", "PE1", "PE2", "PE3", "PE4",
+ "PE5", "PE6", "PE7", "PE8", "PE9";
+ function = "emac";
+ };
+
+ /omit-if-no-ref/
+ uart0_pb8_pins: uart0-pb8-pins {
+ pins = "PB8", "PB9";
+ function = "uart0";
+ };
+
+ /omit-if-no-ref/
+ uart1_pg6_pins: uart1-pg6-pins {
+ pins = "PG6", "PG7";
+ function = "uart1";
+ };
+
+ /omit-if-no-ref/
+ uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins {
+ pins = "PG8", "PG9";
+ function = "uart1";
+ };
+ };
+
+ ccu: clock-controller@2001000 {
+ compatible = "allwinner,sun20i-d1-ccu";
+ reg = <0x2001000 0x1000>;
+ clocks = <&osc24M>,
+ <&rtc CLK_OSC32K>,
+ <&rtc CLK_IOSC>;
+ clock-names = "hosc", "losc", "iosc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ lradc: keys@2009800 {
+ compatible = "allwinner,sun20i-d1-lradc",
+ "allwinner,sun50i-r329-lradc";
+ reg = <0x2009800 0x400>;
+ interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_LRADC>;
+ resets = <&ccu RST_BUS_LRADC>;
+ status = "disabled";
+ };
+
+ codec: audio-codec@2030000 {
+ compatible = "simple-mfd", "syscon";
+ reg = <0x2030000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ regulators@2030348 {
+ compatible = "allwinner,sun20i-d1-analog-ldos";
+ reg = <0x2030348 0x4>;
+ nvmem-cells = <&bg_trim>;
+ nvmem-cell-names = "bg_trim";
+
+ reg_aldo: aldo {
+ };
+
+ reg_hpldo: hpldo {
+ };
+ };
+ };
+
+ i2s0: i2s@2032000 {
+ compatible = "allwinner,sun20i-d1-i2s",
+ "allwinner,sun50i-r329-i2s";
+ reg = <0x2032000 0x1000>;
+ interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S0>,
+ <&ccu CLK_I2S0>;
+ clock-names = "apb", "mod";
+ resets = <&ccu RST_BUS_I2S0>;
+ dmas = <&dma 3>, <&dma 3>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #sound-dai-cells = <0>;
+ };
+
+ i2s1: i2s@2033000 {
+ compatible = "allwinner,sun20i-d1-i2s",
+ "allwinner,sun50i-r329-i2s";
+ reg = <0x2033000 0x1000>;
+ interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S1>,
+ <&ccu CLK_I2S1>;
+ clock-names = "apb", "mod";
+ resets = <&ccu RST_BUS_I2S1>;
+ dmas = <&dma 4>, <&dma 4>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #sound-dai-cells = <0>;
+ };
+
+ i2s2: i2s@2034000 {
+ compatible = "allwinner,sun20i-d1-i2s",
+ "allwinner,sun50i-r329-i2s";
+ reg = <0x2034000 0x1000>;
+ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S2>,
+ <&ccu CLK_I2S2>;
+ clock-names = "apb", "mod";
+ resets = <&ccu RST_BUS_I2S2>;
+ dmas = <&dma 5>, <&dma 5>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #sound-dai-cells = <0>;
+ };
+
+ timer: timer@2050000 {
+ compatible = "allwinner,sun20i-d1-timer",
+ "allwinner,sun8i-a23-timer";
+ reg = <0x2050000 0xa0>;
+ interrupts = <75 IRQ_TYPE_LEVEL_HIGH>,
+ <76 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
+ wdt: watchdog@20500a0 {
+ compatible = "allwinner,sun20i-d1-wdt-reset",
+ "allwinner,sun20i-d1-wdt";
+ reg = <0x20500a0 0x20>;
+ interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>, <&rtc CLK_OSC32K>;
+ clock-names = "hosc", "losc";
+ status = "reserved";
+ };
+
+ uart0: serial@2500000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x2500000 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_UART0>;
+ resets = <&ccu RST_BUS_UART0>;
+ dmas = <&dma 14>, <&dma 14>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart1: serial@2500400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x2500400 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_UART1>;
+ resets = <&ccu RST_BUS_UART1>;
+ dmas = <&dma 15>, <&dma 15>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart2: serial@2500800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x2500800 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_UART2>;
+ resets = <&ccu RST_BUS_UART2>;
+ dmas = <&dma 16>, <&dma 16>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart3: serial@2500c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x2500c00 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_UART3>;
+ resets = <&ccu RST_BUS_UART3>;
+ dmas = <&dma 17>, <&dma 17>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart4: serial@2501000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x2501000 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_UART4>;
+ resets = <&ccu RST_BUS_UART4>;
+ dmas = <&dma 18>, <&dma 18>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart5: serial@2501400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x2501400 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_UART5>;
+ resets = <&ccu RST_BUS_UART5>;
+ dmas = <&dma 19>, <&dma 19>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c0: i2c@2502000 {
+ compatible = "allwinner,sun20i-d1-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x2502000 0x400>;
+ interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C0>;
+ resets = <&ccu RST_BUS_I2C0>;
+ dmas = <&dma 43>, <&dma 43>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@2502400 {
+ compatible = "allwinner,sun20i-d1-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x2502400 0x400>;
+ interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C1>;
+ resets = <&ccu RST_BUS_I2C1>;
+ dmas = <&dma 44>, <&dma 44>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@2502800 {
+ compatible = "allwinner,sun20i-d1-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x2502800 0x400>;
+ interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C2>;
+ resets = <&ccu RST_BUS_I2C2>;
+ dmas = <&dma 45>, <&dma 45>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c3: i2c@2502c00 {
+ compatible = "allwinner,sun20i-d1-i2c",
+ "allwinner,sun8i-v536-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x2502c00 0x400>;
+ interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C3>;
+ resets = <&ccu RST_BUS_I2C3>;
+ dmas = <&dma 46>, <&dma 46>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ syscon: syscon@3000000 {
+ compatible = "allwinner,sun20i-d1-system-control";
+ reg = <0x3000000 0x1000>;
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ regulators@3000150 {
+ compatible = "allwinner,sun20i-d1-system-ldos";
+ reg = <0x3000150 0x4>;
+
+ reg_ldoa: ldoa {
+ };
+
+ reg_ldob: ldob {
+ };
+ };
+ };
+
+ dma: dma-controller@3002000 {
+ compatible = "allwinner,sun20i-d1-dma";
+ reg = <0x3002000 0x1000>;
+ interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
+ clock-names = "bus", "mbus";
+ resets = <&ccu RST_BUS_DMA>;
+ dma-channels = <16>;
+ dma-requests = <48>;
+ #dma-cells = <1>;
+ };
+
+ sid: efuse@3006000 {
+ compatible = "allwinner,sun20i-d1-sid";
+ reg = <0x3006000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ths_calib: ths-calib@14 {
+ reg = <0x14 0x4>;
+ };
+
+ bg_trim: bg-trim@28 {
+ reg = <0x28 0x4>;
+ bits = <16 8>;
+ };
+ };
+
+ mbus: dram-controller@3102000 {
+ compatible = "allwinner,sun20i-d1-mbus";
+ reg = <0x3102000 0x1000>,
+ <0x3103000 0x1000>;
+ reg-names = "mbus", "dram";
+ interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_MBUS>,
+ <&ccu CLK_DRAM>,
+ <&ccu CLK_BUS_DRAM>;
+ clock-names = "mbus", "dram", "bus";
+ dma-ranges = <0 0x40000000 0x80000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interconnect-cells = <1>;
+ };
+
+ mmc0: mmc@4020000 {
+ compatible = "allwinner,sun20i-d1-mmc";
+ reg = <0x4020000 0x1000>;
+ interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC0>;
+ reset-names = "ahb";
+ cap-sd-highspeed;
+ max-frequency = <150000000>;
+ no-mmc;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@4021000 {
+ compatible = "allwinner,sun20i-d1-mmc";
+ reg = <0x4021000 0x1000>;
+ interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC1>;
+ reset-names = "ahb";
+ cap-sd-highspeed;
+ max-frequency = <150000000>;
+ no-mmc;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc@4022000 {
+ compatible = "allwinner,sun20i-d1-emmc",
+ "allwinner,sun50i-a100-emmc";
+ reg = <0x4022000 0x1000>;
+ interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC2>;
+ reset-names = "ahb";
+ cap-mmc-highspeed;
+ max-frequency = <150000000>;
+ mmc-ddr-1_8v;
+ mmc-ddr-3_3v;
+ no-sd;
+ no-sdio;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ usb_otg: usb@4100000 {
+ compatible = "allwinner,sun20i-d1-musb",
+ "allwinner,sun8i-a33-musb";
+ reg = <0x4100000 0x400>;
+ interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mc";
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
+ extcon = <&usbphy 0>;
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usbphy: phy@4100400 {
+ compatible = "allwinner,sun20i-d1-usb-phy";
+ reg = <0x4100400 0x100>,
+ <0x4101800 0x100>,
+ <0x4200800 0x100>;
+ reg-names = "phy_ctrl",
+ "pmu0",
+ "pmu1";
+ clocks = <&osc24M>,
+ <&osc24M>;
+ clock-names = "usb0_phy",
+ "usb1_phy";
+ resets = <&ccu RST_USB_PHY0>,
+ <&ccu RST_USB_PHY1>;
+ reset-names = "usb0_reset",
+ "usb1_reset";
+ status = "disabled";
+ #phy-cells = <1>;
+ };
+
+ ehci0: usb@4101000 {
+ compatible = "allwinner,sun20i-d1-ehci",
+ "generic-ehci";
+ reg = <0x4101000 0x100>;
+ interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_BUS_EHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>,
+ <&ccu RST_BUS_EHCI0>;
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci0: usb@4101400 {
+ compatible = "allwinner,sun20i-d1-ohci",
+ "generic-ohci";
+ reg = <0x4101400 0x100>;
+ interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>;
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ehci1: usb@4200000 {
+ compatible = "allwinner,sun20i-d1-ehci",
+ "generic-ehci";
+ reg = <0x4200000 0x100>;
+ interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI1>,
+ <&ccu CLK_BUS_EHCI1>,
+ <&ccu CLK_USB_OHCI1>;
+ resets = <&ccu RST_BUS_OHCI1>,
+ <&ccu RST_BUS_EHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci1: usb@4200400 {
+ compatible = "allwinner,sun20i-d1-ohci",
+ "generic-ohci";
+ reg = <0x4200400 0x100>;
+ interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI1>,
+ <&ccu CLK_USB_OHCI1>;
+ resets = <&ccu RST_BUS_OHCI1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ emac: ethernet@4500000 {
+ compatible = "allwinner,sun20i-d1-emac",
+ "allwinner,sun50i-a64-emac";
+ reg = <0x4500000 0x10000>;
+ interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "stmmaceth";
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "stmmaceth";
+ syscon = <&syscon>;
+ status = "disabled";
+
+ mdio: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ display_clocks: clock-controller@5000000 {
+ compatible = "allwinner,sun20i-d1-de2-clk",
+ "allwinner,sun50i-h5-de2-clk";
+ reg = <0x5000000 0x10000>;
+ clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mixer0: mixer@5100000 {
+ compatible = "allwinner,sun20i-d1-de2-mixer-0";
+ reg = <0x5100000 0x100000>;
+ clocks = <&display_clocks CLK_BUS_MIXER0>,
+ <&display_clocks CLK_MIXER0>;
+ clock-names = "bus", "mod";
+ resets = <&display_clocks RST_MIXER0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer0_out: port@1 {
+ reg = <1>;
+
+ mixer0_out_tcon_top_mixer0: endpoint {
+ remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
+ };
+ };
+ };
+ };
+
+ mixer1: mixer@5200000 {
+ compatible = "allwinner,sun20i-d1-de2-mixer-1";
+ reg = <0x5200000 0x100000>;
+ clocks = <&display_clocks CLK_BUS_MIXER1>,
+ <&display_clocks CLK_MIXER1>;
+ clock-names = "bus", "mod";
+ resets = <&display_clocks RST_MIXER1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer1_out: port@1 {
+ reg = <1>;
+
+ mixer1_out_tcon_top_mixer1: endpoint {
+ remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
+ };
+ };
+ };
+ };
+
+ tcon_top: tcon-top@5460000 {
+ compatible = "allwinner,sun20i-d1-tcon-top";
+ reg = <0x5460000 0x1000>;
+ clocks = <&ccu CLK_BUS_DPSS_TOP>,
+ <&ccu CLK_TCON_TV>,
+ <&ccu CLK_TVE>,
+ <&ccu CLK_MIPI_DSI>;
+ clock-names = "bus", "tcon-tv0", "tve0", "dsi";
+ clock-output-names = "tcon-top-tv0", "tcon-top-dsi";
+ resets = <&ccu RST_BUS_DPSS_TOP>;
+ #clock-cells = <1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_top_mixer0_in: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_top_mixer0_in_mixer0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
+ };
+ };
+
+ tcon_top_mixer0_out: port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
+ };
+
+ tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
+ };
+ };
+
+ tcon_top_mixer1_in: port@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_top_mixer1_in_mixer1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
+ };
+ };
+
+ tcon_top_mixer1_out: port@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>;
+ };
+
+ tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
+ };
+ };
+
+ tcon_top_hdmi_in: port@4 {
+ reg = <4>;
+
+ tcon_top_hdmi_in_tcon_tv0: endpoint {
+ remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>;
+ };
+ };
+
+ tcon_top_hdmi_out: port@5 {
+ reg = <5>;
+ };
+ };
+ };
+
+ tcon_lcd0: lcd-controller@5461000 {
+ compatible = "allwinner,sun20i-d1-tcon-lcd";
+ reg = <0x5461000 0x1000>;
+ interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON_LCD0>,
+ <&ccu CLK_TCON_LCD0>;
+ clock-names = "ahb", "tcon-ch0";
+ clock-output-names = "tcon-pixel-clock";
+ resets = <&ccu RST_BUS_TCON_LCD0>,
+ <&ccu RST_BUS_LVDS0>;
+ reset-names = "lcd", "lvds";
+ #clock-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_lcd0_in: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
+ };
+
+ tcon_lcd0_in_tcon_top_mixer1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>;
+ };
+ };
+
+ tcon_lcd0_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ tcon_tv0: lcd-controller@5470000 {
+ compatible = "allwinner,sun20i-d1-tcon-tv";
+ reg = <0x5470000 0x1000>;
+ interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON_TV>,
+ <&tcon_top CLK_TCON_TOP_TV0>;
+ clock-names = "ahb", "tcon-ch1";
+ resets = <&ccu RST_BUS_TCON_TV>;
+ reset-names = "lcd";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_tv0_in: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
+ };
+
+ tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
+ };
+ };
+
+ tcon_tv0_out: port@1 {
+ reg = <1>;
+
+ tcon_tv0_out_tcon_top_hdmi: endpoint {
+ remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
+ };
+ };
+ };
+ };
+
+ riscv_wdt: watchdog@6011000 {
+ compatible = "allwinner,sun20i-d1-wdt";
+ reg = <0x6011000 0x20>;
+ interrupts = <147 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>, <&rtc CLK_OSC32K>;
+ clock-names = "hosc", "losc";
+ };
+
+ r_ccu: clock-controller@7010000 {
+ compatible = "allwinner,sun20i-d1-r-ccu";
+ reg = <0x7010000 0x400>;
+ clocks = <&osc24M>,
+ <&rtc CLK_OSC32K>,
+ <&rtc CLK_IOSC>,
+ <&ccu CLK_PLL_PERIPH0_DIV3>;
+ clock-names = "hosc", "losc", "iosc", "pll-periph";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ rtc: rtc@7090000 {
+ compatible = "allwinner,sun20i-d1-rtc",
+ "allwinner,sun50i-r329-rtc";
+ reg = <0x7090000 0x400>;
+ interrupts = <160 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_BUS_R_RTC>,
+ <&osc24M>,
+ <&r_ccu CLK_R_AHB>;
+ clock-names = "bus", "hosc", "ahb";
+ #clock-cells = <1>;
+ };
+
+ plic: interrupt-controller@10000000 {
+ compatible = "allwinner,sun20i-d1-plic",
+ "thead,c900-plic";
+ reg = <0x10000000 0x4000000>;
+ interrupts-extended = <&cpu0_intc 11>,
+ <&cpu0_intc 9>;
+ interrupt-controller;
+ riscv,ndev = <176>;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ };
+ };
+};
--
2.35.1

2022-08-15 05:46:51

[permalink] [raw]

Subject: [PATCH 09/12] riscv: dts: allwinner: Add MangoPi MQ Pro devicetree

The MangoPi MQ Pro is a tiny SBC with a layout compatible to the
Raspberry Pi Zero. It includes the Allwinner D1 SoC, 512M or 1G of DDR3,
and an RTL8723DS-based WiFi/Bluetooth module.

The board also exposes GPIO Port E via a connector on the end of the
board, which can support either a camera or an RMII Ethernet PHY. The
additional regulators supply that connector.

Signed-off-by: Samuel Holland <[email protected]>
---

arch/riscv/boot/dts/allwinner/Makefile | 1 +
.../allwinner/sun20i-d1-mangopi-mq-pro.dts | 128 ++++++++++++++++++
2 files changed, 129 insertions(+)
create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts

diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile
index 300ada20c735..bcc304175753 100644
--- a/arch/riscv/boot/dts/allwinner/Makefile
+++ b/arch/riscv/boot/dts/allwinner/Makefile
@@ -3,4 +3,5 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-480p.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-dock.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-mangopi-mq-pro.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts
new file mode 100644
index 000000000000..61a26d3db521
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Samuel Holland <[email protected]>
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "sun20i-d1.dtsi"
+#include "sun20i-d1-common-regulators.dtsi"
+
+/ {
+ model = "MangoPi MQ Pro";
+ compatible = "widora,mangopi-mq-pro", "allwinner,sun20i-d1";
+
+ aliases {
+ ethernet0 = &rtl8723ds;
+ mmc0 = &mmc0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_avdd2v8: avdd2v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "avdd2v8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ vin-supply = <&reg_vcc_3v3>;
+ };
+
+ reg_dvdd: dvdd {
+ compatible = "regulator-fixed";
+ regulator-name = "dvdd";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ vin-supply = <&reg_vcc_3v3>;
+ };
+
+ reg_vdd_cpu: vdd-cpu {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-cpu";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&reg_vcc>;
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 6 17 GPIO_ACTIVE_LOW>; /* PG17 */
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_vdd_cpu>;
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&mmc0 {
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ disable-wp;
+ vmmc-supply = <&reg_vcc_3v3>;
+ vqmmc-supply = <&reg_vcc_3v3>;
+ pinctrl-0 = <&mmc0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&mmc1 {
+ bus-width = <4>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ non-removable;
+ vmmc-supply = <&reg_vcc_3v3>;
+ vqmmc-supply = <&reg_vcc_3v3>;
+ pinctrl-0 = <&mmc1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ rtl8723ds: wifi@1 {
+ reg = <1>;
+ interrupt-parent = <&pio>;
+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 */
+ interrupt-names = "host-wake";
+ };
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ vcc-pe-supply = <&reg_avdd2v8>;
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pb8_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart1 {
+ uart-has-rtscts;
+ pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ bluetooth {
+ compatible = "realtek,rtl8723ds-bt";
+ device-wake-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */
+ enable-gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG15 */
+ host-wake-gpios = <&pio 6 14 GPIO_ACTIVE_HIGH>; /* PG14 */
+ };
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_vbus-supply = <&reg_vcc>;
+ status = "okay";
+};
--
2.35.1

2022-08-15 05:58:12

[permalink] [raw]

Subject: [PATCH 11/12] riscv: dts: allwinner: Add ClockworkPi and DevTerm devicetrees

Clockwork Tech manufactures several SoMs for their RasPi CM3-compatible
"ClockworkPi" mainboard. Their R-01 SoM features the Allwinner D1 SoC.
The R-01 contains only the CPU, DRAM, and always-on voltage regulation;
it does not merit a separate devicetree.

The ClockworkPi mainboard features analog audio, a MIPI-DSI panel, USB
host and peripheral ports, an Ampak AP6256 WiFi/Bluetooth module, and an
X-Powers AXP228 PMIC for managing a Li-ion battery.

The DevTerm is a complete system which extends the ClockworkPi mainboard
with a pair of expansion boards. These expansion boards provide a fan, a
keyboard, speakers, and a thermal printer.

Signed-off-by: Samuel Holland <[email protected]>
---

arch/riscv/boot/dts/allwinner/Makefile | 2 +
.../allwinner/sun20i-d1-clockworkpi-v3.14.dts | 242 ++++++++++++++++++
.../dts/allwinner/sun20i-d1-devterm-v3.14.dts | 37 +++
3 files changed, 281 insertions(+)
create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts

diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile
index 530ef8adb8b0..25097da6fdb9 100644
--- a/arch/riscv/boot/dts/allwinner/Makefile
+++ b/arch/riscv/boot/dts/allwinner/Makefile
@@ -1,4 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-clockworkpi-v3.14.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-devterm-v3.14.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-dongshan-nezha-stu.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-480p.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
new file mode 100644
index 000000000000..74b4b6d8363a
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
@@ -0,0 +1,242 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Samuel Holland <[email protected]>
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "sun20i-d1.dtsi"
+#include "sun20i-d1-common-regulators.dtsi"
+
+/ {
+ model = "ClockworkPi v3.14 (R-01)";
+ compatible = "clockwork,r-01-clockworkpi-v3.14", "allwinner,sun20i-d1";
+
+ aliases {
+ ethernet0 = &ap6256;
+ mmc0 = &mmc0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ /*
+ * This regulator is PWM-controlled, but the PWM controller is not
+ * yet supported, so fix the regulator to its default voltage.
+ */
+ reg_vdd_cpu: vdd-cpu {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-cpu";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&reg_vcc>;
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 6 11 GPIO_ACTIVE_LOW>; /* PG11/GPIO3 */
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_vdd_cpu>;
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-0 = <&i2c0_pb10_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ axp221: pmic@34 {
+ compatible = "x-powers,axp228", "x-powers,axp221";
+ reg = <0x34>;
+ interrupt-parent = <&pio>;
+ interrupts = <4 9 IRQ_TYPE_LEVEL_LOW>; /* PE9/GPIO2 */
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ ac_power_supply: ac-power {
+ compatible = "x-powers,axp221-ac-power-supply";
+ };
+
+ axp_adc: adc {
+ compatible = "x-powers,axp221-adc";
+ #io-channel-cells = <1>;
+ };
+
+ battery_power_supply: battery-power {
+ compatible = "x-powers,axp221-battery-power-supply";
+ };
+
+ regulators {
+ x-powers,dcdc-freq = <3000>;
+
+ reg_dcdc1: dcdc1 {
+ regulator-name = "sys-3v3";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_dcdc3: dcdc3 {
+ regulator-name = "sys-1v8";
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ reg_aldo1: aldo1 {
+ regulator-name = "aud-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_aldo2: aldo2 {
+ regulator-name = "disp-3v3";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_aldo3: aldo3 {
+ regulator-name = "vdd-wifi";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ /* DLDO1 and ELDO1-3 are connected in parallel. */
+ reg_dldo1: dldo1 {
+ regulator-name = "vbat-wifi-a";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ /* DLDO2-DLDO4 are connected in parallel. */
+ reg_dldo2: dldo2 {
+ regulator-name = "vcc-3v3-ext-a";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_dldo3: dldo3 {
+ regulator-name = "vcc-3v3-ext-b";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_dldo4: dldo4 {
+ regulator-name = "vcc-3v3-ext-c";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_eldo1: eldo1 {
+ regulator-name = "vbat-wifi-b";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_eldo2: eldo2 {
+ regulator-name = "vbat-wifi-c";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_eldo3: eldo3 {
+ regulator-name = "vbat-wifi-d";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+
+ usb_power_supply: usb-power {
+ compatible = "x-powers,axp221-usb-power-supply";
+ status = "disabled";
+ };
+ };
+};
+
+&mmc0 {
+ broken-cd;
+ bus-width = <4>;
+ disable-wp;
+ vmmc-supply = <&reg_dcdc1>;
+ vqmmc-supply = <&reg_vcc_3v3>;
+ pinctrl-0 = <&mmc0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&mmc1 {
+ bus-width = <4>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ non-removable;
+ vmmc-supply = <&reg_dldo1>;
+ vqmmc-supply = <&reg_aldo3>;
+ pinctrl-0 = <&mmc1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ ap6256: wifi@1 {
+ compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac";
+ reg = <1>;
+ interrupt-parent = <&pio>;
+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10/GPIO4 */
+ interrupt-names = "host-wake";
+ };
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pio {
+ vcc-pg-supply = <&reg_ldoa>;
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pb8_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart1 {
+ uart-has-rtscts;
+ pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4345c5";
+ interrupt-parent = <&pio>;
+ interrupts = <6 17 IRQ_TYPE_LEVEL_HIGH>; /* PG17/GPIO6 */
+ device-wakeup-gpios = <&pio 6 16 GPIO_ACTIVE_HIGH>; /* PG16/GPIO7 */
+ shutdown-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18/GPIO5 */
+ max-speed = <1500000>;
+ vbat-supply = <&reg_dldo1>;
+ vddio-supply = <&reg_aldo3>;
+ };
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_vbus_power-supply = <&ac_power_supply>;
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts
new file mode 100644
index 000000000000..690bfa35a548
--- /dev/null
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+// Copyright (C) 2022 Samuel Holland <[email protected]>
+
+/dts-v1/;
+
+#include "sun20i-d1-clockworkpi-v3.14.dts"
+
+/ {
+ model = "Clockwork DevTerm (R-01)";
+ compatible = "clockwork,r-01-devterm-v3.14",
+ "clockwork,r-01-clockworkpi-v3.14",
+ "allwinner,sun20i-d1";
+
+ fan {
+ compatible = "gpio-fan";
+ gpios = <&pio 3 10 GPIO_ACTIVE_HIGH>; /* PD10/GPIO41 */
+ gpio-fan,speed-map = <0 0>,
+ <6000 1>;
+ #cooling-cells = <2>;
+ };
+
+ i2c-gpio-0 {
+ compatible = "i2c-gpio";
+ sda-gpios = <&pio 3 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PD14/GPIO44 */
+ scl-gpios = <&pio 3 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PD15/GPIO45 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@54 {
+ compatible = "ti,adc101c";
+ reg = <0x54>;
+ interrupt-parent = <&pio>;
+ interrupts = <4 12 IRQ_TYPE_LEVEL_LOW>; /* PE12/GPIO35 */
+ vref-supply = <&reg_dldo2>;
+ };
+ };
+};
--
2.35.1

2022-08-15 07:16:17

[permalink] [raw]

Subject: Re: [PATCH 00/12] riscv: Allwinner D1 platform support

Hey Samuel,
Apologies for the last email, the first 5 patches in this series
didn't correctly land in my inbox and I skimmed & replied to the
wrong cover letter... I blame it being pre 8 AM ;)

On 15/08/2022 06:08, Samuel Holland wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> This series adds the Kconfig/defconfig plumbing and devicetrees for a
> range of Allwinner D1-based boards. Many features are already enabled,
> including USB, Ethernet, and WiFi.
>
> The SoC devicetree uses bindings from the following series which have
> not yet been merged:
> - SRAM controller:
> https://lore.kernel.org/lkml/[email protected]/
> - NVMEM cell bits property change:
> https://lore.kernel.org/lkml/[email protected]/
> - In-package LDO regulators:
> https://lore.kernel.org/lkml/[email protected]/
>
> All three of these are required to set the correct I/O domain voltages
> in the pin controller, which I would consider important to have in the
> initial version of the devicetree.
>
> The SoC devicetree does contain one small hack to avoid a dependency on
> the audio codec binding, since that is not ready yet: the codec node
> uses a bare "simple-mfd", "syscon" compatible.

I tried this series on top of both 6.0-rc1 & next, but I saw a shed
load of errors from dtbs_check. I'll take a look at the rest of the
series later on, but just FYI. This time I did at least read the
right cover letter and actually applied your dependent series..
/facepalm

I have been trying to get riscv down to 0 warnings and would not be
in favour of accepting patches that go in the other direction.
(This patchset currently produces about 47 new warnings)

Thanks,
Conor.
>
>
> Samuel Holland (12):
> MAINTAINERS: Match the sun20i family of Allwinner SoCs
> dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles
> dt-bindings: vendor-prefixes: Add Allwinner D1 board vendors
> dt-bindings: riscv: Add Allwinner D1 board compatibles
> riscv: Add the Allwinner SoC family Kconfig option
> riscv: dts: allwinner: Add the D1 SoC base devicetree
> riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree
> riscv: dts: allwinner: Add Sipeed Lichee RV devicetrees
> riscv: dts: allwinner: Add MangoPi MQ Pro devicetree
> riscv: dts: allwinner: Add Dongshan Nezha STU devicetree
> riscv: dts: allwinner: Add ClockworkPi and DevTerm devicetrees
> riscv: defconfig: Enable the Allwinner D1 platform and drivers
>
> .../devicetree/bindings/riscv/cpus.yaml | 2 +
> .../devicetree/bindings/riscv/sunxi.yaml | 64 ++
> .../devicetree/bindings/vendor-prefixes.yaml | 4 +
> MAINTAINERS | 2 +-
> arch/riscv/Kconfig.socs | 9 +
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/allwinner/Makefile | 10 +
> .../allwinner/sun20i-d1-clockworkpi-v3.14.dts | 242 +++++
> .../sun20i-d1-common-regulators.dtsi | 51 +
> .../dts/allwinner/sun20i-d1-devterm-v3.14.dts | 37 +
> .../sun20i-d1-dongshan-nezha-stu.dts | 114 +++
> .../sun20i-d1-lichee-rv-86-panel-480p.dts | 29 +
> .../sun20i-d1-lichee-rv-86-panel-720p.dts | 10 +
> .../sun20i-d1-lichee-rv-86-panel.dtsi | 92 ++
> .../allwinner/sun20i-d1-lichee-rv-dock.dts | 74 ++
> .../dts/allwinner/sun20i-d1-lichee-rv.dts | 84 ++
> .../allwinner/sun20i-d1-mangopi-mq-pro.dts | 128 +++
> .../boot/dts/allwinner/sun20i-d1-nezha.dts | 171 ++++
> arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 900 ++++++++++++++++++
> arch/riscv/configs/defconfig | 23 +-
> 20 files changed, 2045 insertions(+), 2 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/riscv/sunxi.yaml
> create mode 100644 arch/riscv/boot/dts/allwinner/Makefile
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
>
> --
> 2.35.1
>

2022-08-15 13:26:52

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

On Mon, 15 Aug 2022 00:08:09 -0500
Samuel Holland <[email protected]> wrote:

Hi,

thanks for all the efforts in getting those SoC peripherals supported!

> D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, as well as
> one HiFi 4 DSP. The SoC is based on a design that additionally contained
> a pair of Cortex A7's. For that reason, some peripherals are duplicated.

So because of this, the Allwinner R528 and T113 SoCs would share almost
everything in this file. Would it be useful to already split this DT up?
To have a base .dtsi, basically this file without /cpus and /soc/plic,
then have a RISC-V specific file with just those, including the base?
There is precedence for this across-arch(-directories) sharing with the
Raspberry Pi and Allwinner H3/H5 SoCs.

Or do you plan to leave that for when support for the ARM core versions is
actually submitted? But I don't think we need any extra *code* for that,
it's just the DT?

Cheers,
Andre.

>
> This devicetree includes all of the peripherals that already have a
> documented binding.
>
> Signed-off-by: Samuel Holland <[email protected]>
> ---
>
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/allwinner/Makefile | 1 +
> arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 900 +++++++++++++++++++
> 3 files changed, 902 insertions(+)
> create mode 100644 arch/riscv/boot/dts/allwinner/Makefile
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index ff174996cdfd..f292e31bdb2c 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -1,4 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0
> +subdir-y += allwinner
> subdir-y += sifive
> subdir-y += starfive
> subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile
> new file mode 100644
> index 000000000000..f66554cd5c45
> --- /dev/null
> +++ b/arch/riscv/boot/dts/allwinner/Makefile
> @@ -0,0 +1 @@
> +# SPDX-License-Identifier: GPL-2.0
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
> new file mode 100644
> index 000000000000..d1429274f22e
> --- /dev/null
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
> @@ -0,0 +1,900 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
> +
> +#include <dt-bindings/clock/sun6i-rtc.h>
> +#include <dt-bindings/clock/sun8i-de2.h>
> +#include <dt-bindings/clock/sun8i-tcon-top.h>
> +#include <dt-bindings/clock/sun20i-d1-ccu.h>
> +#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/reset/sun8i-de2.h>
> +#include <dt-bindings/reset/sun20i-d1-ccu.h>
> +#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
> +#include <dt-bindings/thermal/thermal.h>
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpus {
> + timebase-frequency = <24000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + compatible = "thead,c906", "riscv";
> + device_type = "cpu";
> + reg = <0>;
> + clocks = <&ccu CLK_RISCV>;
> + clock-frequency = <24000000>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <256>;
> + d-cache-size = <32768>;
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + mmu-type = "riscv,sv39";
> + riscv,isa = "rv64imafdc";
> + #cooling-cells = <2>;
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + };
> + };
> + };
> +
> + de: display-engine {
> + compatible = "allwinner,sun20i-d1-display-engine";
> + allwinner,pipelines = <&mixer0>, <&mixer1>;
> + status = "disabled";
> + };
> +
> + osc24M: osc24M-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + clock-output-names = "osc24M";
> + #clock-cells = <0>;
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + ranges;
> + interrupt-parent = <&plic>;
> + dma-noncoherent;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + dsp_wdt: watchdog@1700400 {
> + compatible = "allwinner,sun20i-d1-wdt";
> + reg = <0x1700400 0x20>;
> + interrupts = <138 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>, <&rtc CLK_OSC32K>;
> + clock-names = "hosc", "losc";
> + status = "reserved";
> + };
> +
> + pio: pinctrl@2000000 {
> + compatible = "allwinner,sun20i-d1-pinctrl";
> + reg = <0x2000000 0x800>;
> + interrupts = <85 IRQ_TYPE_LEVEL_HIGH>,
> + <87 IRQ_TYPE_LEVEL_HIGH>,
> + <89 IRQ_TYPE_LEVEL_HIGH>,
> + <91 IRQ_TYPE_LEVEL_HIGH>,
> + <93 IRQ_TYPE_LEVEL_HIGH>,
> + <95 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_APB0>,
> + <&osc24M>,
> + <&rtc CLK_OSC32K>;
> + clock-names = "apb", "hosc", "losc";
> + gpio-controller;
> + interrupt-controller;
> + #gpio-cells = <3>;
> + #interrupt-cells = <3>;
> +
> + /omit-if-no-ref/
> + i2c0_pb10_pins: i2c0-pb10-pins {
> + pins = "PB10", "PB11";
> + function = "i2c0";
> + };
> +
> + /omit-if-no-ref/
> + i2c2_pb0_pins: i2c2-pb0-pins {
> + pins = "PB0", "PB1";
> + function = "i2c2";
> + };
> +
> + /omit-if-no-ref/
> + lcd_rgb666_pins: lcd-rgb666-pins {
> + pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
> + "PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
> + "PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
> + "PD18", "PD19", "PD20", "PD21";
> + function = "lcd0";
> + };
> +
> + /omit-if-no-ref/
> + mmc0_pins: mmc0-pins {
> + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
> + function = "mmc0";
> + };
> +
> + /omit-if-no-ref/
> + mmc1_pins: mmc1-pins {
> + pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
> + function = "mmc1";
> + };
> +
> + /omit-if-no-ref/
> + mmc2_pins: mmc2-pins {
> + pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
> + function = "mmc2";
> + };
> +
> + /omit-if-no-ref/
> + rgmii_pe_pins: rgmii-pe-pins {
> + pins = "PE0", "PE1", "PE2", "PE3", "PE4",
> + "PE5", "PE6", "PE7", "PE8", "PE9",
> + "PE11", "PE12", "PE13", "PE14", "PE15";
> + function = "emac";
> + };
> +
> + /omit-if-no-ref/
> + rmii_pe_pins: rmii-pe-pins {
> + pins = "PE0", "PE1", "PE2", "PE3", "PE4",
> + "PE5", "PE6", "PE7", "PE8", "PE9";
> + function = "emac";
> + };
> +
> + /omit-if-no-ref/
> + uart0_pb8_pins: uart0-pb8-pins {
> + pins = "PB8", "PB9";
> + function = "uart0";
> + };
> +
> + /omit-if-no-ref/
> + uart1_pg6_pins: uart1-pg6-pins {
> + pins = "PG6", "PG7";
> + function = "uart1";
> + };
> +
> + /omit-if-no-ref/
> + uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins {
> + pins = "PG8", "PG9";
> + function = "uart1";
> + };
> + };
> +
> + ccu: clock-controller@2001000 {
> + compatible = "allwinner,sun20i-d1-ccu";
> + reg = <0x2001000 0x1000>;
> + clocks = <&osc24M>,
> + <&rtc CLK_OSC32K>,
> + <&rtc CLK_IOSC>;
> + clock-names = "hosc", "losc", "iosc";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + lradc: keys@2009800 {
> + compatible = "allwinner,sun20i-d1-lradc",
> + "allwinner,sun50i-r329-lradc";
> + reg = <0x2009800 0x400>;
> + interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_LRADC>;
> + resets = <&ccu RST_BUS_LRADC>;
> + status = "disabled";
> + };
> +
> + codec: audio-codec@2030000 {
> + compatible = "simple-mfd", "syscon";
> + reg = <0x2030000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + regulators@2030348 {
> + compatible = "allwinner,sun20i-d1-analog-ldos";
> + reg = <0x2030348 0x4>;
> + nvmem-cells = <&bg_trim>;
> + nvmem-cell-names = "bg_trim";
> +
> + reg_aldo: aldo {
> + };
> +
> + reg_hpldo: hpldo {
> + };
> + };
> + };
> +
> + i2s0: i2s@2032000 {
> + compatible = "allwinner,sun20i-d1-i2s",
> + "allwinner,sun50i-r329-i2s";
> + reg = <0x2032000 0x1000>;
> + interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2S0>,
> + <&ccu CLK_I2S0>;
> + clock-names = "apb", "mod";
> + resets = <&ccu RST_BUS_I2S0>;
> + dmas = <&dma 3>, <&dma 3>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + #sound-dai-cells = <0>;
> + };
> +
> + i2s1: i2s@2033000 {
> + compatible = "allwinner,sun20i-d1-i2s",
> + "allwinner,sun50i-r329-i2s";
> + reg = <0x2033000 0x1000>;
> + interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2S1>,
> + <&ccu CLK_I2S1>;
> + clock-names = "apb", "mod";
> + resets = <&ccu RST_BUS_I2S1>;
> + dmas = <&dma 4>, <&dma 4>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + #sound-dai-cells = <0>;
> + };
> +
> + i2s2: i2s@2034000 {
> + compatible = "allwinner,sun20i-d1-i2s",
> + "allwinner,sun50i-r329-i2s";
> + reg = <0x2034000 0x1000>;
> + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2S2>,
> + <&ccu CLK_I2S2>;
> + clock-names = "apb", "mod";
> + resets = <&ccu RST_BUS_I2S2>;
> + dmas = <&dma 5>, <&dma 5>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + #sound-dai-cells = <0>;
> + };
> +
> + timer: timer@2050000 {
> + compatible = "allwinner,sun20i-d1-timer",
> + "allwinner,sun8i-a23-timer";
> + reg = <0x2050000 0xa0>;
> + interrupts = <75 IRQ_TYPE_LEVEL_HIGH>,
> + <76 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>;
> + };
> +
> + wdt: watchdog@20500a0 {
> + compatible = "allwinner,sun20i-d1-wdt-reset",
> + "allwinner,sun20i-d1-wdt";
> + reg = <0x20500a0 0x20>;
> + interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>, <&rtc CLK_OSC32K>;
> + clock-names = "hosc", "losc";
> + status = "reserved";
> + };
> +
> + uart0: serial@2500000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x2500000 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_UART0>;
> + resets = <&ccu RST_BUS_UART0>;
> + dmas = <&dma 14>, <&dma 14>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart1: serial@2500400 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x2500400 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_UART1>;
> + resets = <&ccu RST_BUS_UART1>;
> + dmas = <&dma 15>, <&dma 15>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart2: serial@2500800 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x2500800 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_UART2>;
> + resets = <&ccu RST_BUS_UART2>;
> + dmas = <&dma 16>, <&dma 16>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart3: serial@2500c00 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x2500c00 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_UART3>;
> + resets = <&ccu RST_BUS_UART3>;
> + dmas = <&dma 17>, <&dma 17>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart4: serial@2501000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x2501000 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_UART4>;
> + resets = <&ccu RST_BUS_UART4>;
> + dmas = <&dma 18>, <&dma 18>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart5: serial@2501400 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x2501400 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_UART5>;
> + resets = <&ccu RST_BUS_UART5>;
> + dmas = <&dma 19>, <&dma 19>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + i2c0: i2c@2502000 {
> + compatible = "allwinner,sun20i-d1-i2c",
> + "allwinner,sun8i-v536-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x2502000 0x400>;
> + interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C0>;
> + resets = <&ccu RST_BUS_I2C0>;
> + dmas = <&dma 43>, <&dma 43>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c1: i2c@2502400 {
> + compatible = "allwinner,sun20i-d1-i2c",
> + "allwinner,sun8i-v536-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x2502400 0x400>;
> + interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C1>;
> + resets = <&ccu RST_BUS_I2C1>;
> + dmas = <&dma 44>, <&dma 44>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c2: i2c@2502800 {
> + compatible = "allwinner,sun20i-d1-i2c",
> + "allwinner,sun8i-v536-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x2502800 0x400>;
> + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C2>;
> + resets = <&ccu RST_BUS_I2C2>;
> + dmas = <&dma 45>, <&dma 45>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c3: i2c@2502c00 {
> + compatible = "allwinner,sun20i-d1-i2c",
> + "allwinner,sun8i-v536-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x2502c00 0x400>;
> + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C3>;
> + resets = <&ccu RST_BUS_I2C3>;
> + dmas = <&dma 46>, <&dma 46>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + syscon: syscon@3000000 {
> + compatible = "allwinner,sun20i-d1-system-control";
> + reg = <0x3000000 0x1000>;
> + ranges;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + regulators@3000150 {
> + compatible = "allwinner,sun20i-d1-system-ldos";
> + reg = <0x3000150 0x4>;
> +
> + reg_ldoa: ldoa {
> + };
> +
> + reg_ldob: ldob {
> + };
> + };
> + };
> +
> + dma: dma-controller@3002000 {
> + compatible = "allwinner,sun20i-d1-dma";
> + reg = <0x3002000 0x1000>;
> + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
> + clock-names = "bus", "mbus";
> + resets = <&ccu RST_BUS_DMA>;
> + dma-channels = <16>;
> + dma-requests = <48>;
> + #dma-cells = <1>;
> + };
> +
> + sid: efuse@3006000 {
> + compatible = "allwinner,sun20i-d1-sid";
> + reg = <0x3006000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + ths_calib: ths-calib@14 {
> + reg = <0x14 0x4>;
> + };
> +
> + bg_trim: bg-trim@28 {
> + reg = <0x28 0x4>;
> + bits = <16 8>;
> + };
> + };
> +
> + mbus: dram-controller@3102000 {
> + compatible = "allwinner,sun20i-d1-mbus";
> + reg = <0x3102000 0x1000>,
> + <0x3103000 0x1000>;
> + reg-names = "mbus", "dram";
> + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_MBUS>,
> + <&ccu CLK_DRAM>,
> + <&ccu CLK_BUS_DRAM>;
> + clock-names = "mbus", "dram", "bus";
> + dma-ranges = <0 0x40000000 0x80000000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + #interconnect-cells = <1>;
> + };
> +
> + mmc0: mmc@4020000 {
> + compatible = "allwinner,sun20i-d1-mmc";
> + reg = <0x4020000 0x1000>;
> + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
> + clock-names = "ahb", "mmc";
> + resets = <&ccu RST_BUS_MMC0>;
> + reset-names = "ahb";
> + cap-sd-highspeed;
> + max-frequency = <150000000>;
> + no-mmc;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc1: mmc@4021000 {
> + compatible = "allwinner,sun20i-d1-mmc";
> + reg = <0x4021000 0x1000>;
> + interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
> + clock-names = "ahb", "mmc";
> + resets = <&ccu RST_BUS_MMC1>;
> + reset-names = "ahb";
> + cap-sd-highspeed;
> + max-frequency = <150000000>;
> + no-mmc;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc2: mmc@4022000 {
> + compatible = "allwinner,sun20i-d1-emmc",
> + "allwinner,sun50i-a100-emmc";
> + reg = <0x4022000 0x1000>;
> + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
> + clock-names = "ahb", "mmc";
> + resets = <&ccu RST_BUS_MMC2>;
> + reset-names = "ahb";
> + cap-mmc-highspeed;
> + max-frequency = <150000000>;
> + mmc-ddr-1_8v;
> + mmc-ddr-3_3v;
> + no-sd;
> + no-sdio;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + usb_otg: usb@4100000 {
> + compatible = "allwinner,sun20i-d1-musb",
> + "allwinner,sun8i-a33-musb";
> + reg = <0x4100000 0x400>;
> + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "mc";
> + clocks = <&ccu CLK_BUS_OTG>;
> + resets = <&ccu RST_BUS_OTG>;
> + extcon = <&usbphy 0>;
> + phys = <&usbphy 0>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + usbphy: phy@4100400 {
> + compatible = "allwinner,sun20i-d1-usb-phy";
> + reg = <0x4100400 0x100>,
> + <0x4101800 0x100>,
> + <0x4200800 0x100>;
> + reg-names = "phy_ctrl",
> + "pmu0",
> + "pmu1";
> + clocks = <&osc24M>,
> + <&osc24M>;
> + clock-names = "usb0_phy",
> + "usb1_phy";
> + resets = <&ccu RST_USB_PHY0>,
> + <&ccu RST_USB_PHY1>;
> + reset-names = "usb0_reset",
> + "usb1_reset";
> + status = "disabled";
> + #phy-cells = <1>;
> + };
> +
> + ehci0: usb@4101000 {
> + compatible = "allwinner,sun20i-d1-ehci",
> + "generic-ehci";
> + reg = <0x4101000 0x100>;
> + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_OHCI0>,
> + <&ccu CLK_BUS_EHCI0>,
> + <&ccu CLK_USB_OHCI0>;
> + resets = <&ccu RST_BUS_OHCI0>,
> + <&ccu RST_BUS_EHCI0>;
> + phys = <&usbphy 0>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + ohci0: usb@4101400 {
> + compatible = "allwinner,sun20i-d1-ohci",
> + "generic-ohci";
> + reg = <0x4101400 0x100>;
> + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_OHCI0>,
> + <&ccu CLK_USB_OHCI0>;
> + resets = <&ccu RST_BUS_OHCI0>;
> + phys = <&usbphy 0>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + ehci1: usb@4200000 {
> + compatible = "allwinner,sun20i-d1-ehci",
> + "generic-ehci";
> + reg = <0x4200000 0x100>;
> + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_OHCI1>,
> + <&ccu CLK_BUS_EHCI1>,
> + <&ccu CLK_USB_OHCI1>;
> + resets = <&ccu RST_BUS_OHCI1>,
> + <&ccu RST_BUS_EHCI1>;
> + phys = <&usbphy 1>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + ohci1: usb@4200400 {
> + compatible = "allwinner,sun20i-d1-ohci",
> + "generic-ohci";
> + reg = <0x4200400 0x100>;
> + interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_OHCI1>,
> + <&ccu CLK_USB_OHCI1>;
> + resets = <&ccu RST_BUS_OHCI1>;
> + phys = <&usbphy 1>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + emac: ethernet@4500000 {
> + compatible = "allwinner,sun20i-d1-emac",
> + "allwinner,sun50i-a64-emac";
> + reg = <0x4500000 0x10000>;
> + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq";
> + clocks = <&ccu CLK_BUS_EMAC>;
> + clock-names = "stmmaceth";
> + resets = <&ccu RST_BUS_EMAC>;
> + reset-names = "stmmaceth";
> + syscon = <&syscon>;
> + status = "disabled";
> +
> + mdio: mdio {
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + display_clocks: clock-controller@5000000 {
> + compatible = "allwinner,sun20i-d1-de2-clk",
> + "allwinner,sun50i-h5-de2-clk";
> + reg = <0x5000000 0x10000>;
> + clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
> + clock-names = "bus", "mod";
> + resets = <&ccu RST_BUS_DE>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + mixer0: mixer@5100000 {
> + compatible = "allwinner,sun20i-d1-de2-mixer-0";
> + reg = <0x5100000 0x100000>;
> + clocks = <&display_clocks CLK_BUS_MIXER0>,
> + <&display_clocks CLK_MIXER0>;
> + clock-names = "bus", "mod";
> + resets = <&display_clocks RST_MIXER0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mixer0_out: port@1 {
> + reg = <1>;
> +
> + mixer0_out_tcon_top_mixer0: endpoint {
> + remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
> + };
> + };
> + };
> + };
> +
> + mixer1: mixer@5200000 {
> + compatible = "allwinner,sun20i-d1-de2-mixer-1";
> + reg = <0x5200000 0x100000>;
> + clocks = <&display_clocks CLK_BUS_MIXER1>,
> + <&display_clocks CLK_MIXER1>;
> + clock-names = "bus", "mod";
> + resets = <&display_clocks RST_MIXER1>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mixer1_out: port@1 {
> + reg = <1>;
> +
> + mixer1_out_tcon_top_mixer1: endpoint {
> + remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
> + };
> + };
> + };
> + };
> +
> + tcon_top: tcon-top@5460000 {
> + compatible = "allwinner,sun20i-d1-tcon-top";
> + reg = <0x5460000 0x1000>;
> + clocks = <&ccu CLK_BUS_DPSS_TOP>,
> + <&ccu CLK_TCON_TV>,
> + <&ccu CLK_TVE>,
> + <&ccu CLK_MIPI_DSI>;
> + clock-names = "bus", "tcon-tv0", "tve0", "dsi";
> + clock-output-names = "tcon-top-tv0", "tcon-top-dsi";
> + resets = <&ccu RST_BUS_DPSS_TOP>;
> + #clock-cells = <1>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_top_mixer0_in: port@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_top_mixer0_in_mixer0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
> + };
> + };
> +
> + tcon_top_mixer0_out: port@1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
> + };
> +
> + tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
> + reg = <2>;
> + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
> + };
> + };
> +
> + tcon_top_mixer1_in: port@2 {
> + reg = <2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_top_mixer1_in_mixer1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
> + };
> + };
> +
> + tcon_top_mixer1_out: port@3 {
> + reg = <3>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>;
> + };
> +
> + tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
> + reg = <2>;
> + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
> + };
> + };
> +
> + tcon_top_hdmi_in: port@4 {
> + reg = <4>;
> +
> + tcon_top_hdmi_in_tcon_tv0: endpoint {
> + remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>;
> + };
> + };
> +
> + tcon_top_hdmi_out: port@5 {
> + reg = <5>;
> + };
> + };
> + };
> +
> + tcon_lcd0: lcd-controller@5461000 {
> + compatible = "allwinner,sun20i-d1-tcon-lcd";
> + reg = <0x5461000 0x1000>;
> + interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_TCON_LCD0>,
> + <&ccu CLK_TCON_LCD0>;
> + clock-names = "ahb", "tcon-ch0";
> + clock-output-names = "tcon-pixel-clock";
> + resets = <&ccu RST_BUS_TCON_LCD0>,
> + <&ccu RST_BUS_LVDS0>;
> + reset-names = "lcd", "lvds";
> + #clock-cells = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_lcd0_in: port@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
> + };
> +
> + tcon_lcd0_in_tcon_top_mixer1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>;
> + };
> + };
> +
> + tcon_lcd0_out: port@1 {
> + reg = <1>;
> + };
> + };
> + };
> +
> + tcon_tv0: lcd-controller@5470000 {
> + compatible = "allwinner,sun20i-d1-tcon-tv";
> + reg = <0x5470000 0x1000>;
> + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_TCON_TV>,
> + <&tcon_top CLK_TCON_TOP_TV0>;
> + clock-names = "ahb", "tcon-ch1";
> + resets = <&ccu RST_BUS_TCON_TV>;
> + reset-names = "lcd";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_tv0_in: port@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
> + };
> +
> + tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
> + };
> + };
> +
> + tcon_tv0_out: port@1 {
> + reg = <1>;
> +
> + tcon_tv0_out_tcon_top_hdmi: endpoint {
> + remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
> + };
> + };
> + };
> + };
> +
> + riscv_wdt: watchdog@6011000 {
> + compatible = "allwinner,sun20i-d1-wdt";
> + reg = <0x6011000 0x20>;
> + interrupts = <147 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>, <&rtc CLK_OSC32K>;
> + clock-names = "hosc", "losc";
> + };
> +
> + r_ccu: clock-controller@7010000 {
> + compatible = "allwinner,sun20i-d1-r-ccu";
> + reg = <0x7010000 0x400>;
> + clocks = <&osc24M>,
> + <&rtc CLK_OSC32K>,
> + <&rtc CLK_IOSC>,
> + <&ccu CLK_PLL_PERIPH0_DIV3>;
> + clock-names = "hosc", "losc", "iosc", "pll-periph";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + rtc: rtc@7090000 {
> + compatible = "allwinner,sun20i-d1-rtc",
> + "allwinner,sun50i-r329-rtc";
> + reg = <0x7090000 0x400>;
> + interrupts = <160 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&r_ccu CLK_BUS_R_RTC>,
> + <&osc24M>,
> + <&r_ccu CLK_R_AHB>;
> + clock-names = "bus", "hosc", "ahb";
> + #clock-cells = <1>;
> + };
> +
> + plic: interrupt-controller@10000000 {
> + compatible = "allwinner,sun20i-d1-plic",
> + "thead,c900-plic";
> + reg = <0x10000000 0x4000000>;
> + interrupts-extended = <&cpu0_intc 11>,
> + <&cpu0_intc 9>;
> + interrupt-controller;
> + riscv,ndev = <176>;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + };
> + };
> +};

2022-08-15 17:13:02

[permalink] [raw]

Subject: Re: [PATCH 05/12] riscv: Add the Allwinner SoC family Kconfig option

On 15/08/2022 06:08, Samuel Holland wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Allwinner manufactures the sunxi family of application processors. This
> includes the "sun8i" series of ARMv7 SoCs, the "sun50i" series of ARMv8
> SoCs, and now the "sun20i" series of 64-bit RISC-V SoCs.
>
> The first SoC in the sun20i series is D1, containing a single T-HEAD
> C906 core. D1s is a low-pin-count variant of D1 with co-packaged DRAM.
>
> Most peripherals are shared across the entire chip family. In fact, the
> ARMv7 T113 SoC is pin-compatible and almost entirely register-compatible
> with the D1s.
>
> This means many existing device drivers can be reused. To facilitate
> this reuse, name the symbol ARCH_SUNXI, since that is what the existing
> drivers have as their dependency.

Hey Samuel,
I think this and patch 12/12 with the defconfig changes should be
deferred until post LPC (which still leaves plenty of time for
making the 6.1 merge window). We already have like 4 different
approaches between the existing SOC_FOO symbols & two more when
D1 stuff and the Renesas stuff is considered.

Plan is to decide at LPC on one approach for what to do with
Kconfig.socs & to me it seems like a good idea to do what's being
done here - it's likely that further arm vendors will move and
keeping the common symbols makes a lot of sense to me...

Thanks,
Conor.

>
> Signed-off-by: Samuel Holland <[email protected]>
> ---
>
> arch/riscv/Kconfig.socs | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 69774bb362d6..1caacbfac1a5 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -1,5 +1,14 @@
> menu "SoC selection"
>
> +config ARCH_SUNXI
> + bool "Allwinner sun20i SoCs"
> + select ERRATA_THEAD if MMU && !XIP_KERNEL
> + select SIFIVE_PLIC
> + select SUN4I_TIMER
> + help
> + This enables support for Allwinner sun20i platform hardware,
> + including boards based on the D1 and D1s SoCs.
> +
> config SOC_MICROCHIP_POLARFIRE
> bool "Microchip PolarFire SoCs"
> select MCHP_CLK_MPFS
> --
> 2.35.1
>

2022-08-15 17:24:37

[permalink] [raw]

Subject: Re: [PATCH 01/12] MAINTAINERS: Match the sun20i family of Allwinner SoCs

Am Montag, 15. August 2022, 07:08:04 CEST schrieb Samuel Holland:
> Allwinner sunxi SoCs with a RISC-V CPU use the sun20i designator. Match
> that pattern in addition to the designators for 32 and 64-bit ARM SoCs.
>
> Signed-off-by: Samuel Holland <[email protected]>
> ---
>
> MAINTAINERS | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 8a5012ba6ff9..59bcaa405a6f 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1800,7 +1800,7 @@ F: drivers/pinctrl/sunxi/
> F: drivers/soc/sunxi/
> N: allwinner
> N: sun[x456789]i
> -N: sun50i
> +N: sun[25]0i
>
> ARM/Amlogic Meson SoC CLOCK FRAMEWORK
> M: Neil Armstrong <[email protected]>
>

Reviewed-by: Heiko Stuebner <[email protected]>

2022-08-15 17:25:36

[permalink] [raw]

Subject: Re: [PATCH 02/12] dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles

Am Montag, 15. August 2022, 07:08:05 CEST schrieb Samuel Holland:
> The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor.
> Notably, the C906 core is used in the Allwinner D1 SoC.
>
> Signed-off-by: Samuel Holland <[email protected]>

Reviewed-by: Heiko Stuebner <[email protected]>

2022-08-15 17:27:15

[permalink] [raw]

Subject: Re: [PATCH 03/12] dt-bindings: vendor-prefixes: Add Allwinner D1 board vendors

Am Montag, 15. August 2022, 07:08:06 CEST schrieb Samuel Holland:
> Some boards using the Allwinner D1 SoC are made by vendors not
> previously documented.
>
> Clockwork Tech LLC (https://www.clockworkpi.com/) manufactures the
> ClockworkPi and DevTerm boards.
>
> Beijing Widora Technology Co., Ltd. (https://mangopi.cc/) manufactures
> the MangoPi family of boards.
>
> Signed-off-by: Samuel Holland <[email protected]>

Reviewed-by: Heiko Stuebner <[email protected]>

2022-08-15 17:27:28

[permalink] [raw]

Subject: Re: [PATCH 05/12] riscv: Add the Allwinner SoC family Kconfig option

Am Montag, 15. August 2022, 07:08:08 CEST schrieb Samuel Holland:
> Allwinner manufactures the sunxi family of application processors. This
> includes the "sun8i" series of ARMv7 SoCs, the "sun50i" series of ARMv8
> SoCs, and now the "sun20i" series of 64-bit RISC-V SoCs.
>
> The first SoC in the sun20i series is D1, containing a single T-HEAD
> C906 core. D1s is a low-pin-count variant of D1 with co-packaged DRAM.
>
> Most peripherals are shared across the entire chip family. In fact, the
> ARMv7 T113 SoC is pin-compatible and almost entirely register-compatible
> with the D1s.
>
> This means many existing device drivers can be reused. To facilitate
> this reuse, name the symbol ARCH_SUNXI, since that is what the existing
> drivers have as their dependency.
>
> Signed-off-by: Samuel Holland <[email protected]>

Reviewed-by: Heiko Stuebner <[email protected]>
Tested-by: Heiko Stuebner <[email protected]>

2022-08-15 17:38:03

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

On 15/08/2022 14:11, Andre Przywara wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Mon, 15 Aug 2022 00:08:09 -0500
> Samuel Holland <[email protected]> wrote:
>
> Hi,
>
> thanks for all the efforts in getting those SoC peripherals supported!
>
>> D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, as well as
>> one HiFi 4 DSP. The SoC is based on a design that additionally contained
>> a pair of Cortex A7's. For that reason, some peripherals are duplicated.
>
> So because of this, the Allwinner R528 and T113 SoCs would share almost
> everything in this file. Would it be useful to already split this DT up?
> To have a base .dtsi, basically this file without /cpus and /soc/plic,
> then have a RISC-V specific file with just those, including the base?
> There is precedence for this across-arch(-directories) sharing with the
> Raspberry Pi and Allwinner H3/H5 SoCs.

For those playing along at home, one example is the arm64 bananapi m2
dts which looks like:
> /dts-v1/;
> #include "sun50i-h5.dtsi"
> #include "sun50i-h5-cpu-opp.dtsi"
> #include <arm/sunxi-bananapi-m2-plus-v1.2.dtsi>
>
> / {
> model = "Banana Pi BPI-M2-Plus v1.2 H5";
> compatible = "bananapi,bpi-m2-plus-v1.2", "allwinner,sun50i-h5";
> };

I think this is a pretty good idea, and putting in the modularity up
front seems logical to me, so when the arm one does eventually get
added it can be done by only touching a single arch.

Thanks,
Conor.
>
> Or do you plan to leave that for when support for the ARM core versions is
> actually submitted? But I don't think we need any extra *code* for that,
> it's just the DT?
>
> Cheers,
> Andre.
>
>
>>
>> This devicetree includes all of the peripherals that already have a
>> documented binding.
>>
>> Signed-off-by: Samuel Holland <[email protected]>
>> ---
>>
>> arch/riscv/boot/dts/Makefile | 1 +
>> arch/riscv/boot/dts/allwinner/Makefile | 1 +
>> arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 900 +++++++++++++++++++
>> 3 files changed, 902 insertions(+)
>> create mode 100644 arch/riscv/boot/dts/allwinner/Makefile
>> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
>>
>> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
>> index ff174996cdfd..f292e31bdb2c 100644
>> --- a/arch/riscv/boot/dts/Makefile
>> +++ b/arch/riscv/boot/dts/Makefile
>> @@ -1,4 +1,5 @@
>> # SPDX-License-Identifier: GPL-2.0
>> +subdir-y += allwinner
>> subdir-y += sifive
>> subdir-y += starfive
>> subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
>> diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile
>> new file mode 100644
>> index 000000000000..f66554cd5c45
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/allwinner/Makefile
>> @@ -0,0 +1 @@
>> +# SPDX-License-Identifier: GPL-2.0
>> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
>> new file mode 100644
>> index 000000000000..d1429274f22e
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
>> @@ -0,0 +1,900 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
>> +// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
>> +
>> +#include <dt-bindings/clock/sun6i-rtc.h>
>> +#include <dt-bindings/clock/sun8i-de2.h>
>> +#include <dt-bindings/clock/sun8i-tcon-top.h>
>> +#include <dt-bindings/clock/sun20i-d1-ccu.h>
>> +#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +#include <dt-bindings/reset/sun8i-de2.h>
>> +#include <dt-bindings/reset/sun20i-d1-ccu.h>
>> +#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
>> +#include <dt-bindings/thermal/thermal.h>
>> +
>> +/ {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + cpus {
>> + timebase-frequency = <24000000>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu0: cpu@0 {
>> + compatible = "thead,c906", "riscv";
>> + device_type = "cpu";
>> + reg = <0>;
>> + clocks = <&ccu CLK_RISCV>;
>> + clock-frequency = <24000000>;
>> + d-cache-block-size = <64>;
>> + d-cache-sets = <256>;
>> + d-cache-size = <32768>;
>> + i-cache-block-size = <64>;
>> + i-cache-sets = <128>;
>> + i-cache-size = <32768>;
>> + mmu-type = "riscv,sv39";
>> + riscv,isa = "rv64imafdc";
>> + #cooling-cells = <2>;
>> +
>> + cpu0_intc: interrupt-controller {
>> + compatible = "riscv,cpu-intc";
>> + interrupt-controller;
>> + #address-cells = <0>;
>> + #interrupt-cells = <1>;
>> + };
>> + };
>> + };
>> +
>> + de: display-engine {
>> + compatible = "allwinner,sun20i-d1-display-engine";
>> + allwinner,pipelines = <&mixer0>, <&mixer1>;
>> + status = "disabled";
>> + };
>> +
>> + osc24M: osc24M-clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <24000000>;
>> + clock-output-names = "osc24M";
>> + #clock-cells = <0>;
>> + };
>> +
>> + soc {
>> + compatible = "simple-bus";
>> + ranges;
>> + interrupt-parent = <&plic>;
>> + dma-noncoherent;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + dsp_wdt: watchdog@1700400 {
>> + compatible = "allwinner,sun20i-d1-wdt";
>> + reg = <0x1700400 0x20>;
>> + interrupts = <138 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&osc24M>, <&rtc CLK_OSC32K>;
>> + clock-names = "hosc", "losc";
>> + status = "reserved";
>> + };
>> +
>> + pio: pinctrl@2000000 {
>> + compatible = "allwinner,sun20i-d1-pinctrl";
>> + reg = <0x2000000 0x800>;
>> + interrupts = <85 IRQ_TYPE_LEVEL_HIGH>,
>> + <87 IRQ_TYPE_LEVEL_HIGH>,
>> + <89 IRQ_TYPE_LEVEL_HIGH>,
>> + <91 IRQ_TYPE_LEVEL_HIGH>,
>> + <93 IRQ_TYPE_LEVEL_HIGH>,
>> + <95 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_APB0>,
>> + <&osc24M>,
>> + <&rtc CLK_OSC32K>;
>> + clock-names = "apb", "hosc", "losc";
>> + gpio-controller;
>> + interrupt-controller;
>> + #gpio-cells = <3>;
>> + #interrupt-cells = <3>;
>> +
>> + /omit-if-no-ref/
>> + i2c0_pb10_pins: i2c0-pb10-pins {
>> + pins = "PB10", "PB11";
>> + function = "i2c0";
>> + };
>> +
>> + /omit-if-no-ref/
>> + i2c2_pb0_pins: i2c2-pb0-pins {
>> + pins = "PB0", "PB1";
>> + function = "i2c2";
>> + };
>> +
>> + /omit-if-no-ref/
>> + lcd_rgb666_pins: lcd-rgb666-pins {
>> + pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
>> + "PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
>> + "PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
>> + "PD18", "PD19", "PD20", "PD21";
>> + function = "lcd0";
>> + };
>> +
>> + /omit-if-no-ref/
>> + mmc0_pins: mmc0-pins {
>> + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
>> + function = "mmc0";
>> + };
>> +
>> + /omit-if-no-ref/
>> + mmc1_pins: mmc1-pins {
>> + pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
>> + function = "mmc1";
>> + };
>> +
>> + /omit-if-no-ref/
>> + mmc2_pins: mmc2-pins {
>> + pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
>> + function = "mmc2";
>> + };
>> +
>> + /omit-if-no-ref/
>> + rgmii_pe_pins: rgmii-pe-pins {
>> + pins = "PE0", "PE1", "PE2", "PE3", "PE4",
>> + "PE5", "PE6", "PE7", "PE8", "PE9",
>> + "PE11", "PE12", "PE13", "PE14", "PE15";
>> + function = "emac";
>> + };
>> +
>> + /omit-if-no-ref/
>> + rmii_pe_pins: rmii-pe-pins {
>> + pins = "PE0", "PE1", "PE2", "PE3", "PE4",
>> + "PE5", "PE6", "PE7", "PE8", "PE9";
>> + function = "emac";
>> + };
>> +
>> + /omit-if-no-ref/
>> + uart0_pb8_pins: uart0-pb8-pins {
>> + pins = "PB8", "PB9";
>> + function = "uart0";
>> + };
>> +
>> + /omit-if-no-ref/
>> + uart1_pg6_pins: uart1-pg6-pins {
>> + pins = "PG6", "PG7";
>> + function = "uart1";
>> + };
>> +
>> + /omit-if-no-ref/
>> + uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins {
>> + pins = "PG8", "PG9";
>> + function = "uart1";
>> + };
>> + };
>> +
>> + ccu: clock-controller@2001000 {
>> + compatible = "allwinner,sun20i-d1-ccu";
>> + reg = <0x2001000 0x1000>;
>> + clocks = <&osc24M>,
>> + <&rtc CLK_OSC32K>,
>> + <&rtc CLK_IOSC>;
>> + clock-names = "hosc", "losc", "iosc";
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + };
>> +
>> + lradc: keys@2009800 {
>> + compatible = "allwinner,sun20i-d1-lradc",
>> + "allwinner,sun50i-r329-lradc";
>> + reg = <0x2009800 0x400>;
>> + interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_LRADC>;
>> + resets = <&ccu RST_BUS_LRADC>;
>> + status = "disabled";
>> + };
>> +
>> + codec: audio-codec@2030000 {
>> + compatible = "simple-mfd", "syscon";
>> + reg = <0x2030000 0x1000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + regulators@2030348 {
>> + compatible = "allwinner,sun20i-d1-analog-ldos";
>> + reg = <0x2030348 0x4>;
>> + nvmem-cells = <&bg_trim>;
>> + nvmem-cell-names = "bg_trim";
>> +
>> + reg_aldo: aldo {
>> + };
>> +
>> + reg_hpldo: hpldo {
>> + };
>> + };
>> + };
>> +
>> + i2s0: i2s@2032000 {
>> + compatible = "allwinner,sun20i-d1-i2s",
>> + "allwinner,sun50i-r329-i2s";
>> + reg = <0x2032000 0x1000>;
>> + interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_I2S0>,
>> + <&ccu CLK_I2S0>;
>> + clock-names = "apb", "mod";
>> + resets = <&ccu RST_BUS_I2S0>;
>> + dmas = <&dma 3>, <&dma 3>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + #sound-dai-cells = <0>;
>> + };
>> +
>> + i2s1: i2s@2033000 {
>> + compatible = "allwinner,sun20i-d1-i2s",
>> + "allwinner,sun50i-r329-i2s";
>> + reg = <0x2033000 0x1000>;
>> + interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_I2S1>,
>> + <&ccu CLK_I2S1>;
>> + clock-names = "apb", "mod";
>> + resets = <&ccu RST_BUS_I2S1>;
>> + dmas = <&dma 4>, <&dma 4>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + #sound-dai-cells = <0>;
>> + };
>> +
>> + i2s2: i2s@2034000 {
>> + compatible = "allwinner,sun20i-d1-i2s",
>> + "allwinner,sun50i-r329-i2s";
>> + reg = <0x2034000 0x1000>;
>> + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_I2S2>,
>> + <&ccu CLK_I2S2>;
>> + clock-names = "apb", "mod";
>> + resets = <&ccu RST_BUS_I2S2>;
>> + dmas = <&dma 5>, <&dma 5>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + #sound-dai-cells = <0>;
>> + };
>> +
>> + timer: timer@2050000 {
>> + compatible = "allwinner,sun20i-d1-timer",
>> + "allwinner,sun8i-a23-timer";
>> + reg = <0x2050000 0xa0>;
>> + interrupts = <75 IRQ_TYPE_LEVEL_HIGH>,
>> + <76 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&osc24M>;
>> + };
>> +
>> + wdt: watchdog@20500a0 {
>> + compatible = "allwinner,sun20i-d1-wdt-reset",
>> + "allwinner,sun20i-d1-wdt";
>> + reg = <0x20500a0 0x20>;
>> + interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&osc24M>, <&rtc CLK_OSC32K>;
>> + clock-names = "hosc", "losc";
>> + status = "reserved";
>> + };
>> +
>> + uart0: serial@2500000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x2500000 0x400>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_UART0>;
>> + resets = <&ccu RST_BUS_UART0>;
>> + dmas = <&dma 14>, <&dma 14>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart1: serial@2500400 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x2500400 0x400>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_UART1>;
>> + resets = <&ccu RST_BUS_UART1>;
>> + dmas = <&dma 15>, <&dma 15>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart2: serial@2500800 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x2500800 0x400>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_UART2>;
>> + resets = <&ccu RST_BUS_UART2>;
>> + dmas = <&dma 16>, <&dma 16>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart3: serial@2500c00 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x2500c00 0x400>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_UART3>;
>> + resets = <&ccu RST_BUS_UART3>;
>> + dmas = <&dma 17>, <&dma 17>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart4: serial@2501000 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x2501000 0x400>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_UART4>;
>> + resets = <&ccu RST_BUS_UART4>;
>> + dmas = <&dma 18>, <&dma 18>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + uart5: serial@2501400 {
>> + compatible = "snps,dw-apb-uart";
>> + reg = <0x2501400 0x400>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_UART5>;
>> + resets = <&ccu RST_BUS_UART5>;
>> + dmas = <&dma 19>, <&dma 19>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + i2c0: i2c@2502000 {
>> + compatible = "allwinner,sun20i-d1-i2c",
>> + "allwinner,sun8i-v536-i2c",
>> + "allwinner,sun6i-a31-i2c";
>> + reg = <0x2502000 0x400>;
>> + interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_I2C0>;
>> + resets = <&ccu RST_BUS_I2C0>;
>> + dmas = <&dma 43>, <&dma 43>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + i2c1: i2c@2502400 {
>> + compatible = "allwinner,sun20i-d1-i2c",
>> + "allwinner,sun8i-v536-i2c",
>> + "allwinner,sun6i-a31-i2c";
>> + reg = <0x2502400 0x400>;
>> + interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_I2C1>;
>> + resets = <&ccu RST_BUS_I2C1>;
>> + dmas = <&dma 44>, <&dma 44>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + i2c2: i2c@2502800 {
>> + compatible = "allwinner,sun20i-d1-i2c",
>> + "allwinner,sun8i-v536-i2c",
>> + "allwinner,sun6i-a31-i2c";
>> + reg = <0x2502800 0x400>;
>> + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_I2C2>;
>> + resets = <&ccu RST_BUS_I2C2>;
>> + dmas = <&dma 45>, <&dma 45>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + i2c3: i2c@2502c00 {
>> + compatible = "allwinner,sun20i-d1-i2c",
>> + "allwinner,sun8i-v536-i2c",
>> + "allwinner,sun6i-a31-i2c";
>> + reg = <0x2502c00 0x400>;
>> + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_I2C3>;
>> + resets = <&ccu RST_BUS_I2C3>;
>> + dmas = <&dma 46>, <&dma 46>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + syscon: syscon@3000000 {
>> + compatible = "allwinner,sun20i-d1-system-control";
>> + reg = <0x3000000 0x1000>;
>> + ranges;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + regulators@3000150 {
>> + compatible = "allwinner,sun20i-d1-system-ldos";
>> + reg = <0x3000150 0x4>;
>> +
>> + reg_ldoa: ldoa {
>> + };
>> +
>> + reg_ldob: ldob {
>> + };
>> + };
>> + };
>> +
>> + dma: dma-controller@3002000 {
>> + compatible = "allwinner,sun20i-d1-dma";
>> + reg = <0x3002000 0x1000>;
>> + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
>> + clock-names = "bus", "mbus";
>> + resets = <&ccu RST_BUS_DMA>;
>> + dma-channels = <16>;
>> + dma-requests = <48>;
>> + #dma-cells = <1>;
>> + };
>> +
>> + sid: efuse@3006000 {
>> + compatible = "allwinner,sun20i-d1-sid";
>> + reg = <0x3006000 0x1000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + ths_calib: ths-calib@14 {
>> + reg = <0x14 0x4>;
>> + };
>> +
>> + bg_trim: bg-trim@28 {
>> + reg = <0x28 0x4>;
>> + bits = <16 8>;
>> + };
>> + };
>> +
>> + mbus: dram-controller@3102000 {
>> + compatible = "allwinner,sun20i-d1-mbus";
>> + reg = <0x3102000 0x1000>,
>> + <0x3103000 0x1000>;
>> + reg-names = "mbus", "dram";
>> + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_MBUS>,
>> + <&ccu CLK_DRAM>,
>> + <&ccu CLK_BUS_DRAM>;
>> + clock-names = "mbus", "dram", "bus";
>> + dma-ranges = <0 0x40000000 0x80000000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + #interconnect-cells = <1>;
>> + };
>> +
>> + mmc0: mmc@4020000 {
>> + compatible = "allwinner,sun20i-d1-mmc";
>> + reg = <0x4020000 0x1000>;
>> + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
>> + clock-names = "ahb", "mmc";
>> + resets = <&ccu RST_BUS_MMC0>;
>> + reset-names = "ahb";
>> + cap-sd-highspeed;
>> + max-frequency = <150000000>;
>> + no-mmc;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + mmc1: mmc@4021000 {
>> + compatible = "allwinner,sun20i-d1-mmc";
>> + reg = <0x4021000 0x1000>;
>> + interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
>> + clock-names = "ahb", "mmc";
>> + resets = <&ccu RST_BUS_MMC1>;
>> + reset-names = "ahb";
>> + cap-sd-highspeed;
>> + max-frequency = <150000000>;
>> + no-mmc;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + mmc2: mmc@4022000 {
>> + compatible = "allwinner,sun20i-d1-emmc",
>> + "allwinner,sun50i-a100-emmc";
>> + reg = <0x4022000 0x1000>;
>> + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
>> + clock-names = "ahb", "mmc";
>> + resets = <&ccu RST_BUS_MMC2>;
>> + reset-names = "ahb";
>> + cap-mmc-highspeed;
>> + max-frequency = <150000000>;
>> + mmc-ddr-1_8v;
>> + mmc-ddr-3_3v;
>> + no-sd;
>> + no-sdio;
>> + status = "disabled";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + usb_otg: usb@4100000 {
>> + compatible = "allwinner,sun20i-d1-musb",
>> + "allwinner,sun8i-a33-musb";
>> + reg = <0x4100000 0x400>;
>> + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "mc";
>> + clocks = <&ccu CLK_BUS_OTG>;
>> + resets = <&ccu RST_BUS_OTG>;
>> + extcon = <&usbphy 0>;
>> + phys = <&usbphy 0>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + usbphy: phy@4100400 {
>> + compatible = "allwinner,sun20i-d1-usb-phy";
>> + reg = <0x4100400 0x100>,
>> + <0x4101800 0x100>,
>> + <0x4200800 0x100>;
>> + reg-names = "phy_ctrl",
>> + "pmu0",
>> + "pmu1";
>> + clocks = <&osc24M>,
>> + <&osc24M>;
>> + clock-names = "usb0_phy",
>> + "usb1_phy";
>> + resets = <&ccu RST_USB_PHY0>,
>> + <&ccu RST_USB_PHY1>;
>> + reset-names = "usb0_reset",
>> + "usb1_reset";
>> + status = "disabled";
>> + #phy-cells = <1>;
>> + };
>> +
>> + ehci0: usb@4101000 {
>> + compatible = "allwinner,sun20i-d1-ehci",
>> + "generic-ehci";
>> + reg = <0x4101000 0x100>;
>> + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_OHCI0>,
>> + <&ccu CLK_BUS_EHCI0>,
>> + <&ccu CLK_USB_OHCI0>;
>> + resets = <&ccu RST_BUS_OHCI0>,
>> + <&ccu RST_BUS_EHCI0>;
>> + phys = <&usbphy 0>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + ohci0: usb@4101400 {
>> + compatible = "allwinner,sun20i-d1-ohci",
>> + "generic-ohci";
>> + reg = <0x4101400 0x100>;
>> + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_OHCI0>,
>> + <&ccu CLK_USB_OHCI0>;
>> + resets = <&ccu RST_BUS_OHCI0>;
>> + phys = <&usbphy 0>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + ehci1: usb@4200000 {
>> + compatible = "allwinner,sun20i-d1-ehci",
>> + "generic-ehci";
>> + reg = <0x4200000 0x100>;
>> + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_OHCI1>,
>> + <&ccu CLK_BUS_EHCI1>,
>> + <&ccu CLK_USB_OHCI1>;
>> + resets = <&ccu RST_BUS_OHCI1>,
>> + <&ccu RST_BUS_EHCI1>;
>> + phys = <&usbphy 1>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + ohci1: usb@4200400 {
>> + compatible = "allwinner,sun20i-d1-ohci",
>> + "generic-ohci";
>> + reg = <0x4200400 0x100>;
>> + interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_OHCI1>,
>> + <&ccu CLK_USB_OHCI1>;
>> + resets = <&ccu RST_BUS_OHCI1>;
>> + phys = <&usbphy 1>;
>> + phy-names = "usb";
>> + status = "disabled";
>> + };
>> +
>> + emac: ethernet@4500000 {
>> + compatible = "allwinner,sun20i-d1-emac",
>> + "allwinner,sun50i-a64-emac";
>> + reg = <0x4500000 0x10000>;
>> + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "macirq";
>> + clocks = <&ccu CLK_BUS_EMAC>;
>> + clock-names = "stmmaceth";
>> + resets = <&ccu RST_BUS_EMAC>;
>> + reset-names = "stmmaceth";
>> + syscon = <&syscon>;
>> + status = "disabled";
>> +
>> + mdio: mdio {
>> + compatible = "snps,dwmac-mdio";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> + };
>> +
>> + display_clocks: clock-controller@5000000 {
>> + compatible = "allwinner,sun20i-d1-de2-clk",
>> + "allwinner,sun50i-h5-de2-clk";
>> + reg = <0x5000000 0x10000>;
>> + clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
>> + clock-names = "bus", "mod";
>> + resets = <&ccu RST_BUS_DE>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + };
>> +
>> + mixer0: mixer@5100000 {
>> + compatible = "allwinner,sun20i-d1-de2-mixer-0";
>> + reg = <0x5100000 0x100000>;
>> + clocks = <&display_clocks CLK_BUS_MIXER0>,
>> + <&display_clocks CLK_MIXER0>;
>> + clock-names = "bus", "mod";
>> + resets = <&display_clocks RST_MIXER0>;
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + mixer0_out: port@1 {
>> + reg = <1>;
>> +
>> + mixer0_out_tcon_top_mixer0: endpoint {
>> + remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + mixer1: mixer@5200000 {
>> + compatible = "allwinner,sun20i-d1-de2-mixer-1";
>> + reg = <0x5200000 0x100000>;
>> + clocks = <&display_clocks CLK_BUS_MIXER1>,
>> + <&display_clocks CLK_MIXER1>;
>> + clock-names = "bus", "mod";
>> + resets = <&display_clocks RST_MIXER1>;
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + mixer1_out: port@1 {
>> + reg = <1>;
>> +
>> + mixer1_out_tcon_top_mixer1: endpoint {
>> + remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + tcon_top: tcon-top@5460000 {
>> + compatible = "allwinner,sun20i-d1-tcon-top";
>> + reg = <0x5460000 0x1000>;
>> + clocks = <&ccu CLK_BUS_DPSS_TOP>,
>> + <&ccu CLK_TCON_TV>,
>> + <&ccu CLK_TVE>,
>> + <&ccu CLK_MIPI_DSI>;
>> + clock-names = "bus", "tcon-tv0", "tve0", "dsi";
>> + clock-output-names = "tcon-top-tv0", "tcon-top-dsi";
>> + resets = <&ccu RST_BUS_DPSS_TOP>;
>> + #clock-cells = <1>;
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + tcon_top_mixer0_in: port@0 {
>> + reg = <0>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + tcon_top_mixer0_in_mixer0: endpoint@0 {
>> + reg = <0>;
>> + remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
>> + };
>> + };
>> +
>> + tcon_top_mixer0_out: port@1 {
>> + reg = <1>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
>> + reg = <0>;
>> + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
>> + };
>> +
>> + tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
>> + reg = <2>;
>> + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
>> + };
>> + };
>> +
>> + tcon_top_mixer1_in: port@2 {
>> + reg = <2>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + tcon_top_mixer1_in_mixer1: endpoint@1 {
>> + reg = <1>;
>> + remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
>> + };
>> + };
>> +
>> + tcon_top_mixer1_out: port@3 {
>> + reg = <3>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
>> + reg = <0>;
>> + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>;
>> + };
>> +
>> + tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
>> + reg = <2>;
>> + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
>> + };
>> + };
>> +
>> + tcon_top_hdmi_in: port@4 {
>> + reg = <4>;
>> +
>> + tcon_top_hdmi_in_tcon_tv0: endpoint {
>> + remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>;
>> + };
>> + };
>> +
>> + tcon_top_hdmi_out: port@5 {
>> + reg = <5>;
>> + };
>> + };
>> + };
>> +
>> + tcon_lcd0: lcd-controller@5461000 {
>> + compatible = "allwinner,sun20i-d1-tcon-lcd";
>> + reg = <0x5461000 0x1000>;
>> + interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_TCON_LCD0>,
>> + <&ccu CLK_TCON_LCD0>;
>> + clock-names = "ahb", "tcon-ch0";
>> + clock-output-names = "tcon-pixel-clock";
>> + resets = <&ccu RST_BUS_TCON_LCD0>,
>> + <&ccu RST_BUS_LVDS0>;
>> + reset-names = "lcd", "lvds";
>> + #clock-cells = <0>;
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + tcon_lcd0_in: port@0 {
>> + reg = <0>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
>> + reg = <0>;
>> + remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
>> + };
>> +
>> + tcon_lcd0_in_tcon_top_mixer1: endpoint@1 {
>> + reg = <1>;
>> + remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>;
>> + };
>> + };
>> +
>> + tcon_lcd0_out: port@1 {
>> + reg = <1>;
>> + };
>> + };
>> + };
>> +
>> + tcon_tv0: lcd-controller@5470000 {
>> + compatible = "allwinner,sun20i-d1-tcon-tv";
>> + reg = <0x5470000 0x1000>;
>> + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&ccu CLK_BUS_TCON_TV>,
>> + <&tcon_top CLK_TCON_TOP_TV0>;
>> + clock-names = "ahb", "tcon-ch1";
>> + resets = <&ccu RST_BUS_TCON_TV>;
>> + reset-names = "lcd";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + tcon_tv0_in: port@0 {
>> + reg = <0>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
>> + reg = <0>;
>> + remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
>> + };
>> +
>> + tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
>> + reg = <1>;
>> + remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
>> + };
>> + };
>> +
>> + tcon_tv0_out: port@1 {
>> + reg = <1>;
>> +
>> + tcon_tv0_out_tcon_top_hdmi: endpoint {
>> + remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + riscv_wdt: watchdog@6011000 {
>> + compatible = "allwinner,sun20i-d1-wdt";
>> + reg = <0x6011000 0x20>;
>> + interrupts = <147 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&osc24M>, <&rtc CLK_OSC32K>;
>> + clock-names = "hosc", "losc";
>> + };
>> +
>> + r_ccu: clock-controller@7010000 {
>> + compatible = "allwinner,sun20i-d1-r-ccu";
>> + reg = <0x7010000 0x400>;
>> + clocks = <&osc24M>,
>> + <&rtc CLK_OSC32K>,
>> + <&rtc CLK_IOSC>,
>> + <&ccu CLK_PLL_PERIPH0_DIV3>;
>> + clock-names = "hosc", "losc", "iosc", "pll-periph";
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + };
>> +
>> + rtc: rtc@7090000 {
>> + compatible = "allwinner,sun20i-d1-rtc",
>> + "allwinner,sun50i-r329-rtc";
>> + reg = <0x7090000 0x400>;
>> + interrupts = <160 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&r_ccu CLK_BUS_R_RTC>,
>> + <&osc24M>,
>> + <&r_ccu CLK_R_AHB>;
>> + clock-names = "bus", "hosc", "ahb";
>> + #clock-cells = <1>;
>> + };
>> +
>> + plic: interrupt-controller@10000000 {
>> + compatible = "allwinner,sun20i-d1-plic",
>> + "thead,c900-plic";
>> + reg = <0x10000000 0x4000000>;
>> + interrupts-extended = <&cpu0_intc 11>,
>> + <&cpu0_intc 9>;
>> + interrupt-controller;
>> + riscv,ndev = <176>;
>> + #address-cells = <0>;
>> + #interrupt-cells = <2>;
>> + };
>> + };
>> +};
>

2022-08-15 17:47:39

[permalink] [raw]

Subject: Re: [PATCH 00/12] riscv: Allwinner D1 platform support

On 15/08/2022 08:05, Conor Dooley wrote:
> Hey Samuel,
> Apologies for the last email, the first 5 patches in this series
> didn't correctly land in my inbox and I skimmed & replied to the
> wrong cover letter... I blame it being pre 8 AM ;)
>
> On 15/08/2022 06:08, Samuel Holland wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> This series adds the Kconfig/defconfig plumbing and devicetrees for a
>> range of Allwinner D1-based boards. Many features are already enabled,
>> including USB, Ethernet, and WiFi.
>>
>> The SoC devicetree uses bindings from the following series which have
>> not yet been merged:
>> - SRAM controller:
>>    https://lore.kernel.org/lkml/[email protected]/
>> - NVMEM cell bits property change:
>>    https://lore.kernel.org/lkml/[email protected]/
>> - In-package LDO regulators:
>>    https://lore.kernel.org/lkml/[email protected]/
>>
>> All three of these are required to set the correct I/O domain voltages
>> in the pin controller, which I would consider important to have in the
>> initial version of the devicetree.
>>
>> The SoC devicetree does contain one small hack to avoid a dependency on
>> the audio codec binding, since that is not ready yet: the codec node
>> uses a bare "simple-mfd", "syscon" compatible.
>
>
> I tried this series on top of both 6.0-rc1 & next, but I saw a shed
> load of errors from dtbs_check. I'll take a look at the rest of the
> series later on, but just FYI. This time I did at least read the
> right cover letter and actually applied your dependent series..
> /facepalm
>
> I have been trying to get riscv down to 0 warnings and would not be
> in favour of accepting patches that go in the other direction.
> (This patchset currently produces about 47 new warnings)

FWIW this is what I see, LMK if I am missing something.
allwinner/sun20i-d1-lichee-rv.dtb: i2c@2502000: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-clockworkpi-v3.14.dtb: i2c@2502000: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-lichee-rv.dtb: i2c@2502400: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-lichee-rv-86-panel-720p.dtb: i2c@2502000: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-lichee-rv-dock.dtb: i2c@2502000: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-clockworkpi-v3.14.dtb: pmic@34: compatible: 'oneOf' conditional failed, one must be fixed:
allwinner/sun20i-d1-dongshan-nezha-stu.dtb: i2c@2502000: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-lichee-rv.dtb: i2c@2502800: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-lichee-rv-86-panel-720p.dtb: i2c@2502400: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-lichee-rv-dock.dtb: i2c@2502400: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-mangopi-mq-pro.dtb: i2c@2502000: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-dongshan-nezha-stu.dtb: i2c@2502400: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-devterm-v3.14.dtb: i2c@2502000: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-lichee-rv-86-panel-480p.dtb: i2c@2502000: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-lichee-rv.dtb: i2c@2502c00: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-lichee-rv-86-panel-720p.dtb: i2c@2502800: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-dongshan-nezha-stu.dtb: i2c@2502800: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-mangopi-mq-pro.dtb: i2c@2502400: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-lichee-rv-dock.dtb: i2c@2502800: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-lichee-rv-86-panel-480p.dtb: i2c@2502400: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-devterm-v3.14.dtb: pmic@34: compatible: 'oneOf' conditional failed, one must be fixed:
allwinner/sun20i-d1-lichee-rv-86-panel-720p.dtb: i2c@2502c00: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-mangopi-mq-pro.dtb: i2c@2502800: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-dongshan-nezha-stu.dtb: i2c@2502c00: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-lichee-rv-dock.dtb: i2c@2502c00: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-lichee-rv-86-panel-480p.dtb: i2c@2502800: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-mangopi-mq-pro.dtb: i2c@2502c00: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-lichee-rv-86-panel-480p.dtb: i2c@2502c00: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-clockworkpi-v3.14.dtb: i2c@2502400: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-clockworkpi-v3.14.dtb: i2c@2502800: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-clockworkpi-v3.14.dtb: i2c@2502c00: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-devterm-v3.14.dtb: i2c@2502400: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-devterm-v3.14.dtb: i2c@2502800: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-devterm-v3.14.dtb: i2c@2502c00: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-lichee-rv.dtb: ethernet@4500000: Unevaluated properties are not allowed ('mdio', 'reset-names', 'resets' were unexpected)
allwinner/sun20i-d1-lichee-rv-86-panel-720p.dtb: ethernet@4500000: Unevaluated properties are not allowed ('phy-supply' was unexpected)
allwinner/sun20i-d1-dongshan-nezha-stu.dtb: ethernet@4500000: Unevaluated properties are not allowed ('phy-supply' was unexpected)
allwinner/sun20i-d1-lichee-rv-dock.dtb: ethernet@4500000: Unevaluated properties are not allowed ('mdio', 'reset-names', 'resets' were unexpected)
allwinner/sun20i-d1-mangopi-mq-pro.dtb: ethernet@4500000: Unevaluated properties are not allowed ('mdio', 'reset-names', 'resets' were unexpected)
allwinner/sun20i-d1-lichee-rv-86-panel-480p.dtb: ethernet@4500000: Unevaluated properties are not allowed ('phy-supply' was unexpected)
allwinner/sun20i-d1-nezha.dtb: i2c@2502000: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-nezha.dtb: i2c@2502400: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-clockworkpi-v3.14.dtb: ethernet@4500000: Unevaluated properties are not allowed ('mdio', 'reset-names', 'resets' were unexpected)
allwinner/sun20i-d1-nezha.dtb: i2c@2502800: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-nezha.dtb: i2c@2502c00: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
allwinner/sun20i-d1-devterm-v3.14.dtb: ethernet@4500000: Unevaluated properties are not allowed ('mdio', 'reset-names', 'resets' were unexpected)
allwinner/sun20i-d1-nezha.dtb: ethernet@4500000: Unevaluated properties are not allowed ('phy-supply' was unexpected)

>
> Thanks,
> Conor.
>>
>>
>> Samuel Holland (12):
>>    MAINTAINERS: Match the sun20i family of Allwinner SoCs
>>    dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles
>>    dt-bindings: vendor-prefixes: Add Allwinner D1 board vendors
>>    dt-bindings: riscv: Add Allwinner D1 board compatibles
>>    riscv: Add the Allwinner SoC family Kconfig option
>>    riscv: dts: allwinner: Add the D1 SoC base devicetree
>>    riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree
>>    riscv: dts: allwinner: Add Sipeed Lichee RV devicetrees
>>    riscv: dts: allwinner: Add MangoPi MQ Pro devicetree
>>    riscv: dts: allwinner: Add Dongshan Nezha STU devicetree
>>    riscv: dts: allwinner: Add ClockworkPi and DevTerm devicetrees
>>    riscv: defconfig: Enable the Allwinner D1 platform and drivers
>>
>> .../devicetree/bindings/riscv/cpus.yaml       |   2 +
>> .../devicetree/bindings/riscv/sunxi.yaml      | 64 ++
>> .../devicetree/bindings/vendor-prefixes.yaml |   4 +
>> MAINTAINERS                                   |   2 +-
>> arch/riscv/Kconfig.socs                       |   9 +
>> arch/riscv/boot/dts/Makefile                  |   1 +
>> arch/riscv/boot/dts/allwinner/Makefile        | 10 +
>> .../allwinner/sun20i-d1-clockworkpi-v3.14.dts | 242 +++++
>> .../sun20i-d1-common-regulators.dtsi          | 51 +
>> .../dts/allwinner/sun20i-d1-devterm-v3.14.dts | 37 +
>> .../sun20i-d1-dongshan-nezha-stu.dts          | 114 +++
>> .../sun20i-d1-lichee-rv-86-panel-480p.dts     | 29 +
>> .../sun20i-d1-lichee-rv-86-panel-720p.dts     | 10 +
>> .../sun20i-d1-lichee-rv-86-panel.dtsi         | 92 ++
>> .../allwinner/sun20i-d1-lichee-rv-dock.dts    | 74 ++
>> .../dts/allwinner/sun20i-d1-lichee-rv.dts     | 84 ++
>> .../allwinner/sun20i-d1-mangopi-mq-pro.dts    | 128 +++
>> .../boot/dts/allwinner/sun20i-d1-nezha.dts    | 171 ++++
>> arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 900 ++++++++++++++++++
>> arch/riscv/configs/defconfig                  | 23 +-
>> 20 files changed, 2045 insertions(+), 2 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/riscv/sunxi.yaml
>> create mode 100644 arch/riscv/boot/dts/allwinner/Makefile
>> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
>> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
>> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts
>> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
>> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
>> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts
>> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
>> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
>> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
>> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts
>> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
>> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
>>
>> --
>> 2.35.1
>>
>

2022-08-15 17:51:24

[permalink] [raw]

Subject: Re: [PATCH 07/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree

On 15/08/2022 06:08, Samuel Holland wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> "D1 Nezha" is Allwinner's first-party development board for the D1 SoC.
> It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard audio,
> HDMI, gigabit Ethernet, WiFi and Bluetooth, USB 2.0 host and OTG ports,
> plus low-speed I/O from the SoC and a GPIO expander chip.
>
> Most other D1 boards copied the Nezha's power tree, with the 1.8V rail
> powered by the SoCs internal LDOA, analog domains powered by ALDO, and
> the rest of the board powered by always-on fixed regulators. Some (but
> not all) boards also copied the PWM CPU regulator. To avoid duplication,
> factor out the out the regulator references that are common across all
> known boards.
>
> Signed-off-by: Samuel Holland <[email protected]>

Hey Samuel,
Replying here as it's the board I happen to have but I saw some kernel
panics. Some of this has reproduced for Ron/drmpeg on an unmatched:
https://www.w6rz.net/segfault.png
but some of this is different:
https://gist.github.com/ConchuOD/7d87f574df1ddc56f192e505ecab6574

defconfig is default riscv defconfig - the DRM modules + my cmdline:
CONFIG_CMDLINE="earlyprintk=sunxi-uart,0x02500000 earlycon console=ttyS0,115200"

lmk if you want anymore info :)
Conor.

> ---
>
> arch/riscv/boot/dts/allwinner/Makefile | 1 +
> .../sun20i-d1-common-regulators.dtsi | 51 ++++++
> .../boot/dts/allwinner/sun20i-d1-nezha.dts | 171 ++++++++++++++++++
> 3 files changed, 223 insertions(+)
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
>
> diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile
> index f66554cd5c45..b0a15e8c8d82 100644
> --- a/arch/riscv/boot/dts/allwinner/Makefile
> +++ b/arch/riscv/boot/dts/allwinner/Makefile
> @@ -1 +1,2 @@
> # SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
> new file mode 100644
> index 000000000000..143a3e710c3c
> --- /dev/null
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
> @@ -0,0 +1,51 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
> +
> +/ {
> + reg_vcc: vcc {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + };
> +
> + reg_vcc_3v3: vcc-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc-3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + vin-supply = <&reg_vcc>;
> + };
> +};
> +
> +&lradc {
> + vref-supply = <&reg_aldo>;
> +};
> +
> +&pio {
> + vcc-pb-supply = <&reg_vcc_3v3>;
> + vcc-pc-supply = <&reg_vcc_3v3>;
> + vcc-pd-supply = <&reg_vcc_3v3>;
> + vcc-pe-supply = <&reg_vcc_3v3>;
> + vcc-pf-supply = <&reg_vcc_3v3>;
> + vcc-pg-supply = <&reg_vcc_3v3>;
> +};
> +
> +&reg_aldo {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + vdd33-supply = <&reg_vcc_3v3>;
> +};
> +
> +&reg_hpldo {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + hpldoin-supply = <&reg_vcc_3v3>;
> +};
> +
> +&reg_ldoa {
> + regulator-always-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + ldo-in-supply = <&reg_vcc_3v3>;
> +};
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
> new file mode 100644
> index 000000000000..df865ee15fcf
> --- /dev/null
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
> @@ -0,0 +1,171 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +
> +#include "sun20i-d1.dtsi"
> +#include "sun20i-d1-common-regulators.dtsi"
> +
> +/ {
> + model = "Allwinner D1 Nezha";
> + compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1";
> +
> + aliases {
> + ethernet0 = &emac;
> + ethernet1 = &xr829;
> + mmc0 = &mmc0;
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + reg_usbvbus: usbvbus {
> + compatible = "regulator-fixed";
> + regulator-name = "usbvbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
> + enable-active-high;
> + vin-supply = <&reg_vcc>;
> + };
> +
> + /*
> + * This regulator is PWM-controlled, but the PWM controller is not
> + * yet supported, so fix the regulator to its default voltage.
> + */
> + reg_vdd_cpu: vdd-cpu {
> + compatible = "regulator-fixed";
> + regulator-name = "vdd-cpu";
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1100000>;
> + vin-supply = <&reg_vcc>;
> + };
> +
> + wifi_pwrseq: wifi-pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
> + };
> +};
> +
> +&cpu0 {
> + cpu-supply = <&reg_vdd_cpu>;
> +};
> +
> +&ehci0 {
> + status = "okay";
> +};
> +
> +&ehci1 {
> + status = "okay";
> +};
> +
> +&emac {
> + pinctrl-0 = <&rgmii_pe_pins>;
> + pinctrl-names = "default";
> + phy-handle = <&ext_rgmii_phy>;
> + phy-mode = "rgmii-id";
> + phy-supply = <&reg_vcc_3v3>;
> + status = "okay";
> +};
> +
> +&i2c2 {
> + pinctrl-0 = <&i2c2_pb0_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + pcf8574a: gpio@38 {
> + compatible = "nxp,pcf8574a";
> + reg = <0x38>;
> + interrupt-parent = <&pio>;
> + interrupts = <1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */
> + interrupt-controller;
> + gpio-controller;
> + #gpio-cells = <2>;
> + #interrupt-cells = <2>;
> + };
> +};
> +
> +&lradc {
> + status = "okay";
> +
> + button-160 {
> + label = "OK";
> + linux,code = <KEY_OK>;
> + channel = <0>;
> + voltage = <160000>;
> + };
> +};
> +
> +&mdio {
> + ext_rgmii_phy: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
> + };
> +};
> +
> +&mmc0 {
> + bus-width = <4>;
> + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
> + disable-wp;
> + vmmc-supply = <&reg_vcc_3v3>;
> + vqmmc-supply = <&reg_vcc_3v3>;
> + pinctrl-0 = <&mmc0_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&mmc1 {
> + bus-width = <4>;
> + mmc-pwrseq = <&wifi_pwrseq>;
> + non-removable;
> + vmmc-supply = <&reg_vcc_3v3>;
> + vqmmc-supply = <&reg_vcc_3v3>;
> + pinctrl-0 = <&mmc1_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + xr829: wifi@1 {
> + reg = <1>;
> + };
> +};
> +
> +&ohci0 {
> + status = "okay";
> +};
> +
> +&ohci1 {
> + status = "okay";
> +};
> +
> +&uart0 {
> + pinctrl-0 = <&uart0_pb8_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&uart1 {
> + uart-has-rtscts;
> + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + /* XR829 bluetooth is connected here */
> +};
> +
> +&usb_otg {
> + dr_mode = "otg";
> + status = "okay";
> +};
> +
> +&usbphy {
> + usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
> + usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
> + usb0_vbus-supply = <&reg_usbvbus>;
> + usb1_vbus-supply = <&reg_vcc>;
> + status = "okay";
> +};
> --
> 2.35.1
>

2022-08-15 20:17:19

[permalink] [raw]

Subject: Re: [PATCH 07/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree

On 15/08/2022 18:37, Conor Dooley - M52691 wrote:
> On 15/08/2022 06:08, Samuel Holland wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> "D1 Nezha" is Allwinner's first-party development board for the D1 SoC.
>> It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard audio,
>> HDMI, gigabit Ethernet, WiFi and Bluetooth, USB 2.0 host and OTG ports,
>> plus low-speed I/O from the SoC and a GPIO expander chip.
>>
>> Most other D1 boards copied the Nezha's power tree, with the 1.8V rail
>> powered by the SoCs internal LDOA, analog domains powered by ALDO, and
>> the rest of the board powered by always-on fixed regulators. Some (but
>> not all) boards also copied the PWM CPU regulator. To avoid duplication,
>> factor out the out the regulator references that are common across all
>> known boards.
>>
>> Signed-off-by: Samuel Holland <[email protected]>
>
> Hey Samuel,
> Replying here as it's the board I happen to have but I saw some kernel
> panics. Some of this has reproduced for Ron/drmpeg on an unmatched:
> https://www.w6rz.net/segfault.png
> but some of this is different:
> https://gist.github.com/ConchuOD/7d87f574df1ddc56f192e505ecab6574
>
> defconfig is default riscv defconfig - the DRM modules + my cmdline:
> CONFIG_CMDLINE="earlyprintk=sunxi-uart,0x02500000 earlycon console=ttyS0,115200"

I seem to be making a hames of things today. Started it with the email
to the wrong patchset this morning and now here I am 12h later and I am
messing up my stuff here too :/

I think I confused myself with the configs & logs. This one here was the
default defconfig + CONFIG_CMDLINE [0]:
https://gist.github.com/ConchuOD/7d87f574df1ddc56f192e505ecab6574#file-log-txt-no-drm

This one was from the d1-wip branch that I had been using prior
to the patchset with CONFIG_CMDLINE [0]:
https://gist.github.com/ConchuOD/7d87f574df1ddc56f192e505ecab6574#file-log-txt-with-drm

And with a defconfig from Heiko I get hangs where output dies using
CONFIG_CMDLINE [1]:
https://paste.debian.net/1250519/
https://gist.github.com/ConchuOD/7d87f574df1ddc56f192e505ecab6574#file-heiko-config

For all of the above I have used:
0 - CONFIG_CMDLINE="root=/dev/nfs ip=dhcp nfsroot=192.168.2.5:/stuff/nfs_share earlyprintk=sunxi-uart,0x02500000 earlycon console=ttyS0,115200"
1 - CONFIG_CMDLINE="earlyprintk=sunxi-uart,0x02500000 earlycon console=ttyS0,115200"

If I don't use [1], I don't get any output on the uart my u-boot uses.

Heiko reminded me that the D1 needs the memory nodes from the dts etc,
so it's actually using the u-boot dts. Did you make breaking changes
between what worked with the d1-wip branch and this submission?
I'll update what my u-boot has, but in the meantime hopefully this
makes things a little clearer.

Sorry for all the noise etc, I seem to be all over the shop today.
Conor.

>
> lmk if you want anymore info :)
> Conor.
>
>> ---
>>
>> arch/riscv/boot/dts/allwinner/Makefile | 1 +
>> .../sun20i-d1-common-regulators.dtsi | 51 ++++++
>> .../boot/dts/allwinner/sun20i-d1-nezha.dts | 171 ++++++++++++++++++
>> 3 files changed, 223 insertions(+)
>> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
>> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
>>
>> diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile
>> index f66554cd5c45..b0a15e8c8d82 100644
>> --- a/arch/riscv/boot/dts/allwinner/Makefile
>> +++ b/arch/riscv/boot/dts/allwinner/Makefile
>> @@ -1 +1,2 @@
>> # SPDX-License-Identifier: GPL-2.0
>> +dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb
>> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
>> new file mode 100644
>> index 000000000000..143a3e710c3c
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
>> @@ -0,0 +1,51 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
>> +// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
>> +
>> +/ {
>> + reg_vcc: vcc {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vcc";
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> + };
>> +
>> + reg_vcc_3v3: vcc-3v3 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vcc-3v3";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + vin-supply = <&reg_vcc>;
>> + };
>> +};
>> +
>> +&lradc {
>> + vref-supply = <&reg_aldo>;
>> +};
>> +
>> +&pio {
>> + vcc-pb-supply = <&reg_vcc_3v3>;
>> + vcc-pc-supply = <&reg_vcc_3v3>;
>> + vcc-pd-supply = <&reg_vcc_3v3>;
>> + vcc-pe-supply = <&reg_vcc_3v3>;
>> + vcc-pf-supply = <&reg_vcc_3v3>;
>> + vcc-pg-supply = <&reg_vcc_3v3>;
>> +};
>> +
>> +&reg_aldo {
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + vdd33-supply = <&reg_vcc_3v3>;
>> +};
>> +
>> +&reg_hpldo {
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + hpldoin-supply = <&reg_vcc_3v3>;
>> +};
>> +
>> +&reg_ldoa {
>> + regulator-always-on;
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <1800000>;
>> + ldo-in-supply = <&reg_vcc_3v3>;
>> +};
>> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
>> new file mode 100644
>> index 000000000000..df865ee15fcf
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
>> @@ -0,0 +1,171 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
>> +// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
>> +
>> +/dts-v1/;
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/input/input.h>
>> +
>> +#include "sun20i-d1.dtsi"
>> +#include "sun20i-d1-common-regulators.dtsi"
>> +
>> +/ {
>> + model = "Allwinner D1 Nezha";
>> + compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1";
>> +
>> + aliases {
>> + ethernet0 = &emac;
>> + ethernet1 = &xr829;
>> + mmc0 = &mmc0;
>> + serial0 = &uart0;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + reg_usbvbus: usbvbus {
>> + compatible = "regulator-fixed";
>> + regulator-name = "usbvbus";
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> + gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
>> + enable-active-high;
>> + vin-supply = <&reg_vcc>;
>> + };
>> +
>> + /*
>> + * This regulator is PWM-controlled, but the PWM controller is not
>> + * yet supported, so fix the regulator to its default voltage.
>> + */
>> + reg_vdd_cpu: vdd-cpu {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vdd-cpu";
>> + regulator-min-microvolt = <1100000>;
>> + regulator-max-microvolt = <1100000>;
>> + vin-supply = <&reg_vcc>;
>> + };
>> +
>> + wifi_pwrseq: wifi-pwrseq {
>> + compatible = "mmc-pwrseq-simple";
>> + reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
>> + };
>> +};
>> +
>> +&cpu0 {
>> + cpu-supply = <&reg_vdd_cpu>;
>> +};
>> +
>> +&ehci0 {
>> + status = "okay";
>> +};
>> +
>> +&ehci1 {
>> + status = "okay";
>> +};
>> +
>> +&emac {
>> + pinctrl-0 = <&rgmii_pe_pins>;
>> + pinctrl-names = "default";
>> + phy-handle = <&ext_rgmii_phy>;
>> + phy-mode = "rgmii-id";
>> + phy-supply = <&reg_vcc_3v3>;
>> + status = "okay";
>> +};
>> +
>> +&i2c2 {
>> + pinctrl-0 = <&i2c2_pb0_pins>;
>> + pinctrl-names = "default";
>> + status = "okay";
>> +
>> + pcf8574a: gpio@38 {
>> + compatible = "nxp,pcf8574a";
>> + reg = <0x38>;
>> + interrupt-parent = <&pio>;
>> + interrupts = <1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */
>> + interrupt-controller;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + #interrupt-cells = <2>;
>> + };
>> +};
>> +
>> +&lradc {
>> + status = "okay";
>> +
>> + button-160 {
>> + label = "OK";
>> + linux,code = <KEY_OK>;
>> + channel = <0>;
>> + voltage = <160000>;
>> + };
>> +};
>> +
>> +&mdio {
>> + ext_rgmii_phy: ethernet-phy@1 {
>> + compatible = "ethernet-phy-ieee802.3-c22";
>> + reg = <1>;
>> + };
>> +};
>> +
>> +&mmc0 {
>> + bus-width = <4>;
>> + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
>> + disable-wp;
>> + vmmc-supply = <&reg_vcc_3v3>;
>> + vqmmc-supply = <&reg_vcc_3v3>;
>> + pinctrl-0 = <&mmc0_pins>;
>> + pinctrl-names = "default";
>> + status = "okay";
>> +};
>> +
>> +&mmc1 {
>> + bus-width = <4>;
>> + mmc-pwrseq = <&wifi_pwrseq>;
>> + non-removable;
>> + vmmc-supply = <&reg_vcc_3v3>;
>> + vqmmc-supply = <&reg_vcc_3v3>;
>> + pinctrl-0 = <&mmc1_pins>;
>> + pinctrl-names = "default";
>> + status = "okay";
>> +
>> + xr829: wifi@1 {
>> + reg = <1>;
>> + };
>> +};
>> +
>> +&ohci0 {
>> + status = "okay";
>> +};
>> +
>> +&ohci1 {
>> + status = "okay";
>> +};
>> +
>> +&uart0 {
>> + pinctrl-0 = <&uart0_pb8_pins>;
>> + pinctrl-names = "default";
>> + status = "okay";
>> +};
>> +
>> +&uart1 {
>> + uart-has-rtscts;
>> + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
>> + pinctrl-names = "default";
>> + status = "okay";
>> +
>> + /* XR829 bluetooth is connected here */
>> +};
>> +
>> +&usb_otg {
>> + dr_mode = "otg";
>> + status = "okay";
>> +};
>> +
>> +&usbphy {
>> + usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
>> + usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
>> + usb0_vbus-supply = <&reg_usbvbus>;
>> + usb1_vbus-supply = <&reg_vcc>;
>> + status = "okay";
>> +};
>> --
>> 2.35.1
>>
>

2022-08-16 07:27:45

[permalink] [raw]

Subject: Re: [PATCH 00/12] riscv: Allwinner D1 platform support

On 8/15/22 12:12 PM, [email protected] wrote:
> On 15/08/2022 08:05, Conor Dooley wrote:
>> Hey Samuel,
>> Apologies for the last email, the first 5 patches in this series
>> didn't correctly land in my inbox and I skimmed & replied to the
>> wrong cover letter... I blame it being pre 8 AM ;)
>>
>> On 15/08/2022 06:08, Samuel Holland wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> This series adds the Kconfig/defconfig plumbing and devicetrees for a
>>> range of Allwinner D1-based boards. Many features are already enabled,
>>> including USB, Ethernet, and WiFi.
>>>
>>> The SoC devicetree uses bindings from the following series which have
>>> not yet been merged:
>>> - SRAM controller:
>>>    https://lore.kernel.org/lkml/[email protected]/
>>> - NVMEM cell bits property change:
>>>    https://lore.kernel.org/lkml/[email protected]/
>>> - In-package LDO regulators:
>>>    https://lore.kernel.org/lkml/[email protected]/
>>>
>>> All three of these are required to set the correct I/O domain voltages
>>> in the pin controller, which I would consider important to have in the
>>> initial version of the devicetree.
>>>
>>> The SoC devicetree does contain one small hack to avoid a dependency on
>>> the audio codec binding, since that is not ready yet: the codec node
>>> uses a bare "simple-mfd", "syscon" compatible.
>>
>>
>> I tried this series on top of both 6.0-rc1 & next, but I saw a shed
>> load of errors from dtbs_check. I'll take a look at the rest of the
>> series later on, but just FYI. This time I did at least read the
>> right cover letter and actually applied your dependent series..
>> /facepalm
>>
>> I have been trying to get riscv down to 0 warnings and would not be
>> in favour of accepting patches that go in the other direction.
>> (This patchset currently produces about 47 new warnings)

Only 4 unique ones :)

Thanks for checking this. I had done a couple of passes cleaning things up. The
remaining warnings are the ones I was unsure how to fix.

> FWIW this is what I see, LMK if I am missing something.
> allwinner/sun20i-d1-lichee-rv.dtb: i2c@2502000: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)

This one is new with dt-schema 2022.08.1 (I was previously on d1f3102e locally).
I'm not sure if it is a bug in the binding or in the dt-schema tool. The
warnings go away if I do:

--- a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
@@ -72,6 +72,7 @@ required:
- interrupts

allOf:
+ - $ref: /schemas/dma/dma.yaml#
- $ref: /schemas/i2c/i2c-controller.yaml#
- if:
properties:

But I wouldn't expect this to be necessary, since dma.yaml has "select: true".
Compare the this with the UARTs. Neither serial/snps-dw-apb-uart.yaml nor
serial/serial.yaml references any DMA properties, yet there is no warning for those.

> allwinner/sun20i-d1-clockworkpi-v3.14.dtb: pmic@34: compatible: 'oneOf' conditional failed, one must be fixed:
> allwinner/sun20i-d1-devterm-v3.14.dtb: pmic@34: compatible: 'oneOf' conditional failed, one must be fixed:

The new compatible is in linux-next. I can add it to the cover letter for v2:
https://lore.kernel.org/linux-devicetree/[email protected]/
https://git.kernel.org/lee/mfd/c/97ecda0f615e

> allwinner/sun20i-d1-lichee-rv.dtb: ethernet@4500000: Unevaluated properties are not allowed ('mdio', 'reset-names', 'resets' were unexpected)

This showed up with a dt-schema update in the last year or so. This may be a bug
in the binding? allwinner,sun8i-a83t-emac.yaml picks up these three properties
from snps,dwmac.yaml, but does not have them in its own "properties" block.
(resets and reset-names are even in "required"!)

> allwinner/sun20i-d1-lichee-rv-86-panel-720p.dtb: ethernet@4500000: Unevaluated properties are not allowed ('phy-supply' was unexpected)
> allwinner/sun20i-d1-dongshan-nezha-stu.dtb: ethernet@4500000: Unevaluated properties are not allowed ('phy-supply' was unexpected)

I think this one is just flat out missing from the binding. It is present in the
other two Allwinner Ethernet MAC bindings, but not this one.

Regards,
Samuel

2022-08-16 09:23:14

[permalink] [raw]

Subject: Re: [PATCH 00/12] riscv: Allwinner D1 platform support

On 16/08/2022 03:42, Samuel Holland wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 8/15/22 12:12 PM, [email protected] wrote:
>> On 15/08/2022 08:05, Conor Dooley wrote:
>>> Hey Samuel,
>>> Apologies for the last email, the first 5 patches in this series
>>> didn't correctly land in my inbox and I skimmed & replied to the
>>> wrong cover letter... I blame it being pre 8 AM ;)
>>>
>>> On 15/08/2022 06:08, Samuel Holland wrote:
>>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>>
>>>> This series adds the Kconfig/defconfig plumbing and devicetrees for a
>>>> range of Allwinner D1-based boards. Many features are already enabled,
>>>> including USB, Ethernet, and WiFi.
>>>>
>>>> The SoC devicetree uses bindings from the following series which have
>>>> not yet been merged:
>>>> - SRAM controller:
>>>> https://lore.kernel.org/lkml/[email protected]/
>>>> - NVMEM cell bits property change:
>>>> https://lore.kernel.org/lkml/[email protected]/
>>>> - In-package LDO regulators:
>>>> https://lore.kernel.org/lkml/[email protected]/
>>>>
>>>> All three of these are required to set the correct I/O domain voltages
>>>> in the pin controller, which I would consider important to have in the
>>>> initial version of the devicetree.
>>>>
>>>> The SoC devicetree does contain one small hack to avoid a dependency on
>>>> the audio codec binding, since that is not ready yet: the codec node
>>>> uses a bare "simple-mfd", "syscon" compatible.
>>>
>>>
>>> I tried this series on top of both 6.0-rc1 & next, but I saw a shed
>>> load of errors from dtbs_check. I'll take a look at the rest of the
>>> series later on, but just FYI. This time I did at least read the
>>> right cover letter and actually applied your dependent series..
>>> /facepalm
>>>
>>> I have been trying to get riscv down to 0 warnings and would not be
>>> in favour of accepting patches that go in the other direction.
>>> (This patchset currently produces about 47 new warnings)
>
> Only 4 unique ones :)
>
> Thanks for checking this. I had done a couple of passes cleaning things up. The
> remaining warnings are the ones I was unsure how to fix.
>
>> FWIW this is what I see, LMK if I am missing something.
>> allwinner/sun20i-d1-lichee-rv.dtb: i2c@2502000: Unevaluated properties are not allowed ('dma-names', 'dmas' were unexpected)
>
> This one is new with dt-schema 2022.08.1 (I was previously on d1f3102e locally).
> I'm not sure if it is a bug in the binding or in the dt-schema tool. The
> warnings go away if I do:

Yup, there were some changes to handling of unevaluatedProperties
between .07 & .08
>
> --- a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
> +++ b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
> @@ -72,6 +72,7 @@ required:
> - interrupts
>
> allOf:
> + - $ref: /schemas/dma/dma.yaml#
> - $ref: /schemas/i2c/i2c-controller.yaml#
> - if:
> properties:
>
> But I wouldn't expect this to be necessary, since dma.yaml has "select: true".
> Compare the this with the UARTs. Neither serial/snps-dw-apb-uart.yaml nor
> serial/serial.yaml references any DMA properties, yet there is no warning for those.
>
>> allwinner/sun20i-d1-clockworkpi-v3.14.dtb: pmic@34: compatible: 'oneOf' conditional failed, one must be fixed:
>> allwinner/sun20i-d1-devterm-v3.14.dtb: pmic@34: compatible: 'oneOf' conditional failed, one must be fixed:
>
> The new compatible is in linux-next. I can add it to the cover letter for v2:
> https://lore.kernel.org/linux-devicetree/[email protected]/
> https://git.kernel.org/lee/mfd/c/97ecda0f615e

Please do :)

>
>> allwinner/sun20i-d1-lichee-rv.dtb: ethernet@4500000: Unevaluated properties are not allowed ('mdio', 'reset-names', 'resets' were unexpected)
>
> This showed up with a dt-schema update in the last year or so. This may be a bug
> in the binding? allwinner,sun8i-a83t-emac.yaml picks up these three properties
> from snps,dwmac.yaml, but does not have them in its own "properties" block.
> (resets and reset-names are even in "required"!)
>
>> allwinner/sun20i-d1-lichee-rv-86-panel-720p.dtb: ethernet@4500000: Unevaluated properties are not allowed ('phy-supply' was unexpected)
>> allwinner/sun20i-d1-dongshan-nezha-stu.dtb: ethernet@4500000: Unevaluated properties are not allowed ('phy-supply' was unexpected)
>
> I think this one is just flat out missing from the binding. It is present in the
> other two Allwinner Ethernet MAC bindings, but not this one.

Cool. Maybe Rob Or Krzysztof can shed some light on the others.

Thanks,
Conor.

2022-08-16 09:32:09

[permalink] [raw]

Subject: Re: [PATCH 04/12] dt-bindings: riscv: Add Allwinner D1 board compatibles

On 15/08/2022 08:08, Samuel Holland wrote:
> Several SoMs and boards are available that feature the Allwinner D1 SoC.
> Document their compatible strings.
>
> Signed-off-by: Samuel Holland <[email protected]>
> ---
>
> .../devicetree/bindings/riscv/sunxi.yaml | 64 +++++++++++++++++++
> 1 file changed, 64 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/riscv/sunxi.yaml
>
> diff --git a/Documentation/devicetree/bindings/riscv/sunxi.yaml b/Documentation/devicetree/bindings/riscv/sunxi.yaml
> new file mode 100644
> index 000000000000..564a89499894
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/riscv/sunxi.yaml
> @@ -0,0 +1,64 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/riscv/sunxi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Allwinner RISC-V SoC-based boards
> +
> +maintainers:
> + - Chen-Yu Tsai <[email protected]>
> + - Jernej Skrabec <[email protected]>
> + - Samuel Holland <[email protected]>
> +
> +description:
> + Allwinner RISC-V SoC-based boards
> +
> +properties:
> + $nodename:
> + const: '/'
> + compatible:
> + oneOf:
> + - description: Dongshan Nezha STU SoM
> + items:
> + - const: 100ask,dongshan-nezha-stu
> + - const: allwinner,sun20i-d1
> +
> + - description: D1 Nezha board
> + items:
> + - const: allwinner,d1-nezha

You grow the list unnecessary. Several entries should be an enum, unless
platform maintainer insists on such approach for all Allwinner Riscv
platforms. Just be aware it will grow...

Best regards,
Krzysztof

2022-08-16 09:33:33

by Jernej Škrabec

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

Dne torek, 16. avgust 2022 ob 09:41:45 CEST je Krzysztof Kozlowski napisal(a):
> On 15/08/2022 08:08, Samuel Holland wrote:
> > +
> > + de: display-engine {
> > + compatible = "allwinner,sun20i-d1-display-engine";
> > + allwinner,pipelines = <&mixer0>, <&mixer1>;
> > + status = "disabled";
> > + };
> > +
> > + osc24M: osc24M-clk {
>
> lowercase
>
> > + compatible = "fixed-clock";
> > + clock-frequency = <24000000>;
>
> This is a property of the board, not SoC.

SoC needs 24 MHz oscillator for correct operation, so each and every board has
it. Having it here simplifies board DT files.

Best regards,
Jernej

>
> > + clock-output-names = "osc24M";
> > + #clock-cells = <0>;
> > + };
> > +
>
> Best regards,
> Krzysztof

2022-08-16 09:56:05

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

On 15/08/2022 08:08, Samuel Holland wrote:
> +
> + de: display-engine {
> + compatible = "allwinner,sun20i-d1-display-engine";
> + allwinner,pipelines = <&mixer0>, <&mixer1>;
> + status = "disabled";
> + };
> +
> + osc24M: osc24M-clk {

lowercase

> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;

This is a property of the board, not SoC.

> + clock-output-names = "osc24M";
> + #clock-cells = <0>;
> + };
> +

Best regards,
Krzysztof

2022-08-16 10:01:55

[permalink] [raw]

Subject: Re: [PATCH 07/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree

Am Montag, 15. August 2022, 07:08:10 CEST schrieb Samuel Holland:
> "D1 Nezha" is Allwinner's first-party development board for the D1 SoC.
> It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard audio,
> HDMI, gigabit Ethernet, WiFi and Bluetooth, USB 2.0 host and OTG ports,
> plus low-speed I/O from the SoC and a GPIO expander chip.
>
> Most other D1 boards copied the Nezha's power tree, with the 1.8V rail
> powered by the SoCs internal LDOA, analog domains powered by ALDO, and
> the rest of the board powered by always-on fixed regulators. Some (but
> not all) boards also copied the PWM CPU regulator. To avoid duplication,
> factor out the out the regulator references that are common across all
> known boards.
>
> Signed-off-by: Samuel Holland <[email protected]>
> ---
>
> arch/riscv/boot/dts/allwinner/Makefile | 1 +
> .../sun20i-d1-common-regulators.dtsi | 51 ++++++
> .../boot/dts/allwinner/sun20i-d1-nezha.dts | 171 ++++++++++++++++++
> 3 files changed, 223 insertions(+)
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
>
> diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile
> index f66554cd5c45..b0a15e8c8d82 100644
> --- a/arch/riscv/boot/dts/allwinner/Makefile
> +++ b/arch/riscv/boot/dts/allwinner/Makefile
> @@ -1 +1,2 @@
> # SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
> new file mode 100644
> index 000000000000..143a3e710c3c
> --- /dev/null
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
> @@ -0,0 +1,51 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +// Copyright (C) 2021-2022 Samuel Holland <[email protected]>

in (most/all) other devicetrees this is looks more like

// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/* Copyright (C) 2021-2022 Samuel Holland <[email protected]> */

otherwise
Tested-by: Heiko Stuebner <[email protected]>
Reviewed-by: Heiko Stuebner <[email protected]>

2022-08-16 10:18:14

by Jernej Škrabec

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

Dne torek, 16. avgust 2022 ob 11:12:05 CEST je Heiko Stübner napisal(a):
> Am Dienstag, 16. August 2022, 09:49:58 CEST schrieb Jernej Škrabec:
> > Dne torek, 16. avgust 2022 ob 09:41:45 CEST je Krzysztof Kozlowski
napisal(a):
> > > On 15/08/2022 08:08, Samuel Holland wrote:
> > > > +
> > > > + de: display-engine {
> > > > + compatible = "allwinner,sun20i-d1-display-engine";
> > > > + allwinner,pipelines = <&mixer0>, <&mixer1>;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + osc24M: osc24M-clk {
> > >
> > > lowercase
> > >
> > > > + compatible = "fixed-clock";
> > > > + clock-frequency = <24000000>;
> > >
> > > This is a property of the board, not SoC.
> >
> > SoC needs 24 MHz oscillator for correct operation, so each and every board
> > has it. Having it here simplifies board DT files.
>
> I guess the oscillator is a separate component on each board, right?

Correct.

> And DT obvious is meant to describe the hardware - independently from
> implementation-specific choices.

There is no choice in this case. 24 MHz crystal has to be present.

FWIW, including crystal node in SoC specific DTSI is already common pattern in
Allwinner ARM SoC DTSI files.

>
> Starting to discuss which exceptions to allow then might lead to even more
> exceptions.
>
> Also having to look for a board-component in the soc dtsi also is surprising
> if one gets to the party later on :-) .

As I said, if one is accustomed to Allwinner ARM DT development, it would be
more surprising to include 24 MHz crystal node in each and every board DT.

Best regards,
Jernej

2022-08-16 10:20:37

[permalink] [raw]

Subject: Re: [PATCH 05/12] riscv: Add the Allwinner SoC family Kconfig option

On 16/08/2022 10:17, Heiko Stübner wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Am Montag, 15. August 2022, 18:56:23 CEST schrieb [email protected]:
>> On 15/08/2022 06:08, Samuel Holland wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> Allwinner manufactures the sunxi family of application processors. This
>>> includes the "sun8i" series of ARMv7 SoCs, the "sun50i" series of ARMv8
>>> SoCs, and now the "sun20i" series of 64-bit RISC-V SoCs.
>>>
>>> The first SoC in the sun20i series is D1, containing a single T-HEAD
>>> C906 core. D1s is a low-pin-count variant of D1 with co-packaged DRAM.
>>>
>>> Most peripherals are shared across the entire chip family. In fact, the
>>> ARMv7 T113 SoC is pin-compatible and almost entirely register-compatible
>>> with the D1s.
>>>
>>> This means many existing device drivers can be reused. To facilitate
>>> this reuse, name the symbol ARCH_SUNXI, since that is what the existing
>>> drivers have as their dependency.
>>
>> Hey Samuel,
>> I think this and patch 12/12 with the defconfig changes should be
>> deferred until post LPC (which still leaves plenty of time for
>> making the 6.1 merge window). We already have like 4 different
>> approaches between the existing SOC_FOO symbols & two more when
>> D1 stuff and the Renesas stuff is considered.
>
> On the other hand, I don't really think it's that hard to change things
> after the fact? I.e. ARCH_SUNXI is pretty much set in stone anyway,
> so there isn't very much that _could_ change without affecting most
> driver subsystems in the kernel.
>
> So I don't think we'd actually need to wait with the Allwinner symbol.

True, but it'd be the same release anyway most likely so I don't
think that there'd really be any waiting involved. I /like/ the
idea of using ARCH_FOO rather than SOC_FOO as it's far more
consistent across the kernel - it's more a question of not doing
one thing here and another with the Renesas stuff to me.

>
>
> Heiko
>
>> Plan is to decide at LPC on one approach for what to do with
>> Kconfig.socs & to me it seems like a good idea to do what's being
>> done here - it's likely that further arm vendors will move and
>> keeping the common symbols makes a lot of sense to me...
>>
>> Thanks,
>> Conor.
>>
>>>
>>> Signed-off-by: Samuel Holland <[email protected]>
>>> ---
>>>
>>> arch/riscv/Kconfig.socs | 9 +++++++++
>>> 1 file changed, 9 insertions(+)
>>>
>>> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
>>> index 69774bb362d6..1caacbfac1a5 100644
>>> --- a/arch/riscv/Kconfig.socs
>>> +++ b/arch/riscv/Kconfig.socs
>>> @@ -1,5 +1,14 @@
>>> menu "SoC selection"
>>>
>>> +config ARCH_SUNXI
>>> + bool "Allwinner sun20i SoCs"
>>> + select ERRATA_THEAD if MMU && !XIP_KERNEL
>>> + select SIFIVE_PLIC
>>> + select SUN4I_TIMER
>>> + help
>>> + This enables support for Allwinner sun20i platform hardware,
>>> + including boards based on the D1 and D1s SoCs.
>>> +
>>> config SOC_MICROCHIP_POLARFIRE
>>> bool "Microchip PolarFire SoCs"
>>> select MCHP_CLK_MPFS
>>> --
>>> 2.35.1
>>>
>>
>> _______________________________________________
>> linux-riscv mailing list
>> [email protected]
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
>>
>
>
>
>

2022-08-16 10:24:18

[permalink] [raw]

Subject: Re: [PATCH 04/12] dt-bindings: riscv: Add Allwinner D1 board compatibles

Am Montag, 15. August 2022, 07:08:07 CEST schrieb Samuel Holland:
> Several SoMs and boards are available that feature the Allwinner D1 SoC.
> Document their compatible strings.
>
> Signed-off-by: Samuel Holland <[email protected]>

Tested-by: Heiko Stuebner <[email protected]>
Reviewed-by: Heiko Stuebner <[email protected]>

2022-08-16 10:50:04

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

Am Montag, 15. August 2022, 07:08:09 CEST schrieb Samuel Holland:
> D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, as well as
> one HiFi 4 DSP. The SoC is based on a design that additionally contained
> a pair of Cortex A7's. For that reason, some peripherals are duplicated.
>
> This devicetree includes all of the peripherals that already have a
> documented binding.
>
> Signed-off-by: Samuel Holland <[email protected]>

Tested-by: Heiko Stuebner <[email protected]>

2022-08-16 10:51:59

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

Am Dienstag, 16. August 2022, 09:49:58 CEST schrieb Jernej Škrabec:
> Dne torek, 16. avgust 2022 ob 09:41:45 CEST je Krzysztof Kozlowski napisal(a):
> > On 15/08/2022 08:08, Samuel Holland wrote:
> > > +
> > > + de: display-engine {
> > > + compatible = "allwinner,sun20i-d1-display-engine";
> > > + allwinner,pipelines = <&mixer0>, <&mixer1>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + osc24M: osc24M-clk {
> >
> > lowercase
> >
> > > + compatible = "fixed-clock";
> > > + clock-frequency = <24000000>;
> >
> > This is a property of the board, not SoC.
>
> SoC needs 24 MHz oscillator for correct operation, so each and every board has
> it. Having it here simplifies board DT files.

I guess the oscillator is a separate component on each board, right?
And DT obvious is meant to describe the hardware - independently from
implementation-specific choices.

Starting to discuss which exceptions to allow then might lead to even more
exceptions.

Also having to look for a board-component in the soc dtsi also is surprising
if one gets to the party later on :-) .

2022-08-16 11:20:35

[permalink] [raw]

Subject: Re: [PATCH 04/12] dt-bindings: riscv: Add Allwinner D1 board compatibles

Am Dienstag, 16. August 2022, 09:39:38 CEST schrieb Krzysztof Kozlowski:
> On 15/08/2022 08:08, Samuel Holland wrote:
> > Several SoMs and boards are available that feature the Allwinner D1 SoC.
> > Document their compatible strings.
> >
> > Signed-off-by: Samuel Holland <[email protected]>
> > ---
> >
> > .../devicetree/bindings/riscv/sunxi.yaml | 64 +++++++++++++++++++
> > 1 file changed, 64 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/riscv/sunxi.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/sunxi.yaml b/Documentation/devicetree/bindings/riscv/sunxi.yaml
> > new file mode 100644
> > index 000000000000..564a89499894
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/riscv/sunxi.yaml
> > @@ -0,0 +1,64 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/riscv/sunxi.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Allwinner RISC-V SoC-based boards
> > +
> > +maintainers:
> > + - Chen-Yu Tsai <[email protected]>
> > + - Jernej Skrabec <[email protected]>
> > + - Samuel Holland <[email protected]>
> > +
> > +description:
> > + Allwinner RISC-V SoC-based boards
> > +
> > +properties:
> > + $nodename:
> > + const: '/'
> > + compatible:
> > + oneOf:
> > + - description: Dongshan Nezha STU SoM
> > + items:
> > + - const: 100ask,dongshan-nezha-stu
> > + - const: allwinner,sun20i-d1
> > +
> > + - description: D1 Nezha board
> > + items:
> > + - const: allwinner,d1-nezha
>
> You grow the list unnecessary. Several entries should be an enum, unless
> platform maintainer insists on such approach for all Allwinner Riscv
> platforms. Just be aware it will grow...

Having the binding document provide value to mere mortals and not only
the automated tools is plus for me :-) . So obviously personally I like
the current style more. But yeah, it's mainly a matter of preference :-) .

2022-08-16 11:23:31

[permalink] [raw]

Subject: Re: [PATCH 05/12] riscv: Add the Allwinner SoC family Kconfig option

Am Montag, 15. August 2022, 18:56:23 CEST schrieb [email protected]:
> On 15/08/2022 06:08, Samuel Holland wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Allwinner manufactures the sunxi family of application processors. This
> > includes the "sun8i" series of ARMv7 SoCs, the "sun50i" series of ARMv8
> > SoCs, and now the "sun20i" series of 64-bit RISC-V SoCs.
> >
> > The first SoC in the sun20i series is D1, containing a single T-HEAD
> > C906 core. D1s is a low-pin-count variant of D1 with co-packaged DRAM.
> >
> > Most peripherals are shared across the entire chip family. In fact, the
> > ARMv7 T113 SoC is pin-compatible and almost entirely register-compatible
> > with the D1s.
> >
> > This means many existing device drivers can be reused. To facilitate
> > this reuse, name the symbol ARCH_SUNXI, since that is what the existing
> > drivers have as their dependency.
>
> Hey Samuel,
> I think this and patch 12/12 with the defconfig changes should be
> deferred until post LPC (which still leaves plenty of time for
> making the 6.1 merge window). We already have like 4 different
> approaches between the existing SOC_FOO symbols & two more when
> D1 stuff and the Renesas stuff is considered.

On the other hand, I don't really think it's that hard to change things
after the fact? I.e. ARCH_SUNXI is pretty much set in stone anyway,
so there isn't very much that _could_ change without affecting most
driver subsystems in the kernel.

So I don't think we'd actually need to wait with the Allwinner symbol.

Heiko

> Plan is to decide at LPC on one approach for what to do with
> Kconfig.socs & to me it seems like a good idea to do what's being
> done here - it's likely that further arm vendors will move and
> keeping the common symbols makes a lot of sense to me...
>
> Thanks,
> Conor.
>
> >
> > Signed-off-by: Samuel Holland <[email protected]>
> > ---
> >
> > arch/riscv/Kconfig.socs | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > index 69774bb362d6..1caacbfac1a5 100644
> > --- a/arch/riscv/Kconfig.socs
> > +++ b/arch/riscv/Kconfig.socs
> > @@ -1,5 +1,14 @@
> > menu "SoC selection"
> >
> > +config ARCH_SUNXI
> > + bool "Allwinner sun20i SoCs"
> > + select ERRATA_THEAD if MMU && !XIP_KERNEL
> > + select SIFIVE_PLIC
> > + select SUN4I_TIMER
> > + help
> > + This enables support for Allwinner sun20i platform hardware,
> > + including boards based on the D1 and D1s SoCs.
> > +
> > config SOC_MICROCHIP_POLARFIRE
> > bool "Microchip PolarFire SoCs"
> > select MCHP_CLK_MPFS
> > --
> > 2.35.1
> >
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv
>

2022-08-16 11:28:36

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

On 16/08/2022 12:25, Jernej Škrabec wrote:
> Dne torek, 16. avgust 2022 ob 11:12:05 CEST je Heiko Stübner napisal(a):
>> Am Dienstag, 16. August 2022, 09:49:58 CEST schrieb Jernej Škrabec:
>>> Dne torek, 16. avgust 2022 ob 09:41:45 CEST je Krzysztof Kozlowski
> napisal(a):
>>>> On 15/08/2022 08:08, Samuel Holland wrote:
>>>>> +
>>>>> + de: display-engine {
>>>>> + compatible = "allwinner,sun20i-d1-display-engine";
>>>>> + allwinner,pipelines = <&mixer0>, <&mixer1>;
>>>>> + status = "disabled";
>>>>> + };
>>>>> +
>>>>> + osc24M: osc24M-clk {
>>>>
>>>> lowercase
>>>>
>>>>> + compatible = "fixed-clock";
>>>>> + clock-frequency = <24000000>;
>>>>
>>>> This is a property of the board, not SoC.
>>>
>>> SoC needs 24 MHz oscillator for correct operation, so each and every board
>>> has it. Having it here simplifies board DT files.
>>
>> I guess the oscillator is a separate component on each board, right?
>
> Correct.
>
>> And DT obvious is meant to describe the hardware - independently from
>> implementation-specific choices.
>
> There is no choice in this case. 24 MHz crystal has to be present.
>
> FWIW, including crystal node in SoC specific DTSI is already common pattern in
> Allwinner ARM SoC DTSI files.
>
>>
>> Starting to discuss which exceptions to allow then might lead to even more
>> exceptions.
>>
>> Also having to look for a board-component in the soc dtsi also is surprising
>> if one gets to the party later on :-) .
>
> As I said, if one is accustomed to Allwinner ARM DT development, it would be
> more surprising to include 24 MHz crystal node in each and every board DT.

It's same everywhere. Allwinner, Exynos, iMX, Qualcomm. Everywhere this
is a part of the board, so even if oscillator frequency is fixed (as in
99% of cases although some SoCs I think might just allow to implement
one of few), still this is a property of the board. Because:
1. DTSI describes the SoC part, not board.
2. So the DTS developer is a bit more conscious about his design.

Keeping things in SoC DTSI just because it simplifies DTS is not correct
IMHO. So again - like in several other cases - minimum the frequency is
property of the board, not the SoC DTSI.

Everywhere. Allwinner is not special to receive exceptions.

Best regards,
Krzysztof

2022-08-16 11:51:52

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

On 16/08/2022 14:11, Krzysztof Kozlowski wrote:
>>
>> I think one reason might be that this is so central to the whole SoC
>> operation, that it's already referenced multiple times in the base .dtsi.
>> And having a yet unresolved reference in the .dtsi looks dodgy.
>>
>> NVidia seems to omit a base oscillator (maybe it's implicit in their
>> binding design), Marvell doesn't use a fixed-clock (but still puts their
>> base clock in armada-37xx.dtsi).
>>
>> Exynos and Renesas put a *stub* fixed-clock in the .dtsi, and set the
>> frequency in the board .dts files. Would this be a compromise?
>
> This is exactly what I said before. The clock frequency is a property of
> the board. Feel free to keep the rest of the clock in the SoC DTSI to
> reduce duplication, but at minimum the clock should go to the board.

s/minimum the clock should go to the board/minimum the clock frequency
should go to the board./

Best regards,
Krzysztof

2022-08-16 12:08:38

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

On Tue, 16 Aug 2022 12:42:39 +0300
Krzysztof Kozlowski <[email protected]> wrote:

Hi,

> On 16/08/2022 12:25, Jernej Škrabec wrote:
> > Dne torek, 16. avgust 2022 ob 11:12:05 CEST je Heiko Stübner napisal(a):
> >> Am Dienstag, 16. August 2022, 09:49:58 CEST schrieb Jernej Škrabec:
> >>> Dne torek, 16. avgust 2022 ob 09:41:45 CEST je Krzysztof Kozlowski
> > napisal(a):
> >>>> On 15/08/2022 08:08, Samuel Holland wrote:
> >>>>> +
> >>>>> + de: display-engine {
> >>>>> + compatible = "allwinner,sun20i-d1-display-engine";
> >>>>> + allwinner,pipelines = <&mixer0>, <&mixer1>;
> >>>>> + status = "disabled";
> >>>>> + };
> >>>>> +
> >>>>> + osc24M: osc24M-clk {
> >>>>
> >>>> lowercase
> >>>>
> >>>>> + compatible = "fixed-clock";
> >>>>> + clock-frequency = <24000000>;
> >>>>
> >>>> This is a property of the board, not SoC.
> >>>
> >>> SoC needs 24 MHz oscillator for correct operation, so each and every board
> >>> has it. Having it here simplifies board DT files.
> >>
> >> I guess the oscillator is a separate component on each board, right?
> >
> > Correct.
> >
> >> And DT obvious is meant to describe the hardware - independently from
> >> implementation-specific choices.
> >
> > There is no choice in this case. 24 MHz crystal has to be present.
> >
> > FWIW, including crystal node in SoC specific DTSI is already common pattern in
> > Allwinner ARM SoC DTSI files.
> >
> >>
> >> Starting to discuss which exceptions to allow then might lead to even more
> >> exceptions.
> >>
> >> Also having to look for a board-component in the soc dtsi also is surprising
> >> if one gets to the party later on :-) .
> >
> > As I said, if one is accustomed to Allwinner ARM DT development, it would be
> > more surprising to include 24 MHz crystal node in each and every board DT.
>
> It's same everywhere. Allwinner, Exynos, iMX, Qualcomm. Everywhere this
> is a part of the board, so even if oscillator frequency is fixed (as in
> 99% of cases although some SoCs I think might just allow to implement
> one of few), still this is a property of the board. Because:
> 1. DTSI describes the SoC part, not board.
> 2. So the DTS developer is a bit more conscious about his design.

1) is certainly true, but indeed most platforms put the base
crystal oscillator in the SoC .dtsi: I just sampled Rockchip (rk3399.dtsi,
rk356x.dtsi, rk3328.dtsi), Amlogic (meson-g12-common.dtsi), ActionSemi (s[79]00.dtsi),
Qualcomm (msm8916.dtsi, sm8450.dtsi, sc7180.dtsi), Freescale (imx8mm.dtsi,
imx8qxp.dtsi), Realtek (rtd129x.dtsi), Broadcom (bcm283x.dtsi), Mediatek
(mt8183.dtsi, mt8516.dtsi). The list probably goes on (I just stopped
here).

I think one reason might be that this is so central to the whole SoC
operation, that it's already referenced multiple times in the base .dtsi.
And having a yet unresolved reference in the .dtsi looks dodgy.

NVidia seems to omit a base oscillator (maybe it's implicit in their
binding design), Marvell doesn't use a fixed-clock (but still puts their
base clock in armada-37xx.dtsi).

Exynos and Renesas put a *stub* fixed-clock in the .dtsi, and set the
frequency in the board .dts files. Would this be a compromise?

Cheers,
Andre

> Keeping things in SoC DTSI just because it simplifies DTS is not correct
> IMHO. So again - like in several other cases - minimum the frequency is
> property of the board, not the SoC DTSI.
>
> Everywhere. Allwinner is not special to receive exceptions.
>
> Best regards,
> Krzysztof
>

2022-08-16 12:39:42

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

On 16/08/2022 12:12, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 16/08/2022 14:11, Krzysztof Kozlowski wrote:
>>>
>>> I think one reason might be that this is so central to the whole SoC
>>> operation, that it's already referenced multiple times in the base .dtsi.
>>> And having a yet unresolved reference in the .dtsi looks dodgy.
>>>
>>> NVidia seems to omit a base oscillator (maybe it's implicit in their
>>> binding design), Marvell doesn't use a fixed-clock (but still puts their
>>> base clock in armada-37xx.dtsi).
>>>
>>> Exynos and Renesas put a *stub* fixed-clock in the .dtsi, and set the
>>> frequency in the board .dts files. Would this be a compromise?
>>
>> This is exactly what I said before. The clock frequency is a property of
>> the board. Feel free to keep the rest of the clock in the SoC DTSI to
>> reduce duplication, but at minimum the clock should go to the board.
>
>
> s/minimum the clock should go to the board/minimum the clock frequency
> should go to the board./

FWIW this is what the PolarFire SoC stuff does (thanks to either
yourself or Geert) & it'd be nice to continue that precedence for
riscv dts going forward. No point IMO in duplicating things done
in the past in arch/arm if that's now considered bad practice.

2022-08-16 12:43:02

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

On 16/08/2022 14:00, Andre Przywara wrote:
> On Tue, 16 Aug 2022 12:42:39 +0300
> Krzysztof Kozlowski <[email protected]> wrote:
>
> Hi,
>
>> On 16/08/2022 12:25, Jernej Škrabec wrote:
>>> Dne torek, 16. avgust 2022 ob 11:12:05 CEST je Heiko Stübner napisal(a):
>>>> Am Dienstag, 16. August 2022, 09:49:58 CEST schrieb Jernej Škrabec:
>>>>> Dne torek, 16. avgust 2022 ob 09:41:45 CEST je Krzysztof Kozlowski
>>> napisal(a):
>>>>>> On 15/08/2022 08:08, Samuel Holland wrote:
>>>>>>> +
>>>>>>> + de: display-engine {
>>>>>>> + compatible = "allwinner,sun20i-d1-display-engine";
>>>>>>> + allwinner,pipelines = <&mixer0>, <&mixer1>;
>>>>>>> + status = "disabled";
>>>>>>> + };
>>>>>>> +
>>>>>>> + osc24M: osc24M-clk {
>>>>>>
>>>>>> lowercase
>>>>>>
>>>>>>> + compatible = "fixed-clock";
>>>>>>> + clock-frequency = <24000000>;
>>>>>>
>>>>>> This is a property of the board, not SoC.
>>>>>
>>>>> SoC needs 24 MHz oscillator for correct operation, so each and every board
>>>>> has it. Having it here simplifies board DT files.
>>>>
>>>> I guess the oscillator is a separate component on each board, right?
>>>
>>> Correct.
>>>
>>>> And DT obvious is meant to describe the hardware - independently from
>>>> implementation-specific choices.
>>>
>>> There is no choice in this case. 24 MHz crystal has to be present.
>>>
>>> FWIW, including crystal node in SoC specific DTSI is already common pattern in
>>> Allwinner ARM SoC DTSI files.
>>>
>>>>
>>>> Starting to discuss which exceptions to allow then might lead to even more
>>>> exceptions.
>>>>
>>>> Also having to look for a board-component in the soc dtsi also is surprising
>>>> if one gets to the party later on :-) .
>>>
>>> As I said, if one is accustomed to Allwinner ARM DT development, it would be
>>> more surprising to include 24 MHz crystal node in each and every board DT.
>>
>> It's same everywhere. Allwinner, Exynos, iMX, Qualcomm. Everywhere this
>> is a part of the board, so even if oscillator frequency is fixed (as in
>> 99% of cases although some SoCs I think might just allow to implement
>> one of few), still this is a property of the board. Because:
>> 1. DTSI describes the SoC part, not board.
>> 2. So the DTS developer is a bit more conscious about his design.
>
> 1) is certainly true, but indeed most platforms put the base
> crystal oscillator in the SoC .dtsi:

Yes. And once per week when I look at new DTS I need to repeat the same
arguments. :)

> I just sampled Rockchip (rk3399.dtsi,
> rk356x.dtsi, rk3328.dtsi), Amlogic (meson-g12-common.dtsi), ActionSemi (s[79]00.dtsi),
> Qualcomm (msm8916.dtsi, sm8450.dtsi, sc7180.dtsi), Freescale (imx8mm.dtsi,
> imx8qxp.dtsi), Realtek (rtd129x.dtsi), Broadcom (bcm283x.dtsi), Mediatek
> (mt8183.dtsi, mt8516.dtsi). The list probably goes on (I just stopped
> here).
>
> I think one reason might be that this is so central to the whole SoC
> operation, that it's already referenced multiple times in the base .dtsi.
> And having a yet unresolved reference in the .dtsi looks dodgy.
>
> NVidia seems to omit a base oscillator (maybe it's implicit in their
> binding design), Marvell doesn't use a fixed-clock (but still puts their
> base clock in armada-37xx.dtsi).
>
> Exynos and Renesas put a *stub* fixed-clock in the .dtsi, and set the
> frequency in the board .dts files. Would this be a compromise?

This is exactly what I said before. The clock frequency is a property of
the board. Feel free to keep the rest of the clock in the SoC DTSI to
reduce duplication, but at minimum the clock should go to the board.

Best regards,
Krzysztof

2022-08-16 17:42:14

by Rob Herring (Arm)

[permalink] [raw]

Subject: Re: [PATCH 03/12] dt-bindings: vendor-prefixes: Add Allwinner D1 board vendors

On Mon, 15 Aug 2022 00:08:06 -0500, Samuel Holland wrote:
> Some boards using the Allwinner D1 SoC are made by vendors not
> previously documented.
>
> Clockwork Tech LLC (https://www.clockworkpi.com/) manufactures the
> ClockworkPi and DevTerm boards.
>
> Beijing Widora Technology Co., Ltd. (https://mangopi.cc/) manufactures
> the MangoPi family of boards.
>
> Signed-off-by: Samuel Holland <[email protected]>
> ---
>
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>

Acked-by: Rob Herring <[email protected]>

2022-08-16 17:53:13

by Rob Herring (Arm)

[permalink] [raw]

Subject: Re: [PATCH 04/12] dt-bindings: riscv: Add Allwinner D1 board compatibles

On Mon, 15 Aug 2022 00:08:07 -0500, Samuel Holland wrote:
> Several SoMs and boards are available that feature the Allwinner D1 SoC.
> Document their compatible strings.
>
> Signed-off-by: Samuel Holland <[email protected]>
> ---
>
> .../devicetree/bindings/riscv/sunxi.yaml | 64 +++++++++++++++++++
> 1 file changed, 64 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/riscv/sunxi.yaml
>

Acked-by: Rob Herring <[email protected]>

2022-08-16 18:00:44

by Rob Herring (Arm)

[permalink] [raw]

Subject: Re: [PATCH 02/12] dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles

On Mon, 15 Aug 2022 00:08:05 -0500, Samuel Holland wrote:
> The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor.
> Notably, the C906 core is used in the Allwinner D1 SoC.
>
> Signed-off-by: Samuel Holland <[email protected]>
> ---
>
> Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>

Acked-by: Rob Herring <[email protected]>

2022-08-17 08:38:55

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

On 15/08/2022 08:08, Samuel Holland wrote:
> D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, as well as
> one HiFi 4 DSP. The SoC is based on a design that additionally contained
> a pair of Cortex A7's. For that reason, some peripherals are duplicated.
>
> This devicetree includes all of the peripherals that already have a
> documented binding.
>
> Signed-off-by: Samuel Holland <[email protected]>

(...)

> +
> + codec: audio-codec@2030000 {
> + compatible = "simple-mfd", "syscon";

This alone is not correct. You must use device specific compatible.

> + reg = <0x2030000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + regulators@2030348 {
> + compatible = "allwinner,sun20i-d1-analog-ldos";
> + reg = <0x2030348 0x4>;
> + nvmem-cells = <&bg_trim>;
> + nvmem-cell-names = "bg_trim";
> +
> + reg_aldo: aldo {
> + };
> +
> + reg_hpldo: hpldo {
> + };
> + };
> + };

Best regards,
Krzysztof

2022-08-19 22:27:32

[permalink] [raw]

Subject: Re: [PATCH 07/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree

Hey Samuel,

Finally got around to giving this a go with the fix for loading
modules which is mostly what was blocking me before..

On 15/08/2022 06:08, Samuel Holland wrote:
> "D1 Nezha" is Allwinner's first-party development board for the D1 SoC.
> It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard audio,

I am really not keen on the way you have things, with the memory
nodes removed from the device tree. I know your preferred flow
for booting these things might be to pass the dtb up from U-Boot,
but I think the devicetree in the kernel should be usable in a
standalone manner, even if that is the barest-minimum memory
config.

I did figure out all of my issues getting booted, thanks partly
to Heiko. The U-Boot dtb being misaligned was part of it as was
my initramfs with some stale sunxi modules in it causing RCU
stalls.. so sorry for the noise on that front (and thanks again
to Heiko!).

Modulo the memory node, since I had to hack that in to get things
working & I do not want to have to keep doing:
Tested-by: Conor Dooley <[email protected]>

Thanks & apologies again for the modules-related issues - it was
hard to debug that one since module loading was broken on RISC-V
at the time.
Conor.

> HDMI, gigabit Ethernet, WiFi and Bluetooth, USB 2.0 host and OTG ports,
> plus low-speed I/O from the SoC and a GPIO expander chip.
>
> Most other D1 boards copied the Nezha's power tree, with the 1.8V rail
> powered by the SoCs internal LDOA, analog domains powered by ALDO, and
> the rest of the board powered by always-on fixed regulators. Some (but
> not all) boards also copied the PWM CPU regulator. To avoid duplication,
> factor out the out the regulator references that are common across all
> known boards.
>
> Signed-off-by: Samuel Holland <[email protected]>
> ---
>
> arch/riscv/boot/dts/allwinner/Makefile | 1 +
> .../sun20i-d1-common-regulators.dtsi | 51 ++++++
> .../boot/dts/allwinner/sun20i-d1-nezha.dts | 171 ++++++++++++++++++
> 3 files changed, 223 insertions(+)
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
>
> diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile
> index f66554cd5c45..b0a15e8c8d82 100644
> --- a/arch/riscv/boot/dts/allwinner/Makefile
> +++ b/arch/riscv/boot/dts/allwinner/Makefile
> @@ -1 +1,2 @@
> # SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
> new file mode 100644
> index 000000000000..143a3e710c3c
> --- /dev/null
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
> @@ -0,0 +1,51 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
> +
> +/ {
> + reg_vcc: vcc {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + };
> +
> + reg_vcc_3v3: vcc-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc-3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + vin-supply = <&reg_vcc>;
> + };
> +};
> +
> +&lradc {
> + vref-supply = <&reg_aldo>;
> +};
> +
> +&pio {
> + vcc-pb-supply = <&reg_vcc_3v3>;
> + vcc-pc-supply = <&reg_vcc_3v3>;
> + vcc-pd-supply = <&reg_vcc_3v3>;
> + vcc-pe-supply = <&reg_vcc_3v3>;
> + vcc-pf-supply = <&reg_vcc_3v3>;
> + vcc-pg-supply = <&reg_vcc_3v3>;
> +};
> +
> +&reg_aldo {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + vdd33-supply = <&reg_vcc_3v3>;
> +};
> +
> +&reg_hpldo {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + hpldoin-supply = <&reg_vcc_3v3>;
> +};
> +
> +&reg_ldoa {
> + regulator-always-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + ldo-in-supply = <&reg_vcc_3v3>;
> +};
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
> new file mode 100644
> index 000000000000..df865ee15fcf
> --- /dev/null
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
> @@ -0,0 +1,171 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +
> +#include "sun20i-d1.dtsi"
> +#include "sun20i-d1-common-regulators.dtsi"
> +
> +/ {
> + model = "Allwinner D1 Nezha";
> + compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1";
> +
> + aliases {
> + ethernet0 = &emac;
> + ethernet1 = &xr829;
> + mmc0 = &mmc0;
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + reg_usbvbus: usbvbus {
> + compatible = "regulator-fixed";
> + regulator-name = "usbvbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
> + enable-active-high;
> + vin-supply = <&reg_vcc>;
> + };
> +
> + /*
> + * This regulator is PWM-controlled, but the PWM controller is not
> + * yet supported, so fix the regulator to its default voltage.
> + */
> + reg_vdd_cpu: vdd-cpu {
> + compatible = "regulator-fixed";
> + regulator-name = "vdd-cpu";
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1100000>;
> + vin-supply = <&reg_vcc>;
> + };
> +
> + wifi_pwrseq: wifi-pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
> + };
> +};
> +
> +&cpu0 {
> + cpu-supply = <&reg_vdd_cpu>;
> +};
> +
> +&ehci0 {
> + status = "okay";
> +};
> +
> +&ehci1 {
> + status = "okay";
> +};
> +
> +&emac {
> + pinctrl-0 = <&rgmii_pe_pins>;
> + pinctrl-names = "default";
> + phy-handle = <&ext_rgmii_phy>;
> + phy-mode = "rgmii-id";
> + phy-supply = <&reg_vcc_3v3>;
> + status = "okay";
> +};
> +
> +&i2c2 {
> + pinctrl-0 = <&i2c2_pb0_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + pcf8574a: gpio@38 {
> + compatible = "nxp,pcf8574a";
> + reg = <0x38>;
> + interrupt-parent = <&pio>;
> + interrupts = <1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */
> + interrupt-controller;
> + gpio-controller;
> + #gpio-cells = <2>;
> + #interrupt-cells = <2>;
> + };
> +};
> +
> +&lradc {
> + status = "okay";
> +
> + button-160 {
> + label = "OK";
> + linux,code = <KEY_OK>;
> + channel = <0>;
> + voltage = <160000>;
> + };
> +};
> +
> +&mdio {
> + ext_rgmii_phy: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
> + };
> +};
> +
> +&mmc0 {
> + bus-width = <4>;
> + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
> + disable-wp;
> + vmmc-supply = <&reg_vcc_3v3>;
> + vqmmc-supply = <&reg_vcc_3v3>;
> + pinctrl-0 = <&mmc0_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&mmc1 {
> + bus-width = <4>;
> + mmc-pwrseq = <&wifi_pwrseq>;
> + non-removable;
> + vmmc-supply = <&reg_vcc_3v3>;
> + vqmmc-supply = <&reg_vcc_3v3>;
> + pinctrl-0 = <&mmc1_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + xr829: wifi@1 {
> + reg = <1>;
> + };
> +};
> +
> +&ohci0 {
> + status = "okay";
> +};
> +
> +&ohci1 {
> + status = "okay";
> +};
> +
> +&uart0 {
> + pinctrl-0 = <&uart0_pb8_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&uart1 {
> + uart-has-rtscts;
> + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + /* XR829 bluetooth is connected here */
> +};
> +
> +&usb_otg {
> + dr_mode = "otg";
> + status = "okay";
> +};
> +
> +&usbphy {
> + usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
> + usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
> + usb0_vbus-supply = <&reg_usbvbus>;
> + usb1_vbus-supply = <&reg_vcc>;
> + status = "okay";
> +};

2022-08-19 23:02:22

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

On 15/08/2022 06:08, Samuel Holland wrote:
> D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, as well as
> one HiFi 4 DSP. The SoC is based on a design that additionally contained
> a pair of Cortex A7's. For that reason, some peripherals are duplicated.
>
> This devicetree includes all of the peripherals that already have a
> documented binding.
>
> Signed-off-by: Samuel Holland <[email protected]>

Tested-by: Conor Dooley <[email protected]> # Nezha D1

Thanks!

> ---
>
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/allwinner/Makefile | 1 +
> arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 900 +++++++++++++++++++
> 3 files changed, 902 insertions(+)
> create mode 100644 arch/riscv/boot/dts/allwinner/Makefile
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index ff174996cdfd..f292e31bdb2c 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -1,4 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0
> +subdir-y += allwinner
> subdir-y += sifive
> subdir-y += starfive
> subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
> diff --git a/arch/riscv/boot/dts/allwinner/Makefile b/arch/riscv/boot/dts/allwinner/Makefile
> new file mode 100644
> index 000000000000..f66554cd5c45
> --- /dev/null
> +++ b/arch/riscv/boot/dts/allwinner/Makefile
> @@ -0,0 +1 @@
> +# SPDX-License-Identifier: GPL-2.0
> diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
> new file mode 100644
> index 000000000000..d1429274f22e
> --- /dev/null
> +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
> @@ -0,0 +1,900 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
> +
> +#include <dt-bindings/clock/sun6i-rtc.h>
> +#include <dt-bindings/clock/sun8i-de2.h>
> +#include <dt-bindings/clock/sun8i-tcon-top.h>
> +#include <dt-bindings/clock/sun20i-d1-ccu.h>
> +#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/reset/sun8i-de2.h>
> +#include <dt-bindings/reset/sun20i-d1-ccu.h>
> +#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
> +#include <dt-bindings/thermal/thermal.h>
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpus {
> + timebase-frequency = <24000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + compatible = "thead,c906", "riscv";
> + device_type = "cpu";
> + reg = <0>;
> + clocks = <&ccu CLK_RISCV>;
> + clock-frequency = <24000000>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <256>;
> + d-cache-size = <32768>;
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + mmu-type = "riscv,sv39";
> + riscv,isa = "rv64imafdc";
> + #cooling-cells = <2>;
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + };
> + };
> + };
> +
> + de: display-engine {
> + compatible = "allwinner,sun20i-d1-display-engine";
> + allwinner,pipelines = <&mixer0>, <&mixer1>;
> + status = "disabled";
> + };
> +
> + osc24M: osc24M-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + clock-output-names = "osc24M";
> + #clock-cells = <0>;
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + ranges;
> + interrupt-parent = <&plic>;
> + dma-noncoherent;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + dsp_wdt: watchdog@1700400 {
> + compatible = "allwinner,sun20i-d1-wdt";
> + reg = <0x1700400 0x20>;
> + interrupts = <138 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>, <&rtc CLK_OSC32K>;
> + clock-names = "hosc", "losc";
> + status = "reserved";
> + };
> +
> + pio: pinctrl@2000000 {
> + compatible = "allwinner,sun20i-d1-pinctrl";
> + reg = <0x2000000 0x800>;
> + interrupts = <85 IRQ_TYPE_LEVEL_HIGH>,
> + <87 IRQ_TYPE_LEVEL_HIGH>,
> + <89 IRQ_TYPE_LEVEL_HIGH>,
> + <91 IRQ_TYPE_LEVEL_HIGH>,
> + <93 IRQ_TYPE_LEVEL_HIGH>,
> + <95 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_APB0>,
> + <&osc24M>,
> + <&rtc CLK_OSC32K>;
> + clock-names = "apb", "hosc", "losc";
> + gpio-controller;
> + interrupt-controller;
> + #gpio-cells = <3>;
> + #interrupt-cells = <3>;
> +
> + /omit-if-no-ref/
> + i2c0_pb10_pins: i2c0-pb10-pins {
> + pins = "PB10", "PB11";
> + function = "i2c0";
> + };
> +
> + /omit-if-no-ref/
> + i2c2_pb0_pins: i2c2-pb0-pins {
> + pins = "PB0", "PB1";
> + function = "i2c2";
> + };
> +
> + /omit-if-no-ref/
> + lcd_rgb666_pins: lcd-rgb666-pins {
> + pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
> + "PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
> + "PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
> + "PD18", "PD19", "PD20", "PD21";
> + function = "lcd0";
> + };
> +
> + /omit-if-no-ref/
> + mmc0_pins: mmc0-pins {
> + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
> + function = "mmc0";
> + };
> +
> + /omit-if-no-ref/
> + mmc1_pins: mmc1-pins {
> + pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
> + function = "mmc1";
> + };
> +
> + /omit-if-no-ref/
> + mmc2_pins: mmc2-pins {
> + pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
> + function = "mmc2";
> + };
> +
> + /omit-if-no-ref/
> + rgmii_pe_pins: rgmii-pe-pins {
> + pins = "PE0", "PE1", "PE2", "PE3", "PE4",
> + "PE5", "PE6", "PE7", "PE8", "PE9",
> + "PE11", "PE12", "PE13", "PE14", "PE15";
> + function = "emac";
> + };
> +
> + /omit-if-no-ref/
> + rmii_pe_pins: rmii-pe-pins {
> + pins = "PE0", "PE1", "PE2", "PE3", "PE4",
> + "PE5", "PE6", "PE7", "PE8", "PE9";
> + function = "emac";
> + };
> +
> + /omit-if-no-ref/
> + uart0_pb8_pins: uart0-pb8-pins {
> + pins = "PB8", "PB9";
> + function = "uart0";
> + };
> +
> + /omit-if-no-ref/
> + uart1_pg6_pins: uart1-pg6-pins {
> + pins = "PG6", "PG7";
> + function = "uart1";
> + };
> +
> + /omit-if-no-ref/
> + uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins {
> + pins = "PG8", "PG9";
> + function = "uart1";
> + };
> + };
> +
> + ccu: clock-controller@2001000 {
> + compatible = "allwinner,sun20i-d1-ccu";
> + reg = <0x2001000 0x1000>;
> + clocks = <&osc24M>,
> + <&rtc CLK_OSC32K>,
> + <&rtc CLK_IOSC>;
> + clock-names = "hosc", "losc", "iosc";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + lradc: keys@2009800 {
> + compatible = "allwinner,sun20i-d1-lradc",
> + "allwinner,sun50i-r329-lradc";
> + reg = <0x2009800 0x400>;
> + interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_LRADC>;
> + resets = <&ccu RST_BUS_LRADC>;
> + status = "disabled";
> + };
> +
> + codec: audio-codec@2030000 {
> + compatible = "simple-mfd", "syscon";
> + reg = <0x2030000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + regulators@2030348 {
> + compatible = "allwinner,sun20i-d1-analog-ldos";
> + reg = <0x2030348 0x4>;
> + nvmem-cells = <&bg_trim>;
> + nvmem-cell-names = "bg_trim";
> +
> + reg_aldo: aldo {
> + };
> +
> + reg_hpldo: hpldo {
> + };
> + };
> + };
> +
> + i2s0: i2s@2032000 {
> + compatible = "allwinner,sun20i-d1-i2s",
> + "allwinner,sun50i-r329-i2s";
> + reg = <0x2032000 0x1000>;
> + interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2S0>,
> + <&ccu CLK_I2S0>;
> + clock-names = "apb", "mod";
> + resets = <&ccu RST_BUS_I2S0>;
> + dmas = <&dma 3>, <&dma 3>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + #sound-dai-cells = <0>;
> + };
> +
> + i2s1: i2s@2033000 {
> + compatible = "allwinner,sun20i-d1-i2s",
> + "allwinner,sun50i-r329-i2s";
> + reg = <0x2033000 0x1000>;
> + interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2S1>,
> + <&ccu CLK_I2S1>;
> + clock-names = "apb", "mod";
> + resets = <&ccu RST_BUS_I2S1>;
> + dmas = <&dma 4>, <&dma 4>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + #sound-dai-cells = <0>;
> + };
> +
> + i2s2: i2s@2034000 {
> + compatible = "allwinner,sun20i-d1-i2s",
> + "allwinner,sun50i-r329-i2s";
> + reg = <0x2034000 0x1000>;
> + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2S2>,
> + <&ccu CLK_I2S2>;
> + clock-names = "apb", "mod";
> + resets = <&ccu RST_BUS_I2S2>;
> + dmas = <&dma 5>, <&dma 5>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + #sound-dai-cells = <0>;
> + };
> +
> + timer: timer@2050000 {
> + compatible = "allwinner,sun20i-d1-timer",
> + "allwinner,sun8i-a23-timer";
> + reg = <0x2050000 0xa0>;
> + interrupts = <75 IRQ_TYPE_LEVEL_HIGH>,
> + <76 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>;
> + };
> +
> + wdt: watchdog@20500a0 {
> + compatible = "allwinner,sun20i-d1-wdt-reset",
> + "allwinner,sun20i-d1-wdt";
> + reg = <0x20500a0 0x20>;
> + interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>, <&rtc CLK_OSC32K>;
> + clock-names = "hosc", "losc";
> + status = "reserved";
> + };
> +
> + uart0: serial@2500000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x2500000 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_UART0>;
> + resets = <&ccu RST_BUS_UART0>;
> + dmas = <&dma 14>, <&dma 14>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart1: serial@2500400 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x2500400 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_UART1>;
> + resets = <&ccu RST_BUS_UART1>;
> + dmas = <&dma 15>, <&dma 15>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart2: serial@2500800 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x2500800 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_UART2>;
> + resets = <&ccu RST_BUS_UART2>;
> + dmas = <&dma 16>, <&dma 16>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart3: serial@2500c00 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x2500c00 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_UART3>;
> + resets = <&ccu RST_BUS_UART3>;
> + dmas = <&dma 17>, <&dma 17>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart4: serial@2501000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x2501000 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_UART4>;
> + resets = <&ccu RST_BUS_UART4>;
> + dmas = <&dma 18>, <&dma 18>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + uart5: serial@2501400 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x2501400 0x400>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_UART5>;
> + resets = <&ccu RST_BUS_UART5>;
> + dmas = <&dma 19>, <&dma 19>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + i2c0: i2c@2502000 {
> + compatible = "allwinner,sun20i-d1-i2c",
> + "allwinner,sun8i-v536-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x2502000 0x400>;
> + interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C0>;
> + resets = <&ccu RST_BUS_I2C0>;
> + dmas = <&dma 43>, <&dma 43>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c1: i2c@2502400 {
> + compatible = "allwinner,sun20i-d1-i2c",
> + "allwinner,sun8i-v536-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x2502400 0x400>;
> + interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C1>;
> + resets = <&ccu RST_BUS_I2C1>;
> + dmas = <&dma 44>, <&dma 44>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c2: i2c@2502800 {
> + compatible = "allwinner,sun20i-d1-i2c",
> + "allwinner,sun8i-v536-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x2502800 0x400>;
> + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C2>;
> + resets = <&ccu RST_BUS_I2C2>;
> + dmas = <&dma 45>, <&dma 45>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c3: i2c@2502c00 {
> + compatible = "allwinner,sun20i-d1-i2c",
> + "allwinner,sun8i-v536-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x2502c00 0x400>;
> + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C3>;
> + resets = <&ccu RST_BUS_I2C3>;
> + dmas = <&dma 46>, <&dma 46>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + syscon: syscon@3000000 {
> + compatible = "allwinner,sun20i-d1-system-control";
> + reg = <0x3000000 0x1000>;
> + ranges;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + regulators@3000150 {
> + compatible = "allwinner,sun20i-d1-system-ldos";
> + reg = <0x3000150 0x4>;
> +
> + reg_ldoa: ldoa {
> + };
> +
> + reg_ldob: ldob {
> + };
> + };
> + };
> +
> + dma: dma-controller@3002000 {
> + compatible = "allwinner,sun20i-d1-dma";
> + reg = <0x3002000 0x1000>;
> + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
> + clock-names = "bus", "mbus";
> + resets = <&ccu RST_BUS_DMA>;
> + dma-channels = <16>;
> + dma-requests = <48>;
> + #dma-cells = <1>;
> + };
> +
> + sid: efuse@3006000 {
> + compatible = "allwinner,sun20i-d1-sid";
> + reg = <0x3006000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + ths_calib: ths-calib@14 {
> + reg = <0x14 0x4>;
> + };
> +
> + bg_trim: bg-trim@28 {
> + reg = <0x28 0x4>;
> + bits = <16 8>;
> + };
> + };
> +
> + mbus: dram-controller@3102000 {
> + compatible = "allwinner,sun20i-d1-mbus";
> + reg = <0x3102000 0x1000>,
> + <0x3103000 0x1000>;
> + reg-names = "mbus", "dram";
> + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_MBUS>,
> + <&ccu CLK_DRAM>,
> + <&ccu CLK_BUS_DRAM>;
> + clock-names = "mbus", "dram", "bus";
> + dma-ranges = <0 0x40000000 0x80000000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + #interconnect-cells = <1>;
> + };
> +
> + mmc0: mmc@4020000 {
> + compatible = "allwinner,sun20i-d1-mmc";
> + reg = <0x4020000 0x1000>;
> + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
> + clock-names = "ahb", "mmc";
> + resets = <&ccu RST_BUS_MMC0>;
> + reset-names = "ahb";
> + cap-sd-highspeed;
> + max-frequency = <150000000>;
> + no-mmc;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc1: mmc@4021000 {
> + compatible = "allwinner,sun20i-d1-mmc";
> + reg = <0x4021000 0x1000>;
> + interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
> + clock-names = "ahb", "mmc";
> + resets = <&ccu RST_BUS_MMC1>;
> + reset-names = "ahb";
> + cap-sd-highspeed;
> + max-frequency = <150000000>;
> + no-mmc;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc2: mmc@4022000 {
> + compatible = "allwinner,sun20i-d1-emmc",
> + "allwinner,sun50i-a100-emmc";
> + reg = <0x4022000 0x1000>;
> + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
> + clock-names = "ahb", "mmc";
> + resets = <&ccu RST_BUS_MMC2>;
> + reset-names = "ahb";
> + cap-mmc-highspeed;
> + max-frequency = <150000000>;
> + mmc-ddr-1_8v;
> + mmc-ddr-3_3v;
> + no-sd;
> + no-sdio;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + usb_otg: usb@4100000 {
> + compatible = "allwinner,sun20i-d1-musb",
> + "allwinner,sun8i-a33-musb";
> + reg = <0x4100000 0x400>;
> + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "mc";
> + clocks = <&ccu CLK_BUS_OTG>;
> + resets = <&ccu RST_BUS_OTG>;
> + extcon = <&usbphy 0>;
> + phys = <&usbphy 0>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + usbphy: phy@4100400 {
> + compatible = "allwinner,sun20i-d1-usb-phy";
> + reg = <0x4100400 0x100>,
> + <0x4101800 0x100>,
> + <0x4200800 0x100>;
> + reg-names = "phy_ctrl",
> + "pmu0",
> + "pmu1";
> + clocks = <&osc24M>,
> + <&osc24M>;
> + clock-names = "usb0_phy",
> + "usb1_phy";
> + resets = <&ccu RST_USB_PHY0>,
> + <&ccu RST_USB_PHY1>;
> + reset-names = "usb0_reset",
> + "usb1_reset";
> + status = "disabled";
> + #phy-cells = <1>;
> + };
> +
> + ehci0: usb@4101000 {
> + compatible = "allwinner,sun20i-d1-ehci",
> + "generic-ehci";
> + reg = <0x4101000 0x100>;
> + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_OHCI0>,
> + <&ccu CLK_BUS_EHCI0>,
> + <&ccu CLK_USB_OHCI0>;
> + resets = <&ccu RST_BUS_OHCI0>,
> + <&ccu RST_BUS_EHCI0>;
> + phys = <&usbphy 0>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + ohci0: usb@4101400 {
> + compatible = "allwinner,sun20i-d1-ohci",
> + "generic-ohci";
> + reg = <0x4101400 0x100>;
> + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_OHCI0>,
> + <&ccu CLK_USB_OHCI0>;
> + resets = <&ccu RST_BUS_OHCI0>;
> + phys = <&usbphy 0>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + ehci1: usb@4200000 {
> + compatible = "allwinner,sun20i-d1-ehci",
> + "generic-ehci";
> + reg = <0x4200000 0x100>;
> + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_OHCI1>,
> + <&ccu CLK_BUS_EHCI1>,
> + <&ccu CLK_USB_OHCI1>;
> + resets = <&ccu RST_BUS_OHCI1>,
> + <&ccu RST_BUS_EHCI1>;
> + phys = <&usbphy 1>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + ohci1: usb@4200400 {
> + compatible = "allwinner,sun20i-d1-ohci",
> + "generic-ohci";
> + reg = <0x4200400 0x100>;
> + interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_OHCI1>,
> + <&ccu CLK_USB_OHCI1>;
> + resets = <&ccu RST_BUS_OHCI1>;
> + phys = <&usbphy 1>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + emac: ethernet@4500000 {
> + compatible = "allwinner,sun20i-d1-emac",
> + "allwinner,sun50i-a64-emac";
> + reg = <0x4500000 0x10000>;
> + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq";
> + clocks = <&ccu CLK_BUS_EMAC>;
> + clock-names = "stmmaceth";
> + resets = <&ccu RST_BUS_EMAC>;
> + reset-names = "stmmaceth";
> + syscon = <&syscon>;
> + status = "disabled";
> +
> + mdio: mdio {
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + display_clocks: clock-controller@5000000 {
> + compatible = "allwinner,sun20i-d1-de2-clk",
> + "allwinner,sun50i-h5-de2-clk";
> + reg = <0x5000000 0x10000>;
> + clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
> + clock-names = "bus", "mod";
> + resets = <&ccu RST_BUS_DE>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + mixer0: mixer@5100000 {
> + compatible = "allwinner,sun20i-d1-de2-mixer-0";
> + reg = <0x5100000 0x100000>;
> + clocks = <&display_clocks CLK_BUS_MIXER0>,
> + <&display_clocks CLK_MIXER0>;
> + clock-names = "bus", "mod";
> + resets = <&display_clocks RST_MIXER0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mixer0_out: port@1 {
> + reg = <1>;
> +
> + mixer0_out_tcon_top_mixer0: endpoint {
> + remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
> + };
> + };
> + };
> + };
> +
> + mixer1: mixer@5200000 {
> + compatible = "allwinner,sun20i-d1-de2-mixer-1";
> + reg = <0x5200000 0x100000>;
> + clocks = <&display_clocks CLK_BUS_MIXER1>,
> + <&display_clocks CLK_MIXER1>;
> + clock-names = "bus", "mod";
> + resets = <&display_clocks RST_MIXER1>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mixer1_out: port@1 {
> + reg = <1>;
> +
> + mixer1_out_tcon_top_mixer1: endpoint {
> + remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
> + };
> + };
> + };
> + };
> +
> + tcon_top: tcon-top@5460000 {
> + compatible = "allwinner,sun20i-d1-tcon-top";
> + reg = <0x5460000 0x1000>;
> + clocks = <&ccu CLK_BUS_DPSS_TOP>,
> + <&ccu CLK_TCON_TV>,
> + <&ccu CLK_TVE>,
> + <&ccu CLK_MIPI_DSI>;
> + clock-names = "bus", "tcon-tv0", "tve0", "dsi";
> + clock-output-names = "tcon-top-tv0", "tcon-top-dsi";
> + resets = <&ccu RST_BUS_DPSS_TOP>;
> + #clock-cells = <1>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_top_mixer0_in: port@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_top_mixer0_in_mixer0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
> + };
> + };
> +
> + tcon_top_mixer0_out: port@1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
> + };
> +
> + tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
> + reg = <2>;
> + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
> + };
> + };
> +
> + tcon_top_mixer1_in: port@2 {
> + reg = <2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_top_mixer1_in_mixer1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
> + };
> + };
> +
> + tcon_top_mixer1_out: port@3 {
> + reg = <3>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>;
> + };
> +
> + tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
> + reg = <2>;
> + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
> + };
> + };
> +
> + tcon_top_hdmi_in: port@4 {
> + reg = <4>;
> +
> + tcon_top_hdmi_in_tcon_tv0: endpoint {
> + remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>;
> + };
> + };
> +
> + tcon_top_hdmi_out: port@5 {
> + reg = <5>;
> + };
> + };
> + };
> +
> + tcon_lcd0: lcd-controller@5461000 {
> + compatible = "allwinner,sun20i-d1-tcon-lcd";
> + reg = <0x5461000 0x1000>;
> + interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_TCON_LCD0>,
> + <&ccu CLK_TCON_LCD0>;
> + clock-names = "ahb", "tcon-ch0";
> + clock-output-names = "tcon-pixel-clock";
> + resets = <&ccu RST_BUS_TCON_LCD0>,
> + <&ccu RST_BUS_LVDS0>;
> + reset-names = "lcd", "lvds";
> + #clock-cells = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_lcd0_in: port@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
> + };
> +
> + tcon_lcd0_in_tcon_top_mixer1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>;
> + };
> + };
> +
> + tcon_lcd0_out: port@1 {
> + reg = <1>;
> + };
> + };
> + };
> +
> + tcon_tv0: lcd-controller@5470000 {
> + compatible = "allwinner,sun20i-d1-tcon-tv";
> + reg = <0x5470000 0x1000>;
> + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_TCON_TV>,
> + <&tcon_top CLK_TCON_TOP_TV0>;
> + clock-names = "ahb", "tcon-ch1";
> + resets = <&ccu RST_BUS_TCON_TV>;
> + reset-names = "lcd";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_tv0_in: port@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
> + };
> +
> + tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
> + };
> + };
> +
> + tcon_tv0_out: port@1 {
> + reg = <1>;
> +
> + tcon_tv0_out_tcon_top_hdmi: endpoint {
> + remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
> + };
> + };
> + };
> + };
> +
> + riscv_wdt: watchdog@6011000 {
> + compatible = "allwinner,sun20i-d1-wdt";
> + reg = <0x6011000 0x20>;
> + interrupts = <147 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>, <&rtc CLK_OSC32K>;
> + clock-names = "hosc", "losc";
> + };
> +
> + r_ccu: clock-controller@7010000 {
> + compatible = "allwinner,sun20i-d1-r-ccu";
> + reg = <0x7010000 0x400>;
> + clocks = <&osc24M>,
> + <&rtc CLK_OSC32K>,
> + <&rtc CLK_IOSC>,
> + <&ccu CLK_PLL_PERIPH0_DIV3>;
> + clock-names = "hosc", "losc", "iosc", "pll-periph";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + rtc: rtc@7090000 {
> + compatible = "allwinner,sun20i-d1-rtc",
> + "allwinner,sun50i-r329-rtc";
> + reg = <0x7090000 0x400>;
> + interrupts = <160 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&r_ccu CLK_BUS_R_RTC>,
> + <&osc24M>,
> + <&r_ccu CLK_R_AHB>;
> + clock-names = "bus", "hosc", "ahb";
> + #clock-cells = <1>;
> + };
> +
> + plic: interrupt-controller@10000000 {
> + compatible = "allwinner,sun20i-d1-plic",
> + "thead,c900-plic";
> + reg = <0x10000000 0x4000000>;
> + interrupts-extended = <&cpu0_intc 11>,
> + <&cpu0_intc 9>;
> + interrupt-controller;
> + riscv,ndev = <176>;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + };
> + };
> +};

2022-08-20 17:42:48

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

On 8/15/22 12:01 PM, [email protected] wrote:
> On 15/08/2022 14:11, Andre Przywara wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> On Mon, 15 Aug 2022 00:08:09 -0500
>> Samuel Holland <[email protected]> wrote:
>>
>> Hi,
>>
>> thanks for all the efforts in getting those SoC peripherals supported!
>>
>>> D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, as well as
>>> one HiFi 4 DSP. The SoC is based on a design that additionally contained
>>> a pair of Cortex A7's. For that reason, some peripherals are duplicated.
>>
>> So because of this, the Allwinner R528 and T113 SoCs would share almost
>> everything in this file. Would it be useful to already split this DT up?
>> To have a base .dtsi, basically this file without /cpus and /soc/plic,
>> then have a RISC-V specific file with just those, including the base?
>> There is precedence for this across-arch(-directories) sharing with the
>> Raspberry Pi and Allwinner H3/H5 SoCs.
>
> For those playing along at home, one example is the arm64 bananapi m2
> dts which looks like:
>> /dts-v1/;
>> #include "sun50i-h5.dtsi"
>> #include "sun50i-h5-cpu-opp.dtsi"
>> #include <arm/sunxi-bananapi-m2-plus-v1.2.dtsi>
>>
>> / {
>> model = "Banana Pi BPI-M2-Plus v1.2 H5";
>> compatible = "bananapi,bpi-m2-plus-v1.2", "allwinner,sun50i-h5";
>> };
>
> I think this is a pretty good idea, and putting in the modularity up
> front seems logical to me, so when the arm one does eventually get
> added it can be done by only touching a single arch.

This is not feasible, due to the different #interrupt-cells. See
https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/

Even if we share some file across architectures, you still have to update files
in both places to get the interrupts properties correct.

I get the desire to deduplicate things, but we already deal with updating the
same/similar nodes across several SoCs, so that is nothing new. I think it would
be more confusing/complicated to have all of the interrupts properties
overridden in a separate file.

Regards,
Samuel

2022-08-20 17:44:23

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

On 20/08/2022 18:24, Samuel Holland wrote:
> On 8/15/22 12:01 PM, [email protected] wrote:
>> On 15/08/2022 14:11, Andre Przywara wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> On Mon, 15 Aug 2022 00:08:09 -0500
>>> Samuel Holland <[email protected]> wrote:
>>>
>>> Hi,
>>>
>>> thanks for all the efforts in getting those SoC peripherals supported!
>>>
>>>> D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, as well as
>>>> one HiFi 4 DSP. The SoC is based on a design that additionally contained
>>>> a pair of Cortex A7's. For that reason, some peripherals are duplicated.
>>>
>>> So because of this, the Allwinner R528 and T113 SoCs would share almost
>>> everything in this file. Would it be useful to already split this DT up?
>>> To have a base .dtsi, basically this file without /cpus and /soc/plic,
>>> then have a RISC-V specific file with just those, including the base?
>>> There is precedence for this across-arch(-directories) sharing with the
>>> Raspberry Pi and Allwinner H3/H5 SoCs.
>>
>> For those playing along at home, one example is the arm64 bananapi m2
>> dts which looks like:
>>> /dts-v1/;
>>> #include "sun50i-h5.dtsi"
>>> #include "sun50i-h5-cpu-opp.dtsi"
>>> #include <arm/sunxi-bananapi-m2-plus-v1.2.dtsi>
>>>
>>> / {
>>> model = "Banana Pi BPI-M2-Plus v1.2 H5";
>>> compatible = "bananapi,bpi-m2-plus-v1.2", "allwinner,sun50i-h5";
>>> };
>>
>> I think this is a pretty good idea, and putting in the modularity up
>> front seems logical to me, so when the arm one does eventually get
>> added it can be done by only touching a single arch.
>
> This is not feasible, due to the different #interrupt-cells. See
> https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/
>
> Even if we share some file across architectures, you still have to update files
> in both places to get the interrupts properties correct.
>
> I get the desire to deduplicate things, but we already deal with updating the
> same/similar nodes across several SoCs, so that is nothing new. I think it would
> be more confusing/complicated to have all of the interrupts properties
> overridden in a separate file.

Yeah, should maybe have circled back after that conversation, would have been
nice but if the DTC can't do it nicely then w/e.

2022-08-21 06:57:33

by Icenowy Zheng

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

在 2022-08-20星期六的 17:29 +0000，[email protected]写道：
> On 20/08/2022 18:24, Samuel Holland wrote:
> > On 8/15/22 12:01 PM, [email protected] wrote:
> > > On 15/08/2022 14:11, Andre Przywara wrote:
> > > > EXTERNAL EMAIL: Do not click links or open attachments unless
> > > > you know the content is safe
> > > >
> > > > On Mon, 15 Aug 2022 00:08:09 -0500
> > > > Samuel Holland <[email protected]> wrote:
> > > >
> > > > Hi,
> > > >
> > > > thanks for all the efforts in getting those SoC peripherals
> > > > supported!
> > > >
> > > > > D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU,
> > > > > as well as
> > > > > one HiFi 4 DSP. The SoC is based on a design that
> > > > > additionally contained
> > > > > a pair of Cortex A7's. For that reason, some peripherals are
> > > > > duplicated.
> > > >
> > > > So because of this, the Allwinner R528 and T113 SoCs would
> > > > share almost
> > > > everything in this file. Would it be useful to already split
> > > > this DT up?
> > > > To have a base .dtsi, basically this file without /cpus and
> > > > /soc/plic,
> > > > then have a RISC-V specific file with just those, including the
> > > > base?
> > > > There is precedence for this across-arch(-directories) sharing
> > > > with the
> > > > Raspberry Pi and Allwinner H3/H5 SoCs.
> > >
> > > For those playing along at home, one example is the arm64
> > > bananapi m2
> > > dts which looks like:
> > > > /dts-v1/;
> > > > #include "sun50i-h5.dtsi"
> > > > #include "sun50i-h5-cpu-opp.dtsi"
> > > > #include <arm/sunxi-bananapi-m2-plus-v1.2.dtsi>
> > > >
> > > > / {
> > > > model = "Banana Pi BPI-M2-Plus v1.2 H5";
> > > > compatible = "bananapi,bpi-m2-plus-v1.2",
> > > > "allwinner,sun50i-h5";
> > > > };
> > >
> > > I think this is a pretty good idea, and putting in the modularity
> > > up
> > > front seems logical to me, so when the arm one does eventually
> > > get
> > > added it can be done by only touching a single arch.
> >
> > This is not feasible, due to the different #interrupt-cells. See
> > https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/
> >
> > Even if we share some file across architectures, you still have to
> > update files
> > in both places to get the interrupts properties correct.
> >
> > I get the desire to deduplicate things, but we already deal with
> > updating the
> > same/similar nodes across several SoCs, so that is nothing new. I
> > think it would
> > be more confusing/complicated to have all of the interrupts
> > properties
> > overridden in a separate file.
>
> Yeah, should maybe have circled back after that conversation, would
> have been
> nice but if the DTC can't do it nicely then w/e.

Well, maybe we can overuse the facility of C preprocessor?

e.g.

```
// For ARM
#define SOC_PERIPHERAL_IRQ(n) GIC_SPI n
// For RISC-V
#define SOC_PERIPHERAL_IRQ(n) n
```

2022-08-21 07:55:51

by Icenowy Zheng

[permalink] [raw]

Subject: Re: [PATCH 07/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree

在 2022-08-19星期五的 22:10 +0000，[email protected]写道：
> Hey Samuel,
>
> Finally got around to giving this a go with the fix for loading
> modules which is mostly what was blocking me before..
>
> On 15/08/2022 06:08, Samuel Holland wrote:
> > "D1 Nezha" is Allwinner's first-party development board for the D1
> > SoC.
> > It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard
> > audio,

BTW I assume 512MB version is never publicly available, it's only some
early samples that have the circuit of one of the DDR chips broken.

>
> I am really not keen on the way you have things, with the memory
> nodes removed from the device tree. I know your preferred flow
> for booting these things might be to pass the dtb up from U-Boot,
> but I think the devicetree in the kernel should be usable in a
> standalone manner, even if that is the barest-minimum memory
> config.

W/o interception of BL, I think there're more complex situations of the
memory, e.g. some part of the memory is reserved.

>
> I did figure out all of my issues getting booted, thanks partly
> to Heiko. The U-Boot dtb being misaligned was part of it as was
> my initramfs with some stale sunxi modules in it causing RCU
> stalls.. so sorry for the noise on that front (and thanks again
> to Heiko!).
>
> Modulo the memory node, since I had to hack that in to get things
> working & I do not want to have to keep doing:
> Tested-by: Conor Dooley <[email protected]>
>
> Thanks & apologies again for the modules-related issues - it was
> hard to debug that one since module loading was broken on RISC-V
> at the time.
> Conor.
>
> > HDMI, gigabit Ethernet, WiFi and Bluetooth, USB 2.0 host and OTG
> > ports,
> > plus low-speed I/O from the SoC and a GPIO expander chip.
> >
> > Most other D1 boards copied the Nezha's power tree, with the 1.8V
> > rail
> > powered by the SoCs internal LDOA, analog domains powered by ALDO,
> > and
> > the rest of the board powered by always-on fixed regulators. Some
> > (but
> > not all) boards also copied the PWM CPU regulator. To avoid
> > duplication,
> > factor out the out the regulator references that are common across
> > all
> > known boards.
> >
> > Signed-off-by: Samuel Holland <[email protected]>
> > ---
> >
> > arch/riscv/boot/dts/allwinner/Makefile        |   1 +
> > .../sun20i-d1-common-regulators.dtsi          | 51 ++++++
> > .../boot/dts/allwinner/sun20i-d1-nezha.dts    | 171
> > ++++++++++++++++++
> > 3 files changed, 223 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-common-
> > regulators.dtsi
> > create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-
> > nezha.dts
> >
> > diff --git a/arch/riscv/boot/dts/allwinner/Makefile
> > b/arch/riscv/boot/dts/allwinner/Makefile
> > index f66554cd5c45..b0a15e8c8d82 100644
> > --- a/arch/riscv/boot/dts/allwinner/Makefile
> > +++ b/arch/riscv/boot/dts/allwinner/Makefile
> > @@ -1 +1,2 @@
> > # SPDX-License-Identifier: GPL-2.0
> > +dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb
> > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-common-
> > regulators.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-
> > regulators.dtsi
> > new file mode 100644
> > index 000000000000..143a3e710c3c
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-
> > regulators.dtsi
> > @@ -0,0 +1,51 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > +// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
> > +
> > +/ {
> > +       reg_vcc: vcc {
> > +               compatible = "regulator-fixed";
> > +               regulator-name = "vcc";
> > +               regulator-min-microvolt = <5000000>;
> > +               regulator-max-microvolt = <5000000>;
> > +       };
> > +
> > +       reg_vcc_3v3: vcc-3v3 {
> > +               compatible = "regulator-fixed";
> > +               regulator-name = "vcc-3v3";
> > +               regulator-min-microvolt = <3300000>;
> > +               regulator-max-microvolt = <3300000>;
> > +               vin-supply = <&reg_vcc>;
> > +       };
> > +};
> > +
> > +&lradc {
> > +       vref-supply = <&reg_aldo>;
> > +};
> > +
> > +&pio {
> > +       vcc-pb-supply = <&reg_vcc_3v3>;
> > +       vcc-pc-supply = <&reg_vcc_3v3>;
> > +       vcc-pd-supply = <&reg_vcc_3v3>;
> > +       vcc-pe-supply = <&reg_vcc_3v3>;
> > +       vcc-pf-supply = <&reg_vcc_3v3>;
> > +       vcc-pg-supply = <&reg_vcc_3v3>;
> > +};
> > +
> > +&reg_aldo {
> > +       regulator-min-microvolt = <1800000>;
> > +       regulator-max-microvolt = <1800000>;
> > +       vdd33-supply = <&reg_vcc_3v3>;
> > +};
> > +
> > +&reg_hpldo {
> > +       regulator-min-microvolt = <1800000>;
> > +       regulator-max-microvolt = <1800000>;
> > +       hpldoin-supply = <&reg_vcc_3v3>;
> > +};
> > +
> > +&reg_ldoa {
> > +       regulator-always-on;
> > +       regulator-min-microvolt = <1800000>;
> > +       regulator-max-microvolt = <1800000>;
> > +       ldo-in-supply = <&reg_vcc_3v3>;
> > +};
> > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
> > b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
> > new file mode 100644
> > index 000000000000..df865ee15fcf
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
> > @@ -0,0 +1,171 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > +// Copyright (C) 2021-2022 Samuel Holland <[email protected]>
> > +
> > +/dts-v1/;
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/input/input.h>
> > +
> > +#include "sun20i-d1.dtsi"
> > +#include "sun20i-d1-common-regulators.dtsi"
> > +
> > +/ {
> > +       model = "Allwinner D1 Nezha";
> > +       compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1";
> > +
> > +       aliases {
> > +               ethernet0 = &emac;
> > +               ethernet1 = &xr829;
> > +               mmc0 = &mmc0;
> > +               serial0 = &uart0;
> > +       };
> > +
> > +       chosen {
> > +               stdout-path = "serial0:115200n8";
> > +       };
> > +
> > +       reg_usbvbus: usbvbus {
> > +               compatible = "regulator-fixed";
> > +               regulator-name = "usbvbus";
> > +               regulator-min-microvolt = <5000000>;
> > +               regulator-max-microvolt = <5000000>;
> > +               gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
> > +               enable-active-high;
> > +               vin-supply = <&reg_vcc>;
> > +       };
> > +
> > +       /*
> > +        * This regulator is PWM-controlled, but the PWM controller
> > is not
> > +        * yet supported, so fix the regulator to its default
> > voltage.
> > +        */
> > +       reg_vdd_cpu: vdd-cpu {
> > +               compatible = "regulator-fixed";
> > +               regulator-name = "vdd-cpu";
> > +               regulator-min-microvolt = <1100000>;
> > +               regulator-max-microvolt = <1100000>;
> > +               vin-supply = <&reg_vcc>;
> > +       };
> > +
> > +       wifi_pwrseq: wifi-pwrseq {
> > +               compatible = "mmc-pwrseq-simple";
> > +               reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12
> > */
> > +       };
> > +};
> > +
> > +&cpu0 {
> > +       cpu-supply = <&reg_vdd_cpu>;
> > +};
> > +
> > +&ehci0 {
> > +       status = "okay";
> > +};
> > +
> > +&ehci1 {
> > +       status = "okay";
> > +};
> > +
> > +&emac {
> > +       pinctrl-0 = <&rgmii_pe_pins>;
> > +       pinctrl-names = "default";
> > +       phy-handle = <&ext_rgmii_phy>;
> > +       phy-mode = "rgmii-id";
> > +       phy-supply = <&reg_vcc_3v3>;
> > +       status = "okay";
> > +};
> > +
> > +&i2c2 {
> > +       pinctrl-0 = <&i2c2_pb0_pins>;
> > +       pinctrl-names = "default";
> > +       status = "okay";
> > +
> > +       pcf8574a: gpio@38 {
> > +               compatible = "nxp,pcf8574a";
> > +               reg = <0x38>;
> > +               interrupt-parent = <&pio>;
> > +               interrupts = <1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */
> > +               interrupt-controller;
> > +               gpio-controller;
> > +               #gpio-cells = <2>;
> > +               #interrupt-cells = <2>;
> > +       };
> > +};
> > +
> > +&lradc {
> > +       status = "okay";
> > +
> > +       button-160 {
> > +               label = "OK";
> > +               linux,code = <KEY_OK>;
> > +               channel = <0>;
> > +               voltage = <160000>;
> > +       };
> > +};
> > +
> > +&mdio {
> > +       ext_rgmii_phy: ethernet-phy@1 {
> > +               compatible = "ethernet-phy-ieee802.3-c22";
> > +               reg = <1>;
> > +       };
> > +};
> > +
> > +&mmc0 {
> > +       bus-width = <4>;
> > +       cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
> > +       disable-wp;
> > +       vmmc-supply = <&reg_vcc_3v3>;
> > +       vqmmc-supply = <&reg_vcc_3v3>;
> > +       pinctrl-0 = <&mmc0_pins>;
> > +       pinctrl-names = "default";
> > +       status = "okay";
> > +};
> > +
> > +&mmc1 {
> > +       bus-width = <4>;
> > +       mmc-pwrseq = <&wifi_pwrseq>;
> > +       non-removable;
> > +       vmmc-supply = <&reg_vcc_3v3>;
> > +       vqmmc-supply = <&reg_vcc_3v3>;
> > +       pinctrl-0 = <&mmc1_pins>;
> > +       pinctrl-names = "default";
> > +       status = "okay";
> > +
> > +       xr829: wifi@1 {
> > +               reg = <1>;
> > +       };
> > +};
> > +
> > +&ohci0 {
> > +       status = "okay";
> > +};
> > +
> > +&ohci1 {
> > +       status = "okay";
> > +};
> > +
> > +&uart0 {
> > +       pinctrl-0 = <&uart0_pb8_pins>;
> > +       pinctrl-names = "default";
> > +       status = "okay";
> > +};
> > +
> > +&uart1 {
> > +       uart-has-rtscts;
> > +       pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
> > +       pinctrl-names = "default";
> > +       status = "okay";
> > +
> > +       /* XR829 bluetooth is connected here */
> > +};
> > +
> > +&usb_otg {
> > +       dr_mode = "otg";
> > +       status = "okay";
> > +};
> > +
> > +&usbphy {
> > +       usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21
> > */
> > +       usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20
> > */
> > +       usb0_vbus-supply = <&reg_usbvbus>;
> > +       usb1_vbus-supply = <&reg_vcc>;
> > +       status = "okay";
> > +};

2022-08-21 10:47:51

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

On 21/08/2022 07:45, Icenowy Zheng wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> 在 2022-08-20星期六的 17:29 +0000，[email protected]写道：
>> On 20/08/2022 18:24, Samuel Holland wrote:
>>> On 8/15/22 12:01 PM, [email protected] wrote:
>>>> On 15/08/2022 14:11, Andre Przywara wrote:
>>>>> EXTERNAL EMAIL: Do not click links or open attachments unless
>>>>> you know the content is safe
>>>>>
>>>>> On Mon, 15 Aug 2022 00:08:09 -0500
>>>>> Samuel Holland <[email protected]> wrote:
>>>>>
>>>>> Hi,
>>>>>
>>>>> thanks for all the efforts in getting those SoC peripherals
>>>>> supported!
>>>>>
>>>>>> D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU,
>>>>>> as well as
>>>>>> one HiFi 4 DSP. The SoC is based on a design that
>>>>>> additionally contained
>>>>>> a pair of Cortex A7's. For that reason, some peripherals are
>>>>>> duplicated.
>>>>>
>>>>> So because of this, the Allwinner R528 and T113 SoCs would
>>>>> share almost
>>>>> everything in this file. Would it be useful to already split
>>>>> this DT up?
>>>>> To have a base .dtsi, basically this file without /cpus and
>>>>> /soc/plic,
>>>>> then have a RISC-V specific file with just those, including the
>>>>> base?
>>>>> There is precedence for this across-arch(-directories) sharing
>>>>> with the
>>>>> Raspberry Pi and Allwinner H3/H5 SoCs.
>>>>
>>>> For those playing along at home, one example is the arm64
>>>> bananapi m2
>>>> dts which looks like:
>>>>> /dts-v1/;
>>>>> #include "sun50i-h5.dtsi"
>>>>> #include "sun50i-h5-cpu-opp.dtsi"
>>>>> #include <arm/sunxi-bananapi-m2-plus-v1.2.dtsi>
>>>>>
>>>>> / {
>>>>> model = "Banana Pi BPI-M2-Plus v1.2 H5";
>>>>> compatible = "bananapi,bpi-m2-plus-v1.2",
>>>>> "allwinner,sun50i-h5";
>>>>> };
>>>>
>>>> I think this is a pretty good idea, and putting in the modularity
>>>> up
>>>> front seems logical to me, so when the arm one does eventually
>>>> get
>>>> added it can be done by only touching a single arch.
>>>
>>> This is not feasible, due to the different #interrupt-cells. See
>>> https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/
>>>
>>> Even if we share some file across architectures, you still have to
>>> update files
>>> in both places to get the interrupts properties correct.
>>>
>>> I get the desire to deduplicate things, but we already deal with
>>> updating the
>>> same/similar nodes across several SoCs, so that is nothing new. I
>>> think it would
>>> be more confusing/complicated to have all of the interrupts
>>> properties
>>> overridden in a separate file.
>>
>> Yeah, should maybe have circled back after that conversation, would
>> have been
>> nice but if the DTC can't do it nicely then w/e.
>
> Well, maybe we can overuse the facility of C preprocessor?
>
> e.g.
>
> ```
> // For ARM
> #define SOC_PERIPHERAL_IRQ(n) GIC_SPI n
> // For RISC-V
> #define SOC_PERIPHERAL_IRQ(n) n
> ```
>

Geert pointed out that this is not possible (at least on the Renesas
stuff) because the GIC interrupt numbers are not the same as the
PLIC's & the DTC is not able to handle the addition:
https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/

Thanks,
Conor.

2022-08-22 11:21:19

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

On Sat, 20 Aug 2022 12:24:55 -0500
Samuel Holland <[email protected]> wrote:

Hi,

> On 8/15/22 12:01 PM, [email protected] wrote:
> > On 15/08/2022 14:11, Andre Przywara wrote:
> >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>
> >> On Mon, 15 Aug 2022 00:08:09 -0500
> >> Samuel Holland <[email protected]> wrote:
> >>
> >> Hi,
> >>
> >> thanks for all the efforts in getting those SoC peripherals supported!
> >>
> >>> D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, as well as
> >>> one HiFi 4 DSP. The SoC is based on a design that additionally contained
> >>> a pair of Cortex A7's. For that reason, some peripherals are duplicated.
> >>
> >> So because of this, the Allwinner R528 and T113 SoCs would share almost
> >> everything in this file. Would it be useful to already split this DT up?
> >> To have a base .dtsi, basically this file without /cpus and /soc/plic,
> >> then have a RISC-V specific file with just those, including the base?
> >> There is precedence for this across-arch(-directories) sharing with the
> >> Raspberry Pi and Allwinner H3/H5 SoCs.
> >
> > For those playing along at home, one example is the arm64 bananapi m2
> > dts which looks like:
> >> /dts-v1/;
> >> #include "sun50i-h5.dtsi"
> >> #include "sun50i-h5-cpu-opp.dtsi"
> >> #include <arm/sunxi-bananapi-m2-plus-v1.2.dtsi>
> >>
> >> / {
> >> model = "Banana Pi BPI-M2-Plus v1.2 H5";
> >> compatible = "bananapi,bpi-m2-plus-v1.2", "allwinner,sun50i-h5";
> >> };
> >
> > I think this is a pretty good idea, and putting in the modularity up
> > front seems logical to me, so when the arm one does eventually get
> > added it can be done by only touching a single arch.
>
> This is not feasible, due to the different #interrupt-cells. See
> https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/
>
> Even if we share some file across architectures, you still have to update files
> in both places to get the interrupts properties correct.

There are interrupt-maps for that:
sun8i-r528.dtsi:
soc {
#interrupt-cells = <1>;
interrupt-map = <0 18 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<0 19 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
....

sun20i-d1.dtsi:
soc {
#interrupt-cells = <1>;
interrupt-map = <0 18 &plic 18 IRQ_TYPE_LEVEL_HIGH>,
<0 19 &plic 19 IRQ_TYPE_LEVEL_HIGH>,

then, in the shared .dtsi:
uart0: serial@2500000 {
compatible = "snps,dw-apb-uart";
...
interrupts = <18>;

This is completely untested, but I have all the files spelt out there, and
dtc seems happy for both architectures (outside of the kernel tree for now).

> I get the desire to deduplicate things, but we already deal with updating the
> same/similar nodes across several SoCs, so that is nothing new. I think it would
> be more confusing/complicated to have all of the interrupts properties
> overridden in a separate file.

So is this the only thing that prevents sharing? The above paragraph
sounds a bit you are not very fond of the idea to begin with?

Cheers,
Andre

2022-08-22 11:52:43

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

Hi Jernej,

On Tue, Aug 16, 2022 at 11:28 AM Jernej Škrabec
<[email protected]> wrote:
> Dne torek, 16. avgust 2022 ob 11:12:05 CEST je Heiko Stübner napisal(a):
> > Am Dienstag, 16. August 2022, 09:49:58 CEST schrieb Jernej Škrabec:
> > > Dne torek, 16. avgust 2022 ob 09:41:45 CEST je Krzysztof Kozlowski
> napisal(a):
> > > > On 15/08/2022 08:08, Samuel Holland wrote:
> > > > > +
> > > > > + de: display-engine {
> > > > > + compatible = "allwinner,sun20i-d1-display-engine";
> > > > > + allwinner,pipelines = <&mixer0>, <&mixer1>;
> > > > > + status = "disabled";
> > > > > + };
> > > > > +
> > > > > + osc24M: osc24M-clk {
> > > >
> > > > lowercase
> > > >
> > > > > + compatible = "fixed-clock";
> > > > > + clock-frequency = <24000000>;
> > > >
> > > > This is a property of the board, not SoC.
> > >
> > > SoC needs 24 MHz oscillator for correct operation, so each and every board
> > > has it. Having it here simplifies board DT files.
> >
> > I guess the oscillator is a separate component on each board, right?
>
> Correct.
>
> > And DT obvious is meant to describe the hardware - independently from
> > implementation-specific choices.
>
> There is no choice in this case. 24 MHz crystal has to be present.
>
> FWIW, including crystal node in SoC specific DTSI is already common pattern in
> Allwinner ARM SoC DTSI files.

I could also be a programmable clock generator on the board, programmed
to generate a 24 MHz clock on one of its outputs? Again, on the board.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

2022-08-22 12:40:51

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

Hi Conor, Andre,

On Sun, Aug 21, 2022 at 12:07 PM <[email protected]> wrote:
> On 21/08/2022 07:45, Icenowy Zheng wrote:
> > 在 2022-08-20星期六的 17:29 +0000，[email protected]写道：
> >> On 20/08/2022 18:24, Samuel Holland wrote:
> >>> On 8/15/22 12:01 PM, [email protected] wrote:
> >>>> On 15/08/2022 14:11, Andre Przywara wrote:
> >>>>> EXTERNAL EMAIL: Do not click links or open attachments unless
> >>>>> you know the content is safe
> >>>>>
> >>>>> On Mon, 15 Aug 2022 00:08:09 -0500
> >>>>> Samuel Holland <[email protected]> wrote:
> >>>>>
> >>>>> Hi,
> >>>>>
> >>>>> thanks for all the efforts in getting those SoC peripherals
> >>>>> supported!
> >>>>>
> >>>>>> D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU,
> >>>>>> as well as
> >>>>>> one HiFi 4 DSP. The SoC is based on a design that
> >>>>>> additionally contained
> >>>>>> a pair of Cortex A7's. For that reason, some peripherals are
> >>>>>> duplicated.
> >>>>>
> >>>>> So because of this, the Allwinner R528 and T113 SoCs would
> >>>>> share almost
> >>>>> everything in this file. Would it be useful to already split
> >>>>> this DT up?
> >>>>> To have a base .dtsi, basically this file without /cpus and
> >>>>> /soc/plic,
> >>>>> then have a RISC-V specific file with just those, including the
> >>>>> base?
> >>>>> There is precedence for this across-arch(-directories) sharing
> >>>>> with the
> >>>>> Raspberry Pi and Allwinner H3/H5 SoCs.
> >>>>
> >>>> For those playing along at home, one example is the arm64
> >>>> bananapi m2
> >>>> dts which looks like:
> >>>>> /dts-v1/;
> >>>>> #include "sun50i-h5.dtsi"
> >>>>> #include "sun50i-h5-cpu-opp.dtsi"
> >>>>> #include <arm/sunxi-bananapi-m2-plus-v1.2.dtsi>
> >>>>>
> >>>>> / {
> >>>>> model = "Banana Pi BPI-M2-Plus v1.2 H5";
> >>>>> compatible = "bananapi,bpi-m2-plus-v1.2",
> >>>>> "allwinner,sun50i-h5";
> >>>>> };
> >>>>
> >>>> I think this is a pretty good idea, and putting in the modularity
> >>>> up
> >>>> front seems logical to me, so when the arm one does eventually
> >>>> get
> >>>> added it can be done by only touching a single arch.
> >>>
> >>> This is not feasible, due to the different #interrupt-cells. See
> >>> https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/
> >>>
> >>> Even if we share some file across architectures, you still have to
> >>> update files
> >>> in both places to get the interrupts properties correct.
> >>>
> >>> I get the desire to deduplicate things, but we already deal with
> >>> updating the
> >>> same/similar nodes across several SoCs, so that is nothing new. I
> >>> think it would
> >>> be more confusing/complicated to have all of the interrupts
> >>> properties
> >>> overridden in a separate file.
> >>
> >> Yeah, should maybe have circled back after that conversation, would
> >> have been
> >> nice but if the DTC can't do it nicely then w/e.
> >
> > Well, maybe we can overuse the facility of C preprocessor?
> >
> > e.g.
> >
> > ```
> > // For ARM
> > #define SOC_PERIPHERAL_IRQ(n) GIC_SPI n
> > // For RISC-V
> > #define SOC_PERIPHERAL_IRQ(n) n
> > ```
> >
>
> Geert pointed out that this is not possible (at least on the Renesas
> stuff) because the GIC interrupt numbers are not the same as the
> PLIC's & the DTC is not able to handle the addition:
> https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/

Without the ability to do additions in DTC, we could e.g. list both
interrupts in the macro, like:

// For ARM
#define SOC_PERIPHERAL_IRQ(na, nr) GIC_SPI na
// For RISC-V
#define SOC_PERIPHERAL_IRQ(na, nr) nr

On Mon, Aug 22, 2022 at 12:52 PM Andre Przywara <[email protected]> wrote:
> There are interrupt-maps for that:
> sun8i-r528.dtsi:
> soc {
> #interrupt-cells = <1>;
> interrupt-map = <0 18 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> <0 19 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> ....
>
> sun20i-d1.dtsi:
> soc {
> #interrupt-cells = <1>;
> interrupt-map = <0 18 &plic 18 IRQ_TYPE_LEVEL_HIGH>,
> <0 19 &plic 19 IRQ_TYPE_LEVEL_HIGH>,
>
> then, in the shared .dtsi:
> uart0: serial@2500000 {
> compatible = "snps,dw-apb-uart";
> ...
> interrupts = <18>;

Nice! But it's gonna be a very large interrupt-map.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

2022-08-22 12:41:55

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

Hey Geert,

On 22/08/2022 12:46, Geert Uytterhoeven wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hi Conor, Andre,
>
> On Sun, Aug 21, 2022 at 12:07 PM <[email protected]> wrote:
>> On 21/08/2022 07:45, Icenowy Zheng wrote:
>>> 在 2022-08-20星期六的 17:29 +0000，[email protected]写道：
>>>> On 20/08/2022 18:24, Samuel Holland wrote:

>>>>> This is not feasible, due to the different #interrupt-cells. See
>>>>> https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/
>>>>>
>>>>> Even if we share some file across architectures, you still have to
>>>>> update files
>>>>> in both places to get the interrupts properties correct.
>>>>>
>>>>> I get the desire to deduplicate things, but we already deal with
>>>>> updating the
>>>>> same/similar nodes across several SoCs, so that is nothing new. I
>>>>> think it would
>>>>> be more confusing/complicated to have all of the interrupts
>>>>> properties
>>>>> overridden in a separate file.
>>>>
>>>> Yeah, should maybe have circled back after that conversation, would
>>>> have been
>>>> nice but if the DTC can't do it nicely then w/e.
>>>
>>> Well, maybe we can overuse the facility of C preprocessor?
>>>
>>> e.g.
>>>
>>> ```
>>> // For ARM
>>> #define SOC_PERIPHERAL_IRQ(n) GIC_SPI n
>>> // For RISC-V
>>> #define SOC_PERIPHERAL_IRQ(n) n
>>> ```
>>>
>>
>> Geert pointed out that this is not possible (at least on the Renesas
>> stuff) because the GIC interrupt numbers are not the same as the
>> PLIC's & the DTC is not able to handle the addition:
>> https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/
>
> Without the ability to do additions in DTC, we could e.g. list both
> interrupts in the macro, like:
>
> // For ARM
> #define SOC_PERIPHERAL_IRQ(na, nr) GIC_SPI na
> // For RISC-V
> #define SOC_PERIPHERAL_IRQ(na, nr) nr

Do you think this is worth doing? Or are you just providing an
example of what could be done?

Where would you envisage putting these macros? I forget the order
of the CPP operations that are done, can they be put in the dts?

>
> On Mon, Aug 22, 2022 at 12:52 PM Andre Przywara <[email protected]> wrote:
>> There are interrupt-maps for that:
>> sun8i-r528.dtsi:
>> soc {
>> #interrupt-cells = <1>;
>> interrupt-map = <0 18 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
>> <0 19 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
>> ....
>>
>> sun20i-d1.dtsi:
>> soc {
>> #interrupt-cells = <1>;
>> interrupt-map = <0 18 &plic 18 IRQ_TYPE_LEVEL_HIGH>,
>> <0 19 &plic 19 IRQ_TYPE_LEVEL_HIGH>,
>>
>> then, in the shared .dtsi:
>> uart0: serial@2500000 {
>> compatible = "snps,dw-apb-uart";
>> ...
>> interrupts = <18>;
>
> Nice! But it's gonna be a very large interrupt-map.

I quite like the idea of not duplicating files across the archs
if it can be helped, but not at the expense of making them hard to
understand & I feel like unfortunately the large interrupt map is
in that territory.

Thanks,
Conor.

2022-08-22 12:57:54

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

On Mon, 22 Aug 2022 12:13:42 +0000
<[email protected]> wrote:

Hi,

> On 22/08/2022 12:46, Geert Uytterhoeven wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Hi Conor, Andre,
> >
> > On Sun, Aug 21, 2022 at 12:07 PM <[email protected]> wrote:
> >> On 21/08/2022 07:45, Icenowy Zheng wrote:
> >>> 在 2022-08-20星期六的 17:29 +0000，[email protected]写道：
> >>>> On 20/08/2022 18:24, Samuel Holland wrote:
>
> >>>>> This is not feasible, due to the different #interrupt-cells. See
> >>>>> https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/
> >>>>>
> >>>>> Even if we share some file across architectures, you still have to
> >>>>> update files
> >>>>> in both places to get the interrupts properties correct.
> >>>>>
> >>>>> I get the desire to deduplicate things, but we already deal with
> >>>>> updating the
> >>>>> same/similar nodes across several SoCs, so that is nothing new. I
> >>>>> think it would
> >>>>> be more confusing/complicated to have all of the interrupts
> >>>>> properties
> >>>>> overridden in a separate file.
> >>>>
> >>>> Yeah, should maybe have circled back after that conversation, would
> >>>> have been
> >>>> nice but if the DTC can't do it nicely then w/e.
> >>>
> >>> Well, maybe we can overuse the facility of C preprocessor?
> >>>
> >>> e.g.
> >>>
> >>> ```
> >>> // For ARM
> >>> #define SOC_PERIPHERAL_IRQ(n) GIC_SPI n
> >>> // For RISC-V
> >>> #define SOC_PERIPHERAL_IRQ(n) n
> >>> ```
> >>>
> >>
> >> Geert pointed out that this is not possible (at least on the Renesas
> >> stuff) because the GIC interrupt numbers are not the same as the
> >> PLIC's & the DTC is not able to handle the addition:
> >> https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/
> >
> > Without the ability to do additions in DTC, we could e.g. list both
> > interrupts in the macro, like:
> >
> > // For ARM
> > #define SOC_PERIPHERAL_IRQ(na, nr) GIC_SPI na
> > // For RISC-V
> > #define SOC_PERIPHERAL_IRQ(na, nr) nr
>
> Do you think this is worth doing? Or are you just providing an
> example of what could be done?
>
> Where would you envisage putting these macros? I forget the order
> of the CPP operations that are done, can they be put in the dts?
>
> >
> > On Mon, Aug 22, 2022 at 12:52 PM Andre Przywara <[email protected]> wrote:
> >> There are interrupt-maps for that:
> >> sun8i-r528.dtsi:
> >> soc {
> >> #interrupt-cells = <1>;
> >> interrupt-map = <0 18 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> >> <0 19 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> >> ....
> >>
> >> sun20i-d1.dtsi:
> >> soc {
> >> #interrupt-cells = <1>;
> >> interrupt-map = <0 18 &plic 18 IRQ_TYPE_LEVEL_HIGH>,
> >> <0 19 &plic 19 IRQ_TYPE_LEVEL_HIGH>,
> >>
> >> then, in the shared .dtsi:
> >> uart0: serial@2500000 {
> >> compatible = "snps,dw-apb-uart";
> >> ...
> >> interrupts = <18>;
> >
> > Nice! But it's gonna be a very large interrupt-map.
>
> I quite like the idea of not duplicating files across the archs
> if it can be helped, but not at the expense of making them hard to
> understand & I feel like unfortunately the large interrupt map is
> in that territory.

Well, I don't know about the Renesas case, but as far as we know the
Allwinner D1 and R528 are using the exact same die, just fused differently.
So expressing this in a common .dtsi sounds very desirable, especially
since a devicetree is an architecture agnostic data structure.

And while it's true that a DT interrupt-map is not for the faint of heart,
I think even the casual reader gets the idea quickly by looking at
it, possibly guided by a comment.
And it doesn't need to be very large. grep counted 32 genuine interrupts
in the current .dtsi file, so I just put those ones needed in. If we need
more IRQs later (quite likely), they are easily added, using copy&paste.

Cheers,
Andre

2022-08-22 13:05:57

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

Hi Conor,

On Mon, Aug 22, 2022 at 2:13 PM <[email protected]> wrote:
> On 22/08/2022 12:46, Geert Uytterhoeven wrote:
> > On Sun, Aug 21, 2022 at 12:07 PM <[email protected]> wrote:
> >> On 21/08/2022 07:45, Icenowy Zheng wrote:
> >>> 在 2022-08-20星期六的 17:29 +0000，[email protected]写道：
> >>>> On 20/08/2022 18:24, Samuel Holland wrote:
>
> >>>>> This is not feasible, due to the different #interrupt-cells. See
> >>>>> https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/
> >>>>>
> >>>>> Even if we share some file across architectures, you still have to
> >>>>> update files
> >>>>> in both places to get the interrupts properties correct.
> >>>>>
> >>>>> I get the desire to deduplicate things, but we already deal with
> >>>>> updating the
> >>>>> same/similar nodes across several SoCs, so that is nothing new. I
> >>>>> think it would
> >>>>> be more confusing/complicated to have all of the interrupts
> >>>>> properties
> >>>>> overridden in a separate file.
> >>>>
> >>>> Yeah, should maybe have circled back after that conversation, would
> >>>> have been
> >>>> nice but if the DTC can't do it nicely then w/e.
> >>>
> >>> Well, maybe we can overuse the facility of C preprocessor?
> >>>
> >>> e.g.
> >>>
> >>> ```
> >>> // For ARM
> >>> #define SOC_PERIPHERAL_IRQ(n) GIC_SPI n
> >>> // For RISC-V
> >>> #define SOC_PERIPHERAL_IRQ(n) n
> >>> ```
> >>>
> >>
> >> Geert pointed out that this is not possible (at least on the Renesas
> >> stuff) because the GIC interrupt numbers are not the same as the
> >> PLIC's & the DTC is not able to handle the addition:
> >> https://lore.kernel.org/linux-riscv/CAMuHMdXHSMcrVOH+vcrdRRF+i2TkMcFisGxHMBPUEa8nTMFpzw@mail.gmail.com/
> >
> > Without the ability to do additions in DTC, we could e.g. list both
> > interrupts in the macro, like:
> >
> > // For ARM
> > #define SOC_PERIPHERAL_IRQ(na, nr) GIC_SPI na
> > // For RISC-V
> > #define SOC_PERIPHERAL_IRQ(na, nr) nr
>
> Do you think this is worth doing? Or are you just providing an
> example of what could be done?

Just some brainstorming...

> Where would you envisage putting these macros? I forget the order
> of the CPP operations that are done, can they be put in the dts?

The SOC_PERIPHERAL_IRQ() macro should be defined in the
ARM-based SoC.dtsi file and the RISC-V-based SoC.dtsi file.

> > On Mon, Aug 22, 2022 at 12:52 PM Andre Przywara <[email protected]> wrote:
> >> There are interrupt-maps for that:
> >> sun8i-r528.dtsi:
> >> soc {
> >> #interrupt-cells = <1>;
> >> interrupt-map = <0 18 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> >> <0 19 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> >> ....
> >>
> >> sun20i-d1.dtsi:
> >> soc {
> >> #interrupt-cells = <1>;
> >> interrupt-map = <0 18 &plic 18 IRQ_TYPE_LEVEL_HIGH>,
> >> <0 19 &plic 19 IRQ_TYPE_LEVEL_HIGH>,
> >>
> >> then, in the shared .dtsi:
> >> uart0: serial@2500000 {
> >> compatible = "snps,dw-apb-uart";
> >> ...
> >> interrupts = <18>;
> >
> > Nice! But it's gonna be a very large interrupt-map.
>
> I quite like the idea of not duplicating files across the archs
> if it can be helped, but not at the expense of making them hard to
> understand & I feel like unfortunately the large interrupt map is
> in that territory.

I feel the same.
Even listing both interrupt numbers in SOC_PERIPHERAL_IRQ(na, nr)
is a risk for making mistakes.

So personally, I'm in favor of teaching dtc arithmetic, so we can
handle the offset in SOC_PERIPHERAL_IRQ().

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

2022-08-22 14:05:11

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

On 22/08/2022 13:31, Geert Uytterhoeven wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>

>> Do you think this is worth doing? Or are you just providing an
>> example of what could be done?
>
> Just some brainstorming...
>
>> Where would you envisage putting these macros? I forget the order
>> of the CPP operations that are done, can they be put in the dts?
>
> The SOC_PERIPHERAL_IRQ() macro should be defined in the
> ARM-based SoC.dtsi file and the RISC-V-based SoC.dtsi file.

Right, one level up but ~the same result.

>>> Nice! But it's gonna be a very large interrupt-map.
>>
>> I quite like the idea of not duplicating files across the archs
>> if it can be helped, but not at the expense of making them hard to
>> understand & I feel like unfortunately the large interrupt map is
>> in that territory.
>
> I feel the same.
> Even listing both interrupt numbers in SOC_PERIPHERAL_IRQ(na, nr)
> is a risk for making mistakes.
>
> So personally, I'm in favor of teaching dtc arithmetic, so we can
> handle the offset in SOC_PERIPHERAL_IRQ().

Yup, in the same boat here. mayb I'll get bored enough to bite..

2022-08-22 16:04:52

by Jessica Clarke

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

On 22 Aug 2022, at 14:56, [email protected] wrote:
>
> On 22/08/2022 13:31, Geert Uytterhoeven wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>
>
>>> Do you think this is worth doing? Or are you just providing an
>>> example of what could be done?
>>
>> Just some brainstorming...
>>
>>> Where would you envisage putting these macros? I forget the order
>>> of the CPP operations that are done, can they be put in the dts?
>>
>> The SOC_PERIPHERAL_IRQ() macro should be defined in the
>> ARM-based SoC.dtsi file and the RISC-V-based SoC.dtsi file.
>
> Right, one level up but ~the same result.
>
>
>>>> Nice! But it's gonna be a very large interrupt-map.
>>>
>>> I quite like the idea of not duplicating files across the archs
>>> if it can be helped, but not at the expense of making them hard to
>>> understand & I feel like unfortunately the large interrupt map is
>>> in that territory.
>>
>> I feel the same.
>> Even listing both interrupt numbers in SOC_PERIPHERAL_IRQ(na, nr)
>> is a risk for making mistakes.
>>
>> So personally, I'm in favor of teaching dtc arithmetic, so we can
>> handle the offset in SOC_PERIPHERAL_IRQ().
>
> Yup, in the same boat here. mayb I'll get bored enough to bite..

Note that GPL’ed dtc isn’t the only implementation. FreeBSD uses a
BSD-licensed implementation[1] and so adding new features like this to
GPL dtc that actually get used would require us to reimplement it too.
I don’t know how much effort it would be but please keep this in mind.

Jess

[1] https://github.com/davidchisnall/dtc

2022-09-01 18:47:11

by Palmer Dabbelt

[permalink] [raw]

Subject: Re: [PATCH 00/12] riscv: Allwinner D1 platform support

On Sun, 14 Aug 2022 22:08:03 PDT (-0700), [email protected] wrote:
> This series adds the Kconfig/defconfig plumbing and devicetrees for a
> range of Allwinner D1-based boards. Many features are already enabled,
> including USB, Ethernet, and WiFi.
>
> The SoC devicetree uses bindings from the following series which have
> not yet been merged:
> - SRAM controller:
> https://lore.kernel.org/lkml/[email protected]/
> - NVMEM cell bits property change:
> https://lore.kernel.org/lkml/[email protected]/
> - In-package LDO regulators:
> https://lore.kernel.org/lkml/[email protected]/
>
> All three of these are required to set the correct I/O domain voltages
> in the pin controller, which I would consider important to have in the
> initial version of the devicetree.
>
> The SoC devicetree does contain one small hack to avoid a dependency on
> the audio codec binding, since that is not ready yet: the codec node
> uses a bare "simple-mfd", "syscon" compatible.
>
>
> Samuel Holland (12):
> MAINTAINERS: Match the sun20i family of Allwinner SoCs
> dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles
> dt-bindings: vendor-prefixes: Add Allwinner D1 board vendors
> dt-bindings: riscv: Add Allwinner D1 board compatibles
> riscv: Add the Allwinner SoC family Kconfig option
> riscv: dts: allwinner: Add the D1 SoC base devicetree
> riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree
> riscv: dts: allwinner: Add Sipeed Lichee RV devicetrees
> riscv: dts: allwinner: Add MangoPi MQ Pro devicetree
> riscv: dts: allwinner: Add Dongshan Nezha STU devicetree
> riscv: dts: allwinner: Add ClockworkPi and DevTerm devicetrees
> riscv: defconfig: Enable the Allwinner D1 platform and drivers
>
> .../devicetree/bindings/riscv/cpus.yaml | 2 +
> .../devicetree/bindings/riscv/sunxi.yaml | 64 ++
> .../devicetree/bindings/vendor-prefixes.yaml | 4 +
> MAINTAINERS | 2 +-
> arch/riscv/Kconfig.socs | 9 +
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/allwinner/Makefile | 10 +
> .../allwinner/sun20i-d1-clockworkpi-v3.14.dts | 242 +++++
> .../sun20i-d1-common-regulators.dtsi | 51 +
> .../dts/allwinner/sun20i-d1-devterm-v3.14.dts | 37 +
> .../sun20i-d1-dongshan-nezha-stu.dts | 114 +++
> .../sun20i-d1-lichee-rv-86-panel-480p.dts | 29 +
> .../sun20i-d1-lichee-rv-86-panel-720p.dts | 10 +
> .../sun20i-d1-lichee-rv-86-panel.dtsi | 92 ++
> .../allwinner/sun20i-d1-lichee-rv-dock.dts | 74 ++
> .../dts/allwinner/sun20i-d1-lichee-rv.dts | 84 ++
> .../allwinner/sun20i-d1-mangopi-mq-pro.dts | 128 +++
> .../boot/dts/allwinner/sun20i-d1-nezha.dts | 171 ++++
> arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 900 ++++++++++++++++++
> arch/riscv/configs/defconfig | 23 +-
> 20 files changed, 2045 insertions(+), 2 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/riscv/sunxi.yaml
> create mode 100644 arch/riscv/boot/dts/allwinner/Makefile
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi

I'm assuming these are aimed at the RISC-V tree? I'm generally OK with
that, though the DT folks have pointed out a handful of issues that look
pretty reasonable to me.

I can't find a v2, not sure if I missed it. No rush on my end, just
want to make sure I'm not dropping the ball on anything.

Thanks!

2022-09-02 05:58:34

[permalink] [raw]

Subject: Re: [PATCH 00/12] riscv: Allwinner D1 platform support

On 01/09/2022 19:10, Palmer Dabbelt wrote:
> On Sun, 14 Aug 2022 22:08:03 PDT (-0700), [email protected] wrote:
>> This series adds the Kconfig/defconfig plumbing and devicetrees for a
>> range of Allwinner D1-based boards. Many features are already enabled,
>> including USB, Ethernet, and WiFi.
>>

> I can't find a v2, not sure if I missed it. No rush on my end, just
> want to make sure I'm not dropping the ball on anything.

There's been no v2 yet.

Thanks,
Conor.

2022-09-03 15:51:29

by Peter Korsgaard

[permalink] [raw]

Subject: Re: [PATCH 07/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree

>>>>> "Samuel" == Samuel Holland <[email protected]> writes:

> "D1 Nezha" is Allwinner's first-party development board for the D1 SoC.
> It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard audio,
> HDMI, gigabit Ethernet, WiFi and Bluetooth, USB 2.0 host and OTG ports,
> plus low-speed I/O from the SoC and a GPIO expander chip.

> Most other D1 boards copied the Nezha's power tree, with the 1.8V rail
> powered by the SoCs internal LDOA, analog domains powered by ALDO, and
> the rest of the board powered by always-on fixed regulators. Some (but
> not all) boards also copied the PWM CPU regulator. To avoid duplication,
> factor out the out the regulator references that are common across all

NIT: s/out the out the/out the/

--
Bye, Peter Korsgaard

2022-09-04 20:26:52

by Peter Korsgaard

[permalink] [raw]

Subject: Re: [PATCH 07/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree

>>>>> <[email protected]> writes:

> Hey Samuel,
> Finally got around to giving this a go with the fix for loading
> modules which is mostly what was blocking me before..

> On 15/08/2022 06:08, Samuel Holland wrote:
>> "D1 Nezha" is Allwinner's first-party development board for the D1 SoC.
>> It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard audio,

> I am really not keen on the way you have things, with the memory
> nodes removed from the device tree. I know your preferred flow
> for booting these things might be to pass the dtb up from U-Boot,
> but I think the devicetree in the kernel should be usable in a
> standalone manner, even if that is the barest-minimum memory
> config.

Yes, this also confused me. Part of the reason seems to be that u-boot
on RISC-V doesn't fixup the memory node of a provided device tree like
it is done on E.G. ARM for some reason.

--
Bye, Peter Korsgaard

2022-09-06 20:41:45

by Jernej Škrabec

[permalink] [raw]

Subject: Re: Re: [PATCH 00/12] riscv: Allwinner D1 platform support

Dne četrtek, 01. september 2022 ob 20:10:13 CEST je Palmer Dabbelt napisal(a):
> On Sun, 14 Aug 2022 22:08:03 PDT (-0700), [email protected] wrote:
> > This series adds the Kconfig/defconfig plumbing and devicetrees for a
> > range of Allwinner D1-based boards. Many features are already enabled,
> > including USB, Ethernet, and WiFi.
> >
> > The SoC devicetree uses bindings from the following series which have
> > not yet been merged:
> >
> > - SRAM controller:
> > https://lore.kernel.org/lkml/[email protected]/
> >
> > - NVMEM cell bits property change:
> > https://lore.kernel.org/lkml/[email protected]/
> >
> > - In-package LDO regulators:
> > https://lore.kernel.org/lkml/[email protected]/
> >
> > All three of these are required to set the correct I/O domain voltages
> > in the pin controller, which I would consider important to have in the
> > initial version of the devicetree.
> >
> > The SoC devicetree does contain one small hack to avoid a dependency on
> > the audio codec binding, since that is not ready yet: the codec node
> > uses a bare "simple-mfd", "syscon" compatible.
> >
> > Samuel Holland (12):
> > MAINTAINERS: Match the sun20i family of Allwinner SoCs
> > dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles
> > dt-bindings: vendor-prefixes: Add Allwinner D1 board vendors
> > dt-bindings: riscv: Add Allwinner D1 board compatibles
> > riscv: Add the Allwinner SoC family Kconfig option
> > riscv: dts: allwinner: Add the D1 SoC base devicetree
> > riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree
> > riscv: dts: allwinner: Add Sipeed Lichee RV devicetrees
> > riscv: dts: allwinner: Add MangoPi MQ Pro devicetree
> > riscv: dts: allwinner: Add Dongshan Nezha STU devicetree
> > riscv: dts: allwinner: Add ClockworkPi and DevTerm devicetrees
> > riscv: defconfig: Enable the Allwinner D1 platform and drivers
> >
> > .../devicetree/bindings/riscv/cpus.yaml | 2 +
> > .../devicetree/bindings/riscv/sunxi.yaml | 64 ++
> > .../devicetree/bindings/vendor-prefixes.yaml | 4 +
> > MAINTAINERS | 2 +-
> > arch/riscv/Kconfig.socs | 9 +
> > arch/riscv/boot/dts/Makefile | 1 +
> > arch/riscv/boot/dts/allwinner/Makefile | 10 +
> > .../allwinner/sun20i-d1-clockworkpi-v3.14.dts | 242 +++++
> > .../sun20i-d1-common-regulators.dtsi | 51 +
> > .../dts/allwinner/sun20i-d1-devterm-v3.14.dts | 37 +
> > .../sun20i-d1-dongshan-nezha-stu.dts | 114 +++
> > .../sun20i-d1-lichee-rv-86-panel-480p.dts | 29 +
> > .../sun20i-d1-lichee-rv-86-panel-720p.dts | 10 +
> > .../sun20i-d1-lichee-rv-86-panel.dtsi | 92 ++
> > .../allwinner/sun20i-d1-lichee-rv-dock.dts | 74 ++
> > .../dts/allwinner/sun20i-d1-lichee-rv.dts | 84 ++
> > .../allwinner/sun20i-d1-mangopi-mq-pro.dts | 128 +++
> > .../boot/dts/allwinner/sun20i-d1-nezha.dts | 171 ++++
> > arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 900 ++++++++++++++++++
> > arch/riscv/configs/defconfig | 23 +-
> > 20 files changed, 2045 insertions(+), 2 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/riscv/sunxi.yaml
> > create mode 100644 arch/riscv/boot/dts/allwinner/Makefile
> > create mode 100644
> > arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts create
> > mode 100644
> > arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi create
> > mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts
> > create mode 100644
> > arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts create
> > mode 100644
> > arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
> > create mode 100644
> > arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts
> > create mode 100644
> > arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi create
> > mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
> > create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
> > create mode 100644
> > arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts create mode
> > 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts create mode
> > 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
>
> I'm assuming these are aimed at the RISC-V tree? I'm generally OK with
> that, though the DT folks have pointed out a handful of issues that look
> pretty reasonable to me.

DT changes for Allwinner ARM SoCs go trough sunxi tree. Should this be handled
differently for RISC-V?

Best regards,
Jernej

>
> I can't find a v2, not sure if I missed it. No rush on my end, just
> want to make sure I'm not dropping the ball on anything.
>
> Thanks!

2022-09-07 21:02:53

[permalink] [raw]

Subject: Re: [PATCH 00/12] riscv: Allwinner D1 platform support

On 06/09/2022 21:29, Jernej Škrabec wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Dne četrtek, 01. september 2022 ob 20:10:13 CEST je Palmer Dabbelt napisal(a):
>> On Sun, 14 Aug 2022 22:08:03 PDT (-0700), [email protected] wrote:
>>> This series adds the Kconfig/defconfig plumbing and devicetrees for a
>>> range of Allwinner D1-based boards. Many features are already enabled,
>>> including USB, Ethernet, and WiFi.
>>>
>>> The SoC devicetree uses bindings from the following series which have
>>> not yet been merged:
>>>
>>> - SRAM controller:
>>> https://lore.kernel.org/lkml/[email protected]/
>>>
>>> - NVMEM cell bits property change:
>>> https://lore.kernel.org/lkml/[email protected]/
>>>
>>> - In-package LDO regulators:
>>> https://lore.kernel.org/lkml/[email protected]/
>>>
>>> All three of these are required to set the correct I/O domain voltages
>>> in the pin controller, which I would consider important to have in the
>>> initial version of the devicetree.
>>>
>>> The SoC devicetree does contain one small hack to avoid a dependency on
>>> the audio codec binding, since that is not ready yet: the codec node
>>> uses a bare "simple-mfd", "syscon" compatible.
>>>
>>> Samuel Holland (12):
>>> MAINTAINERS: Match the sun20i family of Allwinner SoCs
>>> dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles
>>> dt-bindings: vendor-prefixes: Add Allwinner D1 board vendors
>>> dt-bindings: riscv: Add Allwinner D1 board compatibles
>>> riscv: Add the Allwinner SoC family Kconfig option
>>> riscv: dts: allwinner: Add the D1 SoC base devicetree
>>> riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree
>>> riscv: dts: allwinner: Add Sipeed Lichee RV devicetrees
>>> riscv: dts: allwinner: Add MangoPi MQ Pro devicetree
>>> riscv: dts: allwinner: Add Dongshan Nezha STU devicetree
>>> riscv: dts: allwinner: Add ClockworkPi and DevTerm devicetrees
>>> riscv: defconfig: Enable the Allwinner D1 platform and drivers
>>>
>>> .../devicetree/bindings/riscv/cpus.yaml | 2 +
>>> .../devicetree/bindings/riscv/sunxi.yaml | 64 ++
>>> .../devicetree/bindings/vendor-prefixes.yaml | 4 +
>>> MAINTAINERS | 2 +-
>>> arch/riscv/Kconfig.socs | 9 +
>>> arch/riscv/boot/dts/Makefile | 1 +
>>> arch/riscv/boot/dts/allwinner/Makefile | 10 +
>>> .../allwinner/sun20i-d1-clockworkpi-v3.14.dts | 242 +++++
>>> .../sun20i-d1-common-regulators.dtsi | 51 +
>>> .../dts/allwinner/sun20i-d1-devterm-v3.14.dts | 37 +
>>> .../sun20i-d1-dongshan-nezha-stu.dts | 114 +++
>>> .../sun20i-d1-lichee-rv-86-panel-480p.dts | 29 +
>>> .../sun20i-d1-lichee-rv-86-panel-720p.dts | 10 +
>>> .../sun20i-d1-lichee-rv-86-panel.dtsi | 92 ++
>>> .../allwinner/sun20i-d1-lichee-rv-dock.dts | 74 ++
>>> .../dts/allwinner/sun20i-d1-lichee-rv.dts | 84 ++
>>> .../allwinner/sun20i-d1-mangopi-mq-pro.dts | 128 +++
>>> .../boot/dts/allwinner/sun20i-d1-nezha.dts | 171 ++++
>>> arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 900 ++++++++++++++++++
>>> arch/riscv/configs/defconfig | 23 +-
>>> 20 files changed, 2045 insertions(+), 2 deletions(-)
>>> create mode 100644 Documentation/devicetree/bindings/riscv/sunxi.yaml
>>> create mode 100644 arch/riscv/boot/dts/allwinner/Makefile
>>> create mode 100644
>>> arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts create
>>> mode 100644
>>> arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi create
>>> mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts
>>> create mode 100644
>>> arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts create
>>> mode 100644
>>> arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
>>> create mode 100644
>>> arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts
>>> create mode 100644
>>> arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi create
>>> mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
>>> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
>>> create mode 100644
>>> arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts create mode
>>> 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts create mode
>>> 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
>>
>> I'm assuming these are aimed at the RISC-V tree? I'm generally OK with
>> that, though the DT folks have pointed out a handful of issues that look
>> pretty reasonable to me.
>
> DT changes for Allwinner ARM SoCs go trough sunxi tree. Should this be handled
> differently for RISC-V?

Microchip RISC-V DT go via a Microchip tree to Palmer. The other stuff gets
picked directly by him as it has no clear "owner". I think it would be nice
to be consistent for the new {renesas,sunxi} stuff and send those via vendor
trees to Palmer too. Just my 2 cents...

Conor.

2022-09-08 07:57:09

[permalink] [raw]

Subject: Re: [PATCH 00/12] riscv: Allwinner D1 platform support

Hi Conor,

CC soc people

On Wed, Sep 7, 2022 at 10:43 PM <[email protected]> wrote:
> On 06/09/2022 21:29, Jernej Škrabec wrote:
> > Dne četrtek, 01. september 2022 ob 20:10:13 CEST je Palmer Dabbelt napisal(a):
> >> On Sun, 14 Aug 2022 22:08:03 PDT (-0700), [email protected] wrote:
> >>> arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts create
> >>> mode 100644
> >>> arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi create
> >>> mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts
> >>> create mode 100644
> >>> arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts create
> >>> mode 100644
> >>> arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
> >>> create mode 100644
> >>> arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts
> >>> create mode 100644
> >>> arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi create
> >>> mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
> >>> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
> >>> create mode 100644
> >>> arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts create mode
> >>> 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts create mode
> >>> 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
> >>
> >> I'm assuming these are aimed at the RISC-V tree? I'm generally OK with
> >> that, though the DT folks have pointed out a handful of issues that look
> >> pretty reasonable to me.
> >
> > DT changes for Allwinner ARM SoCs go trough sunxi tree. Should this be handled
> > differently for RISC-V?
>
> Microchip RISC-V DT go via a Microchip tree to Palmer. The other stuff gets
> picked directly by him as it has no clear "owner". I think it would be nice
> to be consistent for the new {renesas,sunxi} stuff and send those via vendor
> trees to Palmer too. Just my 2 cents...

Wasn't the intention behind the rename s/arm-soc/soc/ to start
accepting PRs for non-arm DT, too?
Especially if we start having dependencies due to riscv DTS files
including arm64 DTS snippets through scripts/dtc/include-prefixes/arm64/.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

2022-09-08 09:22:23

by Arnd Bergmann

[permalink] [raw]

Subject: Re: [PATCH 00/12] riscv: Allwinner D1 platform support

On Thu, Sep 8, 2022, at 9:00 AM, Geert Uytterhoeven wrote:
> On Wed, Sep 7, 2022 at 10:43 PM <[email protected]> wrote:
>> On 06/09/2022 21:29, Jernej Škrabec wrote:
>> > Dne četrtek, 01. september 2022 ob 20:10:13 CEST je Palmer Dabbelt napisal(a):
>> >> On Sun, 14 Aug 2022 22:08:03 PDT (-0700), [email protected] wrote:
>> >>> arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts create
>> >>> mode 100644
>> >>> arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi create
>> >>> mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts
>> >>> create mode 100644
>> >>> arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts create
>> >>> mode 100644
>> >>> arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
>> >>> create mode 100644
>> >>> arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts
>> >>> create mode 100644
>> >>> arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi create
>> >>> mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
>> >>> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
>> >>> create mode 100644
>> >>> arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts create mode
>> >>> 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts create mode
>> >>> 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
>> >>
>> >> I'm assuming these are aimed at the RISC-V tree? I'm generally OK with
>> >> that, though the DT folks have pointed out a handful of issues that look
>> >> pretty reasonable to me.
>> >
>> > DT changes for Allwinner ARM SoCs go trough sunxi tree. Should this be handled
>> > differently for RISC-V?
>>
>> Microchip RISC-V DT go via a Microchip tree to Palmer. The other stuff gets
>> picked directly by him as it has no clear "owner". I think it would be nice
>> to be consistent for the new {renesas,sunxi} stuff and send those via vendor
>> trees to Palmer too. Just my 2 cents...
>
> Wasn't the intention behind the rename s/arm-soc/soc/ to start
> accepting PRs for non-arm DT, too?
> Especially if we start having dependencies due to riscv DTS files
> including arm64 DTS snippets through scripts/dtc/include-prefixes/arm64/.

Yes, absolutely. My impression was that most architecture
maintainers prefer to handle the SoC support themselves, and
I would not want to step on anyone's toes with this, but I'm
definitely happy to take pull requests for dts files etc on
any architecture if that helps.

Arnd

2022-09-09 03:56:30

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

On 8/22/22 10:29 AM, Jessica Clarke wrote:
> On 22 Aug 2022, at 14:56, [email protected] wrote:
>>
>> On 22/08/2022 13:31, Geert Uytterhoeven wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>
>>
>>>> Do you think this is worth doing? Or are you just providing an
>>>> example of what could be done?
>>>
>>> Just some brainstorming...
>>>
>>>> Where would you envisage putting these macros? I forget the order
>>>> of the CPP operations that are done, can they be put in the dts?
>>>
>>> The SOC_PERIPHERAL_IRQ() macro should be defined in the
>>> ARM-based SoC.dtsi file and the RISC-V-based SoC.dtsi file.
>>
>> Right, one level up but ~the same result.
>>
>>
>>>>> Nice! But it's gonna be a very large interrupt-map.
>>>>
>>>> I quite like the idea of not duplicating files across the archs
>>>> if it can be helped, but not at the expense of making them hard to
>>>> understand & I feel like unfortunately the large interrupt map is
>>>> in that territory.
>>>
>>> I feel the same.
>>> Even listing both interrupt numbers in SOC_PERIPHERAL_IRQ(na, nr)
>>> is a risk for making mistakes.
>>>
>>> So personally, I'm in favor of teaching dtc arithmetic, so we can
>>> handle the offset in SOC_PERIPHERAL_IRQ().
>>
>> Yup, in the same boat here. mayb I'll get bored enough to bite..
>
> Note that GPL’ed dtc isn’t the only implementation. FreeBSD uses a
> BSD-licensed implementation[1] and so adding new features like this to
> GPL dtc that actually get used would require us to reimplement it too.
> I don’t know how much effort it would be but please keep this in mind.

I plan to go with the "SOC_PERIPHERAL_IRQ(na, nr)" implementation for v2. I like
that it only affects the DT source, and does not leak into the DTB. We still
have the freedom to switch to using arithmetic later when all of the tools
support it.

My other concern is that the big interrupt-map property would make DT overlays
even more painful to deal with. I don't think overlays can append to a property,
only replace it.

Regards,
Samuel

2022-09-09 04:43:02

[permalink] [raw]

Subject: Re: [PATCH 07/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree

Hi Conor,

On 8/19/22 5:10 PM, [email protected] wrote:
> Finally got around to giving this a go with the fix for loading
> modules which is mostly what was blocking me before..
>
> On 15/08/2022 06:08, Samuel Holland wrote:
>> "D1 Nezha" is Allwinner's first-party development board for the D1 SoC.
>> It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard audio,
>
> I am really not keen on the way you have things, with the memory
> nodes removed from the device tree. I know your preferred flow
> for booting these things might be to pass the dtb up from U-Boot,
> but I think the devicetree in the kernel should be usable in a
> standalone manner, even if that is the barest-minimum memory
> config.

That is simply not possible to guarantee. As an obvious example, consider the
MangoPi MQ-Pro board with socketed DRAM:

https://twitter.com/mangopi_sbc/status/1516225559214583808

But focusing on the /memory node misses the bigger picture. The DTB is passed
through _all_ of the firmware stages, and gets patched by every one of them:

- SPL/boot0 adds the /memory node with the detected DRAM size.
If the in-tree DTS has a "minimum memory config" (which for a
board with socketed DRAM means the smallest possible die), I
guarantee people will use it and complain about missing DRAM.

- The SBI implementation reserves memory for itself and any
possible secure partitions. Right now, booting happens to work
without the reserved-memory node because the SBI implementation
is loaded at the beginning of RAM, and Linux ignores RAM below
the kernel load address.

However, memory-constrained devices (e.g. D1s) will need to get
those 2 MiB back by loading the kernel at the start of DRAM and
SBI at the end of DRAM. Then the reserved-memory node becomes
quite important.

It also adds nodes for CPU idle states, since the available
states and their latencies depend on the SBI implementation.

It also reserves devices used by it or by a secure partition.
And it is responsible for extracting data (e.g. MAC addresses)
from "secure" eFuses which the OS may not have access to.

- U-Boot adds other information, like boot arguments, the address
of the initramfs and framebuffer, etc. These are less of a
concern because of course U-Boot can patch these in to a DTB
loaded from disk, but they are relevant if you want to load a
DTB from a later bootloader like GRUB.

If you load a DTB from disk, you lose all of the changes made by the earlier
firmware stages. On ARM, U-Boot tries to work around this by copying a few
specific bits of information from the firmware DTB to the DTB loaded from disk.
But this misses the point that the SBI implementation can modify *any* part of
the DTB. (So in practice U-Boot on ARM already loses CPU idle states and
reserved memory nodes that were added by the PSCI implementation.)

As an extreme example, consider paravirtualization, where only a small subset of
DRAM and peripherals may be made available to any one OS partition.

Fundamentally, I reserve the right to make arbitrary changes to the DTB in the
SBI implementation, and thus I cannot condone using the DTBs generated from the
Linux source tree for any purpose other than validation.

Regards,
Samuel

2022-09-09 07:33:02

[permalink] [raw]

Subject: Re: [PATCH 07/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree

On 09/09/2022 05:37, Samuel Holland wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> Hi Conor,
>
> On 8/19/22 5:10 PM, [email protected] wrote:
>> Finally got around to giving this a go with the fix for loading
>> modules which is mostly what was blocking me before..
>>
>> On 15/08/2022 06:08, Samuel Holland wrote:
>>> "D1 Nezha" is Allwinner's first-party development board for the
>>> D1 SoC. It was shipped with 512M, 1G, or 2G of DDR3. It supports
>>> onboard audio,
>>
>> I am really not keen on the way you have things, with the memory
>> nodes removed from the device tree. I know your preferred flow for
>> booting these things might be to pass the dtb up from U-Boot, but I
>> think the devicetree in the kernel should be usable in a standalone
>> manner, even if that is the barest-minimum memory config.
>
> That is simply not possible to guarantee. As an obvious example,
> consider the MangoPi MQ-Pro board with socketed DRAM:

Yeah, I knew in my heart-of-hearts that this probably was a non
runner.

>
> https://twitter.com/mangopi_sbc/status/1516225559214583808
>
> But focusing on the /memory node misses the bigger picture. The DTB
> is passed through _all_ of the firmware stages, and gets patched by
> every one of them:
>
> - SPL/boot0 adds the /memory node with the detected DRAM size. If the
> in-tree DTS has a "minimum memory config" (which for a board with
> socketed DRAM means the smallest possible die), I guarantee people
> will use it and complain about missing DRAM.

True, but they are also complaining about missing DRAM as is ;)
No possibility of winning here unfortunately.

> - The SBI implementation reserves memory for itself and any possible
> secure partitions. Right now, booting happens to work without the
> reserved-memory node because the SBI implementation is loaded at the
> beginning of RAM, and Linux ignores RAM below the kernel load
> address.

Surely this sort of thing is a common problem though, it's not like
any of us are doing something unique here are we? At least if there
was a arch wide policy about the validity of the upstream DTS in the
face of the SBI etc inflicting changes there'd be something to point
to. I am just looking at this from a "everyone else has a usable dts
in the kernel, but the D1 boards wont have" point of view.

> However, memory-constrained devices (e.g. D1s) will need to get those
> 2 MiB back by loading the kernel at the start of DRAM and SBI at the
> end of DRAM. Then the reserved-memory node becomes quite important.
>
> It also adds nodes for CPU idle states, since the available states
> and their latencies depend on the SBI implementation.
>
> It also reserves devices used by it or by a secure partition. And it
> is responsible for extracting data (e.g. MAC addresses) from "secure"
> eFuses which the OS may not have access to.
>
> - U-Boot adds other information, like boot arguments, the address of
> the initramfs and framebuffer, etc. These are less of a concern
> because of course U-Boot can patch these in to a DTB loaded from
> disk, but they are relevant if you want to load a DTB from a later
> bootloader like GRUB.
>
> If you load a DTB from disk, you lose all of the changes made by the
> earlier firmware stages. On ARM, U-Boot tries to work around this by
> copying a few specific bits of information from the firmware DTB to
> the DTB loaded from disk. But this misses the point that the SBI
> implementation can modify *any* part of the DTB. (So in practice
> U-Boot on ARM already loses CPU idle states and reserved memory nodes
> that were added by the PSCI implementation.)

All of these things are valid, but they are reasons why your flow in
your bootloaders etc are the way they are more than a reason why the
upstream dts will not work for someone who is not interested in that
flow. At the end of the day, I only care so much about this as it is
not me that has to deal with any confusion from either approach. I'll
continue to modify my dts in U-Boot so I can test things without me
having to re-program the world. /shrug

> As an extreme example, consider paravirtualization, where only a
> small subset of DRAM and peripherals may be made available to any one
> OS partition.

Or AMP - though not likely that that is a problem for the D1..

> Fundamentally, I reserve the right to make arbitrary changes to the
> DTB in the SBI implementation, and thus I cannot condone using the
> DTBs generated from the Linux source tree for any purpose other than
> validation.

Fundamentally, I reserve the right to complain that the upstream dts
cannot be entirely validated as it does not work out-of-the-box ;)

Either way, I am only going to complain so much about something that
triggers my OCD about keeping things the same, you have a
Tested-by: Conor Dooley <[email protected]>
already and once the other issues are cleaned up an R-b too. Not trying
make an issue out of this, just expressing my dislike for the
inconsistency between the D1 stuff and vendors - partly in the hopes
that the "higher powers" get involved. I can't imagine that this is
the last time something like this comes up.

Thanks,
Conor.

2022-09-09 07:55:53

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

Hi Samuel,

On Fri, Sep 9, 2022 at 5:42 AM Samuel Holland <[email protected]> wrote:
> On 8/22/22 10:29 AM, Jessica Clarke wrote:
> > On 22 Aug 2022, at 14:56, [email protected] wrote:
> >> On 22/08/2022 13:31, Geert Uytterhoeven wrote:
> >>>> Do you think this is worth doing? Or are you just providing an
> >>>> example of what could be done?
> >>>
> >>> Just some brainstorming...
> >>>
> >>>> Where would you envisage putting these macros? I forget the order
> >>>> of the CPP operations that are done, can they be put in the dts?
> >>>
> >>> The SOC_PERIPHERAL_IRQ() macro should be defined in the
> >>> ARM-based SoC.dtsi file and the RISC-V-based SoC.dtsi file.
> >>
> >> Right, one level up but ~the same result.
> >>
> >>>>> Nice! But it's gonna be a very large interrupt-map.
> >>>>
> >>>> I quite like the idea of not duplicating files across the archs
> >>>> if it can be helped, but not at the expense of making them hard to
> >>>> understand & I feel like unfortunately the large interrupt map is
> >>>> in that territory.
> >>>
> >>> I feel the same.
> >>> Even listing both interrupt numbers in SOC_PERIPHERAL_IRQ(na, nr)
> >>> is a risk for making mistakes.
> >>>
> >>> So personally, I'm in favor of teaching dtc arithmetic, so we can
> >>> handle the offset in SOC_PERIPHERAL_IRQ().
> >>
> >> Yup, in the same boat here. mayb I'll get bored enough to bite..
> >
> > Note that GPL’ed dtc isn’t the only implementation. FreeBSD uses a
> > BSD-licensed implementation[1] and so adding new features like this to
> > GPL dtc that actually get used would require us to reimplement it too.
> > I don’t know how much effort it would be but please keep this in mind.
>
> I plan to go with the "SOC_PERIPHERAL_IRQ(na, nr)" implementation for v2. I like
> that it only affects the DT source, and does not leak into the DTB. We still
> have the freedom to switch to using arithmetic later when all of the tools
> support it.

May I suggest an alternative solution, which would be more generic,
and can be extended to other/more CPU cores easily:

Specify both interrupts in the .dtsi, but wrapped inside e.g. ARM()
resp. RISCV() macros:

ARM(interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>;)
RISCV(interrupts = <412 IRQ_TYPE_LEVEL_HIGH>;)

The same construct can be used for e.g. interrupt-parent.
The ARM .dts would define:

#define ARM(x...) x
#define RISCV(x....)

before including the .dtsi.
The RISC-V DTS would define instead:

#define ARM(x...)
#define RISCV(x...) x

Cfr. the AR_CLASS(), M_CLASS(), ARM(), and THUMB() macros in
arch/arm/include/asm/unified.h.

Note that this is not exactly a new issue. It's fairly common for
SoCs to have separate application and real-time cores, and on-SoC
devices may be wired to multiple interrupt controllers serving
the AP resp. RT cores. If both core sets are ARM, both interrupt
controllers may be GIC, and the problem may be less severe and just
need a different #interrupt-parent.
But in case of ARM vs. RISC-V, or different wirings from devices
to interrupt controllers, you do need completely different interrupts
properties.

> My other concern is that the big interrupt-map property would make DT overlays
> even more painful to deal with. I don't think overlays can append to a property,
> only replace it.

Indeed, overlays can only add/replace/delete properties.
Same for plain DTS files, BTW.
But I agree having /append-property/ would be useful in general.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

2022-09-09 08:28:05

[permalink] [raw]

Subject: Re: [PATCH 07/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree

Am Freitag, 9. September 2022, 09:18:40 CEST schrieb [email protected]:
> On 09/09/2022 05:37, Samuel Holland wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you
> > know the content is safe
> >
> > Hi Conor,
> >
> > On 8/19/22 5:10 PM, [email protected] wrote:
> >> Finally got around to giving this a go with the fix for loading
> >> modules which is mostly what was blocking me before..
> >>
> >> On 15/08/2022 06:08, Samuel Holland wrote:
> >>> "D1 Nezha" is Allwinner's first-party development board for the
> >>> D1 SoC. It was shipped with 512M, 1G, or 2G of DDR3. It supports
> >>> onboard audio,
> >>
> >> I am really not keen on the way you have things, with the memory
> >> nodes removed from the device tree. I know your preferred flow for
> >> booting these things might be to pass the dtb up from U-Boot, but I
> >> think the devicetree in the kernel should be usable in a standalone
> >> manner, even if that is the barest-minimum memory config.
> >
> > That is simply not possible to guarantee. As an obvious example,
> > consider the MangoPi MQ-Pro board with socketed DRAM:
>
> Yeah, I knew in my heart-of-hearts that this probably was a non
> runner.
>
> >
> > https://twitter.com/mangopi_sbc/status/1516225559214583808
> >
> > But focusing on the /memory node misses the bigger picture. The DTB
> > is passed through _all_ of the firmware stages, and gets patched by
> > every one of them:
> >
> > - SPL/boot0 adds the /memory node with the detected DRAM size. If the
> > in-tree DTS has a "minimum memory config" (which for a board with
> > socketed DRAM means the smallest possible die), I guarantee people
> > will use it and complain about missing DRAM.
>
> True, but they are also complaining about missing DRAM as is ;)
> No possibility of winning here unfortunately.
>
> > - The SBI implementation reserves memory for itself and any possible
> > secure partitions. Right now, booting happens to work without the
> > reserved-memory node because the SBI implementation is loaded at the
> > beginning of RAM, and Linux ignores RAM below the kernel load
> > address.
>
> Surely this sort of thing is a common problem though, it's not like
> any of us are doing something unique here are we? At least if there
> was a arch wide policy about the validity of the upstream DTS in the
> face of the SBI etc inflicting changes there'd be something to point
> to. I am just looking at this from a "everyone else has a usable dts
> in the kernel, but the D1 boards wont have" point of view.

Not sure if this would fly, but what about having an sbi call for
"modify this dtb for me as well"?

I'll just assume that spl/boot0 + main uboot come in some sort
of package so moving the memory node over should be in uboot's
scope, but for the sbi part just have a call pointing to the
new dtb in memory and have it modify it in the same way as the
original one?

Heiko

> > However, memory-constrained devices (e.g. D1s) will need to get those
> > 2 MiB back by loading the kernel at the start of DRAM and SBI at the
> > end of DRAM. Then the reserved-memory node becomes quite important.
> >
> > It also adds nodes for CPU idle states, since the available states
> > and their latencies depend on the SBI implementation.
> >
> > It also reserves devices used by it or by a secure partition. And it
> > is responsible for extracting data (e.g. MAC addresses) from "secure"
> > eFuses which the OS may not have access to.
> >
> > - U-Boot adds other information, like boot arguments, the address of
> > the initramfs and framebuffer, etc. These are less of a concern
> > because of course U-Boot can patch these in to a DTB loaded from
> > disk, but they are relevant if you want to load a DTB from a later
> > bootloader like GRUB.
> >
> > If you load a DTB from disk, you lose all of the changes made by the
> > earlier firmware stages. On ARM, U-Boot tries to work around this by
> > copying a few specific bits of information from the firmware DTB to
> > the DTB loaded from disk. But this misses the point that the SBI
> > implementation can modify *any* part of the DTB. (So in practice
> > U-Boot on ARM already loses CPU idle states and reserved memory nodes
> > that were added by the PSCI implementation.)
>
> All of these things are valid, but they are reasons why your flow in
> your bootloaders etc are the way they are more than a reason why the
> upstream dts will not work for someone who is not interested in that
> flow. At the end of the day, I only care so much about this as it is
> not me that has to deal with any confusion from either approach. I'll
> continue to modify my dts in U-Boot so I can test things without me
> having to re-program the world. /shrug
>
> > As an extreme example, consider paravirtualization, where only a
> > small subset of DRAM and peripherals may be made available to any one
> > OS partition.
>
> Or AMP - though not likely that that is a problem for the D1..
>
> > Fundamentally, I reserve the right to make arbitrary changes to the
> > DTB in the SBI implementation, and thus I cannot condone using the
> > DTBs generated from the Linux source tree for any purpose other than
> > validation.
>
> Fundamentally, I reserve the right to complain that the upstream dts
> cannot be entirely validated as it does not work out-of-the-box ;)
>
> Either way, I am only going to complain so much about something that
> triggers my OCD about keeping things the same, you have a
> Tested-by: Conor Dooley <[email protected]>
> already and once the other issues are cleaned up an R-b too. Not trying
> make an issue out of this, just expressing my dislike for the
> inconsistency between the D1 stuff and vendors - partly in the hopes
> that the "higher powers" get involved. I can't imagine that this is
> the last time something like this comes up.
>
> Thanks,
> Conor.
>
>
>
>
>
>

2022-09-09 19:28:19

by Jessica Clarke

[permalink] [raw]

Subject: Re: [PATCH 07/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree

On 9 Sept 2022, at 09:11, Heiko Stübner <[email protected]> wrote:
>
> Am Freitag, 9. September 2022, 09:18:40 CEST schrieb [email protected]:
>> On 09/09/2022 05:37, Samuel Holland wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you
>>> know the content is safe
>>>
>>> Hi Conor,
>>>
>>> On 8/19/22 5:10 PM, [email protected] wrote:
>>>> Finally got around to giving this a go with the fix for loading
>>>> modules which is mostly what was blocking me before..
>>>>
>>>> On 15/08/2022 06:08, Samuel Holland wrote:
>>>>> "D1 Nezha" is Allwinner's first-party development board for the
>>>>> D1 SoC. It was shipped with 512M, 1G, or 2G of DDR3. It supports
>>>>> onboard audio,
>>>>
>>>> I am really not keen on the way you have things, with the memory
>>>> nodes removed from the device tree. I know your preferred flow for
>>>> booting these things might be to pass the dtb up from U-Boot, but I
>>>> think the devicetree in the kernel should be usable in a standalone
>>>> manner, even if that is the barest-minimum memory config.
>>>
>>> That is simply not possible to guarantee. As an obvious example,
>>> consider the MangoPi MQ-Pro board with socketed DRAM:
>>
>> Yeah, I knew in my heart-of-hearts that this probably was a non
>> runner.
>>
>>>
>>> https://twitter.com/mangopi_sbc/status/1516225559214583808
>>>
>>> But focusing on the /memory node misses the bigger picture. The DTB
>>> is passed through _all_ of the firmware stages, and gets patched by
>>> every one of them:
>>>
>>> - SPL/boot0 adds the /memory node with the detected DRAM size. If the
>>> in-tree DTS has a "minimum memory config" (which for a board with
>>> socketed DRAM means the smallest possible die), I guarantee people
>>> will use it and complain about missing DRAM.
>>
>> True, but they are also complaining about missing DRAM as is ;)
>> No possibility of winning here unfortunately.
>>
>>> - The SBI implementation reserves memory for itself and any possible
>>> secure partitions. Right now, booting happens to work without the
>>> reserved-memory node because the SBI implementation is loaded at the
>>> beginning of RAM, and Linux ignores RAM below the kernel load
>>> address.
>>
>> Surely this sort of thing is a common problem though, it's not like
>> any of us are doing something unique here are we? At least if there
>> was a arch wide policy about the validity of the upstream DTS in the
>> face of the SBI etc inflicting changes there'd be something to point
>> to. I am just looking at this from a "everyone else has a usable dts
>> in the kernel, but the D1 boards wont have" point of view.
>
> Not sure if this would fly, but what about having an sbi call for
> "modify this dtb for me as well"?
>
> I'll just assume that spl/boot0 + main uboot come in some sort
> of package so moving the memory node over should be in uboot's
> scope, but for the sbi part just have a call pointing to the
> new dtb in memory and have it modify it in the same way as the
> original one?

There’s an EFI protocol for it.

Jess

> Heiko
>
>
>
>>> However, memory-constrained devices (e.g. D1s) will need to get those
>>> 2 MiB back by loading the kernel at the start of DRAM and SBI at the
>>> end of DRAM. Then the reserved-memory node becomes quite important.
>>>
>>> It also adds nodes for CPU idle states, since the available states
>>> and their latencies depend on the SBI implementation.
>>>
>>> It also reserves devices used by it or by a secure partition. And it
>>> is responsible for extracting data (e.g. MAC addresses) from "secure"
>>> eFuses which the OS may not have access to.
>>>
>>> - U-Boot adds other information, like boot arguments, the address of
>>> the initramfs and framebuffer, etc. These are less of a concern
>>> because of course U-Boot can patch these in to a DTB loaded from
>>> disk, but they are relevant if you want to load a DTB from a later
>>> bootloader like GRUB.
>>>
>>> If you load a DTB from disk, you lose all of the changes made by the
>>> earlier firmware stages. On ARM, U-Boot tries to work around this by
>>> copying a few specific bits of information from the firmware DTB to
>>> the DTB loaded from disk. But this misses the point that the SBI
>>> implementation can modify *any* part of the DTB. (So in practice
>>> U-Boot on ARM already loses CPU idle states and reserved memory nodes
>>> that were added by the PSCI implementation.)
>>
>> All of these things are valid, but they are reasons why your flow in
>> your bootloaders etc are the way they are more than a reason why the
>> upstream dts will not work for someone who is not interested in that
>> flow. At the end of the day, I only care so much about this as it is
>> not me that has to deal with any confusion from either approach. I'll
>> continue to modify my dts in U-Boot so I can test things without me
>> having to re-program the world. /shrug
>>
>>> As an extreme example, consider paravirtualization, where only a
>>> small subset of DRAM and peripherals may be made available to any one
>>> OS partition.
>>
>> Or AMP - though not likely that that is a problem for the D1..
>>
>>> Fundamentally, I reserve the right to make arbitrary changes to the
>>> DTB in the SBI implementation, and thus I cannot condone using the
>>> DTBs generated from the Linux source tree for any purpose other than
>>> validation.
>>
>> Fundamentally, I reserve the right to complain that the upstream dts
>> cannot be entirely validated as it does not work out-of-the-box ;)
>>
>> Either way, I am only going to complain so much about something that
>> triggers my OCD about keeping things the same, you have a
>> Tested-by: Conor Dooley <[email protected]>
>> already and once the other issues are cleaned up an R-b too. Not trying
>> make an issue out of this, just expressing my dislike for the
>> inconsistency between the D1 stuff and vendors - partly in the hopes
>> that the "higher powers" get involved. I can't imagine that this is
>> the last time something like this comes up.
>>
>> Thanks,
>> Conor.
>>
>>
>>
>>
>>
>>
>
>
>
>
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv

2022-09-21 08:28:39

[permalink] [raw]

Subject: Re: [PATCH 06/12] riscv: dts: allwinner: Add the D1 SoC base devicetree

On Fri, Sep 9, 2022 at 9:10 AM Geert Uytterhoeven <[email protected]> wrote:
> On Fri, Sep 9, 2022 at 5:42 AM Samuel Holland <[email protected]> wrote:
> > On 8/22/22 10:29 AM, Jessica Clarke wrote:
> > > On 22 Aug 2022, at 14:56, [email protected] wrote:
> > >> On 22/08/2022 13:31, Geert Uytterhoeven wrote:
> > >>>> Do you think this is worth doing? Or are you just providing an
> > >>>> example of what could be done?
> > >>>
> > >>> Just some brainstorming...
> > >>>
> > >>>> Where would you envisage putting these macros? I forget the order
> > >>>> of the CPP operations that are done, can they be put in the dts?
> > >>>
> > >>> The SOC_PERIPHERAL_IRQ() macro should be defined in the
> > >>> ARM-based SoC.dtsi file and the RISC-V-based SoC.dtsi file.
> > >>
> > >> Right, one level up but ~the same result.
> > >>
> > >>>>> Nice! But it's gonna be a very large interrupt-map.
> > >>>>
> > >>>> I quite like the idea of not duplicating files across the archs
> > >>>> if it can be helped, but not at the expense of making them hard to
> > >>>> understand & I feel like unfortunately the large interrupt map is
> > >>>> in that territory.
> > >>>
> > >>> I feel the same.
> > >>> Even listing both interrupt numbers in SOC_PERIPHERAL_IRQ(na, nr)
> > >>> is a risk for making mistakes.
> > >>>
> > >>> So personally, I'm in favor of teaching dtc arithmetic, so we can
> > >>> handle the offset in SOC_PERIPHERAL_IRQ().
> > >>
> > >> Yup, in the same boat here. mayb I'll get bored enough to bite..
> > >
> > > Note that GPL’ed dtc isn’t the only implementation. FreeBSD uses a
> > > BSD-licensed implementation[1] and so adding new features like this to
> > > GPL dtc that actually get used would require us to reimplement it too.
> > > I don’t know how much effort it would be but please keep this in mind.
> >
> > I plan to go with the "SOC_PERIPHERAL_IRQ(na, nr)" implementation for v2. I like
> > that it only affects the DT source, and does not leak into the DTB. We still
> > have the freedom to switch to using arithmetic later when all of the tools
> > support it.
>
> May I suggest an alternative solution, which would be more generic,
> and can be extended to other/more CPU cores easily:
>
> Specify both interrupts in the .dtsi, but wrapped inside e.g. ARM()
> resp. RISCV() macros:
>
> ARM(interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>;)
> RISCV(interrupts = <412 IRQ_TYPE_LEVEL_HIGH>;)
>
> The same construct can be used for e.g. interrupt-parent.
> The ARM .dts would define:
>
> #define ARM(x...) x
> #define RISCV(x....)
>
> before including the .dtsi.
> The RISC-V DTS would define instead:
>
> #define ARM(x...)
> #define RISCV(x...) x
>
> Cfr. the AR_CLASS(), M_CLASS(), ARM(), and THUMB() macros in
> arch/arm/include/asm/unified.h.

I brought it up with the DT people in a separate thread[1].
Please continue the discussion there.
Thanks!

[1] https://lore.kernel.org/r/CAMuHMdUPm36RsxHdVwspR3NCAR3C507AyB6R65W42N2gXWq0ag@mail.gmail.com

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

2022-11-04 03:17:53

by Icenowy Zheng

[permalink] [raw]

Subject: Re: [PATCH 02/12] dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles

在 2022-08-15星期一的 00:08 -0500，Samuel Holland写道：
> The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor.
> Notably, the C906 core is used in the Allwinner D1 SoC.

Could this get applied first?

C906 and C910 now have a fixed-configuration open-source version, which
means these cores could be played by anyone, and having them in the DT
binding really helps people. In addition I am aware of some C906-
equipped SoC out of Allwinner.

>
> Signed-off-by: Samuel Holland <[email protected]>
> ---
>
> Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml
> b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 873dd12f6e89..ce2161d9115a 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -38,6 +38,8 @@ properties:
>                - sifive,u5
>                - sifive,u7
>                - canaan,k210
> +              - thead,c906
> +              - thead,c910
>            - const: riscv
>        - items:
>            - enum:

2022-11-20 11:29:32

[permalink] [raw]

Subject: Re: [PATCH 02/12] dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles

On Sun, Nov 20, 2022 at 11:23:42AM +0000, Conor Dooley wrote:
> On Fri, Nov 04, 2022 at 10:57:58AM +0800, Icenowy Zheng wrote:
> > 在 2022-08-15星期一的 00:08 -0500，Samuel Holland写道：
> > > The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor.
> > > Notably, the C906 core is used in the Allwinner D1 SoC.
> >
> > Could this get applied first?
> >
> > C906 and C910 now have a fixed-configuration open-source version, which
> > means these cores could be played by anyone, and having them in the DT
> > binding really helps people. In addition I am aware of some C906-
> > equipped SoC out of Allwinner.
>
> I've applied this one patch as v6.2 material since I doubt this series is
> gonna make it & the Bouffalolabs dt is going to need this compatible too.
> I applied it on top of v6.1-rc1 just in case:
>
> https://git.kernel.org/conor/c/0d814000ad3589bf4f69c9cb25a3b77bbd55ffec

Woops, totally the wrong hash. Fixed:
https://git.kernel.org/conor/c/41adc2fbad8bc42ed5fdf480e5318133a4941bbb

Thanks,
Conor.

2022-11-20 11:38:01