This patch series enabled basic clock & reset support for StarFive
JH8100 SoC.
This patch series depends on the Initial device tree support for
StarFive JH8100 SoC patch series which can be found at below link:
https://lore.kernel.org/lkml/[email protected]/
StarFive JH8100 shares a similar clock and reset design with JH7110.
To facilitate the reuse of the file and its functionalities, files
containing the 'jh71x0' naming convention are renamed to use the
'common' wording. Internal functions that contain the 'jh71x0'
naming convention are renamed to use 'starfive.' This is accomplished
through patches 1, 2, 3, and 4.
Patch 5 adds documentation to describe System (SYSCRG) Clock & Reset
binding.
Patch 6 adds SYSCRG clock driver.
patch 7 adds documentation to describe System-North-West (SYSCRG-NW)
Clock & Reset binding.
Patch 8 adds SYSCRG-NW clock driver.
patch 9 adds documentation to describe System-North-East (SYSCRG-NE)
Clock & Reset binding.
Patch 10 adds SYSCRG-NE clock driver.
patch 11 adds documentation to describe System-South-West (SYSCRG-SW)
Clock & Reset binding.
Patch 12 adds SYSCRG-SW clock driver.
patch 13 adds documentation to describe Always-On (AON)
Clock & Reset binding.
Patch 14 adds AON clock driver.
Patch 15 adds support for the auxiliary reset driver.
Patch 16 adds clocks and reset nodes to the JH8100 device tree.
Sia Jee Heng (16):
reset: starfive: Rename file name "jh71x0" to "common"
reset: starfive: Convert the word "jh71x0" to "starfive"
clk: starfive: Rename file name "jh71x0" to "common"
clk: starfive: Convert the word "jh71x0" to "starfive"
dt-bindings: clock: Add StarFive JH8100 System clock and reset
generator
clk: starfive: Add JH8100 System clock generator driver
dt-bindings: clock: Add StarFive JH8100 System-North-West clock and
reset generator
clk: starfive: Add JH8100 System-North-West clock generator driver
dt-bindings: clock: Add StarFive JH8100 System-North-East clock and
reset generator
clk: starfive: Add JH8100 System-North-East clock generator driver
dt-bindings: clock: Add StarFive JH8100 System-South-West clock and
reset generator
clk: starfive: Add JH8100 System-South-West clock generator driver
dt-bindings: clock: Add StarFive JH8100 Always-On clock and reset
generator
clk: starfive: Add JH8100 Always-On clock generator driver
reset: starfive: Add StarFive JH8100 reset driver
riscv: dts: starfive: jh8100: Add clocks and resets nodes
.../clock/starfive,jh8100-aoncrg.yaml | 77 +++
.../clock/starfive,jh8100-syscrg-ne.yaml | 158 +++++
.../clock/starfive,jh8100-syscrg-nw.yaml | 119 ++++
.../clock/starfive,jh8100-syscrg-sw.yaml | 66 ++
.../clock/starfive,jh8100-syscrg.yaml | 66 ++
MAINTAINERS | 15 +
arch/riscv/boot/dts/starfive/jh8100-clk.dtsi | 180 ++++++
arch/riscv/boot/dts/starfive/jh8100.dtsi | 115 ++++
drivers/clk/starfive/Kconfig | 49 +-
drivers/clk/starfive/Makefile | 3 +-
drivers/clk/starfive/clk-starfive-common.c | 327 ++++++++++
drivers/clk/starfive/clk-starfive-common.h | 130 ++++
.../clk/starfive/clk-starfive-jh7100-audio.c | 127 ++--
drivers/clk/starfive/clk-starfive-jh7100.c | 503 ++++++++--------
.../clk/starfive/clk-starfive-jh7110-aon.c | 62 +-
.../clk/starfive/clk-starfive-jh7110-isp.c | 72 +--
.../clk/starfive/clk-starfive-jh7110-stg.c | 94 +--
.../clk/starfive/clk-starfive-jh7110-sys.c | 523 ++++++++--------
.../clk/starfive/clk-starfive-jh7110-vout.c | 74 +--
drivers/clk/starfive/clk-starfive-jh7110.h | 4 +-
drivers/clk/starfive/clk-starfive-jh71x0.c | 327 ----------
drivers/clk/starfive/clk-starfive-jh71x0.h | 123 ----
drivers/clk/starfive/jh8100/Makefile | 7 +
drivers/clk/starfive/jh8100/clk-aon.c | 275 +++++++++
.../clk/starfive/jh8100/clk-starfive-jh8100.h | 11 +
drivers/clk/starfive/jh8100/clk-sys-ne.c | 566 ++++++++++++++++++
drivers/clk/starfive/jh8100/clk-sys-nw.c | 268 +++++++++
drivers/clk/starfive/jh8100/clk-sys-sw.c | 136 +++++
drivers/clk/starfive/jh8100/clk-sys.c | 455 ++++++++++++++
drivers/reset/starfive/Kconfig | 14 +-
drivers/reset/starfive/Makefile | 4 +-
...rfive-jh71x0.c => reset-starfive-common.c} | 68 +--
.../reset/starfive/reset-starfive-common.h | 14 +
.../reset/starfive/reset-starfive-jh7100.c | 4 +-
.../reset/starfive/reset-starfive-jh7110.c | 8 +-
.../reset/starfive/reset-starfive-jh71x0.h | 14 -
.../reset/starfive/reset-starfive-jh8100.c | 102 ++++
.../dt-bindings/clock/starfive,jh8100-crg.h | 430 +++++++++++++
.../dt-bindings/reset/starfive,jh8100-crg.h | 127 ++++
...rfive-jh71x0.h => reset-starfive-common.h} | 10 +-
40 files changed, 4485 insertions(+), 1242 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-aoncrg.yaml
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-ne.yaml
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-nw.yaml
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-sw.yaml
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg.yaml
create mode 100644 arch/riscv/boot/dts/starfive/jh8100-clk.dtsi
create mode 100644 drivers/clk/starfive/clk-starfive-common.c
create mode 100644 drivers/clk/starfive/clk-starfive-common.h
delete mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.c
delete mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.h
create mode 100644 drivers/clk/starfive/jh8100/Makefile
create mode 100644 drivers/clk/starfive/jh8100/clk-aon.c
create mode 100644 drivers/clk/starfive/jh8100/clk-starfive-jh8100.h
create mode 100644 drivers/clk/starfive/jh8100/clk-sys-ne.c
create mode 100644 drivers/clk/starfive/jh8100/clk-sys-nw.c
create mode 100644 drivers/clk/starfive/jh8100/clk-sys-sw.c
create mode 100644 drivers/clk/starfive/jh8100/clk-sys.c
rename drivers/reset/starfive/{reset-starfive-jh71x0.c => reset-starfive-common.c} (55%)
create mode 100644 drivers/reset/starfive/reset-starfive-common.h
delete mode 100644 drivers/reset/starfive/reset-starfive-jh71x0.h
create mode 100644 drivers/reset/starfive/reset-starfive-jh8100.c
create mode 100644 include/dt-bindings/clock/starfive,jh8100-crg.h
create mode 100644 include/dt-bindings/reset/starfive,jh8100-crg.h
rename include/soc/starfive/{reset-starfive-jh71x0.h => reset-starfive-common.h} (50%)
--
2.34.1
StarFive JH8100 shares a similar clock and reset design with JH7110.
To facilitate the reuse of the file and its functionalities, files
containing the "jh71x0" naming convention are renamed to use the
"common" wording.
Signed-off-by: Sia Jee Heng <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
---
drivers/clk/starfive/clk-starfive-jh7110-sys.c | 2 +-
drivers/reset/starfive/Kconfig | 6 +++---
drivers/reset/starfive/Makefile | 2 +-
.../{reset-starfive-jh71x0.c => reset-starfive-common.c} | 4 ++--
.../{reset-starfive-jh71x0.h => reset-starfive-common.h} | 6 +++---
drivers/reset/starfive/reset-starfive-jh7100.c | 2 +-
drivers/reset/starfive/reset-starfive-jh7110.c | 4 ++--
.../{reset-starfive-jh71x0.h => reset-starfive-common.h} | 4 ++--
8 files changed, 15 insertions(+), 15 deletions(-)
rename drivers/reset/starfive/{reset-starfive-jh71x0.c => reset-starfive-common.c} (97%)
rename drivers/reset/starfive/{reset-starfive-jh71x0.h => reset-starfive-common.h} (75%)
rename include/soc/starfive/{reset-starfive-jh71x0.h => reset-starfive-common.h} (81%)
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
index 3884eff9fe93..6e45c580c9ba 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -14,7 +14,7 @@
#include <linux/platform_device.h>
#include <linux/slab.h>
-#include <soc/starfive/reset-starfive-jh71x0.h>
+#include <soc/starfive/reset-starfive-common.h>
#include <dt-bindings/clock/starfive,jh7110-crg.h>
diff --git a/drivers/reset/starfive/Kconfig b/drivers/reset/starfive/Kconfig
index d832339f61bc..29fbcf1a7d83 100644
--- a/drivers/reset/starfive/Kconfig
+++ b/drivers/reset/starfive/Kconfig
@@ -1,12 +1,12 @@
# SPDX-License-Identifier: GPL-2.0-only
-config RESET_STARFIVE_JH71X0
+config RESET_STARFIVE_COMMON
bool
config RESET_STARFIVE_JH7100
bool "StarFive JH7100 Reset Driver"
depends on ARCH_STARFIVE || COMPILE_TEST
- select RESET_STARFIVE_JH71X0
+ select RESET_STARFIVE_COMMON
default ARCH_STARFIVE
help
This enables the reset controller driver for the StarFive JH7100 SoC.
@@ -15,7 +15,7 @@ config RESET_STARFIVE_JH7110
bool "StarFive JH7110 Reset Driver"
depends on CLK_STARFIVE_JH7110_SYS
select AUXILIARY_BUS
- select RESET_STARFIVE_JH71X0
+ select RESET_STARFIVE_COMMON
default ARCH_STARFIVE
help
This enables the reset controller driver for the StarFive JH7110 SoC.
diff --git a/drivers/reset/starfive/Makefile b/drivers/reset/starfive/Makefile
index 7a44b66fb9d5..582e4c160bd4 100644
--- a/drivers/reset/starfive/Makefile
+++ b/drivers/reset/starfive/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_RESET_STARFIVE_JH71X0) += reset-starfive-jh71x0.o
+obj-$(CONFIG_RESET_STARFIVE_COMMON) += reset-starfive-common.o
obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
obj-$(CONFIG_RESET_STARFIVE_JH7110) += reset-starfive-jh7110.o
diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.c b/drivers/reset/starfive/reset-starfive-common.c
similarity index 97%
rename from drivers/reset/starfive/reset-starfive-jh71x0.c
rename to drivers/reset/starfive/reset-starfive-common.c
index 55bbbd2de52c..dab454e46bbf 100644
--- a/drivers/reset/starfive/reset-starfive-jh71x0.c
+++ b/drivers/reset/starfive/reset-starfive-common.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Reset driver for the StarFive JH71X0 SoCs
+ * Reset driver for the StarFive SoCs
*
* Copyright (C) 2021 Emil Renner Berthing <[email protected]>
*/
@@ -12,7 +12,7 @@
#include <linux/reset-controller.h>
#include <linux/spinlock.h>
-#include "reset-starfive-jh71x0.h"
+#include "reset-starfive-common.h"
struct jh71x0_reset {
struct reset_controller_dev rcdev;
diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.h b/drivers/reset/starfive/reset-starfive-common.h
similarity index 75%
rename from drivers/reset/starfive/reset-starfive-jh71x0.h
rename to drivers/reset/starfive/reset-starfive-common.h
index db7d39a87f87..266acc4b2caf 100644
--- a/drivers/reset/starfive/reset-starfive-jh71x0.h
+++ b/drivers/reset/starfive/reset-starfive-common.h
@@ -3,12 +3,12 @@
* Copyright (C) 2021 Emil Renner Berthing <[email protected]>
*/
-#ifndef __RESET_STARFIVE_JH71X0_H
-#define __RESET_STARFIVE_JH71X0_H
+#ifndef __RESET_STARFIVE_COMMON_H
+#define __RESET_STARFIVE_COMMON_H
int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
void __iomem *assert, void __iomem *status,
const u32 *asserted, unsigned int nr_resets,
struct module *owner);
-#endif /* __RESET_STARFIVE_JH71X0_H */
+#endif /* __RESET_STARFIVE_COMMON_H */
diff --git a/drivers/reset/starfive/reset-starfive-jh7100.c b/drivers/reset/starfive/reset-starfive-jh7100.c
index 2a56f7fd4ba7..546dea2e5811 100644
--- a/drivers/reset/starfive/reset-starfive-jh7100.c
+++ b/drivers/reset/starfive/reset-starfive-jh7100.c
@@ -8,7 +8,7 @@
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
-#include "reset-starfive-jh71x0.h"
+#include "reset-starfive-common.h"
#include <dt-bindings/reset/starfive-jh7100.h>
diff --git a/drivers/reset/starfive/reset-starfive-jh7110.c b/drivers/reset/starfive/reset-starfive-jh7110.c
index 29a43f0f2ad6..87dba01491ae 100644
--- a/drivers/reset/starfive/reset-starfive-jh7110.c
+++ b/drivers/reset/starfive/reset-starfive-jh7110.c
@@ -7,9 +7,9 @@
#include <linux/auxiliary_bus.h>
-#include <soc/starfive/reset-starfive-jh71x0.h>
+#include <soc/starfive/reset-starfive-common.h>
-#include "reset-starfive-jh71x0.h"
+#include "reset-starfive-common.h"
#include <dt-bindings/reset/starfive,jh7110-crg.h>
diff --git a/include/soc/starfive/reset-starfive-jh71x0.h b/include/soc/starfive/reset-starfive-common.h
similarity index 81%
rename from include/soc/starfive/reset-starfive-jh71x0.h
rename to include/soc/starfive/reset-starfive-common.h
index 47b486ececc5..56d8f413cf18 100644
--- a/include/soc/starfive/reset-starfive-jh71x0.h
+++ b/include/soc/starfive/reset-starfive-common.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __SOC_STARFIVE_RESET_JH71X0_H
-#define __SOC_STARFIVE_RESET_JH71X0_H
+#ifndef __SOC_STARFIVE_RESET_COMMON_H
+#define __SOC_STARFIVE_RESET_COMMON_H
#include <linux/auxiliary_bus.h>
#include <linux/compiler_types.h>
--
2.34.1
Add bindings for the System clocks and reset generator
(SYSCRG) on JH8100 SoC.
Signed-off-by: Sia Jee Heng <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
---
.../clock/starfive,jh8100-syscrg.yaml | 66 ++++++++++
.../dt-bindings/clock/starfive,jh8100-crg.h | 123 ++++++++++++++++++
.../dt-bindings/reset/starfive,jh8100-crg.h | 23 ++++
3 files changed, 212 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg.yaml
create mode 100644 include/dt-bindings/clock/starfive,jh8100-crg.h
create mode 100644 include/dt-bindings/reset/starfive,jh8100-crg.h
diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg.yaml
new file mode 100644
index 000000000000..14ff8e4ef564
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh8100-syscrg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH8100 System Clock and Reset Generator
+
+maintainers:
+ - Sia Jee Heng <[email protected]>
+
+properties:
+ compatible:
+ const: starfive,jh8100-syscrg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Main Oscillator (24 MHz)
+ - description: External I2S Rx BCLK clock
+ - description: External I2S Rx LRCK clock
+ - description: External MCLK clock
+
+ clock-names:
+ items:
+ - const: clk_osc
+ - const: clk_i2srx_bclk_ext
+ - const: clk_i2srx_lrck_ext
+ - const: clk_mclk_ext
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive,jh8100-crg.h> for valid indices.
+
+ '#reset-cells':
+ const: 1
+ description:
+ See <dt-bindings/reset/starfive-jh8100-crg.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/starfive,jh8100-crg.h>
+
+ clock-controller@126d0000 {
+ compatible = "starfive,jh8100-syscrg";
+ reg = <0x126d0000 0x10000>;
+ clocks = <&clk_osc>, <&clk_i2srx_bclk_ext>,
+ <&clk_i2srx_lrck_ext>, <&clk_mclk_ext>;
+ clock-names = "clk_osc", "clk_i2srx_bclk_ext",
+ "clk_i2srx_lrck_ext", "clk_mclk_ext";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h
new file mode 100644
index 000000000000..e5bb588ce798
--- /dev/null
+++ b/include/dt-bindings/clock/starfive,jh8100-crg.h
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Sia Jee Heng <[email protected]>
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__
+#define __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__
+
+/* SYSCRG_CLK */
+#define SYSCRG_CLK_VDEC_ROOT_PREOSC 0
+#define SYSCRG_CLK_VDEC_ROOT 1
+#define SYSCRG_CLK_VENC_ROOT_PREOSC 2
+#define SYSCRG_CLK_VENC_ROOT 3
+#define SYSCRG_CLK_GPU_ROOT 4
+#define SYSCRG_CLK_GPU_CORE 5
+#define SYSCRG_CLK_VOUT_ROOT0_PREOSC 6
+#define SYSCRG_CLK_VOUT_ROOT0 7
+#define SYSCRG_CLK_VOUT_ROOT1_PREOSC 8
+#define SYSCRG_CLK_VOUT_ROOT1 9
+#define SYSCRG_CLK_VOUT_SCAN_ATS 10
+#define SYSCRG_CLK_PERH_ROOT_PREOSC 11
+#define SYSCRG_CLK_PERH_ROOT 12
+#define SYSCRG_CLK_AXI_200_PREOSC 13
+#define SYSCRG_CLK_AXI_200 14
+#define SYSCRG_CLK_AXI_200_GMAC 15
+#define SYSCRG_CLK_AXI_500_PREOSC 16
+#define SYSCRG_CLK_AXI_500 17
+#define SYSCRG_CLK_AXI_500_PCIEX1A 18
+#define SYSCRG_CLK_AXI_500_PCIEX1B 19
+#define SYSCRG_CLK_AXI_500_PCIEX2 20
+#define SYSCRG_CLK_AXI_500_PCIEX8 21
+#define SYSCRG_CLK_AXI_400_PREOSC 22
+#define SYSCRG_CLK_AXI_400 23
+#define SYSCRG_CLK_AXI_400_APBOOTRAM 24
+#define SYSCRG_CLK_AXI_125_PREOSC 25
+#define SYSCRG_CLK_AXI_125 26
+#define SYSCRG_CLK_AHB0_PREOSC 27
+#define SYSCRG_CLK_AHB0 28
+#define SYSCRG_CLK_APB_BUS_FUNC 29
+#define SYSCRG_CLK_APB_BUS 30
+#define SYSCRG_CLK_APB_BUS_PER0 31
+#define SYSCRG_CLK_APB_BUS_PER1 32
+#define SYSCRG_CLK_APB_BUS_PER2 33
+#define SYSCRG_CLK_APB_BUS_PER3 34
+#define SYSCRG_CLK_APB_BUS_PER4 35
+#define SYSCRG_CLK_APB_BUS_PER5 36
+#define SYSCRG_CLK_APB_BUS_PER6 37
+#define SYSCRG_CLK_APB_BUS_PER7 38
+#define SYSCRG_CLK_APB_BUS_PER8 39
+#define SYSCRG_CLK_APB_BUS_PER9 40
+#define SYSCRG_CLK_APB_BUS_PER10 41
+#define SYSCRG_CLK_SPI_CORE_100 42
+#define SYSCRG_CLK_PLL1_DIV2 43
+#define SYSCRG_CLK_PLL2_DIV2 44
+#define SYSCRG_CLK_PLL3_DIV2 45
+#define SYSCRG_CLK_PLL4_DIV2 46
+#define SYSCRG_CLK_PLL6_DIV2 47
+#define SYSCRG_CLK_PLL7_DIV2 48
+#define SYSCRG_CLK_AUDIO_ROOT 49
+#define SYSCRG_CLK_MCLK_INNER 50
+#define SYSCRG_CLK_MCLK 51
+#define SYSCRG_CLK_MCLK_OUT 52
+#define SYSCRG_CLK_ISP_2X_PREOSC 53
+#define SYSCRG_CLK_ISP_2X 54
+#define SYSCRG_CLK_ISP_AXI 55
+#define SYSCRG_CLK_GCLK1 56
+#define SYSCRG_CLK_GCLK2 57
+#define SYSCRG_CLK_GCLK3 58
+#define SYSCRG_CLK_GCLK4 59
+#define SYSCRG_CLK_GCLK6 60
+#define SYSCRG_CLK_GCLK7 61
+#define SYSCRG_CLK_FLEXNOC0_PREOSC 62
+#define SYSCRG_CLK_FLEXNOC0 63
+#define SYSCRG_CLK_FLEXNOC1_PREOSC 64
+#define SYSCRG_CLK_FLEXNOC1 65
+#define SYSCRG_CLK_FLEXNOC2_PREOSC 66
+#define SYSCRG_CLK_FLEXNOC2 67
+#define SYSCRG_CLK_VDEC_CORE 68
+#define SYSCRG_CLK_GPU_CORE_ICG 69
+#define SYSCRG_CLK_IMG_GPU_CLK_APB 70
+#define SYSCRG_CLK_IMG_GPU_RTC_TOGGLE 71
+#define SYSCRG_CLK_IMG_GPU_TIMER_USC 72
+#define SYSCRG_CLK_HIFI4_CORE_PREOSC 73
+#define SYSCRG_CLK_HIFI4_CORE 74
+#define SYSCRG_CLK_ESPI_200_PREOSC 75
+#define SYSCRG_CLK_ESPI_200 76
+#define SYSCRG_CLK_HD_AUDIO_48M 77
+#define SYSCRG_CLK_VOUT_DC_CORE 78
+#define SYSCRG_CLK_VOUT_AXI 79
+#define SYSCRG_CLK_USB_WRAP_625 80
+#define SYSCRG_CLK_USB_WRAP_480 81
+#define SYSCRG_CLK_USB_WRAP_240 82
+#define SYSCRG_CLK_USB_WRAP_60 83
+#define SYSCRG_CLK_USB_WRAP_156P25 84
+#define SYSCRG_CLK_USB_WRAP_312P5 85
+#define SYSCRG_CLK_USB_125M 86
+#define SYSCRG_CLK_FLEXNOC_APBOOTRAM 87
+#define SYSCRG_CLK_FLEXNOC_PCIEX1AMST 88
+#define SYSCRG_CLK_FLEXNOC_PCIEX1ASLV 89
+#define SYSCRG_CLK_FLEXNOC_PCIEX1BMST 90
+#define SYSCRG_CLK_FLEXNOC_PCIEX1BSLV 91
+#define SYSCRG_CLK_FLEXNOC_PCIEX2MST 92
+#define SYSCRG_CLK_FLEXNOC_PCIEX2SLV 93
+#define SYSCRG_CLK_FLEXNOC_PCIEX8MST 94
+#define SYSCRG_CLK_FLEXNOC_PCIEX8SLV 95
+#define SYSCRG_CLK_FLEXNOC_GMACSYSSLV 96
+#define SYSCRG_CLK_GMAC_SRC 97
+#define SYSCRG_CLK_GMAC1_GTXCLK_TOP 98
+#define SYSCRG_CLK_GMAC1_PTP 99
+#define SYSCRG_CLK_HD_AUDIO_SYSTEM_CLOCK 100
+#define SYSCRG_CLK_HD_AUDIO_CLOCK_48 101
+#define SYSCRG_CLK_HD_AUDIO_BCLK_POST_OCC_IN 102
+#define SYSCRG_CLK_NNE_VIP_ACLK 103
+#define SYSCRG_CLK_NNE_VIP_HCLK 104
+#define SYSCRG_CLK_NNE_VIP_CLKCORE 105
+#define SYSCRG_CLK_GPU_ICG_EN 106
+#define SYSCRG_CLK_HD_AUDIO_ICG_EN 107
+#define SYSCRG_CLK_NNE_ICG_EN 108
+
+#define SYSCRG_CLK_END 109
+#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */
diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h
new file mode 100644
index 000000000000..3b7b92488e76
--- /dev/null
+++ b/include/dt-bindings/reset/starfive,jh8100-crg.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (c) 2022-2023 StarFive Technology Co., Ltd.
+ */
+
+#ifndef __DT_BINDINGS_RESET_STARFIVE_JH8100_H__
+#define __DT_BINDINGS_RESET_STARFIVE_JH8100_H__
+
+/*
+ * syscrg: assert0
+ */
+#define SYSCRG_RSTN_SYS_SYSCON 0
+#define SYSCRG_RSTN_CLK_MOD 1
+#define SYSCRG_RSTN_GPU 2
+#define SYSCRG_RSTN_GPU_SPU 3
+#define SYSCRG_RSTN_GPU_TVSENSOR 4
+#define SYSCRG_RSTN_PPU_OP_NORET_GPU_RESET 5
+#define SYSCRG_RSTN_NNE 6
+#define SYSCRG_RSTN_HD_AUDIO 7
+
+#define SYSCRG_RESET_NR_RESETS 8
+
+#endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */
--
2.34.1
Function names that consist of the 'jh71x0' naming convention are
renamed to use the 'starfive' wording.
Signed-off-by: Sia Jee Heng <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
---
drivers/clk/starfive/clk-starfive-common.c | 290 +++++-----
drivers/clk/starfive/clk-starfive-common.h | 68 +--
.../clk/starfive/clk-starfive-jh7100-audio.c | 125 ++---
drivers/clk/starfive/clk-starfive-jh7100.c | 501 ++++++++---------
.../clk/starfive/clk-starfive-jh7110-aon.c | 62 +--
.../clk/starfive/clk-starfive-jh7110-isp.c | 72 +--
.../clk/starfive/clk-starfive-jh7110-stg.c | 94 ++--
.../clk/starfive/clk-starfive-jh7110-sys.c | 517 +++++++++---------
.../clk/starfive/clk-starfive-jh7110-vout.c | 74 +--
drivers/clk/starfive/clk-starfive-jh7110.h | 2 +-
10 files changed, 908 insertions(+), 897 deletions(-)
diff --git a/drivers/clk/starfive/clk-starfive-common.c b/drivers/clk/starfive/clk-starfive-common.c
index a12490c97957..fd608286ca13 100644
--- a/drivers/clk/starfive/clk-starfive-common.c
+++ b/drivers/clk/starfive/clk-starfive-common.c
@@ -12,27 +12,27 @@
#include "clk-starfive-common.h"
-static struct jh71x0_clk *jh71x0_clk_from(struct clk_hw *hw)
+static struct starfive_clk *starfive_clk_from(struct clk_hw *hw)
{
- return container_of(hw, struct jh71x0_clk, hw);
+ return container_of(hw, struct starfive_clk, hw);
}
-static struct jh71x0_clk_priv *jh71x0_priv_from(struct jh71x0_clk *clk)
+static struct starfive_clk_priv *starfive_priv_from(struct starfive_clk *clk)
{
- return container_of(clk, struct jh71x0_clk_priv, reg[clk->idx]);
+ return container_of(clk, struct starfive_clk_priv, reg[clk->idx]);
}
-static u32 jh71x0_clk_reg_get(struct jh71x0_clk *clk)
+static u32 starfive_clk_reg_get(struct starfive_clk *clk)
{
- struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);
+ struct starfive_clk_priv *priv = starfive_priv_from(clk);
void __iomem *reg = priv->base + 4 * clk->idx;
return readl_relaxed(reg);
}
-static void jh71x0_clk_reg_rmw(struct jh71x0_clk *clk, u32 mask, u32 value)
+static void starfive_clk_reg_rmw(struct starfive_clk *clk, u32 mask, u32 value)
{
- struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);
+ struct starfive_clk_priv *priv = starfive_priv_from(clk);
void __iomem *reg = priv->base + 4 * clk->idx;
unsigned long flags;
@@ -42,41 +42,41 @@ static void jh71x0_clk_reg_rmw(struct jh71x0_clk *clk, u32 mask, u32 value)
spin_unlock_irqrestore(&priv->rmw_lock, flags);
}
-static int jh71x0_clk_enable(struct clk_hw *hw)
+static int starfive_clk_enable(struct clk_hw *hw)
{
- struct jh71x0_clk *clk = jh71x0_clk_from(hw);
+ struct starfive_clk *clk = starfive_clk_from(hw);
- jh71x0_clk_reg_rmw(clk, JH71X0_CLK_ENABLE, JH71X0_CLK_ENABLE);
+ starfive_clk_reg_rmw(clk, STARFIVE_CLK_ENABLE, STARFIVE_CLK_ENABLE);
return 0;
}
-static void jh71x0_clk_disable(struct clk_hw *hw)
+static void starfive_clk_disable(struct clk_hw *hw)
{
- struct jh71x0_clk *clk = jh71x0_clk_from(hw);
+ struct starfive_clk *clk = starfive_clk_from(hw);
- jh71x0_clk_reg_rmw(clk, JH71X0_CLK_ENABLE, 0);
+ starfive_clk_reg_rmw(clk, STARFIVE_CLK_ENABLE, 0);
}
-static int jh71x0_clk_is_enabled(struct clk_hw *hw)
+static int starfive_clk_is_enabled(struct clk_hw *hw)
{
- struct jh71x0_clk *clk = jh71x0_clk_from(hw);
+ struct starfive_clk *clk = starfive_clk_from(hw);
- return !!(jh71x0_clk_reg_get(clk) & JH71X0_CLK_ENABLE);
+ return !!(starfive_clk_reg_get(clk) & STARFIVE_CLK_ENABLE);
}
-static unsigned long jh71x0_clk_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
+static unsigned long starfive_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
{
- struct jh71x0_clk *clk = jh71x0_clk_from(hw);
- u32 div = jh71x0_clk_reg_get(clk) & JH71X0_CLK_DIV_MASK;
+ struct starfive_clk *clk = starfive_clk_from(hw);
+ u32 div = starfive_clk_reg_get(clk) & STARFIVE_CLK_DIV_MASK;
return div ? parent_rate / div : 0;
}
-static int jh71x0_clk_determine_rate(struct clk_hw *hw,
- struct clk_rate_request *req)
+static int starfive_clk_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
{
- struct jh71x0_clk *clk = jh71x0_clk_from(hw);
+ struct starfive_clk *clk = starfive_clk_from(hw);
unsigned long parent = req->best_parent_rate;
unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
unsigned long div = min_t(unsigned long, DIV_ROUND_UP(parent, rate), clk->max_div);
@@ -102,226 +102,226 @@ static int jh71x0_clk_determine_rate(struct clk_hw *hw,
return 0;
}
-static int jh71x0_clk_set_rate(struct clk_hw *hw,
- unsigned long rate,
- unsigned long parent_rate)
+static int starfive_clk_set_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long parent_rate)
{
- struct jh71x0_clk *clk = jh71x0_clk_from(hw);
+ struct starfive_clk *clk = starfive_clk_from(hw);
unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate),
1UL, (unsigned long)clk->max_div);
- jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, div);
+ starfive_clk_reg_rmw(clk, STARFIVE_CLK_DIV_MASK, div);
return 0;
}
-static unsigned long jh71x0_clk_frac_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
+static unsigned long starfive_clk_frac_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
{
- struct jh71x0_clk *clk = jh71x0_clk_from(hw);
- u32 reg = jh71x0_clk_reg_get(clk);
- unsigned long div100 = 100 * (reg & JH71X0_CLK_INT_MASK) +
- ((reg & JH71X0_CLK_FRAC_MASK) >> JH71X0_CLK_FRAC_SHIFT);
+ struct starfive_clk *clk = starfive_clk_from(hw);
+ u32 reg = starfive_clk_reg_get(clk);
+ unsigned long div100 = 100 * (reg & STARFIVE_CLK_INT_MASK) +
+ ((reg & STARFIVE_CLK_FRAC_MASK) >> STARFIVE_CLK_FRAC_SHIFT);
- return (div100 >= JH71X0_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0;
+ return (div100 >= STARFIVE_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0;
}
-static int jh71x0_clk_frac_determine_rate(struct clk_hw *hw,
- struct clk_rate_request *req)
+static int starfive_clk_frac_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
{
unsigned long parent100 = 100 * req->best_parent_rate;
unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
unsigned long div100 = clamp(DIV_ROUND_CLOSEST(parent100, rate),
- JH71X0_CLK_FRAC_MIN, JH71X0_CLK_FRAC_MAX);
+ STARFIVE_CLK_FRAC_MIN, STARFIVE_CLK_FRAC_MAX);
unsigned long result = parent100 / div100;
- /* clamp the result as in jh71x0_clk_determine_rate() above */
- if (result > req->max_rate && div100 < JH71X0_CLK_FRAC_MAX)
+ /* clamp the result as in starfive_clk_determine_rate() above */
+ if (result > req->max_rate && div100 < STARFIVE_CLK_FRAC_MAX)
result = parent100 / (div100 + 1);
- if (result < req->min_rate && div100 > JH71X0_CLK_FRAC_MIN)
+ if (result < req->min_rate && div100 > STARFIVE_CLK_FRAC_MIN)
result = parent100 / (div100 - 1);
req->rate = result;
return 0;
}
-static int jh71x0_clk_frac_set_rate(struct clk_hw *hw,
- unsigned long rate,
- unsigned long parent_rate)
+static int starfive_clk_frac_set_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long parent_rate)
{
- struct jh71x0_clk *clk = jh71x0_clk_from(hw);
+ struct starfive_clk *clk = starfive_clk_from(hw);
unsigned long div100 = clamp(DIV_ROUND_CLOSEST(100 * parent_rate, rate),
- JH71X0_CLK_FRAC_MIN, JH71X0_CLK_FRAC_MAX);
- u32 value = ((div100 % 100) << JH71X0_CLK_FRAC_SHIFT) | (div100 / 100);
+ STARFIVE_CLK_FRAC_MIN, STARFIVE_CLK_FRAC_MAX);
+ u32 value = ((div100 % 100) << STARFIVE_CLK_FRAC_SHIFT) | (div100 / 100);
- jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, value);
+ starfive_clk_reg_rmw(clk, STARFIVE_CLK_DIV_MASK, value);
return 0;
}
-static u8 jh71x0_clk_get_parent(struct clk_hw *hw)
+static u8 starfive_clk_get_parent(struct clk_hw *hw)
{
- struct jh71x0_clk *clk = jh71x0_clk_from(hw);
- u32 value = jh71x0_clk_reg_get(clk);
+ struct starfive_clk *clk = starfive_clk_from(hw);
+ u32 value = starfive_clk_reg_get(clk);
- return (value & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT;
+ return (value & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT;
}
-static int jh71x0_clk_set_parent(struct clk_hw *hw, u8 index)
+static int starfive_clk_set_parent(struct clk_hw *hw, u8 index)
{
- struct jh71x0_clk *clk = jh71x0_clk_from(hw);
- u32 value = (u32)index << JH71X0_CLK_MUX_SHIFT;
+ struct starfive_clk *clk = starfive_clk_from(hw);
+ u32 value = (u32)index << STARFIVE_CLK_MUX_SHIFT;
- jh71x0_clk_reg_rmw(clk, JH71X0_CLK_MUX_MASK, value);
+ starfive_clk_reg_rmw(clk, STARFIVE_CLK_MUX_MASK, value);
return 0;
}
-static int jh71x0_clk_get_phase(struct clk_hw *hw)
+static int starfive_clk_get_phase(struct clk_hw *hw)
{
- struct jh71x0_clk *clk = jh71x0_clk_from(hw);
- u32 value = jh71x0_clk_reg_get(clk);
+ struct starfive_clk *clk = starfive_clk_from(hw);
+ u32 value = starfive_clk_reg_get(clk);
- return (value & JH71X0_CLK_INVERT) ? 180 : 0;
+ return (value & STARFIVE_CLK_INVERT) ? 180 : 0;
}
-static int jh71x0_clk_set_phase(struct clk_hw *hw, int degrees)
+static int starfive_clk_set_phase(struct clk_hw *hw, int degrees)
{
- struct jh71x0_clk *clk = jh71x0_clk_from(hw);
+ struct starfive_clk *clk = starfive_clk_from(hw);
u32 value;
if (degrees == 0)
value = 0;
else if (degrees == 180)
- value = JH71X0_CLK_INVERT;
+ value = STARFIVE_CLK_INVERT;
else
return -EINVAL;
- jh71x0_clk_reg_rmw(clk, JH71X0_CLK_INVERT, value);
+ starfive_clk_reg_rmw(clk, STARFIVE_CLK_INVERT, value);
return 0;
}
#ifdef CONFIG_DEBUG_FS
-static void jh71x0_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
+static void starfive_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
{
- static const struct debugfs_reg32 jh71x0_clk_reg = {
+ static const struct debugfs_reg32 starfive_clk_reg = {
.name = "CTRL",
.offset = 0,
};
- struct jh71x0_clk *clk = jh71x0_clk_from(hw);
- struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);
+ struct starfive_clk *clk = starfive_clk_from(hw);
+ struct starfive_clk_priv *priv = starfive_priv_from(clk);
struct debugfs_regset32 *regset;
regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);
if (!regset)
return;
- regset->regs = &jh71x0_clk_reg;
+ regset->regs = &starfive_clk_reg;
regset->nregs = 1;
regset->base = priv->base + 4 * clk->idx;
debugfs_create_regset32("registers", 0400, dentry, regset);
}
#else
-#define jh71x0_clk_debug_init NULL
+#define starfive_clk_debug_init NULL
#endif
-static const struct clk_ops jh71x0_clk_gate_ops = {
- .enable = jh71x0_clk_enable,
- .disable = jh71x0_clk_disable,
- .is_enabled = jh71x0_clk_is_enabled,
- .debug_init = jh71x0_clk_debug_init,
+static const struct clk_ops starfive_clk_gate_ops = {
+ .enable = starfive_clk_enable,
+ .disable = starfive_clk_disable,
+ .is_enabled = starfive_clk_is_enabled,
+ .debug_init = starfive_clk_debug_init,
};
-static const struct clk_ops jh71x0_clk_div_ops = {
- .recalc_rate = jh71x0_clk_recalc_rate,
- .determine_rate = jh71x0_clk_determine_rate,
- .set_rate = jh71x0_clk_set_rate,
- .debug_init = jh71x0_clk_debug_init,
+static const struct clk_ops starfive_clk_div_ops = {
+ .recalc_rate = starfive_clk_recalc_rate,
+ .determine_rate = starfive_clk_determine_rate,
+ .set_rate = starfive_clk_set_rate,
+ .debug_init = starfive_clk_debug_init,
};
-static const struct clk_ops jh71x0_clk_fdiv_ops = {
- .recalc_rate = jh71x0_clk_frac_recalc_rate,
- .determine_rate = jh71x0_clk_frac_determine_rate,
- .set_rate = jh71x0_clk_frac_set_rate,
- .debug_init = jh71x0_clk_debug_init,
+static const struct clk_ops starfive_clk_fdiv_ops = {
+ .recalc_rate = starfive_clk_frac_recalc_rate,
+ .determine_rate = starfive_clk_frac_determine_rate,
+ .set_rate = starfive_clk_frac_set_rate,
+ .debug_init = starfive_clk_debug_init,
};
-static const struct clk_ops jh71x0_clk_gdiv_ops = {
- .enable = jh71x0_clk_enable,
- .disable = jh71x0_clk_disable,
- .is_enabled = jh71x0_clk_is_enabled,
- .recalc_rate = jh71x0_clk_recalc_rate,
- .determine_rate = jh71x0_clk_determine_rate,
- .set_rate = jh71x0_clk_set_rate,
- .debug_init = jh71x0_clk_debug_init,
+static const struct clk_ops starfive_clk_gdiv_ops = {
+ .enable = starfive_clk_enable,
+ .disable = starfive_clk_disable,
+ .is_enabled = starfive_clk_is_enabled,
+ .recalc_rate = starfive_clk_recalc_rate,
+ .determine_rate = starfive_clk_determine_rate,
+ .set_rate = starfive_clk_set_rate,
+ .debug_init = starfive_clk_debug_init,
};
-static const struct clk_ops jh71x0_clk_mux_ops = {
+static const struct clk_ops starfive_clk_mux_ops = {
.determine_rate = __clk_mux_determine_rate,
- .set_parent = jh71x0_clk_set_parent,
- .get_parent = jh71x0_clk_get_parent,
- .debug_init = jh71x0_clk_debug_init,
+ .set_parent = starfive_clk_set_parent,
+ .get_parent = starfive_clk_get_parent,
+ .debug_init = starfive_clk_debug_init,
};
-static const struct clk_ops jh71x0_clk_gmux_ops = {
- .enable = jh71x0_clk_enable,
- .disable = jh71x0_clk_disable,
- .is_enabled = jh71x0_clk_is_enabled,
+static const struct clk_ops starfive_clk_gmux_ops = {
+ .enable = starfive_clk_enable,
+ .disable = starfive_clk_disable,
+ .is_enabled = starfive_clk_is_enabled,
.determine_rate = __clk_mux_determine_rate,
- .set_parent = jh71x0_clk_set_parent,
- .get_parent = jh71x0_clk_get_parent,
- .debug_init = jh71x0_clk_debug_init,
+ .set_parent = starfive_clk_set_parent,
+ .get_parent = starfive_clk_get_parent,
+ .debug_init = starfive_clk_debug_init,
};
-static const struct clk_ops jh71x0_clk_mdiv_ops = {
- .recalc_rate = jh71x0_clk_recalc_rate,
- .determine_rate = jh71x0_clk_determine_rate,
- .get_parent = jh71x0_clk_get_parent,
- .set_parent = jh71x0_clk_set_parent,
- .set_rate = jh71x0_clk_set_rate,
- .debug_init = jh71x0_clk_debug_init,
+static const struct clk_ops starfive_clk_mdiv_ops = {
+ .recalc_rate = starfive_clk_recalc_rate,
+ .determine_rate = starfive_clk_determine_rate,
+ .get_parent = starfive_clk_get_parent,
+ .set_parent = starfive_clk_set_parent,
+ .set_rate = starfive_clk_set_rate,
+ .debug_init = starfive_clk_debug_init,
};
-static const struct clk_ops jh71x0_clk_gmd_ops = {
- .enable = jh71x0_clk_enable,
- .disable = jh71x0_clk_disable,
- .is_enabled = jh71x0_clk_is_enabled,
- .recalc_rate = jh71x0_clk_recalc_rate,
- .determine_rate = jh71x0_clk_determine_rate,
- .get_parent = jh71x0_clk_get_parent,
- .set_parent = jh71x0_clk_set_parent,
- .set_rate = jh71x0_clk_set_rate,
- .debug_init = jh71x0_clk_debug_init,
+static const struct clk_ops starfive_clk_gmd_ops = {
+ .enable = starfive_clk_enable,
+ .disable = starfive_clk_disable,
+ .is_enabled = starfive_clk_is_enabled,
+ .recalc_rate = starfive_clk_recalc_rate,
+ .determine_rate = starfive_clk_determine_rate,
+ .get_parent = starfive_clk_get_parent,
+ .set_parent = starfive_clk_set_parent,
+ .set_rate = starfive_clk_set_rate,
+ .debug_init = starfive_clk_debug_init,
};
-static const struct clk_ops jh71x0_clk_inv_ops = {
- .get_phase = jh71x0_clk_get_phase,
- .set_phase = jh71x0_clk_set_phase,
- .debug_init = jh71x0_clk_debug_init,
+static const struct clk_ops starfive_clk_inv_ops = {
+ .get_phase = starfive_clk_get_phase,
+ .set_phase = starfive_clk_set_phase,
+ .debug_init = starfive_clk_debug_init,
};
-const struct clk_ops *starfive_jh71x0_clk_ops(u32 max)
+const struct clk_ops *starfive_clk_ops(u32 max)
{
- if (max & JH71X0_CLK_DIV_MASK) {
- if (max & JH71X0_CLK_MUX_MASK) {
- if (max & JH71X0_CLK_ENABLE)
- return &jh71x0_clk_gmd_ops;
- return &jh71x0_clk_mdiv_ops;
+ if (max & STARFIVE_CLK_DIV_MASK) {
+ if (max & STARFIVE_CLK_MUX_MASK) {
+ if (max & STARFIVE_CLK_ENABLE)
+ return &starfive_clk_gmd_ops;
+ return &starfive_clk_mdiv_ops;
}
- if (max & JH71X0_CLK_ENABLE)
- return &jh71x0_clk_gdiv_ops;
- if (max == JH71X0_CLK_FRAC_MAX)
- return &jh71x0_clk_fdiv_ops;
- return &jh71x0_clk_div_ops;
+ if (max & STARFIVE_CLK_ENABLE)
+ return &starfive_clk_gdiv_ops;
+ if (max == STARFIVE_CLK_FRAC_MAX)
+ return &starfive_clk_fdiv_ops;
+ return &starfive_clk_div_ops;
}
- if (max & JH71X0_CLK_MUX_MASK) {
- if (max & JH71X0_CLK_ENABLE)
- return &jh71x0_clk_gmux_ops;
- return &jh71x0_clk_mux_ops;
+ if (max & STARFIVE_CLK_MUX_MASK) {
+ if (max & STARFIVE_CLK_ENABLE)
+ return &starfive_clk_gmux_ops;
+ return &starfive_clk_mux_ops;
}
- if (max & JH71X0_CLK_ENABLE)
- return &jh71x0_clk_gate_ops;
+ if (max & STARFIVE_CLK_ENABLE)
+ return &starfive_clk_gate_ops;
- return &jh71x0_clk_inv_ops;
+ return &starfive_clk_inv_ops;
}
-EXPORT_SYMBOL_GPL(starfive_jh71x0_clk_ops);
+EXPORT_SYMBOL_GPL(starfive_clk_ops);
diff --git a/drivers/clk/starfive/clk-starfive-common.h b/drivers/clk/starfive/clk-starfive-common.h
index 1f32f7024e9f..fed45311360c 100644
--- a/drivers/clk/starfive/clk-starfive-common.h
+++ b/drivers/clk/starfive/clk-starfive-common.h
@@ -8,36 +8,36 @@
#include <linux/spinlock.h>
/* register fields */
-#define JH71X0_CLK_ENABLE BIT(31)
-#define JH71X0_CLK_INVERT BIT(30)
-#define JH71X0_CLK_MUX_MASK GENMASK(27, 24)
-#define JH71X0_CLK_MUX_SHIFT 24
-#define JH71X0_CLK_DIV_MASK GENMASK(23, 0)
-#define JH71X0_CLK_FRAC_MASK GENMASK(15, 8)
-#define JH71X0_CLK_FRAC_SHIFT 8
-#define JH71X0_CLK_INT_MASK GENMASK(7, 0)
+#define STARFIVE_CLK_ENABLE BIT(31)
+#define STARFIVE_CLK_INVERT BIT(30)
+#define STARFIVE_CLK_MUX_MASK GENMASK(27, 24)
+#define STARFIVE_CLK_MUX_SHIFT 24
+#define STARFIVE_CLK_DIV_MASK GENMASK(23, 0)
+#define STARFIVE_CLK_FRAC_MASK GENMASK(15, 8)
+#define STARFIVE_CLK_FRAC_SHIFT 8
+#define STARFIVE_CLK_INT_MASK GENMASK(7, 0)
/* fractional divider min/max */
-#define JH71X0_CLK_FRAC_MIN 100UL
-#define JH71X0_CLK_FRAC_MAX 25599UL
+#define STARFIVE_CLK_FRAC_MIN 100UL
+#define STARFIVE_CLK_FRAC_MAX 25599UL
/* clock data */
-struct jh71x0_clk_data {
+struct starfive_clk_data {
const char *name;
unsigned long flags;
u32 max;
u8 parents[4];
};
-#define JH71X0_GATE(_idx, _name, _flags, _parent) \
+#define STARFIVE_GATE(_idx, _name, _flags, _parent) \
[_idx] = { \
.name = _name, \
.flags = CLK_SET_RATE_PARENT | (_flags), \
- .max = JH71X0_CLK_ENABLE, \
+ .max = STARFIVE_CLK_ENABLE, \
.parents = { [0] = _parent }, \
}
-#define JH71X0__DIV(_idx, _name, _max, _parent) \
+#define STARFIVE__DIV(_idx, _name, _max, _parent) \
[_idx] = { \
.name = _name, \
.flags = 0, \
@@ -45,79 +45,79 @@ struct jh71x0_clk_data {
.parents = { [0] = _parent }, \
}
-#define JH71X0_GDIV(_idx, _name, _flags, _max, _parent) \
+#define STARFIVE_GDIV(_idx, _name, _flags, _max, _parent) \
[_idx] = { \
.name = _name, \
.flags = _flags, \
- .max = JH71X0_CLK_ENABLE | (_max), \
+ .max = STARFIVE_CLK_ENABLE | (_max), \
.parents = { [0] = _parent }, \
}
-#define JH71X0_FDIV(_idx, _name, _parent) \
+#define STARFIVE_FDIV(_idx, _name, _parent) \
[_idx] = { \
.name = _name, \
.flags = 0, \
- .max = JH71X0_CLK_FRAC_MAX, \
+ .max = STARFIVE_CLK_FRAC_MAX, \
.parents = { [0] = _parent }, \
}
-#define JH71X0__MUX(_idx, _name, _nparents, ...) \
+#define STARFIVE__MUX(_idx, _name, _nparents, ...) \
[_idx] = { \
.name = _name, \
.flags = 0, \
- .max = ((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT, \
+ .max = ((_nparents) - 1) << STARFIVE_CLK_MUX_SHIFT, \
.parents = { __VA_ARGS__ }, \
}
-#define JH71X0_GMUX(_idx, _name, _flags, _nparents, ...) \
+#define STARFIVE_GMUX(_idx, _name, _flags, _nparents, ...) \
[_idx] = { \
.name = _name, \
.flags = _flags, \
- .max = JH71X0_CLK_ENABLE | \
- (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT), \
+ .max = STARFIVE_CLK_ENABLE | \
+ (((_nparents) - 1) << STARFIVE_CLK_MUX_SHIFT), \
.parents = { __VA_ARGS__ }, \
}
-#define JH71X0_MDIV(_idx, _name, _max, _nparents, ...) \
+#define STARFIVE_MDIV(_idx, _name, _max, _nparents, ...) \
[_idx] = { \
.name = _name, \
.flags = 0, \
- .max = (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT) | (_max), \
+ .max = (((_nparents) - 1) << STARFIVE_CLK_MUX_SHIFT) | (_max), \
.parents = { __VA_ARGS__ }, \
}
-#define JH71X0__GMD(_idx, _name, _flags, _max, _nparents, ...) \
+#define STARFIVE__GMD(_idx, _name, _flags, _max, _nparents, ...) \
[_idx] = { \
.name = _name, \
.flags = _flags, \
- .max = JH71X0_CLK_ENABLE | \
- (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT) | (_max), \
+ .max = STARFIVE_CLK_ENABLE | \
+ (((_nparents) - 1) << STARFIVE_CLK_MUX_SHIFT) | (_max), \
.parents = { __VA_ARGS__ }, \
}
-#define JH71X0__INV(_idx, _name, _parent) \
+#define STARFIVE__INV(_idx, _name, _parent) \
[_idx] = { \
.name = _name, \
.flags = CLK_SET_RATE_PARENT, \
- .max = JH71X0_CLK_INVERT, \
+ .max = STARFIVE_CLK_INVERT, \
.parents = { [0] = _parent }, \
}
-struct jh71x0_clk {
+struct starfive_clk {
struct clk_hw hw;
unsigned int idx;
unsigned int max_div;
};
-struct jh71x0_clk_priv {
+struct starfive_clk_priv {
/* protect clk enable and set rate/parent from happening at the same time */
spinlock_t rmw_lock;
struct device *dev;
void __iomem *base;
struct clk_hw *pll[3];
- struct jh71x0_clk reg[];
+ struct starfive_clk reg[];
};
-const struct clk_ops *starfive_jh71x0_clk_ops(u32 max);
+const struct clk_ops *starfive_clk_ops(u32 max);
#endif
diff --git a/drivers/clk/starfive/clk-starfive-jh7100-audio.c b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
index dc4c278606d7..dfe2befddce5 100644
--- a/drivers/clk/starfive/clk-starfive-jh7100-audio.c
+++ b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
@@ -27,66 +27,68 @@
#define JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD (JH7100_AUDCLK_END + 6)
#define JH7100_AUDCLK_VAD_INTMEM (JH7100_AUDCLK_END + 7)
-static const struct jh71x0_clk_data jh7100_audclk_data[] = {
- JH71X0__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,
- JH7100_AUDCLK_AUDIO_SRC,
- JH7100_AUDCLK_AUDIO_12288),
- JH71X0__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,
- JH7100_AUDCLK_AUDIO_SRC,
- JH7100_AUDCLK_AUDIO_12288),
- JH71X0_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),
- JH71X0_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,
- JH7100_AUDCLK_ADC_MCLK,
- JH7100_AUDCLK_I2SADC_BCLK_IOPAD),
- JH71X0__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),
- JH71X0_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,
- JH7100_AUDCLK_I2SADC_BCLK_N,
- JH7100_AUDCLK_I2SADC_LRCLK_IOPAD,
- JH7100_AUDCLK_I2SADC_BCLK),
- JH71X0_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),
- JH71X0__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,
- JH7100_AUDCLK_AUDIO_SRC,
- JH7100_AUDCLK_AUDIO_12288),
- JH71X0_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),
- JH71X0__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,
- JH7100_AUDCLK_AUDIO_SRC,
- JH7100_AUDCLK_AUDIO_12288),
- JH71X0_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),
- JH71X0_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
- JH71X0__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,
- JH7100_AUDCLK_AUDIO_SRC,
- JH7100_AUDCLK_AUDIO_12288),
- JH71X0_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
- JH71X0_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,
- JH7100_AUDCLK_DAC_MCLK,
- JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
- JH71X0__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),
- JH71X0_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,
- JH7100_AUDCLK_I2S1_MCLK,
- JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
- JH71X0_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),
- JH71X0_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,
- JH7100_AUDCLK_I2S1_MCLK,
- JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
- JH71X0__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),
- JH71X0_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,
- JH7100_AUDCLK_I2S1_BCLK_N,
- JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD),
- JH71X0_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),
- JH71X0__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),
- JH71X0_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),
- JH71X0_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),
- JH71X0_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),
- JH71X0_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),
- JH71X0__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
- JH71X0__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
- JH7100_AUDCLK_VAD_INTMEM,
- JH7100_AUDCLK_AUDIO_12288),
+static const struct starfive_clk_data jh7100_audclk_data[] = {
+ STARFIVE__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,
+ JH7100_AUDCLK_AUDIO_SRC,
+ JH7100_AUDCLK_AUDIO_12288),
+ STARFIVE__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,
+ JH7100_AUDCLK_AUDIO_SRC,
+ JH7100_AUDCLK_AUDIO_12288),
+ STARFIVE_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ STARFIVE_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,
+ JH7100_AUDCLK_ADC_MCLK,
+ JH7100_AUDCLK_I2SADC_BCLK_IOPAD),
+ STARFIVE__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),
+ STARFIVE_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,
+ JH7100_AUDCLK_I2SADC_BCLK_N,
+ JH7100_AUDCLK_I2SADC_LRCLK_IOPAD,
+ JH7100_AUDCLK_I2SADC_BCLK),
+ STARFIVE_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ STARFIVE__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,
+ JH7100_AUDCLK_AUDIO_SRC,
+ JH7100_AUDCLK_AUDIO_12288),
+ STARFIVE_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ STARFIVE__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,
+ JH7100_AUDCLK_AUDIO_SRC,
+ JH7100_AUDCLK_AUDIO_12288),
+ STARFIVE_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ STARFIVE_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ STARFIVE__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,
+ JH7100_AUDCLK_AUDIO_SRC,
+ JH7100_AUDCLK_AUDIO_12288),
+ STARFIVE_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ STARFIVE_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,
+ JH7100_AUDCLK_DAC_MCLK,
+ JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
+ STARFIVE__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),
+ STARFIVE_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,
+ JH7100_AUDCLK_I2S1_MCLK,
+ JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
+ STARFIVE_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ STARFIVE_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,
+ JH7100_AUDCLK_I2S1_MCLK,
+ JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
+ STARFIVE__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),
+ STARFIVE_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,
+ JH7100_AUDCLK_I2S1_BCLK_N,
+ JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD),
+ STARFIVE_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ STARFIVE__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),
+ STARFIVE_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),
+ STARFIVE_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),
+ STARFIVE_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4,
+ JH7100_AUDCLK_USB_APB),
+ STARFIVE_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3,
+ JH7100_AUDCLK_USB_APB),
+ STARFIVE__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
+ STARFIVE__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
+ JH7100_AUDCLK_VAD_INTMEM,
+ JH7100_AUDCLK_AUDIO_12288),
};
static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *data)
{
- struct jh71x0_clk_priv *priv = data;
+ struct starfive_clk_priv *priv = data;
unsigned int idx = clkspec->args[0];
if (idx < JH7100_AUDCLK_END)
@@ -97,7 +99,7 @@ static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *d
static int jh7100_audclk_probe(struct platform_device *pdev)
{
- struct jh71x0_clk_priv *priv;
+ struct starfive_clk_priv *priv;
unsigned int idx;
int ret;
@@ -116,12 +118,13 @@ static int jh7100_audclk_probe(struct platform_device *pdev)
struct clk_parent_data parents[4] = {};
struct clk_init_data init = {
.name = jh7100_audclk_data[idx].name,
- .ops = starfive_jh71x0_clk_ops(max),
+ .ops = starfive_clk_ops(max),
.parent_data = parents,
- .num_parents = ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
+ .num_parents = ((max & STARFIVE_CLK_MUX_MASK)
+ >> STARFIVE_CLK_MUX_SHIFT) + 1,
.flags = jh7100_audclk_data[idx].flags,
};
- struct jh71x0_clk *clk = &priv->reg[idx];
+ struct starfive_clk *clk = &priv->reg[idx];
unsigned int i;
for (i = 0; i < init.num_parents; i++) {
@@ -139,7 +142,7 @@ static int jh7100_audclk_probe(struct platform_device *pdev)
clk->hw.init = &init;
clk->idx = idx;
- clk->max_div = max & JH71X0_CLK_DIV_MASK;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
ret = devm_clk_hw_register(priv->dev, &clk->hw);
if (ret)
diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c
index 6bb6a6af9f28..946a437f534b 100644
--- a/drivers/clk/starfive/clk-starfive-jh7100.c
+++ b/drivers/clk/starfive/clk-starfive-jh7100.c
@@ -23,253 +23,257 @@
#define JH7100_CLK_GMAC_RMII_REF (JH7100_CLK_END + 2)
#define JH7100_CLK_GMAC_GR_MII_RX (JH7100_CLK_END + 3)
-static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {
- JH71X0__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
- JH7100_CLK_OSC_SYS,
- JH7100_CLK_PLL0_OUT,
- JH7100_CLK_PLL1_OUT,
- JH7100_CLK_PLL2_OUT),
- JH71X0__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3,
- JH7100_CLK_OSC_SYS,
- JH7100_CLK_PLL1_OUT,
- JH7100_CLK_PLL2_OUT),
- JH71X0__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4,
- JH7100_CLK_OSC_SYS,
- JH7100_CLK_PLL0_OUT,
- JH7100_CLK_PLL1_OUT,
- JH7100_CLK_PLL2_OUT),
- JH71X0__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3,
- JH7100_CLK_OSC_SYS,
- JH7100_CLK_PLL0_OUT,
- JH7100_CLK_PLL2_OUT),
- JH71X0__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2,
- JH7100_CLK_OSC_SYS,
- JH7100_CLK_PLL0_OUT),
- JH71X0__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2,
- JH7100_CLK_OSC_SYS,
- JH7100_CLK_PLL2_OUT),
- JH71X0__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3,
- JH7100_CLK_OSC_SYS,
- JH7100_CLK_PLL1_OUT,
- JH7100_CLK_PLL2_OUT),
- JH71X0__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3,
- JH7100_CLK_OSC_AUD,
- JH7100_CLK_PLL0_OUT,
- JH7100_CLK_PLL2_OUT),
- JH71X0_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),
- JH71X0__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3,
- JH7100_CLK_OSC_SYS,
- JH7100_CLK_PLL1_OUT,
- JH7100_CLK_PLL2_OUT),
- JH71X0__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3,
- JH7100_CLK_OSC_SYS,
- JH7100_CLK_PLL0_OUT,
- JH7100_CLK_PLL1_OUT),
- JH71X0__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3,
- JH7100_CLK_OSC_AUD,
- JH7100_CLK_PLL0_OUT,
- JH7100_CLK_PLL2_OUT),
- JH71X0__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT),
- JH71X0__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT),
- JH71X0__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT),
- JH71X0__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT),
- JH71X0_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),
- JH71X0_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),
- JH71X0_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),
- JH71X0__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2,
- JH7100_CLK_OSC_SYS,
- JH7100_CLK_OSC_AUD),
- JH71X0__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
- JH71X0__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE),
- JH71X0__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
- JH71X0__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS),
- JH71X0__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS),
- JH71X0_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
- JH71X0_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
- JH71X0_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE),
- JH71X0_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE),
- JH71X0_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI),
- JH71X0_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL, JH7100_CLK_OSC_SYS),
- JH71X0_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI),
- JH71X0_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI),
- JH71X0_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS),
- JH71X0__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT),
- JH71X0_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS),
- JH71X0_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS),
- JH71X0_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS),
- JH71X0_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV),
- JH71X0__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT),
- JH71X0_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC),
- JH71X0__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
- JH71X0__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus", 8, JH7100_CLK_VCDECBUS_SRC),
- JH71X0_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi", 0, JH7100_CLK_VDEC_BUS),
- JH71X0_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk", 0, JH7100_CLK_VDEC_BUS),
- JH71X0_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
- JH71X0_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
- JH71X0_GATE(JH7100_CLK_VDEC_APB, "vdec_apb", 0, JH7100_CLK_APB1_BUS),
- JH71X0_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
- JH71X0_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
- JH71X0_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", 0, JH7100_CLK_APB1_BUS),
- JH71X0_GDIV(JH7100_CLK_GC300_2X, "gc300_2x", 0, 8, JH7100_CLK_CDECHIFI4_ROOT),
- JH71X0_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb", 0, JH7100_CLK_AHB_BUS),
- JH71X0__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus", 8, JH7100_CLK_VCDECBUS_SRC),
- JH71X0_GATE(JH7100_CLK_GC300_AXI, "gc300_axi", 0, JH7100_CLK_JPCGC300_AXIBUS),
- JH71X0_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk", 0, JH7100_CLK_JPCGC300_AXIBUS),
- JH71X0__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC),
- JH71X0_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS),
- JH71X0_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS),
- JH71X0_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
- JH71X0_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
- JH71X0_GATE(JH7100_CLK_VENC_APB, "venc_apb", 0, JH7100_CLK_APB1_BUS),
- JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_PLL1_OUT),
- JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2,
- JH7100_CLK_DDRPLL_DIV2),
- JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2,
- JH7100_CLK_DDRPLL_DIV4),
- JH71X0_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_OSC_SYS),
- JH71X0_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4,
- JH7100_CLK_DDROSC_DIV2,
- JH7100_CLK_DDRPLL_DIV2,
- JH7100_CLK_DDRPLL_DIV4,
- JH7100_CLK_DDRPLL_DIV8),
- JH71X0_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4,
- JH7100_CLK_DDROSC_DIV2,
- JH7100_CLK_DDRPLL_DIV2,
- JH7100_CLK_DDRPLL_DIV4,
- JH7100_CLK_DDRPLL_DIV8),
- JH71X0_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb", 0, JH7100_CLK_APB1_BUS),
- JH71X0__DIV(JH7100_CLK_NOC_ROB, "noc_rob", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
- JH71X0__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT),
- JH71X0_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS),
- JH71X0__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT),
- JH71X0__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2,
- JH7100_CLK_CPU_AXI,
- JH7100_CLK_NNEBUS_SRC1),
- JH71X0_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS),
- JH71X0_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi", 0, JH7100_CLK_NNE_BUS),
- JH71X0_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi", 0, JH7100_CLK_NNE_BUS),
- JH71X0_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi", CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS),
- JH71X0__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
- JH71X0__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree", 8, JH7100_CLK_HIFI4_SRC),
- JH71X0_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core", 0, JH7100_CLK_HIFI4_COREFREE),
- JH71X0__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus", 8, JH7100_CLK_HIFI4_COREFREE),
- JH71X0_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi", 0, JH7100_CLK_HIFI4_BUS),
- JH71X0_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi", 0, JH7100_CLK_HIFI4_BUS),
- JH71X0__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
- JH71X0_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
- JH71X0_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
- JH71X0_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
- JH71X0__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
- JH71X0_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS),
- JH71X0_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS),
- JH71X0__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT),
- JH71X0_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),
- JH71X0_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32,
- JH7100_CLK_USBPHY_ROOTDIV),
- JH71X0__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
- JH7100_CLK_OSC_SYS,
- JH7100_CLK_USBPHY_PLLDIV25M),
- JH71X0_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT),
- JH71X0_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV),
- JH71X0_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD),
- JH71X0_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT),
- JH71X0__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus", 8, JH7100_CLK_VIN_SRC),
- JH71X0_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi", 0, JH7100_CLK_ISP0_BUS),
- JH71X0_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi", 0, JH7100_CLK_ISP0_BUS),
- JH71X0_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi", 0, JH7100_CLK_ISP0_BUS),
- JH71X0__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus", 8, JH7100_CLK_VIN_SRC),
- JH71X0_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi", 0, JH7100_CLK_ISP1_BUS),
- JH71X0_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi", 0, JH7100_CLK_ISP1_BUS),
- JH71X0__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC),
- JH71X0_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS),
- JH71X0_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS),
- JH71X0_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT),
- JH71X0__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT),
- JH71X0__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC),
- JH71X0_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS),
- JH71X0_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS),
- JH71X0_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS),
- JH71X0_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC),
- JH71X0__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT),
- JH71X0_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS),
- JH71X0_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC),
- JH71X0__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT),
- JH71X0_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS),
- JH71X0__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT),
- JH71X0_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV),
- JH71X0_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),
- JH71X0_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
- JH71X0_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
- JH71X0__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3,
- JH7100_CLK_GMAC_GTX,
- JH7100_CLK_GMAC_TX_INV,
- JH7100_CLK_GMAC_RMII_TX),
- JH71X0__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX),
- JH71X0__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2,
- JH7100_CLK_GMAC_GR_MII_RX,
- JH7100_CLK_GMAC_RMII_RX),
- JH71X0__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE),
- JH71X0_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF),
- JH71X0_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV),
- JH71X0_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS),
- JH71X0_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC),
- JH71X0_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS),
- JH71X0_GATE(JH7100_CLK_E24_AHB, "e24_ahb", 0, JH7100_CLK_AHB_BUS),
- JH71X0_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle", 0, JH7100_CLK_OSC_SYS),
- JH71X0_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", 0, JH7100_CLK_AHB_BUS),
- JH71X0_GATE(JH7100_CLK_QSPI_APB, "qspi_apb", 0, JH7100_CLK_APB1_BUS),
- JH71X0_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk", 0, 31, JH7100_CLK_PERH0_SRC),
- JH71X0_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", 0, JH7100_CLK_AHB_BUS),
- JH71X0_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB),
- JH71X0_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB),
- JH71X0_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB),
- JH71X0_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS),
- JH71X0_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS),
- JH71X0_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS),
- JH71X0_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC),
- JH71X0_GATE(JH7100_CLK_UART1_APB, "uart1_apb", 0, JH7100_CLK_APB1_BUS),
- JH71X0_GDIV(JH7100_CLK_UART1_CORE, "uart1_core", 0, 63, JH7100_CLK_PERH1_SRC),
- JH71X0_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", 0, JH7100_CLK_APB1_BUS),
- JH71X0_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 0, 63, JH7100_CLK_PERH1_SRC),
- JH71X0_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", 0, JH7100_CLK_APB1_BUS),
- JH71X0_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 0, 63, JH7100_CLK_PERH1_SRC),
- JH71X0_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", 0, JH7100_CLK_APB1_BUS),
- JH71X0_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 0, 63, JH7100_CLK_PERH1_SRC),
- JH71X0_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", 0, JH7100_CLK_APB1_BUS),
- JH71X0_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 0, 63, JH7100_CLK_PERH1_SRC),
- JH71X0_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", 0, JH7100_CLK_APB1_BUS),
- JH71X0_GATE(JH7100_CLK_UART2_APB, "uart2_apb", 0, JH7100_CLK_APB2_BUS),
- JH71X0_GDIV(JH7100_CLK_UART2_CORE, "uart2_core", 0, 63, JH7100_CLK_PERH0_SRC),
- JH71X0_GATE(JH7100_CLK_UART3_APB, "uart3_apb", 0, JH7100_CLK_APB2_BUS),
- JH71X0_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC),
- JH71X0_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", 0, JH7100_CLK_APB2_BUS),
- JH71X0_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 0, 63, JH7100_CLK_PERH0_SRC),
- JH71X0_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", 0, JH7100_CLK_APB2_BUS),
- JH71X0_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 0, 63, JH7100_CLK_PERH0_SRC),
- JH71X0_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", 0, JH7100_CLK_APB2_BUS),
- JH71X0_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 0, 63, JH7100_CLK_PERH0_SRC),
- JH71X0_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", 0, JH7100_CLK_APB2_BUS),
- JH71X0_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC),
- JH71X0_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS),
- JH71X0_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
- JH71X0_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
- JH71X0_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
- JH71X0_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
- JH71X0_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
- JH71X0_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
- JH71X0_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
- JH71X0_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
- JH71X0_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS),
- JH71X0_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS),
- JH71X0_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS),
- JH71X0_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS),
- JH71X0_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS),
- JH71X0_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS),
+static const struct starfive_clk_data jh7100_clk_data[] __initconst = {
+ STARFIVE__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
+ JH7100_CLK_OSC_SYS,
+ JH7100_CLK_PLL0_OUT,
+ JH7100_CLK_PLL1_OUT,
+ JH7100_CLK_PLL2_OUT),
+ STARFIVE__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3,
+ JH7100_CLK_OSC_SYS,
+ JH7100_CLK_PLL1_OUT,
+ JH7100_CLK_PLL2_OUT),
+ STARFIVE__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4,
+ JH7100_CLK_OSC_SYS,
+ JH7100_CLK_PLL0_OUT,
+ JH7100_CLK_PLL1_OUT,
+ JH7100_CLK_PLL2_OUT),
+ STARFIVE__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3,
+ JH7100_CLK_OSC_SYS,
+ JH7100_CLK_PLL0_OUT,
+ JH7100_CLK_PLL2_OUT),
+ STARFIVE__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2,
+ JH7100_CLK_OSC_SYS,
+ JH7100_CLK_PLL0_OUT),
+ STARFIVE__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2,
+ JH7100_CLK_OSC_SYS,
+ JH7100_CLK_PLL2_OUT),
+ STARFIVE__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3,
+ JH7100_CLK_OSC_SYS,
+ JH7100_CLK_PLL1_OUT,
+ JH7100_CLK_PLL2_OUT),
+ STARFIVE__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3,
+ JH7100_CLK_OSC_AUD,
+ JH7100_CLK_PLL0_OUT,
+ JH7100_CLK_PLL2_OUT),
+ STARFIVE_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),
+ STARFIVE__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3,
+ JH7100_CLK_OSC_SYS,
+ JH7100_CLK_PLL1_OUT,
+ JH7100_CLK_PLL2_OUT),
+ STARFIVE__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3,
+ JH7100_CLK_OSC_SYS,
+ JH7100_CLK_PLL0_OUT,
+ JH7100_CLK_PLL1_OUT),
+ STARFIVE__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3,
+ JH7100_CLK_OSC_AUD,
+ JH7100_CLK_PLL0_OUT,
+ JH7100_CLK_PLL2_OUT),
+ STARFIVE__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT),
+ STARFIVE__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT),
+ STARFIVE__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT),
+ STARFIVE__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT),
+ STARFIVE_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),
+ STARFIVE_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),
+ STARFIVE__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2,
+ JH7100_CLK_OSC_SYS,
+ JH7100_CLK_OSC_AUD),
+ STARFIVE__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+ STARFIVE__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE),
+ STARFIVE__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+ STARFIVE__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS),
+ STARFIVE__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS),
+ STARFIVE_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
+ STARFIVE_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
+ STARFIVE_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE),
+ STARFIVE_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE),
+ STARFIVE_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI),
+ STARFIVE_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL,
+ JH7100_CLK_OSC_SYS),
+ STARFIVE_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI),
+ STARFIVE_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI),
+ STARFIVE_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS),
+ STARFIVE__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT),
+ STARFIVE_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS),
+ STARFIVE_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS),
+ STARFIVE_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV),
+ STARFIVE__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT),
+ STARFIVE_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC),
+ STARFIVE__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
+ STARFIVE__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus", 8, JH7100_CLK_VCDECBUS_SRC),
+ STARFIVE_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi", 0, JH7100_CLK_VDEC_BUS),
+ STARFIVE_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk", 0, JH7100_CLK_VDEC_BUS),
+ STARFIVE_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
+ STARFIVE_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
+ STARFIVE_GATE(JH7100_CLK_VDEC_APB, "vdec_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+ STARFIVE_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+ STARFIVE_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GDIV(JH7100_CLK_GC300_2X, "gc300_2x", 0, 8, JH7100_CLK_CDECHIFI4_ROOT),
+ STARFIVE_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb", 0, JH7100_CLK_AHB_BUS),
+ STARFIVE__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus", 8, JH7100_CLK_VCDECBUS_SRC),
+ STARFIVE_GATE(JH7100_CLK_GC300_AXI, "gc300_axi", 0, JH7100_CLK_JPCGC300_AXIBUS),
+ STARFIVE_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk", 0, JH7100_CLK_JPCGC300_AXIBUS),
+ STARFIVE__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC),
+ STARFIVE_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS),
+ STARFIVE_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS),
+ STARFIVE_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
+ STARFIVE_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
+ STARFIVE_GATE(JH7100_CLK_VENC_APB, "venc_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2,
+ JH7100_CLK_PLL1_OUT),
+ STARFIVE_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2,
+ JH7100_CLK_DDRPLL_DIV2),
+ STARFIVE_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2,
+ JH7100_CLK_DDRPLL_DIV4),
+ STARFIVE_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2,
+ JH7100_CLK_OSC_SYS),
+ STARFIVE_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4,
+ JH7100_CLK_DDROSC_DIV2,
+ JH7100_CLK_DDRPLL_DIV2,
+ JH7100_CLK_DDRPLL_DIV4,
+ JH7100_CLK_DDRPLL_DIV8),
+ STARFIVE_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4,
+ JH7100_CLK_DDROSC_DIV2,
+ JH7100_CLK_DDRPLL_DIV2,
+ JH7100_CLK_DDRPLL_DIV4,
+ JH7100_CLK_DDRPLL_DIV8),
+ STARFIVE_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE__DIV(JH7100_CLK_NOC_ROB, "noc_rob", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+ STARFIVE__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT),
+ STARFIVE_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS),
+ STARFIVE__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT),
+ STARFIVE__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2,
+ JH7100_CLK_CPU_AXI,
+ JH7100_CLK_NNEBUS_SRC1),
+ STARFIVE_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS),
+ STARFIVE_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi", 0, JH7100_CLK_NNE_BUS),
+ STARFIVE_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi", 0, JH7100_CLK_NNE_BUS),
+ STARFIVE_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi", CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS),
+ STARFIVE__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
+ STARFIVE__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree", 8, JH7100_CLK_HIFI4_SRC),
+ STARFIVE_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core", 0, JH7100_CLK_HIFI4_COREFREE),
+ STARFIVE__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus", 8, JH7100_CLK_HIFI4_COREFREE),
+ STARFIVE_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi", 0, JH7100_CLK_HIFI4_BUS),
+ STARFIVE_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi", 0, JH7100_CLK_HIFI4_BUS),
+ STARFIVE__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+ STARFIVE_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
+ STARFIVE_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
+ STARFIVE_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8,
+ JH7100_CLK_CPUNBUS_ROOT_DIV),
+ STARFIVE__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+ STARFIVE_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS),
+ STARFIVE_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS),
+ STARFIVE__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT),
+ STARFIVE_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),
+ STARFIVE_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32,
+ JH7100_CLK_USBPHY_ROOTDIV),
+ STARFIVE__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
+ JH7100_CLK_OSC_SYS,
+ JH7100_CLK_USBPHY_PLLDIV25M),
+ STARFIVE_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT),
+ STARFIVE_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV),
+ STARFIVE_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD),
+ STARFIVE_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT),
+ STARFIVE__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus", 8, JH7100_CLK_VIN_SRC),
+ STARFIVE_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi", 0, JH7100_CLK_ISP0_BUS),
+ STARFIVE_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi", 0, JH7100_CLK_ISP0_BUS),
+ STARFIVE_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi", 0, JH7100_CLK_ISP0_BUS),
+ STARFIVE__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus", 8, JH7100_CLK_VIN_SRC),
+ STARFIVE_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi", 0, JH7100_CLK_ISP1_BUS),
+ STARFIVE_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi", 0, JH7100_CLK_ISP1_BUS),
+ STARFIVE__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC),
+ STARFIVE_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS),
+ STARFIVE_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS),
+ STARFIVE_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT),
+ STARFIVE__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT),
+ STARFIVE__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC),
+ STARFIVE_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS),
+ STARFIVE_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS),
+ STARFIVE_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS),
+ STARFIVE_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC),
+ STARFIVE__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT),
+ STARFIVE_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS),
+ STARFIVE_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC),
+ STARFIVE__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT),
+ STARFIVE_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS),
+ STARFIVE__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT),
+ STARFIVE_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV),
+ STARFIVE_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),
+ STARFIVE_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
+ STARFIVE_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
+ STARFIVE__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3,
+ JH7100_CLK_GMAC_GTX,
+ JH7100_CLK_GMAC_TX_INV,
+ JH7100_CLK_GMAC_RMII_TX),
+ STARFIVE__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX),
+ STARFIVE__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2,
+ JH7100_CLK_GMAC_GR_MII_RX,
+ JH7100_CLK_GMAC_RMII_RX),
+ STARFIVE__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE),
+ STARFIVE_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF),
+ STARFIVE_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV),
+ STARFIVE_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS),
+ STARFIVE_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS),
+ STARFIVE_GATE(JH7100_CLK_E24_AHB, "e24_ahb", 0, JH7100_CLK_AHB_BUS),
+ STARFIVE_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle", 0, JH7100_CLK_OSC_SYS),
+ STARFIVE_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", 0, JH7100_CLK_AHB_BUS),
+ STARFIVE_GATE(JH7100_CLK_QSPI_APB, "qspi_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk", 0, 31, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", 0, JH7100_CLK_AHB_BUS),
+ STARFIVE_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB),
+ STARFIVE_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB),
+ STARFIVE_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB),
+ STARFIVE_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC),
+ STARFIVE_GATE(JH7100_CLK_UART1_APB, "uart1_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GDIV(JH7100_CLK_UART1_CORE, "uart1_core", 0, 63, JH7100_CLK_PERH1_SRC),
+ STARFIVE_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 0, 63, JH7100_CLK_PERH1_SRC),
+ STARFIVE_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 0, 63, JH7100_CLK_PERH1_SRC),
+ STARFIVE_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 0, 63, JH7100_CLK_PERH1_SRC),
+ STARFIVE_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 0, 63, JH7100_CLK_PERH1_SRC),
+ STARFIVE_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", 0, JH7100_CLK_APB1_BUS),
+ STARFIVE_GATE(JH7100_CLK_UART2_APB, "uart2_apb", 0, JH7100_CLK_APB2_BUS),
+ STARFIVE_GDIV(JH7100_CLK_UART2_CORE, "uart2_core", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GATE(JH7100_CLK_UART3_APB, "uart3_apb", 0, JH7100_CLK_APB2_BUS),
+ STARFIVE_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", 0, JH7100_CLK_APB2_BUS),
+ STARFIVE_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", 0, JH7100_CLK_APB2_BUS),
+ STARFIVE_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", 0, JH7100_CLK_APB2_BUS),
+ STARFIVE_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", 0, JH7100_CLK_APB2_BUS),
+ STARFIVE_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS),
+ STARFIVE_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+ STARFIVE_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS),
+ STARFIVE_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS),
+ STARFIVE_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS),
+ STARFIVE_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS),
+ STARFIVE_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS),
+ STARFIVE_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS),
};
static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data)
{
- struct jh71x0_clk_priv *priv = data;
+ struct starfive_clk_priv *priv = data;
unsigned int idx = clkspec->args[0];
if (idx < JH7100_CLK_PLL0_OUT)
@@ -283,7 +287,7 @@ static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data
static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
{
- struct jh71x0_clk_priv *priv;
+ struct starfive_clk_priv *priv;
unsigned int idx;
int ret;
@@ -317,12 +321,13 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
struct clk_parent_data parents[4] = {};
struct clk_init_data init = {
.name = jh7100_clk_data[idx].name,
- .ops = starfive_jh71x0_clk_ops(max),
+ .ops = starfive_clk_ops(max),
.parent_data = parents,
- .num_parents = ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
+ .num_parents = ((max & STARFIVE_CLK_MUX_MASK)
+ >> STARFIVE_CLK_MUX_SHIFT) + 1,
.flags = jh7100_clk_data[idx].flags,
};
- struct jh71x0_clk *clk = &priv->reg[idx];
+ struct starfive_clk *clk = &priv->reg[idx];
unsigned int i;
for (i = 0; i < init.num_parents; i++) {
@@ -344,7 +349,7 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
clk->hw.init = &init;
clk->idx = idx;
- clk->max_div = max & JH71X0_CLK_DIV_MASK;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
ret = devm_clk_hw_register(priv->dev, &clk->hw);
if (ret)
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-aon.c b/drivers/clk/starfive/clk-starfive-jh7110-aon.c
index 62954eb7b50a..a7ce89b566eb 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-aon.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-aon.c
@@ -23,40 +23,40 @@
#define JH7110_AONCLK_GMAC0_GTXCLK (JH7110_AONCLK_END + 5)
#define JH7110_AONCLK_RTC_OSC (JH7110_AONCLK_END + 6)
-static const struct jh71x0_clk_data jh7110_aonclk_data[] = {
+static const struct starfive_clk_data jh7110_aonclk_data[] = {
/* source */
- JH71X0__DIV(JH7110_AONCLK_OSC_DIV4, "osc_div4", 4, JH7110_AONCLK_OSC),
- JH71X0__MUX(JH7110_AONCLK_APB_FUNC, "apb_func", 2,
- JH7110_AONCLK_OSC_DIV4,
- JH7110_AONCLK_OSC),
+ STARFIVE__DIV(JH7110_AONCLK_OSC_DIV4, "osc_div4", 4, JH7110_AONCLK_OSC),
+ STARFIVE__MUX(JH7110_AONCLK_APB_FUNC, "apb_func", 2,
+ JH7110_AONCLK_OSC_DIV4,
+ JH7110_AONCLK_OSC),
/* gmac0 */
- JH71X0_GATE(JH7110_AONCLK_GMAC0_AHB, "gmac0_ahb", 0, JH7110_AONCLK_STG_AXIAHB),
- JH71X0_GATE(JH7110_AONCLK_GMAC0_AXI, "gmac0_axi", 0, JH7110_AONCLK_STG_AXIAHB),
- JH71X0__DIV(JH7110_AONCLK_GMAC0_RMII_RTX, "gmac0_rmii_rtx", 30,
- JH7110_AONCLK_GMAC0_RMII_REFIN),
- JH71X0_GMUX(JH7110_AONCLK_GMAC0_TX, "gmac0_tx",
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2,
- JH7110_AONCLK_GMAC0_GTXCLK,
- JH7110_AONCLK_GMAC0_RMII_RTX),
- JH71X0__INV(JH7110_AONCLK_GMAC0_TX_INV, "gmac0_tx_inv", JH7110_AONCLK_GMAC0_TX),
- JH71X0__MUX(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", 2,
- JH7110_AONCLK_GMAC0_RGMII_RXIN,
- JH7110_AONCLK_GMAC0_RMII_RTX),
- JH71X0__INV(JH7110_AONCLK_GMAC0_RX_INV, "gmac0_rx_inv", JH7110_AONCLK_GMAC0_RX),
+ STARFIVE_GATE(JH7110_AONCLK_GMAC0_AHB, "gmac0_ahb", 0, JH7110_AONCLK_STG_AXIAHB),
+ STARFIVE_GATE(JH7110_AONCLK_GMAC0_AXI, "gmac0_axi", 0, JH7110_AONCLK_STG_AXIAHB),
+ STARFIVE__DIV(JH7110_AONCLK_GMAC0_RMII_RTX, "gmac0_rmii_rtx", 30,
+ JH7110_AONCLK_GMAC0_RMII_REFIN),
+ STARFIVE_GMUX(JH7110_AONCLK_GMAC0_TX, "gmac0_tx",
+ CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2,
+ JH7110_AONCLK_GMAC0_GTXCLK,
+ JH7110_AONCLK_GMAC0_RMII_RTX),
+ STARFIVE__INV(JH7110_AONCLK_GMAC0_TX_INV, "gmac0_tx_inv", JH7110_AONCLK_GMAC0_TX),
+ STARFIVE__MUX(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", 2,
+ JH7110_AONCLK_GMAC0_RGMII_RXIN,
+ JH7110_AONCLK_GMAC0_RMII_RTX),
+ STARFIVE__INV(JH7110_AONCLK_GMAC0_RX_INV, "gmac0_rx_inv", JH7110_AONCLK_GMAC0_RX),
/* otpc */
- JH71X0_GATE(JH7110_AONCLK_OTPC_APB, "otpc_apb", 0, JH7110_AONCLK_APB_BUS),
+ STARFIVE_GATE(JH7110_AONCLK_OTPC_APB, "otpc_apb", 0, JH7110_AONCLK_APB_BUS),
/* rtc */
- JH71X0_GATE(JH7110_AONCLK_RTC_APB, "rtc_apb", 0, JH7110_AONCLK_APB_BUS),
- JH71X0__DIV(JH7110_AONCLK_RTC_INTERNAL, "rtc_internal", 1022, JH7110_AONCLK_OSC),
- JH71X0__MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", 2,
- JH7110_AONCLK_RTC_OSC,
- JH7110_AONCLK_RTC_INTERNAL),
- JH71X0_GATE(JH7110_AONCLK_RTC_CAL, "rtc_cal", 0, JH7110_AONCLK_OSC),
+ STARFIVE_GATE(JH7110_AONCLK_RTC_APB, "rtc_apb", 0, JH7110_AONCLK_APB_BUS),
+ STARFIVE__DIV(JH7110_AONCLK_RTC_INTERNAL, "rtc_internal", 1022, JH7110_AONCLK_OSC),
+ STARFIVE__MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", 2,
+ JH7110_AONCLK_RTC_OSC,
+ JH7110_AONCLK_RTC_INTERNAL),
+ STARFIVE_GATE(JH7110_AONCLK_RTC_CAL, "rtc_cal", 0, JH7110_AONCLK_OSC),
};
static struct clk_hw *jh7110_aonclk_get(struct of_phandle_args *clkspec, void *data)
{
- struct jh71x0_clk_priv *priv = data;
+ struct starfive_clk_priv *priv = data;
unsigned int idx = clkspec->args[0];
if (idx < JH7110_AONCLK_END)
@@ -67,7 +67,7 @@ static struct clk_hw *jh7110_aonclk_get(struct of_phandle_args *clkspec, void *d
static int jh7110_aoncrg_probe(struct platform_device *pdev)
{
- struct jh71x0_clk_priv *priv;
+ struct starfive_clk_priv *priv;
unsigned int idx;
int ret;
@@ -88,13 +88,13 @@ static int jh7110_aoncrg_probe(struct platform_device *pdev)
struct clk_parent_data parents[4] = {};
struct clk_init_data init = {
.name = jh7110_aonclk_data[idx].name,
- .ops = starfive_jh71x0_clk_ops(max),
+ .ops = starfive_clk_ops(max),
.parent_data = parents,
.num_parents =
- ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
+ ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
.flags = jh7110_aonclk_data[idx].flags,
};
- struct jh71x0_clk *clk = &priv->reg[idx];
+ struct starfive_clk *clk = &priv->reg[idx];
unsigned int i;
for (i = 0; i < init.num_parents; i++) {
@@ -120,7 +120,7 @@ static int jh7110_aoncrg_probe(struct platform_device *pdev)
clk->hw.init = &init;
clk->idx = idx;
- clk->max_div = max & JH71X0_CLK_DIV_MASK;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
if (ret)
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-isp.c b/drivers/clk/starfive/clk-starfive-jh7110-isp.c
index ce034ed28532..be6040f718c0 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-isp.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-isp.c
@@ -28,41 +28,41 @@ static struct clk_bulk_data jh7110_isp_top_clks[] = {
{ .id = "isp_top_axi" }
};
-static const struct jh71x0_clk_data jh7110_ispclk_data[] = {
+static const struct starfive_clk_data jh7110_ispclk_data[] = {
/* syscon */
- JH71X0__DIV(JH7110_ISPCLK_DOM4_APB_FUNC, "dom4_apb_func", 15,
- JH7110_ISPCLK_ISP_TOP_AXI),
- JH71X0__DIV(JH7110_ISPCLK_MIPI_RX0_PXL, "mipi_rx0_pxl", 8,
- JH7110_ISPCLK_ISP_TOP_CORE),
- JH71X0__INV(JH7110_ISPCLK_DVP_INV, "dvp_inv", JH7110_ISPCLK_DVP_CLK),
+ STARFIVE__DIV(JH7110_ISPCLK_DOM4_APB_FUNC, "dom4_apb_func", 15,
+ JH7110_ISPCLK_ISP_TOP_AXI),
+ STARFIVE__DIV(JH7110_ISPCLK_MIPI_RX0_PXL, "mipi_rx0_pxl", 8,
+ JH7110_ISPCLK_ISP_TOP_CORE),
+ STARFIVE__INV(JH7110_ISPCLK_DVP_INV, "dvp_inv", JH7110_ISPCLK_DVP_CLK),
/* vin */
- JH71X0__DIV(JH7110_ISPCLK_M31DPHY_CFG_IN, "m31dphy_cfg_in", 16,
- JH7110_ISPCLK_ISP_TOP_CORE),
- JH71X0__DIV(JH7110_ISPCLK_M31DPHY_REF_IN, "m31dphy_ref_in", 16,
- JH7110_ISPCLK_ISP_TOP_CORE),
- JH71X0__DIV(JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0, "m31dphy_tx_esc_lan0", 60,
- JH7110_ISPCLK_ISP_TOP_CORE),
- JH71X0_GATE(JH7110_ISPCLK_VIN_APB, "vin_apb", 0,
- JH7110_ISPCLK_DOM4_APB_FUNC),
- JH71X0__DIV(JH7110_ISPCLK_VIN_SYS, "vin_sys", 8, JH7110_ISPCLK_ISP_TOP_CORE),
- JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF0, "vin_pixel_if0", 0,
- JH7110_ISPCLK_MIPI_RX0_PXL),
- JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF1, "vin_pixel_if1", 0,
- JH7110_ISPCLK_MIPI_RX0_PXL),
- JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF2, "vin_pixel_if2", 0,
- JH7110_ISPCLK_MIPI_RX0_PXL),
- JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF3, "vin_pixel_if3", 0,
- JH7110_ISPCLK_MIPI_RX0_PXL),
- JH71X0__MUX(JH7110_ISPCLK_VIN_P_AXI_WR, "vin_p_axi_wr", 2,
- JH7110_ISPCLK_MIPI_RX0_PXL,
- JH7110_ISPCLK_DVP_INV),
+ STARFIVE__DIV(JH7110_ISPCLK_M31DPHY_CFG_IN, "m31dphy_cfg_in", 16,
+ JH7110_ISPCLK_ISP_TOP_CORE),
+ STARFIVE__DIV(JH7110_ISPCLK_M31DPHY_REF_IN, "m31dphy_ref_in", 16,
+ JH7110_ISPCLK_ISP_TOP_CORE),
+ STARFIVE__DIV(JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0, "m31dphy_tx_esc_lan0", 60,
+ JH7110_ISPCLK_ISP_TOP_CORE),
+ STARFIVE_GATE(JH7110_ISPCLK_VIN_APB, "vin_apb", 0,
+ JH7110_ISPCLK_DOM4_APB_FUNC),
+ STARFIVE__DIV(JH7110_ISPCLK_VIN_SYS, "vin_sys", 8, JH7110_ISPCLK_ISP_TOP_CORE),
+ STARFIVE_GATE(JH7110_ISPCLK_VIN_PIXEL_IF0, "vin_pixel_if0", 0,
+ JH7110_ISPCLK_MIPI_RX0_PXL),
+ STARFIVE_GATE(JH7110_ISPCLK_VIN_PIXEL_IF1, "vin_pixel_if1", 0,
+ JH7110_ISPCLK_MIPI_RX0_PXL),
+ STARFIVE_GATE(JH7110_ISPCLK_VIN_PIXEL_IF2, "vin_pixel_if2", 0,
+ JH7110_ISPCLK_MIPI_RX0_PXL),
+ STARFIVE_GATE(JH7110_ISPCLK_VIN_PIXEL_IF3, "vin_pixel_if3", 0,
+ JH7110_ISPCLK_MIPI_RX0_PXL),
+ STARFIVE__MUX(JH7110_ISPCLK_VIN_P_AXI_WR, "vin_p_axi_wr", 2,
+ JH7110_ISPCLK_MIPI_RX0_PXL,
+ JH7110_ISPCLK_DVP_INV),
/* ispv2_top_wrapper */
- JH71X0_GMUX(JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C, "ispv2_top_wrapper_c", 0, 2,
- JH7110_ISPCLK_MIPI_RX0_PXL,
- JH7110_ISPCLK_DVP_INV),
+ STARFIVE_GMUX(JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C, "ispv2_top_wrapper_c", 0, 2,
+ JH7110_ISPCLK_MIPI_RX0_PXL,
+ JH7110_ISPCLK_DVP_INV),
};
-static inline int jh7110_isp_top_rst_init(struct jh71x0_clk_priv *priv)
+static inline int jh7110_isp_top_rst_init(struct starfive_clk_priv *priv)
{
struct reset_control *top_rsts;
@@ -77,7 +77,7 @@ static inline int jh7110_isp_top_rst_init(struct jh71x0_clk_priv *priv)
static struct clk_hw *jh7110_ispclk_get(struct of_phandle_args *clkspec, void *data)
{
- struct jh71x0_clk_priv *priv = data;
+ struct starfive_clk_priv *priv = data;
unsigned int idx = clkspec->args[0];
if (idx < JH7110_ISPCLK_END)
@@ -110,7 +110,7 @@ static const struct dev_pm_ops jh7110_ispcrg_pm_ops = {
static int jh7110_ispcrg_probe(struct platform_device *pdev)
{
- struct jh71x0_clk_priv *priv;
+ struct starfive_clk_priv *priv;
struct jh7110_top_sysclk *top;
unsigned int idx;
int ret;
@@ -153,13 +153,13 @@ static int jh7110_ispcrg_probe(struct platform_device *pdev)
struct clk_parent_data parents[4] = {};
struct clk_init_data init = {
.name = jh7110_ispclk_data[idx].name,
- .ops = starfive_jh71x0_clk_ops(max),
+ .ops = starfive_clk_ops(max),
.parent_data = parents,
.num_parents =
- ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
+ ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
.flags = jh7110_ispclk_data[idx].flags,
};
- struct jh71x0_clk *clk = &priv->reg[idx];
+ struct starfive_clk *clk = &priv->reg[idx];
unsigned int i;
const char *fw_name[JH7110_ISPCLK_EXT_END - JH7110_ISPCLK_END] = {
"isp_top_core",
@@ -179,7 +179,7 @@ static int jh7110_ispcrg_probe(struct platform_device *pdev)
clk->hw.init = &init;
clk->idx = idx;
- clk->max_div = max & JH71X0_CLK_DIV_MASK;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
if (ret)
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-stg.c b/drivers/clk/starfive/clk-starfive-jh7110-stg.c
index dafcb7190592..2d6ee0ad343a 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-stg.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-stg.c
@@ -25,59 +25,59 @@
#define JH7110_STGCLK_APB_BUS (JH7110_STGCLK_END + 7)
#define JH7110_STGCLK_EXT_END (JH7110_STGCLK_END + 8)
-static const struct jh71x0_clk_data jh7110_stgclk_data[] = {
+static const struct starfive_clk_data jh7110_stgclk_data[] = {
/* hifi4 */
- JH71X0_GATE(JH7110_STGCLK_HIFI4_CLK_CORE, "hifi4_clk_core", 0,
- JH7110_STGCLK_HIFI4_CORE),
+ STARFIVE_GATE(JH7110_STGCLK_HIFI4_CLK_CORE, "hifi4_clk_core", 0,
+ JH7110_STGCLK_HIFI4_CORE),
/* usb */
- JH71X0_GATE(JH7110_STGCLK_USB0_APB, "usb0_apb", 0, JH7110_STGCLK_APB_BUS),
- JH71X0_GATE(JH7110_STGCLK_USB0_UTMI_APB, "usb0_utmi_apb", 0, JH7110_STGCLK_APB_BUS),
- JH71X0_GATE(JH7110_STGCLK_USB0_AXI, "usb0_axi", 0, JH7110_STGCLK_STG_AXIAHB),
- JH71X0_GDIV(JH7110_STGCLK_USB0_LPM, "usb0_lpm", 0, 2, JH7110_STGCLK_OSC),
- JH71X0_GDIV(JH7110_STGCLK_USB0_STB, "usb0_stb", 0, 4, JH7110_STGCLK_OSC),
- JH71X0_GATE(JH7110_STGCLK_USB0_APP_125, "usb0_app_125", 0, JH7110_STGCLK_USB_125M),
- JH71X0__DIV(JH7110_STGCLK_USB0_REFCLK, "usb0_refclk", 2, JH7110_STGCLK_OSC),
+ STARFIVE_GATE(JH7110_STGCLK_USB0_APB, "usb0_apb", 0, JH7110_STGCLK_APB_BUS),
+ STARFIVE_GATE(JH7110_STGCLK_USB0_UTMI_APB, "usb0_utmi_apb", 0, JH7110_STGCLK_APB_BUS),
+ STARFIVE_GATE(JH7110_STGCLK_USB0_AXI, "usb0_axi", 0, JH7110_STGCLK_STG_AXIAHB),
+ STARFIVE_GDIV(JH7110_STGCLK_USB0_LPM, "usb0_lpm", 0, 2, JH7110_STGCLK_OSC),
+ STARFIVE_GDIV(JH7110_STGCLK_USB0_STB, "usb0_stb", 0, 4, JH7110_STGCLK_OSC),
+ STARFIVE_GATE(JH7110_STGCLK_USB0_APP_125, "usb0_app_125", 0, JH7110_STGCLK_USB_125M),
+ STARFIVE__DIV(JH7110_STGCLK_USB0_REFCLK, "usb0_refclk", 2, JH7110_STGCLK_OSC),
/* pci-e */
- JH71X0_GATE(JH7110_STGCLK_PCIE0_AXI_MST0, "pcie0_axi_mst0", 0,
- JH7110_STGCLK_STG_AXIAHB),
- JH71X0_GATE(JH7110_STGCLK_PCIE0_APB, "pcie0_apb", 0, JH7110_STGCLK_APB_BUS),
- JH71X0_GATE(JH7110_STGCLK_PCIE0_TL, "pcie0_tl", 0, JH7110_STGCLK_STG_AXIAHB),
- JH71X0_GATE(JH7110_STGCLK_PCIE1_AXI_MST0, "pcie1_axi_mst0", 0,
- JH7110_STGCLK_STG_AXIAHB),
- JH71X0_GATE(JH7110_STGCLK_PCIE1_APB, "pcie1_apb", 0, JH7110_STGCLK_APB_BUS),
- JH71X0_GATE(JH7110_STGCLK_PCIE1_TL, "pcie1_tl", 0, JH7110_STGCLK_STG_AXIAHB),
- JH71X0_GATE(JH7110_STGCLK_PCIE_SLV_MAIN, "pcie_slv_main", CLK_IS_CRITICAL,
- JH7110_STGCLK_STG_AXIAHB),
+ STARFIVE_GATE(JH7110_STGCLK_PCIE0_AXI_MST0, "pcie0_axi_mst0", 0,
+ JH7110_STGCLK_STG_AXIAHB),
+ STARFIVE_GATE(JH7110_STGCLK_PCIE0_APB, "pcie0_apb", 0, JH7110_STGCLK_APB_BUS),
+ STARFIVE_GATE(JH7110_STGCLK_PCIE0_TL, "pcie0_tl", 0, JH7110_STGCLK_STG_AXIAHB),
+ STARFIVE_GATE(JH7110_STGCLK_PCIE1_AXI_MST0, "pcie1_axi_mst0", 0,
+ JH7110_STGCLK_STG_AXIAHB),
+ STARFIVE_GATE(JH7110_STGCLK_PCIE1_APB, "pcie1_apb", 0, JH7110_STGCLK_APB_BUS),
+ STARFIVE_GATE(JH7110_STGCLK_PCIE1_TL, "pcie1_tl", 0, JH7110_STGCLK_STG_AXIAHB),
+ STARFIVE_GATE(JH7110_STGCLK_PCIE_SLV_MAIN, "pcie_slv_main", CLK_IS_CRITICAL,
+ JH7110_STGCLK_STG_AXIAHB),
/* security */
- JH71X0_GATE(JH7110_STGCLK_SEC_AHB, "sec_ahb", 0, JH7110_STGCLK_STG_AXIAHB),
- JH71X0_GATE(JH7110_STGCLK_SEC_MISC_AHB, "sec_misc_ahb", 0, JH7110_STGCLK_STG_AXIAHB),
+ STARFIVE_GATE(JH7110_STGCLK_SEC_AHB, "sec_ahb", 0, JH7110_STGCLK_STG_AXIAHB),
+ STARFIVE_GATE(JH7110_STGCLK_SEC_MISC_AHB, "sec_misc_ahb", 0, JH7110_STGCLK_STG_AXIAHB),
/* stg mtrx */
- JH71X0_GATE(JH7110_STGCLK_GRP0_MAIN, "mtrx_grp0_main", CLK_IS_CRITICAL,
- JH7110_STGCLK_CPU_BUS),
- JH71X0_GATE(JH7110_STGCLK_GRP0_BUS, "mtrx_grp0_bus", CLK_IS_CRITICAL,
- JH7110_STGCLK_NOCSTG_BUS),
- JH71X0_GATE(JH7110_STGCLK_GRP0_STG, "mtrx_grp0_stg", CLK_IS_CRITICAL,
- JH7110_STGCLK_STG_AXIAHB),
- JH71X0_GATE(JH7110_STGCLK_GRP1_MAIN, "mtrx_grp1_main", CLK_IS_CRITICAL,
- JH7110_STGCLK_CPU_BUS),
- JH71X0_GATE(JH7110_STGCLK_GRP1_BUS, "mtrx_grp1_bus", CLK_IS_CRITICAL,
- JH7110_STGCLK_NOCSTG_BUS),
- JH71X0_GATE(JH7110_STGCLK_GRP1_STG, "mtrx_grp1_stg", CLK_IS_CRITICAL,
- JH7110_STGCLK_STG_AXIAHB),
- JH71X0_GATE(JH7110_STGCLK_GRP1_HIFI, "mtrx_grp1_hifi", CLK_IS_CRITICAL,
- JH7110_STGCLK_HIFI4_AXI),
+ STARFIVE_GATE(JH7110_STGCLK_GRP0_MAIN, "mtrx_grp0_main", CLK_IS_CRITICAL,
+ JH7110_STGCLK_CPU_BUS),
+ STARFIVE_GATE(JH7110_STGCLK_GRP0_BUS, "mtrx_grp0_bus", CLK_IS_CRITICAL,
+ JH7110_STGCLK_NOCSTG_BUS),
+ STARFIVE_GATE(JH7110_STGCLK_GRP0_STG, "mtrx_grp0_stg", CLK_IS_CRITICAL,
+ JH7110_STGCLK_STG_AXIAHB),
+ STARFIVE_GATE(JH7110_STGCLK_GRP1_MAIN, "mtrx_grp1_main", CLK_IS_CRITICAL,
+ JH7110_STGCLK_CPU_BUS),
+ STARFIVE_GATE(JH7110_STGCLK_GRP1_BUS, "mtrx_grp1_bus", CLK_IS_CRITICAL,
+ JH7110_STGCLK_NOCSTG_BUS),
+ STARFIVE_GATE(JH7110_STGCLK_GRP1_STG, "mtrx_grp1_stg", CLK_IS_CRITICAL,
+ JH7110_STGCLK_STG_AXIAHB),
+ STARFIVE_GATE(JH7110_STGCLK_GRP1_HIFI, "mtrx_grp1_hifi", CLK_IS_CRITICAL,
+ JH7110_STGCLK_HIFI4_AXI),
/* e24_rvpi */
- JH71X0_GDIV(JH7110_STGCLK_E2_RTC, "e2_rtc", 0, 24, JH7110_STGCLK_OSC),
- JH71X0_GATE(JH7110_STGCLK_E2_CORE, "e2_core", 0, JH7110_STGCLK_STG_AXIAHB),
- JH71X0_GATE(JH7110_STGCLK_E2_DBG, "e2_dbg", 0, JH7110_STGCLK_STG_AXIAHB),
+ STARFIVE_GDIV(JH7110_STGCLK_E2_RTC, "e2_rtc", 0, 24, JH7110_STGCLK_OSC),
+ STARFIVE_GATE(JH7110_STGCLK_E2_CORE, "e2_core", 0, JH7110_STGCLK_STG_AXIAHB),
+ STARFIVE_GATE(JH7110_STGCLK_E2_DBG, "e2_dbg", 0, JH7110_STGCLK_STG_AXIAHB),
/* dw_sgdma1p */
- JH71X0_GATE(JH7110_STGCLK_DMA1P_AXI, "dma1p_axi", 0, JH7110_STGCLK_STG_AXIAHB),
- JH71X0_GATE(JH7110_STGCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7110_STGCLK_STG_AXIAHB),
+ STARFIVE_GATE(JH7110_STGCLK_DMA1P_AXI, "dma1p_axi", 0, JH7110_STGCLK_STG_AXIAHB),
+ STARFIVE_GATE(JH7110_STGCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7110_STGCLK_STG_AXIAHB),
};
static struct clk_hw *jh7110_stgclk_get(struct of_phandle_args *clkspec, void *data)
{
- struct jh71x0_clk_priv *priv = data;
+ struct starfive_clk_priv *priv = data;
unsigned int idx = clkspec->args[0];
if (idx < JH7110_STGCLK_END)
@@ -88,7 +88,7 @@ static struct clk_hw *jh7110_stgclk_get(struct of_phandle_args *clkspec, void *d
static int jh7110_stgcrg_probe(struct platform_device *pdev)
{
- struct jh71x0_clk_priv *priv;
+ struct starfive_clk_priv *priv;
unsigned int idx;
int ret;
@@ -108,13 +108,13 @@ static int jh7110_stgcrg_probe(struct platform_device *pdev)
struct clk_parent_data parents[4] = {};
struct clk_init_data init = {
.name = jh7110_stgclk_data[idx].name,
- .ops = starfive_jh71x0_clk_ops(max),
+ .ops = starfive_clk_ops(max),
.parent_data = parents,
.num_parents =
- ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
+ ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
.flags = jh7110_stgclk_data[idx].flags,
};
- struct jh71x0_clk *clk = &priv->reg[idx];
+ struct starfive_clk *clk = &priv->reg[idx];
const char *fw_name[JH7110_STGCLK_EXT_END - JH7110_STGCLK_END] = {
"osc",
"hifi4_core",
@@ -138,7 +138,7 @@ static int jh7110_stgcrg_probe(struct platform_device *pdev)
clk->hw.init = &init;
clk->idx = idx;
- clk->max_div = max & JH71X0_CLK_DIV_MASK;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
if (ret)
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
index e63353c70209..00ef88d9c2fd 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -34,298 +34,301 @@
#define JH7110_SYSCLK_PLL1_OUT (JH7110_SYSCLK_END + 10)
#define JH7110_SYSCLK_PLL2_OUT (JH7110_SYSCLK_END + 11)
-static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
+static const struct starfive_clk_data jh7110_sysclk_data[] __initconst = {
/* root */
- JH71X0__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 2,
- JH7110_SYSCLK_OSC,
- JH7110_SYSCLK_PLL0_OUT),
- JH71X0__DIV(JH7110_SYSCLK_CPU_CORE, "cpu_core", 7, JH7110_SYSCLK_CPU_ROOT),
- JH71X0__DIV(JH7110_SYSCLK_CPU_BUS, "cpu_bus", 2, JH7110_SYSCLK_CPU_CORE),
- JH71X0__MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", 2,
- JH7110_SYSCLK_PLL2_OUT,
- JH7110_SYSCLK_PLL1_OUT),
- JH71X0_MDIV(JH7110_SYSCLK_PERH_ROOT, "perh_root", 2, 2,
- JH7110_SYSCLK_PLL0_OUT,
- JH7110_SYSCLK_PLL2_OUT),
- JH71X0__MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", 2,
- JH7110_SYSCLK_OSC,
- JH7110_SYSCLK_PLL2_OUT),
- JH71X0__DIV(JH7110_SYSCLK_NOCSTG_BUS, "nocstg_bus", 3, JH7110_SYSCLK_BUS_ROOT),
- JH71X0__DIV(JH7110_SYSCLK_AXI_CFG0, "axi_cfg0", 3, JH7110_SYSCLK_BUS_ROOT),
- JH71X0__DIV(JH7110_SYSCLK_STG_AXIAHB, "stg_axiahb", 2, JH7110_SYSCLK_AXI_CFG0),
- JH71X0_GATE(JH7110_SYSCLK_AHB0, "ahb0", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB),
- JH71X0_GATE(JH7110_SYSCLK_AHB1, "ahb1", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB),
- JH71X0__DIV(JH7110_SYSCLK_APB_BUS, "apb_bus", 8, JH7110_SYSCLK_STG_AXIAHB),
- JH71X0_GATE(JH7110_SYSCLK_APB0, "apb0", CLK_IS_CRITICAL, JH7110_SYSCLK_APB_BUS),
- JH71X0__DIV(JH7110_SYSCLK_PLL0_DIV2, "pll0_div2", 2, JH7110_SYSCLK_PLL0_OUT),
- JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV2, "pll1_div2", 2, JH7110_SYSCLK_PLL1_OUT),
- JH71X0__DIV(JH7110_SYSCLK_PLL2_DIV2, "pll2_div2", 2, JH7110_SYSCLK_PLL2_OUT),
- JH71X0__DIV(JH7110_SYSCLK_AUDIO_ROOT, "audio_root", 8, JH7110_SYSCLK_PLL2_OUT),
- JH71X0__DIV(JH7110_SYSCLK_MCLK_INNER, "mclk_inner", 64, JH7110_SYSCLK_AUDIO_ROOT),
- JH71X0__MUX(JH7110_SYSCLK_MCLK, "mclk", 2,
- JH7110_SYSCLK_MCLK_INNER,
- JH7110_SYSCLK_MCLK_EXT),
- JH71X0_GATE(JH7110_SYSCLK_MCLK_OUT, "mclk_out", 0, JH7110_SYSCLK_MCLK_INNER),
- JH71X0_MDIV(JH7110_SYSCLK_ISP_2X, "isp_2x", 8, 2,
- JH7110_SYSCLK_PLL2_OUT,
- JH7110_SYSCLK_PLL1_OUT),
- JH71X0__DIV(JH7110_SYSCLK_ISP_AXI, "isp_axi", 4, JH7110_SYSCLK_ISP_2X),
- JH71X0_GDIV(JH7110_SYSCLK_GCLK0, "gclk0", 0, 62, JH7110_SYSCLK_PLL0_DIV2),
- JH71X0_GDIV(JH7110_SYSCLK_GCLK1, "gclk1", 0, 62, JH7110_SYSCLK_PLL1_DIV2),
- JH71X0_GDIV(JH7110_SYSCLK_GCLK2, "gclk2", 0, 62, JH7110_SYSCLK_PLL2_DIV2),
+ STARFIVE__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 2,
+ JH7110_SYSCLK_OSC,
+ JH7110_SYSCLK_PLL0_OUT),
+ STARFIVE__DIV(JH7110_SYSCLK_CPU_CORE, "cpu_core", 7, JH7110_SYSCLK_CPU_ROOT),
+ STARFIVE__DIV(JH7110_SYSCLK_CPU_BUS, "cpu_bus", 2, JH7110_SYSCLK_CPU_CORE),
+ STARFIVE__MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", 2,
+ JH7110_SYSCLK_PLL2_OUT,
+ JH7110_SYSCLK_PLL1_OUT),
+ STARFIVE_MDIV(JH7110_SYSCLK_PERH_ROOT, "perh_root", 2, 2,
+ JH7110_SYSCLK_PLL0_OUT,
+ JH7110_SYSCLK_PLL2_OUT),
+ STARFIVE__MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", 2,
+ JH7110_SYSCLK_OSC,
+ JH7110_SYSCLK_PLL2_OUT),
+ STARFIVE__DIV(JH7110_SYSCLK_NOCSTG_BUS, "nocstg_bus", 3, JH7110_SYSCLK_BUS_ROOT),
+ STARFIVE__DIV(JH7110_SYSCLK_AXI_CFG0, "axi_cfg0", 3, JH7110_SYSCLK_BUS_ROOT),
+ STARFIVE__DIV(JH7110_SYSCLK_STG_AXIAHB, "stg_axiahb", 2, JH7110_SYSCLK_AXI_CFG0),
+ STARFIVE_GATE(JH7110_SYSCLK_AHB0, "ahb0", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB),
+ STARFIVE_GATE(JH7110_SYSCLK_AHB1, "ahb1", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB),
+ STARFIVE__DIV(JH7110_SYSCLK_APB_BUS, "apb_bus", 8, JH7110_SYSCLK_STG_AXIAHB),
+ STARFIVE_GATE(JH7110_SYSCLK_APB0, "apb0", CLK_IS_CRITICAL, JH7110_SYSCLK_APB_BUS),
+ STARFIVE__DIV(JH7110_SYSCLK_PLL0_DIV2, "pll0_div2", 2, JH7110_SYSCLK_PLL0_OUT),
+ STARFIVE__DIV(JH7110_SYSCLK_PLL1_DIV2, "pll1_div2", 2, JH7110_SYSCLK_PLL1_OUT),
+ STARFIVE__DIV(JH7110_SYSCLK_PLL2_DIV2, "pll2_div2", 2, JH7110_SYSCLK_PLL2_OUT),
+ STARFIVE__DIV(JH7110_SYSCLK_AUDIO_ROOT, "audio_root", 8, JH7110_SYSCLK_PLL2_OUT),
+ STARFIVE__DIV(JH7110_SYSCLK_MCLK_INNER, "mclk_inner", 64, JH7110_SYSCLK_AUDIO_ROOT),
+ STARFIVE__MUX(JH7110_SYSCLK_MCLK, "mclk", 2,
+ JH7110_SYSCLK_MCLK_INNER,
+ JH7110_SYSCLK_MCLK_EXT),
+ STARFIVE_GATE(JH7110_SYSCLK_MCLK_OUT, "mclk_out", 0, JH7110_SYSCLK_MCLK_INNER),
+ STARFIVE_MDIV(JH7110_SYSCLK_ISP_2X, "isp_2x", 8, 2,
+ JH7110_SYSCLK_PLL2_OUT,
+ JH7110_SYSCLK_PLL1_OUT),
+ STARFIVE__DIV(JH7110_SYSCLK_ISP_AXI, "isp_axi", 4, JH7110_SYSCLK_ISP_2X),
+ STARFIVE_GDIV(JH7110_SYSCLK_GCLK0, "gclk0", 0, 62, JH7110_SYSCLK_PLL0_DIV2),
+ STARFIVE_GDIV(JH7110_SYSCLK_GCLK1, "gclk1", 0, 62, JH7110_SYSCLK_PLL1_DIV2),
+ STARFIVE_GDIV(JH7110_SYSCLK_GCLK2, "gclk2", 0, 62, JH7110_SYSCLK_PLL2_DIV2),
/* cores */
- JH71X0_GATE(JH7110_SYSCLK_CORE, "core", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
- JH71X0_GATE(JH7110_SYSCLK_CORE1, "core1", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
- JH71X0_GATE(JH7110_SYSCLK_CORE2, "core2", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
- JH71X0_GATE(JH7110_SYSCLK_CORE3, "core3", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
- JH71X0_GATE(JH7110_SYSCLK_CORE4, "core4", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
- JH71X0_GATE(JH7110_SYSCLK_DEBUG, "debug", 0, JH7110_SYSCLK_CPU_BUS),
- JH71X0__DIV(JH7110_SYSCLK_RTC_TOGGLE, "rtc_toggle", 6, JH7110_SYSCLK_OSC),
- JH71X0_GATE(JH7110_SYSCLK_TRACE0, "trace0", 0, JH7110_SYSCLK_CPU_CORE),
- JH71X0_GATE(JH7110_SYSCLK_TRACE1, "trace1", 0, JH7110_SYSCLK_CPU_CORE),
- JH71X0_GATE(JH7110_SYSCLK_TRACE2, "trace2", 0, JH7110_SYSCLK_CPU_CORE),
- JH71X0_GATE(JH7110_SYSCLK_TRACE3, "trace3", 0, JH7110_SYSCLK_CPU_CORE),
- JH71X0_GATE(JH7110_SYSCLK_TRACE4, "trace4", 0, JH7110_SYSCLK_CPU_CORE),
- JH71X0_GATE(JH7110_SYSCLK_TRACE_COM, "trace_com", 0, JH7110_SYSCLK_CPU_BUS),
+ STARFIVE_GATE(JH7110_SYSCLK_CORE, "core", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
+ STARFIVE_GATE(JH7110_SYSCLK_CORE1, "core1", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
+ STARFIVE_GATE(JH7110_SYSCLK_CORE2, "core2", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
+ STARFIVE_GATE(JH7110_SYSCLK_CORE3, "core3", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
+ STARFIVE_GATE(JH7110_SYSCLK_CORE4, "core4", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
+ STARFIVE_GATE(JH7110_SYSCLK_DEBUG, "debug", 0, JH7110_SYSCLK_CPU_BUS),
+ STARFIVE__DIV(JH7110_SYSCLK_RTC_TOGGLE, "rtc_toggle", 6, JH7110_SYSCLK_OSC),
+ STARFIVE_GATE(JH7110_SYSCLK_TRACE0, "trace0", 0, JH7110_SYSCLK_CPU_CORE),
+ STARFIVE_GATE(JH7110_SYSCLK_TRACE1, "trace1", 0, JH7110_SYSCLK_CPU_CORE),
+ STARFIVE_GATE(JH7110_SYSCLK_TRACE2, "trace2", 0, JH7110_SYSCLK_CPU_CORE),
+ STARFIVE_GATE(JH7110_SYSCLK_TRACE3, "trace3", 0, JH7110_SYSCLK_CPU_CORE),
+ STARFIVE_GATE(JH7110_SYSCLK_TRACE4, "trace4", 0, JH7110_SYSCLK_CPU_CORE),
+ STARFIVE_GATE(JH7110_SYSCLK_TRACE_COM, "trace_com", 0, JH7110_SYSCLK_CPU_BUS),
/* noc */
- JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_CPU_AXI, "noc_bus_cpu_axi", CLK_IS_CRITICAL,
- JH7110_SYSCLK_CPU_BUS),
- JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI, "noc_bus_axicfg0_axi", CLK_IS_CRITICAL,
- JH7110_SYSCLK_AXI_CFG0),
+ STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_CPU_AXI, "noc_bus_cpu_axi", CLK_IS_CRITICAL,
+ JH7110_SYSCLK_CPU_BUS),
+ STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI, "noc_bus_axicfg0_axi", CLK_IS_CRITICAL,
+ JH7110_SYSCLK_AXI_CFG0),
/* ddr */
- JH71X0__DIV(JH7110_SYSCLK_OSC_DIV2, "osc_div2", 2, JH7110_SYSCLK_OSC),
- JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV4, "pll1_div4", 2, JH7110_SYSCLK_PLL1_DIV2),
- JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV8, "pll1_div8", 2, JH7110_SYSCLK_PLL1_DIV4),
- JH71X0__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 4,
- JH7110_SYSCLK_OSC_DIV2,
- JH7110_SYSCLK_PLL1_DIV2,
- JH7110_SYSCLK_PLL1_DIV4,
- JH7110_SYSCLK_PLL1_DIV8),
- JH71X0_GATE(JH7110_SYSCLK_DDR_AXI, "ddr_axi", CLK_IS_CRITICAL, JH7110_SYSCLK_DDR_BUS),
+ STARFIVE__DIV(JH7110_SYSCLK_OSC_DIV2, "osc_div2", 2, JH7110_SYSCLK_OSC),
+ STARFIVE__DIV(JH7110_SYSCLK_PLL1_DIV4, "pll1_div4", 2, JH7110_SYSCLK_PLL1_DIV2),
+ STARFIVE__DIV(JH7110_SYSCLK_PLL1_DIV8, "pll1_div8", 2, JH7110_SYSCLK_PLL1_DIV4),
+ STARFIVE__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 4,
+ JH7110_SYSCLK_OSC_DIV2,
+ JH7110_SYSCLK_PLL1_DIV2,
+ JH7110_SYSCLK_PLL1_DIV4,
+ JH7110_SYSCLK_PLL1_DIV8),
+ STARFIVE_GATE(JH7110_SYSCLK_DDR_AXI, "ddr_axi", CLK_IS_CRITICAL, JH7110_SYSCLK_DDR_BUS),
/* gpu */
- JH71X0__DIV(JH7110_SYSCLK_GPU_CORE, "gpu_core", 7, JH7110_SYSCLK_GPU_ROOT),
- JH71X0_GATE(JH7110_SYSCLK_GPU_CORE_CLK, "gpu_core_clk", 0, JH7110_SYSCLK_GPU_CORE),
- JH71X0_GATE(JH7110_SYSCLK_GPU_SYS_CLK, "gpu_sys_clk", 0, JH7110_SYSCLK_ISP_AXI),
- JH71X0_GATE(JH7110_SYSCLK_GPU_APB, "gpu_apb", 0, JH7110_SYSCLK_APB_BUS),
- JH71X0_GDIV(JH7110_SYSCLK_GPU_RTC_TOGGLE, "gpu_rtc_toggle", 0, 12, JH7110_SYSCLK_OSC),
- JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_GPU_AXI, "noc_bus_gpu_axi", 0, JH7110_SYSCLK_GPU_CORE),
+ STARFIVE__DIV(JH7110_SYSCLK_GPU_CORE, "gpu_core", 7, JH7110_SYSCLK_GPU_ROOT),
+ STARFIVE_GATE(JH7110_SYSCLK_GPU_CORE_CLK, "gpu_core_clk", 0, JH7110_SYSCLK_GPU_CORE),
+ STARFIVE_GATE(JH7110_SYSCLK_GPU_SYS_CLK, "gpu_sys_clk", 0, JH7110_SYSCLK_ISP_AXI),
+ STARFIVE_GATE(JH7110_SYSCLK_GPU_APB, "gpu_apb", 0, JH7110_SYSCLK_APB_BUS),
+ STARFIVE_GDIV(JH7110_SYSCLK_GPU_RTC_TOGGLE, "gpu_rtc_toggle", 0, 12, JH7110_SYSCLK_OSC),
+ STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_GPU_AXI, "noc_bus_gpu_axi", 0, JH7110_SYSCLK_GPU_CORE),
/* isp */
- JH71X0_GATE(JH7110_SYSCLK_ISP_TOP_CORE, "isp_top_core", 0, JH7110_SYSCLK_ISP_2X),
- JH71X0_GATE(JH7110_SYSCLK_ISP_TOP_AXI, "isp_top_axi", 0, JH7110_SYSCLK_ISP_AXI),
- JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_ISP_AXI, "noc_bus_isp_axi", CLK_IS_CRITICAL,
- JH7110_SYSCLK_ISP_AXI),
+ STARFIVE_GATE(JH7110_SYSCLK_ISP_TOP_CORE, "isp_top_core", 0, JH7110_SYSCLK_ISP_2X),
+ STARFIVE_GATE(JH7110_SYSCLK_ISP_TOP_AXI, "isp_top_axi", 0, JH7110_SYSCLK_ISP_AXI),
+ STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_ISP_AXI, "noc_bus_isp_axi", CLK_IS_CRITICAL,
+ JH7110_SYSCLK_ISP_AXI),
/* hifi4 */
- JH71X0__DIV(JH7110_SYSCLK_HIFI4_CORE, "hifi4_core", 15, JH7110_SYSCLK_BUS_ROOT),
- JH71X0__DIV(JH7110_SYSCLK_HIFI4_AXI, "hifi4_axi", 2, JH7110_SYSCLK_HIFI4_CORE),
+ STARFIVE__DIV(JH7110_SYSCLK_HIFI4_CORE, "hifi4_core", 15, JH7110_SYSCLK_BUS_ROOT),
+ STARFIVE__DIV(JH7110_SYSCLK_HIFI4_AXI, "hifi4_axi", 2, JH7110_SYSCLK_HIFI4_CORE),
/* axi_cfg1 */
- JH71X0_GATE(JH7110_SYSCLK_AXI_CFG1_MAIN, "axi_cfg1_main", CLK_IS_CRITICAL,
- JH7110_SYSCLK_ISP_AXI),
- JH71X0_GATE(JH7110_SYSCLK_AXI_CFG1_AHB, "axi_cfg1_ahb", CLK_IS_CRITICAL,
- JH7110_SYSCLK_AHB0),
+ STARFIVE_GATE(JH7110_SYSCLK_AXI_CFG1_MAIN, "axi_cfg1_main", CLK_IS_CRITICAL,
+ JH7110_SYSCLK_ISP_AXI),
+ STARFIVE_GATE(JH7110_SYSCLK_AXI_CFG1_AHB, "axi_cfg1_ahb", CLK_IS_CRITICAL,
+ JH7110_SYSCLK_AHB0),
/* vout */
- JH71X0_GATE(JH7110_SYSCLK_VOUT_SRC, "vout_src", 0, JH7110_SYSCLK_PLL2_OUT),
- JH71X0__DIV(JH7110_SYSCLK_VOUT_AXI, "vout_axi", 7, JH7110_SYSCLK_PLL2_OUT),
- JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_DISP_AXI, "noc_bus_disp_axi", 0, JH7110_SYSCLK_VOUT_AXI),
- JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_AHB, "vout_top_ahb", 0, JH7110_SYSCLK_AHB1),
- JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_AXI, "vout_top_axi", 0, JH7110_SYSCLK_VOUT_AXI),
- JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK, "vout_top_hdmitx0_mclk", 0,
- JH7110_SYSCLK_MCLK),
- JH71X0__DIV(JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF, "vout_top_mipiphy_ref", 2,
- JH7110_SYSCLK_OSC),
+ STARFIVE_GATE(JH7110_SYSCLK_VOUT_SRC, "vout_src", 0, JH7110_SYSCLK_PLL2_OUT),
+ STARFIVE__DIV(JH7110_SYSCLK_VOUT_AXI, "vout_axi", 7, JH7110_SYSCLK_PLL2_OUT),
+ STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_DISP_AXI, "noc_bus_disp_axi", 0,
+ JH7110_SYSCLK_VOUT_AXI),
+ STARFIVE_GATE(JH7110_SYSCLK_VOUT_TOP_AHB, "vout_top_ahb", 0, JH7110_SYSCLK_AHB1),
+ STARFIVE_GATE(JH7110_SYSCLK_VOUT_TOP_AXI, "vout_top_axi", 0, JH7110_SYSCLK_VOUT_AXI),
+ STARFIVE_GATE(JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK, "vout_top_hdmitx0_mclk", 0,
+ JH7110_SYSCLK_MCLK),
+ STARFIVE__DIV(JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF, "vout_top_mipiphy_ref", 2,
+ JH7110_SYSCLK_OSC),
/* jpegc */
- JH71X0__DIV(JH7110_SYSCLK_JPEGC_AXI, "jpegc_axi", 16, JH7110_SYSCLK_PLL2_OUT),
- JH71X0_GATE(JH7110_SYSCLK_CODAJ12_AXI, "codaj12_axi", 0, JH7110_SYSCLK_JPEGC_AXI),
- JH71X0_GDIV(JH7110_SYSCLK_CODAJ12_CORE, "codaj12_core", 0, 16, JH7110_SYSCLK_PLL2_OUT),
- JH71X0_GATE(JH7110_SYSCLK_CODAJ12_APB, "codaj12_apb", 0, JH7110_SYSCLK_APB_BUS),
+ STARFIVE__DIV(JH7110_SYSCLK_JPEGC_AXI, "jpegc_axi", 16, JH7110_SYSCLK_PLL2_OUT),
+ STARFIVE_GATE(JH7110_SYSCLK_CODAJ12_AXI, "codaj12_axi", 0, JH7110_SYSCLK_JPEGC_AXI),
+ STARFIVE_GDIV(JH7110_SYSCLK_CODAJ12_CORE, "codaj12_core", 0, 16, JH7110_SYSCLK_PLL2_OUT),
+ STARFIVE_GATE(JH7110_SYSCLK_CODAJ12_APB, "codaj12_apb", 0, JH7110_SYSCLK_APB_BUS),
/* vdec */
- JH71X0__DIV(JH7110_SYSCLK_VDEC_AXI, "vdec_axi", 7, JH7110_SYSCLK_BUS_ROOT),
- JH71X0_GATE(JH7110_SYSCLK_WAVE511_AXI, "wave511_axi", 0, JH7110_SYSCLK_VDEC_AXI),
- JH71X0_GDIV(JH7110_SYSCLK_WAVE511_BPU, "wave511_bpu", 0, 7, JH7110_SYSCLK_BUS_ROOT),
- JH71X0_GDIV(JH7110_SYSCLK_WAVE511_VCE, "wave511_vce", 0, 7, JH7110_SYSCLK_PLL0_OUT),
- JH71X0_GATE(JH7110_SYSCLK_WAVE511_APB, "wave511_apb", 0, JH7110_SYSCLK_APB_BUS),
- JH71X0_GATE(JH7110_SYSCLK_VDEC_JPG, "vdec_jpg", 0, JH7110_SYSCLK_JPEGC_AXI),
- JH71X0_GATE(JH7110_SYSCLK_VDEC_MAIN, "vdec_main", 0, JH7110_SYSCLK_VDEC_AXI),
- JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_VDEC_AXI, "noc_bus_vdec_axi", 0, JH7110_SYSCLK_VDEC_AXI),
+ STARFIVE__DIV(JH7110_SYSCLK_VDEC_AXI, "vdec_axi", 7, JH7110_SYSCLK_BUS_ROOT),
+ STARFIVE_GATE(JH7110_SYSCLK_WAVE511_AXI, "wave511_axi", 0, JH7110_SYSCLK_VDEC_AXI),
+ STARFIVE_GDIV(JH7110_SYSCLK_WAVE511_BPU, "wave511_bpu", 0, 7, JH7110_SYSCLK_BUS_ROOT),
+ STARFIVE_GDIV(JH7110_SYSCLK_WAVE511_VCE, "wave511_vce", 0, 7, JH7110_SYSCLK_PLL0_OUT),
+ STARFIVE_GATE(JH7110_SYSCLK_WAVE511_APB, "wave511_apb", 0, JH7110_SYSCLK_APB_BUS),
+ STARFIVE_GATE(JH7110_SYSCLK_VDEC_JPG, "vdec_jpg", 0, JH7110_SYSCLK_JPEGC_AXI),
+ STARFIVE_GATE(JH7110_SYSCLK_VDEC_MAIN, "vdec_main", 0, JH7110_SYSCLK_VDEC_AXI),
+ STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_VDEC_AXI, "noc_bus_vdec_axi", 0,
+ JH7110_SYSCLK_VDEC_AXI),
/* venc */
- JH71X0__DIV(JH7110_SYSCLK_VENC_AXI, "venc_axi", 15, JH7110_SYSCLK_PLL2_OUT),
- JH71X0_GATE(JH7110_SYSCLK_WAVE420L_AXI, "wave420l_axi", 0, JH7110_SYSCLK_VENC_AXI),
- JH71X0_GDIV(JH7110_SYSCLK_WAVE420L_BPU, "wave420l_bpu", 0, 15, JH7110_SYSCLK_PLL2_OUT),
- JH71X0_GDIV(JH7110_SYSCLK_WAVE420L_VCE, "wave420l_vce", 0, 15, JH7110_SYSCLK_PLL2_OUT),
- JH71X0_GATE(JH7110_SYSCLK_WAVE420L_APB, "wave420l_apb", 0, JH7110_SYSCLK_APB_BUS),
- JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_VENC_AXI, "noc_bus_venc_axi", 0, JH7110_SYSCLK_VENC_AXI),
+ STARFIVE__DIV(JH7110_SYSCLK_VENC_AXI, "venc_axi", 15, JH7110_SYSCLK_PLL2_OUT),
+ STARFIVE_GATE(JH7110_SYSCLK_WAVE420L_AXI, "wave420l_axi", 0, JH7110_SYSCLK_VENC_AXI),
+ STARFIVE_GDIV(JH7110_SYSCLK_WAVE420L_BPU, "wave420l_bpu", 0, 15, JH7110_SYSCLK_PLL2_OUT),
+ STARFIVE_GDIV(JH7110_SYSCLK_WAVE420L_VCE, "wave420l_vce", 0, 15, JH7110_SYSCLK_PLL2_OUT),
+ STARFIVE_GATE(JH7110_SYSCLK_WAVE420L_APB, "wave420l_apb", 0, JH7110_SYSCLK_APB_BUS),
+ STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_VENC_AXI, "noc_bus_venc_axi", 0,
+ JH7110_SYSCLK_VENC_AXI),
/* axi_cfg0 */
- JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN_DIV, "axi_cfg0_main_div", CLK_IS_CRITICAL,
- JH7110_SYSCLK_AHB1),
- JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN, "axi_cfg0_main", CLK_IS_CRITICAL,
- JH7110_SYSCLK_AXI_CFG0),
- JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_HIFI4, "axi_cfg0_hifi4", CLK_IS_CRITICAL,
- JH7110_SYSCLK_HIFI4_AXI),
+ STARFIVE_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN_DIV, "axi_cfg0_main_div", CLK_IS_CRITICAL,
+ JH7110_SYSCLK_AHB1),
+ STARFIVE_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN, "axi_cfg0_main", CLK_IS_CRITICAL,
+ JH7110_SYSCLK_AXI_CFG0),
+ STARFIVE_GATE(JH7110_SYSCLK_AXI_CFG0_HIFI4, "axi_cfg0_hifi4", CLK_IS_CRITICAL,
+ JH7110_SYSCLK_HIFI4_AXI),
/* intmem */
- JH71X0_GATE(JH7110_SYSCLK_AXIMEM2_AXI, "aximem2_axi", 0, JH7110_SYSCLK_AXI_CFG0),
+ STARFIVE_GATE(JH7110_SYSCLK_AXIMEM2_AXI, "aximem2_axi", 0, JH7110_SYSCLK_AXI_CFG0),
/* qspi */
- JH71X0_GATE(JH7110_SYSCLK_QSPI_AHB, "qspi_ahb", 0, JH7110_SYSCLK_AHB1),
- JH71X0_GATE(JH7110_SYSCLK_QSPI_APB, "qspi_apb", 0, JH7110_SYSCLK_APB_BUS),
- JH71X0__DIV(JH7110_SYSCLK_QSPI_REF_SRC, "qspi_ref_src", 16, JH7110_SYSCLK_PLL0_OUT),
- JH71X0_GMUX(JH7110_SYSCLK_QSPI_REF, "qspi_ref", 0, 2,
- JH7110_SYSCLK_OSC,
- JH7110_SYSCLK_QSPI_REF_SRC),
+ STARFIVE_GATE(JH7110_SYSCLK_QSPI_AHB, "qspi_ahb", 0, JH7110_SYSCLK_AHB1),
+ STARFIVE_GATE(JH7110_SYSCLK_QSPI_APB, "qspi_apb", 0, JH7110_SYSCLK_APB_BUS),
+ STARFIVE__DIV(JH7110_SYSCLK_QSPI_REF_SRC, "qspi_ref_src", 16, JH7110_SYSCLK_PLL0_OUT),
+ STARFIVE_GMUX(JH7110_SYSCLK_QSPI_REF, "qspi_ref", 0, 2,
+ JH7110_SYSCLK_OSC,
+ JH7110_SYSCLK_QSPI_REF_SRC),
/* sdio */
- JH71X0_GATE(JH7110_SYSCLK_SDIO0_AHB, "sdio0_ahb", 0, JH7110_SYSCLK_AHB0),
- JH71X0_GATE(JH7110_SYSCLK_SDIO1_AHB, "sdio1_ahb", 0, JH7110_SYSCLK_AHB0),
- JH71X0_GDIV(JH7110_SYSCLK_SDIO0_SDCARD, "sdio0_sdcard", 0, 15, JH7110_SYSCLK_AXI_CFG0),
- JH71X0_GDIV(JH7110_SYSCLK_SDIO1_SDCARD, "sdio1_sdcard", 0, 15, JH7110_SYSCLK_AXI_CFG0),
+ STARFIVE_GATE(JH7110_SYSCLK_SDIO0_AHB, "sdio0_ahb", 0, JH7110_SYSCLK_AHB0),
+ STARFIVE_GATE(JH7110_SYSCLK_SDIO1_AHB, "sdio1_ahb", 0, JH7110_SYSCLK_AHB0),
+ STARFIVE_GDIV(JH7110_SYSCLK_SDIO0_SDCARD, "sdio0_sdcard", 0, 15, JH7110_SYSCLK_AXI_CFG0),
+ STARFIVE_GDIV(JH7110_SYSCLK_SDIO1_SDCARD, "sdio1_sdcard", 0, 15, JH7110_SYSCLK_AXI_CFG0),
/* stg */
- JH71X0__DIV(JH7110_SYSCLK_USB_125M, "usb_125m", 15, JH7110_SYSCLK_PLL0_OUT),
- JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_STG_AXI, "noc_bus_stg_axi", CLK_IS_CRITICAL,
- JH7110_SYSCLK_NOCSTG_BUS),
+ STARFIVE__DIV(JH7110_SYSCLK_USB_125M, "usb_125m", 15, JH7110_SYSCLK_PLL0_OUT),
+ STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_STG_AXI, "noc_bus_stg_axi", CLK_IS_CRITICAL,
+ JH7110_SYSCLK_NOCSTG_BUS),
/* gmac1 */
- JH71X0_GATE(JH7110_SYSCLK_GMAC1_AHB, "gmac1_ahb", 0, JH7110_SYSCLK_AHB0),
- JH71X0_GATE(JH7110_SYSCLK_GMAC1_AXI, "gmac1_axi", 0, JH7110_SYSCLK_STG_AXIAHB),
- JH71X0__DIV(JH7110_SYSCLK_GMAC_SRC, "gmac_src", 7, JH7110_SYSCLK_PLL0_OUT),
- JH71X0__DIV(JH7110_SYSCLK_GMAC1_GTXCLK, "gmac1_gtxclk", 15, JH7110_SYSCLK_PLL0_OUT),
- JH71X0__DIV(JH7110_SYSCLK_GMAC1_RMII_RTX, "gmac1_rmii_rtx", 30,
- JH7110_SYSCLK_GMAC1_RMII_REFIN),
- JH71X0_GDIV(JH7110_SYSCLK_GMAC1_PTP, "gmac1_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC),
- JH71X0__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 2,
- JH7110_SYSCLK_GMAC1_RGMII_RXIN,
- JH7110_SYSCLK_GMAC1_RMII_RTX),
- JH71X0__INV(JH7110_SYSCLK_GMAC1_RX_INV, "gmac1_rx_inv", JH7110_SYSCLK_GMAC1_RX),
- JH71X0_GMUX(JH7110_SYSCLK_GMAC1_TX, "gmac1_tx",
- CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2,
- JH7110_SYSCLK_GMAC1_GTXCLK,
- JH7110_SYSCLK_GMAC1_RMII_RTX),
- JH71X0__INV(JH7110_SYSCLK_GMAC1_TX_INV, "gmac1_tx_inv", JH7110_SYSCLK_GMAC1_TX),
- JH71X0_GATE(JH7110_SYSCLK_GMAC1_GTXC, "gmac1_gtxc", 0, JH7110_SYSCLK_GMAC1_GTXCLK),
+ STARFIVE_GATE(JH7110_SYSCLK_GMAC1_AHB, "gmac1_ahb", 0, JH7110_SYSCLK_AHB0),
+ STARFIVE_GATE(JH7110_SYSCLK_GMAC1_AXI, "gmac1_axi", 0, JH7110_SYSCLK_STG_AXIAHB),
+ STARFIVE__DIV(JH7110_SYSCLK_GMAC_SRC, "gmac_src", 7, JH7110_SYSCLK_PLL0_OUT),
+ STARFIVE__DIV(JH7110_SYSCLK_GMAC1_GTXCLK, "gmac1_gtxclk", 15, JH7110_SYSCLK_PLL0_OUT),
+ STARFIVE__DIV(JH7110_SYSCLK_GMAC1_RMII_RTX, "gmac1_rmii_rtx", 30,
+ JH7110_SYSCLK_GMAC1_RMII_REFIN),
+ STARFIVE_GDIV(JH7110_SYSCLK_GMAC1_PTP, "gmac1_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC),
+ STARFIVE__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 2,
+ JH7110_SYSCLK_GMAC1_RGMII_RXIN,
+ JH7110_SYSCLK_GMAC1_RMII_RTX),
+ STARFIVE__INV(JH7110_SYSCLK_GMAC1_RX_INV, "gmac1_rx_inv", JH7110_SYSCLK_GMAC1_RX),
+ STARFIVE_GMUX(JH7110_SYSCLK_GMAC1_TX, "gmac1_tx",
+ CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2,
+ JH7110_SYSCLK_GMAC1_GTXCLK,
+ JH7110_SYSCLK_GMAC1_RMII_RTX),
+ STARFIVE__INV(JH7110_SYSCLK_GMAC1_TX_INV, "gmac1_tx_inv", JH7110_SYSCLK_GMAC1_TX),
+ STARFIVE_GATE(JH7110_SYSCLK_GMAC1_GTXC, "gmac1_gtxc", 0, JH7110_SYSCLK_GMAC1_GTXCLK),
/* gmac0 */
- JH71X0_GDIV(JH7110_SYSCLK_GMAC0_GTXCLK, "gmac0_gtxclk", 0, 15, JH7110_SYSCLK_PLL0_OUT),
- JH71X0_GDIV(JH7110_SYSCLK_GMAC0_PTP, "gmac0_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC),
- JH71X0_GDIV(JH7110_SYSCLK_GMAC_PHY, "gmac_phy", 0, 31, JH7110_SYSCLK_GMAC_SRC),
- JH71X0_GATE(JH7110_SYSCLK_GMAC0_GTXC, "gmac0_gtxc", 0, JH7110_SYSCLK_GMAC0_GTXCLK),
+ STARFIVE_GDIV(JH7110_SYSCLK_GMAC0_GTXCLK, "gmac0_gtxclk", 0, 15, JH7110_SYSCLK_PLL0_OUT),
+ STARFIVE_GDIV(JH7110_SYSCLK_GMAC0_PTP, "gmac0_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC),
+ STARFIVE_GDIV(JH7110_SYSCLK_GMAC_PHY, "gmac_phy", 0, 31, JH7110_SYSCLK_GMAC_SRC),
+ STARFIVE_GATE(JH7110_SYSCLK_GMAC0_GTXC, "gmac0_gtxc", 0, JH7110_SYSCLK_GMAC0_GTXCLK),
/* apb misc */
- JH71X0_GATE(JH7110_SYSCLK_IOMUX_APB, "iomux_apb", 0, JH7110_SYSCLK_APB_BUS),
- JH71X0_GATE(JH7110_SYSCLK_MAILBOX_APB, "mailbox_apb", 0, JH7110_SYSCLK_APB_BUS),
- JH71X0_GATE(JH7110_SYSCLK_INT_CTRL_APB, "int_ctrl_apb", 0, JH7110_SYSCLK_APB_BUS),
+ STARFIVE_GATE(JH7110_SYSCLK_IOMUX_APB, "iomux_apb", 0, JH7110_SYSCLK_APB_BUS),
+ STARFIVE_GATE(JH7110_SYSCLK_MAILBOX_APB, "mailbox_apb", 0, JH7110_SYSCLK_APB_BUS),
+ STARFIVE_GATE(JH7110_SYSCLK_INT_CTRL_APB, "int_ctrl_apb", 0, JH7110_SYSCLK_APB_BUS),
/* can0 */
- JH71X0_GATE(JH7110_SYSCLK_CAN0_APB, "can0_apb", 0, JH7110_SYSCLK_APB_BUS),
- JH71X0_GDIV(JH7110_SYSCLK_CAN0_TIMER, "can0_timer", 0, 24, JH7110_SYSCLK_OSC),
- JH71X0_GDIV(JH7110_SYSCLK_CAN0_CAN, "can0_can", 0, 63, JH7110_SYSCLK_PERH_ROOT),
+ STARFIVE_GATE(JH7110_SYSCLK_CAN0_APB, "can0_apb", 0, JH7110_SYSCLK_APB_BUS),
+ STARFIVE_GDIV(JH7110_SYSCLK_CAN0_TIMER, "can0_timer", 0, 24, JH7110_SYSCLK_OSC),
+ STARFIVE_GDIV(JH7110_SYSCLK_CAN0_CAN, "can0_can", 0, 63, JH7110_SYSCLK_PERH_ROOT),
/* can1 */
- JH71X0_GATE(JH7110_SYSCLK_CAN1_APB, "can1_apb", 0, JH7110_SYSCLK_APB_BUS),
- JH71X0_GDIV(JH7110_SYSCLK_CAN1_TIMER, "can1_timer", 0, 24, JH7110_SYSCLK_OSC),
- JH71X0_GDIV(JH7110_SYSCLK_CAN1_CAN, "can1_can", 0, 63, JH7110_SYSCLK_PERH_ROOT),
+ STARFIVE_GATE(JH7110_SYSCLK_CAN1_APB, "can1_apb", 0, JH7110_SYSCLK_APB_BUS),
+ STARFIVE_GDIV(JH7110_SYSCLK_CAN1_TIMER, "can1_timer", 0, 24, JH7110_SYSCLK_OSC),
+ STARFIVE_GDIV(JH7110_SYSCLK_CAN1_CAN, "can1_can", 0, 63, JH7110_SYSCLK_PERH_ROOT),
/* pwm */
- JH71X0_GATE(JH7110_SYSCLK_PWM_APB, "pwm_apb", 0, JH7110_SYSCLK_APB_BUS),
+ STARFIVE_GATE(JH7110_SYSCLK_PWM_APB, "pwm_apb", 0, JH7110_SYSCLK_APB_BUS),
/* wdt */
- JH71X0_GATE(JH7110_SYSCLK_WDT_APB, "wdt_apb", 0, JH7110_SYSCLK_APB_BUS),
- JH71X0_GATE(JH7110_SYSCLK_WDT_CORE, "wdt_core", 0, JH7110_SYSCLK_OSC),
+ STARFIVE_GATE(JH7110_SYSCLK_WDT_APB, "wdt_apb", 0, JH7110_SYSCLK_APB_BUS),
+ STARFIVE_GATE(JH7110_SYSCLK_WDT_CORE, "wdt_core", 0, JH7110_SYSCLK_OSC),
/* timer */
- JH71X0_GATE(JH7110_SYSCLK_TIMER_APB, "timer_apb", 0, JH7110_SYSCLK_APB_BUS),
- JH71X0_GATE(JH7110_SYSCLK_TIMER0, "timer0", 0, JH7110_SYSCLK_OSC),
- JH71X0_GATE(JH7110_SYSCLK_TIMER1, "timer1", 0, JH7110_SYSCLK_OSC),
- JH71X0_GATE(JH7110_SYSCLK_TIMER2, "timer2", 0, JH7110_SYSCLK_OSC),
- JH71X0_GATE(JH7110_SYSCLK_TIMER3, "timer3", 0, JH7110_SYSCLK_OSC),
+ STARFIVE_GATE(JH7110_SYSCLK_TIMER_APB, "timer_apb", 0, JH7110_SYSCLK_APB_BUS),
+ STARFIVE_GATE(JH7110_SYSCLK_TIMER0, "timer0", 0, JH7110_SYSCLK_OSC),
+ STARFIVE_GATE(JH7110_SYSCLK_TIMER1, "timer1", 0, JH7110_SYSCLK_OSC),
+ STARFIVE_GATE(JH7110_SYSCLK_TIMER2, "timer2", 0, JH7110_SYSCLK_OSC),
+ STARFIVE_GATE(JH7110_SYSCLK_TIMER3, "timer3", 0, JH7110_SYSCLK_OSC),
/* temp sensor */
- JH71X0_GATE(JH7110_SYSCLK_TEMP_APB, "temp_apb", 0, JH7110_SYSCLK_APB_BUS),
- JH71X0_GDIV(JH7110_SYSCLK_TEMP_CORE, "temp_core", 0, 24, JH7110_SYSCLK_OSC),
+ STARFIVE_GATE(JH7110_SYSCLK_TEMP_APB, "temp_apb", 0, JH7110_SYSCLK_APB_BUS),
+ STARFIVE_GDIV(JH7110_SYSCLK_TEMP_CORE, "temp_core", 0, 24, JH7110_SYSCLK_OSC),
/* spi */
- JH71X0_GATE(JH7110_SYSCLK_SPI0_APB, "spi0_apb", 0, JH7110_SYSCLK_APB0),
- JH71X0_GATE(JH7110_SYSCLK_SPI1_APB, "spi1_apb", 0, JH7110_SYSCLK_APB0),
- JH71X0_GATE(JH7110_SYSCLK_SPI2_APB, "spi2_apb", 0, JH7110_SYSCLK_APB0),
- JH71X0_GATE(JH7110_SYSCLK_SPI3_APB, "spi3_apb", 0, JH7110_SYSCLK_APB_BUS),
- JH71X0_GATE(JH7110_SYSCLK_SPI4_APB, "spi4_apb", 0, JH7110_SYSCLK_APB_BUS),
- JH71X0_GATE(JH7110_SYSCLK_SPI5_APB, "spi5_apb", 0, JH7110_SYSCLK_APB_BUS),
- JH71X0_GATE(JH7110_SYSCLK_SPI6_APB, "spi6_apb", 0, JH7110_SYSCLK_APB_BUS),
+ STARFIVE_GATE(JH7110_SYSCLK_SPI0_APB, "spi0_apb", 0, JH7110_SYSCLK_APB0),
+ STARFIVE_GATE(JH7110_SYSCLK_SPI1_APB, "spi1_apb", 0, JH7110_SYSCLK_APB0),
+ STARFIVE_GATE(JH7110_SYSCLK_SPI2_APB, "spi2_apb", 0, JH7110_SYSCLK_APB0),
+ STARFIVE_GATE(JH7110_SYSCLK_SPI3_APB, "spi3_apb", 0, JH7110_SYSCLK_APB_BUS),
+ STARFIVE_GATE(JH7110_SYSCLK_SPI4_APB, "spi4_apb", 0, JH7110_SYSCLK_APB_BUS),
+ STARFIVE_GATE(JH7110_SYSCLK_SPI5_APB, "spi5_apb", 0, JH7110_SYSCLK_APB_BUS),
+ STARFIVE_GATE(JH7110_SYSCLK_SPI6_APB, "spi6_apb", 0, JH7110_SYSCLK_APB_BUS),
/* i2c */
- JH71X0_GATE(JH7110_SYSCLK_I2C0_APB, "i2c0_apb", 0, JH7110_SYSCLK_APB0),
- JH71X0_GATE(JH7110_SYSCLK_I2C1_APB, "i2c1_apb", 0, JH7110_SYSCLK_APB0),
- JH71X0_GATE(JH7110_SYSCLK_I2C2_APB, "i2c2_apb", 0, JH7110_SYSCLK_APB0),
- JH71X0_GATE(JH7110_SYSCLK_I2C3_APB, "i2c3_apb", 0, JH7110_SYSCLK_APB_BUS),
- JH71X0_GATE(JH7110_SYSCLK_I2C4_APB, "i2c4_apb", 0, JH7110_SYSCLK_APB_BUS),
- JH71X0_GATE(JH7110_SYSCLK_I2C5_APB, "i2c5_apb", 0, JH7110_SYSCLK_APB_BUS),
- JH71X0_GATE(JH7110_SYSCLK_I2C6_APB, "i2c6_apb", 0, JH7110_SYSCLK_APB_BUS),
+ STARFIVE_GATE(JH7110_SYSCLK_I2C0_APB, "i2c0_apb", 0, JH7110_SYSCLK_APB0),
+ STARFIVE_GATE(JH7110_SYSCLK_I2C1_APB, "i2c1_apb", 0, JH7110_SYSCLK_APB0),
+ STARFIVE_GATE(JH7110_SYSCLK_I2C2_APB, "i2c2_apb", 0, JH7110_SYSCLK_APB0),
+ STARFIVE_GATE(JH7110_SYSCLK_I2C3_APB, "i2c3_apb", 0, JH7110_SYSCLK_APB_BUS),
+ STARFIVE_GATE(JH7110_SYSCLK_I2C4_APB, "i2c4_apb", 0, JH7110_SYSCLK_APB_BUS),
+ STARFIVE_GATE(JH7110_SYSCLK_I2C5_APB, "i2c5_apb", 0, JH7110_SYSCLK_APB_BUS),
+ STARFIVE_GATE(JH7110_SYSCLK_I2C6_APB, "i2c6_apb", 0, JH7110_SYSCLK_APB_BUS),
/* uart */
- JH71X0_GATE(JH7110_SYSCLK_UART0_APB, "uart0_apb", 0, JH7110_SYSCLK_APB0),
- JH71X0_GATE(JH7110_SYSCLK_UART0_CORE, "uart0_core", 0, JH7110_SYSCLK_OSC),
- JH71X0_GATE(JH7110_SYSCLK_UART1_APB, "uart1_apb", 0, JH7110_SYSCLK_APB0),
- JH71X0_GATE(JH7110_SYSCLK_UART1_CORE, "uart1_core", 0, JH7110_SYSCLK_OSC),
- JH71X0_GATE(JH7110_SYSCLK_UART2_APB, "uart2_apb", 0, JH7110_SYSCLK_APB0),
- JH71X0_GATE(JH7110_SYSCLK_UART2_CORE, "uart2_core", 0, JH7110_SYSCLK_OSC),
- JH71X0_GATE(JH7110_SYSCLK_UART3_APB, "uart3_apb", 0, JH7110_SYSCLK_APB0),
- JH71X0_GDIV(JH7110_SYSCLK_UART3_CORE, "uart3_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
- JH71X0_GATE(JH7110_SYSCLK_UART4_APB, "uart4_apb", 0, JH7110_SYSCLK_APB0),
- JH71X0_GDIV(JH7110_SYSCLK_UART4_CORE, "uart4_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
- JH71X0_GATE(JH7110_SYSCLK_UART5_APB, "uart5_apb", 0, JH7110_SYSCLK_APB0),
- JH71X0_GDIV(JH7110_SYSCLK_UART5_CORE, "uart5_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
+ STARFIVE_GATE(JH7110_SYSCLK_UART0_APB, "uart0_apb", 0, JH7110_SYSCLK_APB0),
+ STARFIVE_GATE(JH7110_SYSCLK_UART0_CORE, "uart0_core", 0, JH7110_SYSCLK_OSC),
+ STARFIVE_GATE(JH7110_SYSCLK_UART1_APB, "uart1_apb", 0, JH7110_SYSCLK_APB0),
+ STARFIVE_GATE(JH7110_SYSCLK_UART1_CORE, "uart1_core", 0, JH7110_SYSCLK_OSC),
+ STARFIVE_GATE(JH7110_SYSCLK_UART2_APB, "uart2_apb", 0, JH7110_SYSCLK_APB0),
+ STARFIVE_GATE(JH7110_SYSCLK_UART2_CORE, "uart2_core", 0, JH7110_SYSCLK_OSC),
+ STARFIVE_GATE(JH7110_SYSCLK_UART3_APB, "uart3_apb", 0, JH7110_SYSCLK_APB0),
+ STARFIVE_GDIV(JH7110_SYSCLK_UART3_CORE, "uart3_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
+ STARFIVE_GATE(JH7110_SYSCLK_UART4_APB, "uart4_apb", 0, JH7110_SYSCLK_APB0),
+ STARFIVE_GDIV(JH7110_SYSCLK_UART4_CORE, "uart4_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
+ STARFIVE_GATE(JH7110_SYSCLK_UART5_APB, "uart5_apb", 0, JH7110_SYSCLK_APB0),
+ STARFIVE_GDIV(JH7110_SYSCLK_UART5_CORE, "uart5_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
/* pwmdac */
- JH71X0_GATE(JH7110_SYSCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7110_SYSCLK_APB0),
- JH71X0_GDIV(JH7110_SYSCLK_PWMDAC_CORE, "pwmdac_core", 0, 256, JH7110_SYSCLK_AUDIO_ROOT),
+ STARFIVE_GATE(JH7110_SYSCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7110_SYSCLK_APB0),
+ STARFIVE_GDIV(JH7110_SYSCLK_PWMDAC_CORE, "pwmdac_core", 0, 256, JH7110_SYSCLK_AUDIO_ROOT),
/* spdif */
- JH71X0_GATE(JH7110_SYSCLK_SPDIF_APB, "spdif_apb", 0, JH7110_SYSCLK_APB0),
- JH71X0_GATE(JH7110_SYSCLK_SPDIF_CORE, "spdif_core", 0, JH7110_SYSCLK_MCLK),
+ STARFIVE_GATE(JH7110_SYSCLK_SPDIF_APB, "spdif_apb", 0, JH7110_SYSCLK_APB0),
+ STARFIVE_GATE(JH7110_SYSCLK_SPDIF_CORE, "spdif_core", 0, JH7110_SYSCLK_MCLK),
/* i2stx0 */
- JH71X0_GATE(JH7110_SYSCLK_I2STX0_APB, "i2stx0_apb", 0, JH7110_SYSCLK_APB0),
- JH71X0_GDIV(JH7110_SYSCLK_I2STX0_BCLK_MST, "i2stx0_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
- JH71X0__INV(JH7110_SYSCLK_I2STX0_BCLK_MST_INV, "i2stx0_bclk_mst_inv",
- JH7110_SYSCLK_I2STX0_BCLK_MST),
- JH71X0_MDIV(JH7110_SYSCLK_I2STX0_LRCK_MST, "i2stx0_lrck_mst", 64, 2,
- JH7110_SYSCLK_I2STX0_BCLK_MST_INV,
- JH7110_SYSCLK_I2STX0_BCLK_MST),
- JH71X0__MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk", 2,
- JH7110_SYSCLK_I2STX0_BCLK_MST,
- JH7110_SYSCLK_I2STX_BCLK_EXT),
- JH71X0__INV(JH7110_SYSCLK_I2STX0_BCLK_INV, "i2stx0_bclk_inv", JH7110_SYSCLK_I2STX0_BCLK),
- JH71X0__MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", 2,
- JH7110_SYSCLK_I2STX0_LRCK_MST,
- JH7110_SYSCLK_I2STX_LRCK_EXT),
+ STARFIVE_GATE(JH7110_SYSCLK_I2STX0_APB, "i2stx0_apb", 0, JH7110_SYSCLK_APB0),
+ STARFIVE_GDIV(JH7110_SYSCLK_I2STX0_BCLK_MST, "i2stx0_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
+ STARFIVE__INV(JH7110_SYSCLK_I2STX0_BCLK_MST_INV, "i2stx0_bclk_mst_inv",
+ JH7110_SYSCLK_I2STX0_BCLK_MST),
+ STARFIVE_MDIV(JH7110_SYSCLK_I2STX0_LRCK_MST, "i2stx0_lrck_mst", 64, 2,
+ JH7110_SYSCLK_I2STX0_BCLK_MST_INV,
+ JH7110_SYSCLK_I2STX0_BCLK_MST),
+ STARFIVE__MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk", 2,
+ JH7110_SYSCLK_I2STX0_BCLK_MST,
+ JH7110_SYSCLK_I2STX_BCLK_EXT),
+ STARFIVE__INV(JH7110_SYSCLK_I2STX0_BCLK_INV, "i2stx0_bclk_inv", JH7110_SYSCLK_I2STX0_BCLK),
+ STARFIVE__MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", 2,
+ JH7110_SYSCLK_I2STX0_LRCK_MST,
+ JH7110_SYSCLK_I2STX_LRCK_EXT),
/* i2stx1 */
- JH71X0_GATE(JH7110_SYSCLK_I2STX1_APB, "i2stx1_apb", 0, JH7110_SYSCLK_APB0),
- JH71X0_GDIV(JH7110_SYSCLK_I2STX1_BCLK_MST, "i2stx1_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
- JH71X0__INV(JH7110_SYSCLK_I2STX1_BCLK_MST_INV, "i2stx1_bclk_mst_inv",
- JH7110_SYSCLK_I2STX1_BCLK_MST),
- JH71X0_MDIV(JH7110_SYSCLK_I2STX1_LRCK_MST, "i2stx1_lrck_mst", 64, 2,
- JH7110_SYSCLK_I2STX1_BCLK_MST_INV,
- JH7110_SYSCLK_I2STX1_BCLK_MST),
- JH71X0__MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", 2,
- JH7110_SYSCLK_I2STX1_BCLK_MST,
- JH7110_SYSCLK_I2STX_BCLK_EXT),
- JH71X0__INV(JH7110_SYSCLK_I2STX1_BCLK_INV, "i2stx1_bclk_inv", JH7110_SYSCLK_I2STX1_BCLK),
- JH71X0__MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", 2,
- JH7110_SYSCLK_I2STX1_LRCK_MST,
- JH7110_SYSCLK_I2STX_LRCK_EXT),
+ STARFIVE_GATE(JH7110_SYSCLK_I2STX1_APB, "i2stx1_apb", 0, JH7110_SYSCLK_APB0),
+ STARFIVE_GDIV(JH7110_SYSCLK_I2STX1_BCLK_MST, "i2stx1_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
+ STARFIVE__INV(JH7110_SYSCLK_I2STX1_BCLK_MST_INV, "i2stx1_bclk_mst_inv",
+ JH7110_SYSCLK_I2STX1_BCLK_MST),
+ STARFIVE_MDIV(JH7110_SYSCLK_I2STX1_LRCK_MST, "i2stx1_lrck_mst", 64, 2,
+ JH7110_SYSCLK_I2STX1_BCLK_MST_INV,
+ JH7110_SYSCLK_I2STX1_BCLK_MST),
+ STARFIVE__MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", 2,
+ JH7110_SYSCLK_I2STX1_BCLK_MST,
+ JH7110_SYSCLK_I2STX_BCLK_EXT),
+ STARFIVE__INV(JH7110_SYSCLK_I2STX1_BCLK_INV, "i2stx1_bclk_inv", JH7110_SYSCLK_I2STX1_BCLK),
+ STARFIVE__MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", 2,
+ JH7110_SYSCLK_I2STX1_LRCK_MST,
+ JH7110_SYSCLK_I2STX_LRCK_EXT),
/* i2srx */
- JH71X0_GATE(JH7110_SYSCLK_I2SRX_APB, "i2srx_apb", 0, JH7110_SYSCLK_APB0),
- JH71X0_GDIV(JH7110_SYSCLK_I2SRX_BCLK_MST, "i2srx_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
- JH71X0__INV(JH7110_SYSCLK_I2SRX_BCLK_MST_INV, "i2srx_bclk_mst_inv",
- JH7110_SYSCLK_I2SRX_BCLK_MST),
- JH71X0_MDIV(JH7110_SYSCLK_I2SRX_LRCK_MST, "i2srx_lrck_mst", 64, 2,
- JH7110_SYSCLK_I2SRX_BCLK_MST_INV,
- JH7110_SYSCLK_I2SRX_BCLK_MST),
- JH71X0__MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", 2,
- JH7110_SYSCLK_I2SRX_BCLK_MST,
- JH7110_SYSCLK_I2SRX_BCLK_EXT),
- JH71X0__INV(JH7110_SYSCLK_I2SRX_BCLK_INV, "i2srx_bclk_inv", JH7110_SYSCLK_I2SRX_BCLK),
- JH71X0__MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", 2,
- JH7110_SYSCLK_I2SRX_LRCK_MST,
- JH7110_SYSCLK_I2SRX_LRCK_EXT),
+ STARFIVE_GATE(JH7110_SYSCLK_I2SRX_APB, "i2srx_apb", 0, JH7110_SYSCLK_APB0),
+ STARFIVE_GDIV(JH7110_SYSCLK_I2SRX_BCLK_MST, "i2srx_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
+ STARFIVE__INV(JH7110_SYSCLK_I2SRX_BCLK_MST_INV, "i2srx_bclk_mst_inv",
+ JH7110_SYSCLK_I2SRX_BCLK_MST),
+ STARFIVE_MDIV(JH7110_SYSCLK_I2SRX_LRCK_MST, "i2srx_lrck_mst", 64, 2,
+ JH7110_SYSCLK_I2SRX_BCLK_MST_INV,
+ JH7110_SYSCLK_I2SRX_BCLK_MST),
+ STARFIVE__MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", 2,
+ JH7110_SYSCLK_I2SRX_BCLK_MST,
+ JH7110_SYSCLK_I2SRX_BCLK_EXT),
+ STARFIVE__INV(JH7110_SYSCLK_I2SRX_BCLK_INV, "i2srx_bclk_inv", JH7110_SYSCLK_I2SRX_BCLK),
+ STARFIVE__MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", 2,
+ JH7110_SYSCLK_I2SRX_LRCK_MST,
+ JH7110_SYSCLK_I2SRX_LRCK_EXT),
/* pdm */
- JH71X0_GDIV(JH7110_SYSCLK_PDM_DMIC, "pdm_dmic", 0, 64, JH7110_SYSCLK_MCLK),
- JH71X0_GATE(JH7110_SYSCLK_PDM_APB, "pdm_apb", 0, JH7110_SYSCLK_APB0),
+ STARFIVE_GDIV(JH7110_SYSCLK_PDM_DMIC, "pdm_dmic", 0, 64, JH7110_SYSCLK_MCLK),
+ STARFIVE_GATE(JH7110_SYSCLK_PDM_APB, "pdm_apb", 0, JH7110_SYSCLK_APB0),
/* tdm */
- JH71X0_GATE(JH7110_SYSCLK_TDM_AHB, "tdm_ahb", 0, JH7110_SYSCLK_AHB0),
- JH71X0_GATE(JH7110_SYSCLK_TDM_APB, "tdm_apb", 0, JH7110_SYSCLK_APB0),
- JH71X0_GDIV(JH7110_SYSCLK_TDM_INTERNAL, "tdm_internal", 0, 64, JH7110_SYSCLK_MCLK),
- JH71X0__MUX(JH7110_SYSCLK_TDM_TDM, "tdm_tdm", 2,
- JH7110_SYSCLK_TDM_INTERNAL,
- JH7110_SYSCLK_TDM_EXT),
- JH71X0__INV(JH7110_SYSCLK_TDM_TDM_INV, "tdm_tdm_inv", JH7110_SYSCLK_TDM_TDM),
+ STARFIVE_GATE(JH7110_SYSCLK_TDM_AHB, "tdm_ahb", 0, JH7110_SYSCLK_AHB0),
+ STARFIVE_GATE(JH7110_SYSCLK_TDM_APB, "tdm_apb", 0, JH7110_SYSCLK_APB0),
+ STARFIVE_GDIV(JH7110_SYSCLK_TDM_INTERNAL, "tdm_internal", 0, 64, JH7110_SYSCLK_MCLK),
+ STARFIVE__MUX(JH7110_SYSCLK_TDM_TDM, "tdm_tdm", 2,
+ JH7110_SYSCLK_TDM_INTERNAL,
+ JH7110_SYSCLK_TDM_EXT),
+ STARFIVE__INV(JH7110_SYSCLK_TDM_TDM_INV, "tdm_tdm_inv", JH7110_SYSCLK_TDM_TDM),
/* jtag */
- JH71X0__DIV(JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG, "jtag_certification_trng", 4,
- JH7110_SYSCLK_OSC),
+ STARFIVE__DIV(JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG, "jtag_certification_trng", 4,
+ JH7110_SYSCLK_OSC),
};
static struct clk_hw *jh7110_sysclk_get(struct of_phandle_args *clkspec, void *data)
{
- struct jh71x0_clk_priv *priv = data;
+ struct starfive_clk_priv *priv = data;
unsigned int idx = clkspec->args[0];
if (idx < JH7110_SYSCLK_END)
@@ -350,7 +353,7 @@ static void jh7110_reset_adev_release(struct device *dev)
kfree(rdev);
}
-int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
+int jh7110_reset_controller_register(struct starfive_clk_priv *priv,
const char *adev_name,
u32 adev_id)
{
@@ -387,7 +390,7 @@ EXPORT_SYMBOL_GPL(jh7110_reset_controller_register);
static int __init jh7110_syscrg_probe(struct platform_device *pdev)
{
- struct jh71x0_clk_priv *priv;
+ struct starfive_clk_priv *priv;
unsigned int idx;
int ret;
struct clk *pllclk;
@@ -446,13 +449,13 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev)
struct clk_parent_data parents[4] = {};
struct clk_init_data init = {
.name = jh7110_sysclk_data[idx].name,
- .ops = starfive_jh71x0_clk_ops(max),
+ .ops = starfive_clk_ops(max),
.parent_data = parents,
.num_parents =
- ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
+ ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
.flags = jh7110_sysclk_data[idx].flags,
};
- struct jh71x0_clk *clk = &priv->reg[idx];
+ struct starfive_clk *clk = &priv->reg[idx];
unsigned int i;
for (i = 0; i < init.num_parents; i++) {
@@ -490,7 +493,7 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev)
clk->hw.init = &init;
clk->idx = idx;
- clk->max_div = max & JH71X0_CLK_DIV_MASK;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
if (ret)
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-vout.c b/drivers/clk/starfive/clk-starfive-jh7110-vout.c
index 10cc1ec43925..aca93c370bce 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-vout.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-vout.c
@@ -30,45 +30,45 @@ static struct clk_bulk_data jh7110_vout_top_clks[] = {
{ .id = "vout_top_ahb" }
};
-static const struct jh71x0_clk_data jh7110_voutclk_data[] = {
+static const struct starfive_clk_data jh7110_voutclk_data[] = {
/* divider */
- JH71X0__DIV(JH7110_VOUTCLK_APB, "apb", 8, JH7110_VOUTCLK_VOUT_TOP_AHB),
- JH71X0__DIV(JH7110_VOUTCLK_DC8200_PIX, "dc8200_pix", 63, JH7110_VOUTCLK_VOUT_SRC),
- JH71X0__DIV(JH7110_VOUTCLK_DSI_SYS, "dsi_sys", 31, JH7110_VOUTCLK_VOUT_SRC),
- JH71X0__DIV(JH7110_VOUTCLK_TX_ESC, "tx_esc", 31, JH7110_VOUTCLK_VOUT_TOP_AHB),
+ STARFIVE__DIV(JH7110_VOUTCLK_APB, "apb", 8, JH7110_VOUTCLK_VOUT_TOP_AHB),
+ STARFIVE__DIV(JH7110_VOUTCLK_DC8200_PIX, "dc8200_pix", 63, JH7110_VOUTCLK_VOUT_SRC),
+ STARFIVE__DIV(JH7110_VOUTCLK_DSI_SYS, "dsi_sys", 31, JH7110_VOUTCLK_VOUT_SRC),
+ STARFIVE__DIV(JH7110_VOUTCLK_TX_ESC, "tx_esc", 31, JH7110_VOUTCLK_VOUT_TOP_AHB),
/* dc8200 */
- JH71X0_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
- JH71X0_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
- JH71X0_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0, JH7110_VOUTCLK_VOUT_TOP_AHB),
- JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0, 2,
- JH7110_VOUTCLK_DC8200_PIX,
- JH7110_VOUTCLK_HDMITX0_PIXELCLK),
- JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0, 2,
- JH7110_VOUTCLK_DC8200_PIX,
- JH7110_VOUTCLK_HDMITX0_PIXELCLK),
+ STARFIVE_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
+ STARFIVE_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
+ STARFIVE_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0, JH7110_VOUTCLK_VOUT_TOP_AHB),
+ STARFIVE_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0, 2,
+ JH7110_VOUTCLK_DC8200_PIX,
+ JH7110_VOUTCLK_HDMITX0_PIXELCLK),
+ STARFIVE_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0, 2,
+ JH7110_VOUTCLK_DC8200_PIX,
+ JH7110_VOUTCLK_HDMITX0_PIXELCLK),
/* LCD */
- JH71X0_GMUX(JH7110_VOUTCLK_DOM_VOUT_TOP_LCD, "dom_vout_top_lcd", 0, 2,
- JH7110_VOUTCLK_DC8200_PIX0,
- JH7110_VOUTCLK_DC8200_PIX1),
+ STARFIVE_GMUX(JH7110_VOUTCLK_DOM_VOUT_TOP_LCD, "dom_vout_top_lcd", 0, 2,
+ JH7110_VOUTCLK_DC8200_PIX0,
+ JH7110_VOUTCLK_DC8200_PIX1),
/* dsiTx */
- JH71X0_GATE(JH7110_VOUTCLK_DSITX_APB, "dsiTx_apb", 0, JH7110_VOUTCLK_DSI_SYS),
- JH71X0_GATE(JH7110_VOUTCLK_DSITX_SYS, "dsiTx_sys", 0, JH7110_VOUTCLK_DSI_SYS),
- JH71X0_GMUX(JH7110_VOUTCLK_DSITX_DPI, "dsiTx_dpi", 0, 2,
- JH7110_VOUTCLK_DC8200_PIX,
- JH7110_VOUTCLK_HDMITX0_PIXELCLK),
- JH71X0_GATE(JH7110_VOUTCLK_DSITX_TXESC, "dsiTx_txesc", 0, JH7110_VOUTCLK_TX_ESC),
+ STARFIVE_GATE(JH7110_VOUTCLK_DSITX_APB, "dsiTx_apb", 0, JH7110_VOUTCLK_DSI_SYS),
+ STARFIVE_GATE(JH7110_VOUTCLK_DSITX_SYS, "dsiTx_sys", 0, JH7110_VOUTCLK_DSI_SYS),
+ STARFIVE_GMUX(JH7110_VOUTCLK_DSITX_DPI, "dsiTx_dpi", 0, 2,
+ JH7110_VOUTCLK_DC8200_PIX,
+ JH7110_VOUTCLK_HDMITX0_PIXELCLK),
+ STARFIVE_GATE(JH7110_VOUTCLK_DSITX_TXESC, "dsiTx_txesc", 0, JH7110_VOUTCLK_TX_ESC),
/* mipitx DPHY */
- JH71X0_GATE(JH7110_VOUTCLK_MIPITX_DPHY_TXESC, "mipitx_dphy_txesc", 0,
- JH7110_VOUTCLK_TX_ESC),
+ STARFIVE_GATE(JH7110_VOUTCLK_MIPITX_DPHY_TXESC, "mipitx_dphy_txesc", 0,
+ JH7110_VOUTCLK_TX_ESC),
/* hdmi */
- JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_MCLK, "hdmi_tx_mclk", 0,
- JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK),
- JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_BCLK, "hdmi_tx_bclk", 0,
- JH7110_VOUTCLK_I2STX0_BCLK),
- JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_SYS, "hdmi_tx_sys", 0, JH7110_VOUTCLK_APB),
+ STARFIVE_GATE(JH7110_VOUTCLK_HDMI_TX_MCLK, "hdmi_tx_mclk", 0,
+ JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK),
+ STARFIVE_GATE(JH7110_VOUTCLK_HDMI_TX_BCLK, "hdmi_tx_bclk", 0,
+ JH7110_VOUTCLK_I2STX0_BCLK),
+ STARFIVE_GATE(JH7110_VOUTCLK_HDMI_TX_SYS, "hdmi_tx_sys", 0, JH7110_VOUTCLK_APB),
};
-static int jh7110_vout_top_rst_init(struct jh71x0_clk_priv *priv)
+static int jh7110_vout_top_rst_init(struct starfive_clk_priv *priv)
{
struct reset_control *top_rst;
@@ -82,7 +82,7 @@ static int jh7110_vout_top_rst_init(struct jh71x0_clk_priv *priv)
static struct clk_hw *jh7110_voutclk_get(struct of_phandle_args *clkspec, void *data)
{
- struct jh71x0_clk_priv *priv = data;
+ struct starfive_clk_priv *priv = data;
unsigned int idx = clkspec->args[0];
if (idx < JH7110_VOUTCLK_END)
@@ -115,7 +115,7 @@ static const struct dev_pm_ops jh7110_voutcrg_pm_ops = {
static int jh7110_voutcrg_probe(struct platform_device *pdev)
{
- struct jh71x0_clk_priv *priv;
+ struct starfive_clk_priv *priv;
struct jh7110_top_sysclk *top;
unsigned int idx;
int ret;
@@ -158,13 +158,13 @@ static int jh7110_voutcrg_probe(struct platform_device *pdev)
struct clk_parent_data parents[4] = {};
struct clk_init_data init = {
.name = jh7110_voutclk_data[idx].name,
- .ops = starfive_jh71x0_clk_ops(max),
+ .ops = starfive_clk_ops(max),
.parent_data = parents,
.num_parents =
- ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
+ ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
.flags = jh7110_voutclk_data[idx].flags,
};
- struct jh71x0_clk *clk = &priv->reg[idx];
+ struct starfive_clk *clk = &priv->reg[idx];
unsigned int i;
const char *fw_name[JH7110_VOUTCLK_EXT_END - JH7110_VOUTCLK_END] = {
"vout_src",
@@ -186,7 +186,7 @@ static int jh7110_voutcrg_probe(struct platform_device *pdev)
clk->hw.init = &init;
clk->idx = idx;
- clk->max_div = max & JH71X0_CLK_DIV_MASK;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
if (ret)
diff --git a/drivers/clk/starfive/clk-starfive-jh7110.h b/drivers/clk/starfive/clk-starfive-jh7110.h
index 6b1bdf860f00..4a6dfd8d8636 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110.h
+++ b/drivers/clk/starfive/clk-starfive-jh7110.h
@@ -10,7 +10,7 @@ struct jh7110_top_sysclk {
int top_clks_num;
};
-int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
+int jh7110_reset_controller_register(struct starfive_clk_priv *priv,
const char *adev_name,
u32 adev_id);
--
2.34.1
Add support for JH8100 System clock generator.
Signed-off-by: Sia Jee Heng <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
---
MAINTAINERS | 8 +
drivers/clk/starfive/Kconfig | 9 +
drivers/clk/starfive/Makefile | 1 +
drivers/clk/starfive/clk-starfive-common.h | 9 +-
drivers/clk/starfive/jh8100/Makefile | 3 +
.../clk/starfive/jh8100/clk-starfive-jh8100.h | 11 +
drivers/clk/starfive/jh8100/clk-sys.c | 455 ++++++++++++++++++
7 files changed, 495 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/starfive/jh8100/Makefile
create mode 100644 drivers/clk/starfive/jh8100/clk-starfive-jh8100.h
create mode 100644 drivers/clk/starfive/jh8100/clk-sys.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 788be9ab5b73..87bcb25becc1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20763,6 +20763,14 @@ F: Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
F: drivers/phy/starfive/phy-jh7110-pcie.c
F: drivers/phy/starfive/phy-jh7110-usb.c
+STARFIVE JH8100 CLOCK DRIVERS
+M: Sia Jee Heng <[email protected]>
+M: Ley Foon Tan <[email protected]>
+S: Maintained
+F: Documentation/devicetree/bindings/clock/starfive,jh81*.yaml
+F: drivers/clk/starfive/jh8100
+F: include/dt-bindings/clock/starfive?jh81*.h
+
STATIC BRANCH/CALL
M: Peter Zijlstra <[email protected]>
M: Josh Poimboeuf <[email protected]>
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index ff8eace36e64..d8c7b9bb3895 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -72,3 +72,12 @@ config CLK_STARFIVE_JH7110_VOUT
help
Say yes here to support the Video-Output clock controller
on the StarFive JH7110 SoC.
+
+config CLK_STARFIVE_JH8100_SYS
+ bool "StarFive JH8100 System clock support"
+ depends on SOC_STARFIVE || COMPILE_TEST
+ select AUXILIARY_BUS
+ select CLK_STARFIVE_COMMON
+ default ARCH_STARFIVE
+ help
+ Say yes here to support the System clock controller on the StarFive JH8100 SoC.
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 012f7ee83f8e..6cb3ce823330 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
+obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS) += jh8100/
diff --git a/drivers/clk/starfive/clk-starfive-common.h b/drivers/clk/starfive/clk-starfive-common.h
index fed45311360c..ec30af0658cf 100644
--- a/drivers/clk/starfive/clk-starfive-common.h
+++ b/drivers/clk/starfive/clk-starfive-common.h
@@ -103,6 +103,13 @@ struct starfive_clk_data {
.parents = { [0] = _parent }, \
}
+#define STARFIVE_GINV(_idx, _name, _flags, _parent)[_idx] = { \
+ .name = _name, \
+ .flags = _flags, \
+ .max = STARFIVE_CLK_ENABLE | STARFIVE_CLK_INVERT, \
+ .parents = { [0] = _parent }, \
+}
+
struct starfive_clk {
struct clk_hw hw;
unsigned int idx;
@@ -114,7 +121,7 @@ struct starfive_clk_priv {
spinlock_t rmw_lock;
struct device *dev;
void __iomem *base;
- struct clk_hw *pll[3];
+ struct clk_hw *pll[8];
struct starfive_clk reg[];
};
diff --git a/drivers/clk/starfive/jh8100/Makefile b/drivers/clk/starfive/jh8100/Makefile
new file mode 100644
index 000000000000..af6a09e220d3
--- /dev/null
+++ b/drivers/clk/starfive/jh8100/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+# StarFive JH8100 Clock
+obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS) += clk-sys.o
diff --git a/drivers/clk/starfive/jh8100/clk-starfive-jh8100.h b/drivers/clk/starfive/jh8100/clk-starfive-jh8100.h
new file mode 100644
index 000000000000..7c8249c11464
--- /dev/null
+++ b/drivers/clk/starfive/jh8100/clk-starfive-jh8100.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __CLK_STARFIVE_JH8100_H
+#define __CLK_STARFIVE_JH8100_H
+
+#include "../clk-starfive-common.h"
+
+int jh8100_reset_controller_register(struct starfive_clk_priv *priv,
+ const char *adev_name,
+ u32 adev_id);
+
+#endif
diff --git a/drivers/clk/starfive/jh8100/clk-sys.c b/drivers/clk/starfive/jh8100/clk-sys.c
new file mode 100644
index 000000000000..e2c802523c7d
--- /dev/null
+++ b/drivers/clk/starfive/jh8100/clk-sys.c
@@ -0,0 +1,455 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH8100 System Clock Driver
+ *
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ *
+ * Author: Jee Heng Sia <[email protected]>
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/auxiliary_bus.h>
+#include <linux/clk-provider.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <soc/starfive/reset-starfive-common.h>
+
+#include <dt-bindings/clock/starfive,jh8100-crg.h>
+
+#include "clk-starfive-jh8100.h"
+
+/* external clocks */
+#define SYSCRG_CLK_OSC (SYSCRG_CLK_END + 0)
+#define SYSCRG_CLK_MCLK_EXT (SYSCRG_CLK_END + 1)
+#define SYSCRG_CLK_PLL0_OUT (SYSCRG_CLK_END + 2)
+#define SYSCRG_CLK_PLL1_OUT (SYSCRG_CLK_END + 3)
+#define SYSCRG_CLK_PLL2_OUT (SYSCRG_CLK_END + 4)
+#define SYSCRG_CLK_PLL3_OUT (SYSCRG_CLK_END + 5)
+#define SYSCRG_CLK_PLL4_OUT (SYSCRG_CLK_END + 6)
+#define SYSCRG_CLK_PLL6_OUT (SYSCRG_CLK_END + 7)
+#define SYSCRG_CLK_PLL7_OUT (SYSCRG_CLK_END + 8)
+
+static const struct starfive_clk_data jh8100_syscrg_clk_data[] __initconst = {
+ /* root */
+ STARFIVE__DIV(SYSCRG_CLK_VDEC_ROOT_PREOSC, "sys_clk_vdec_root_preosc", 10,
+ SYSCRG_CLK_PLL7_OUT),
+ STARFIVE__MUX(SYSCRG_CLK_VDEC_ROOT, "sys_clk_vdec_root", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_VDEC_ROOT_PREOSC),
+ STARFIVE__DIV(SYSCRG_CLK_VENC_ROOT_PREOSC, "sys_clk_venc_root_preosc", 10,
+ SYSCRG_CLK_PLL7_OUT),
+ STARFIVE__MUX(SYSCRG_CLK_VENC_ROOT, "sys_clk_venc_root", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_VENC_ROOT_PREOSC),
+ STARFIVE__DIV(SYSCRG_CLK_GPU_ROOT, "sys_clk_gpu_root", 7,
+ SYSCRG_CLK_PLL0_OUT),
+ STARFIVE__MUX(SYSCRG_CLK_GPU_CORE, "sys_clk_gpu_core", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_GPU_ROOT),
+ STARFIVE__DIV(SYSCRG_CLK_VOUT_ROOT0_PREOSC, "sys_clk_vout_root0_preosc", 127,
+ SYSCRG_CLK_PLL1_OUT),
+ STARFIVE__MUX(SYSCRG_CLK_VOUT_ROOT0, "sys_clk_vout_root0", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_VOUT_ROOT0_PREOSC),
+ STARFIVE__DIV(SYSCRG_CLK_VOUT_ROOT1_PREOSC, "sys_clk_vout_root1_preosc", 127,
+ SYSCRG_CLK_PLL6_OUT),
+ STARFIVE__MUX(SYSCRG_CLK_VOUT_ROOT1, "sys_clk_vout_root1", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_VOUT_ROOT1_PREOSC),
+ STARFIVE__DIV(SYSCRG_CLK_VOUT_SCAN_ATS, "sys_clk_vout_scan_ats", 6,
+ SYSCRG_CLK_PLL3_OUT),
+ STARFIVE__DIV(SYSCRG_CLK_PERH_ROOT_PREOSC, "sys_clk_perh_root_preosc", 4,
+ SYSCRG_CLK_PLL0_OUT),
+ STARFIVE__MUX(SYSCRG_CLK_PERH_ROOT, "sys_clk_perh_root", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_PERH_ROOT_PREOSC),
+ STARFIVE__DIV(SYSCRG_CLK_AXI_200_PREOSC, "sys_clk_axi_200_preosc", 4,
+ SYSCRG_CLK_PLL0_OUT),
+ STARFIVE__MUX(SYSCRG_CLK_AXI_200, "sys_clk_axi_200", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_200_PREOSC),
+ STARFIVE__MUX(SYSCRG_CLK_AXI_200_GMAC, "sys_clk_axi_200_gmac", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_200_PREOSC),
+ STARFIVE__DIV(SYSCRG_CLK_AXI_500_PREOSC, "sys_clk_axi_500_preosc", 10,
+ SYSCRG_CLK_PLL0_OUT),
+ STARFIVE__MUX(SYSCRG_CLK_AXI_500, "sys_clk_axi_500", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_500_PREOSC),
+ STARFIVE__MUX(SYSCRG_CLK_AXI_500_PCIEX1A, "sys_clk_axi_500_pciex1a", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_500_PREOSC),
+ STARFIVE__MUX(SYSCRG_CLK_AXI_500_PCIEX1B, "sys_clk_axi_500_pciex1b", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_500_PREOSC),
+ STARFIVE__MUX(SYSCRG_CLK_AXI_500_PCIEX2, "sys_clk_axi_500_pciex2", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_500_PREOSC),
+ STARFIVE__MUX(SYSCRG_CLK_AXI_500_PCIEX8, "sys_clk_axi_500_pciex8", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_500_PREOSC),
+ STARFIVE__DIV(SYSCRG_CLK_AXI_400_PREOSC, "sys_clk_axi_400_preosc", 10,
+ SYSCRG_CLK_PLL0_OUT),
+ STARFIVE__MUX(SYSCRG_CLK_AXI_400, "sys_clk_axi_400", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_400_PREOSC),
+ STARFIVE__MUX(SYSCRG_CLK_AXI_400_APBOOTRAM, "sys_clk_axi_400_apbootram", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_400_PREOSC),
+ STARFIVE__DIV(SYSCRG_CLK_AXI_125_PREOSC, "sys_clk_axi_125_preosc", 32,
+ SYSCRG_CLK_PLL0_OUT),
+ STARFIVE__MUX(SYSCRG_CLK_AXI_125, "sys_clk_axi_125", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_125_PREOSC),
+ STARFIVE__DIV(SYSCRG_CLK_AHB0_PREOSC, "sys_clk_ahb0_preosc", 15,
+ SYSCRG_CLK_PLL0_OUT),
+ STARFIVE__MUX(SYSCRG_CLK_AHB0, "sys_clk_ahb0", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_AHB0_PREOSC),
+ STARFIVE__DIV(SYSCRG_CLK_APB_BUS_FUNC, "sys_clk_apb_bus_func", 30,
+ SYSCRG_CLK_PLL0_OUT),
+ STARFIVE__MUX(SYSCRG_CLK_APB_BUS, "sys_clk_apb_bus", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
+ STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER0, "sys_clk_apb_bus_per0", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
+ STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER1, "sys_clk_apb_bus_per1", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
+ STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER2, "sys_clk_apb_bus_per2", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
+ STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER3, "sys_clk_apb_bus_per3", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
+ STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER4, "sys_clk_apb_bus_per4", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
+ STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER5, "sys_clk_apb_bus_per5", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
+ STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER6, "sys_clk_apb_bus_per6", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
+ STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER7, "sys_clk_apb_bus_per7", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
+ STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER8, "sys_clk_apb_bus_per8", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
+ STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER9, "sys_clk_apb_bus_per9", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
+ STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER10, "sys_clk_apb_bus_per10", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
+ STARFIVE__MUX(SYSCRG_CLK_SPI_CORE_100, "sys_clk_spi_core_100", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
+ STARFIVE__DIV(SYSCRG_CLK_PLL1_DIV2, "sys_clk_pll1_div2", 2,
+ SYSCRG_CLK_PLL1_OUT),
+ STARFIVE__DIV(SYSCRG_CLK_PLL2_DIV2, "sys_clk_pll2_div2", 2,
+ SYSCRG_CLK_PLL2_OUT),
+ STARFIVE__DIV(SYSCRG_CLK_PLL3_DIV2, "sys_clk_pll3_div2", 2,
+ SYSCRG_CLK_PLL3_OUT),
+ STARFIVE__DIV(SYSCRG_CLK_PLL4_DIV2, "sys_clk_pll4_div2", 2,
+ SYSCRG_CLK_PLL4_OUT),
+ STARFIVE__DIV(SYSCRG_CLK_PLL6_DIV2, "sys_clk_pll6_div2", 2,
+ SYSCRG_CLK_PLL6_OUT),
+ STARFIVE__DIV(SYSCRG_CLK_PLL7_DIV2, "sys_clk_pll7_div2", 2,
+ SYSCRG_CLK_PLL7_OUT),
+ STARFIVE__DIV(SYSCRG_CLK_AUDIO_ROOT, "sys_clk_audio_root", 8,
+ SYSCRG_CLK_PLL2_OUT),
+ STARFIVE__DIV(SYSCRG_CLK_MCLK_INNER, "sys_clk_mclk_inner", 64,
+ SYSCRG_CLK_AUDIO_ROOT),
+ STARFIVE__MUX(SYSCRG_CLK_MCLK, "sys_clk_mclk", 2,
+ SYSCRG_CLK_MCLK_INNER, SYSCRG_CLK_MCLK_EXT),
+ STARFIVE_GATE(SYSCRG_CLK_MCLK_OUT, "sys_clk_mclk_out", 0,
+ SYSCRG_CLK_MCLK_INNER),
+ STARFIVE_MDIV(SYSCRG_CLK_ISP_2X_PREOSC, "sys_clk_isp_2x_preosc", 8, 2,
+ SYSCRG_CLK_PLL7_OUT, SYSCRG_CLK_PLL0_OUT),
+ STARFIVE__MUX(SYSCRG_CLK_ISP_2X, "sys_clk_isp_2x", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_ISP_2X_PREOSC),
+ STARFIVE__DIV(SYSCRG_CLK_ISP_AXI, "sys_clk_isp_axi", 4,
+ SYSCRG_CLK_ISP_2X),
+ STARFIVE_GDIV(SYSCRG_CLK_GCLK1, "sys_clk_gclk1", CLK_IS_CRITICAL, 120,
+ SYSCRG_CLK_PLL1_DIV2),
+ STARFIVE_GDIV(SYSCRG_CLK_GCLK2, "sys_clk_gclk2", CLK_IS_CRITICAL, 120,
+ SYSCRG_CLK_PLL2_DIV2),
+ STARFIVE_GDIV(SYSCRG_CLK_GCLK3, "sys_clk_gclk3", CLK_IS_CRITICAL, 120,
+ SYSCRG_CLK_PLL3_DIV2),
+ STARFIVE_GDIV(SYSCRG_CLK_GCLK4, "sys_clk_gclk4", CLK_IS_CRITICAL, 120,
+ SYSCRG_CLK_PLL4_DIV2),
+ STARFIVE_GDIV(SYSCRG_CLK_GCLK6, "sys_clk_gclk6", CLK_IS_CRITICAL, 120,
+ SYSCRG_CLK_PLL6_DIV2),
+ STARFIVE_GDIV(SYSCRG_CLK_GCLK7, "sys_clk_gclk7", CLK_IS_CRITICAL, 120,
+ SYSCRG_CLK_PLL7_DIV2),
+ /* flexnoc (se) */
+ STARFIVE__DIV(SYSCRG_CLK_FLEXNOC0_PREOSC, "sys_clk_flexnoc0_preosc", 8,
+ SYSCRG_CLK_PLL0_OUT),
+ STARFIVE__MUX(SYSCRG_CLK_FLEXNOC0, "sys_clk_flexnoc0", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_FLEXNOC0_PREOSC),
+ STARFIVE__DIV(SYSCRG_CLK_FLEXNOC1_PREOSC, "sys_clk_flexnoc1_preosc", 8,
+ SYSCRG_CLK_PLL0_OUT),
+ STARFIVE__MUX(SYSCRG_CLK_FLEXNOC1, "sys_clk_flexnoc1", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_FLEXNOC1_PREOSC),
+ STARFIVE__DIV(SYSCRG_CLK_FLEXNOC2_PREOSC, "sys_clk_flexnoc2_preosc", 12,
+ SYSCRG_CLK_PLL0_OUT),
+ STARFIVE__MUX(SYSCRG_CLK_FLEXNOC2, "sys_clk_flexnoc2", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_FLEXNOC2_PREOSC),
+ STARFIVE__MUX(SYSCRG_CLK_VDEC_CORE, "sys_clk_vdec_core", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_FLEXNOC1_PREOSC),
+ /* img_gpu (se) */
+ STARFIVE_GATE(SYSCRG_CLK_GPU_CORE_ICG, "sys_clk_gpu_core_icg", 0,
+ SYSCRG_CLK_GPU_CORE),
+ STARFIVE_GATE(SYSCRG_CLK_IMG_GPU_CLK_APB, "sys_clk_img_gpu_clk_apb", 0,
+ SYSCRG_CLK_APB_BUS_PER7),
+ STARFIVE_GATE(SYSCRG_CLK_IMG_GPU_RTC_TOGGLE, "sys_clk_img_gpu_rtc_toggle", 0,
+ SYSCRG_CLK_OSC),
+ STARFIVE_GATE(SYSCRG_CLK_IMG_GPU_TIMER_USC, "sys_clk_img_gpu_timer_usc", 0,
+ SYSCRG_CLK_OSC),
+ /* hifi4 (se) */
+ STARFIVE__DIV(SYSCRG_CLK_HIFI4_CORE_PREOSC, "sys_clk_hifi4_core_preosc", 15,
+ SYSCRG_CLK_PLL0_OUT),
+ STARFIVE__MUX(SYSCRG_CLK_HIFI4_CORE, "sys_clk_hifi4_core", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_HIFI4_CORE_PREOSC),
+ /* espi */
+ STARFIVE__DIV(SYSCRG_CLK_ESPI_200_PREOSC, "sys_clk_espi_200_preosc", 2,
+ SYSCRG_CLK_PLL0_OUT),
+ STARFIVE__MUX(SYSCRG_CLK_ESPI_200, "sys_clk_espi_200", 2,
+ SYSCRG_CLK_OSC, SYSCRG_CLK_ESPI_200_PREOSC),
+ /* hd audio */
+ STARFIVE__DIV(SYSCRG_CLK_HD_AUDIO_48M, "sys_clk_hd_audio_48m", 80,
+ SYSCRG_CLK_PLL7_OUT),
+ /* dom vout */
+ STARFIVE__DIV(SYSCRG_CLK_VOUT_DC_CORE, "sys_clk_vout_dc_core", 10,
+ SYSCRG_CLK_PLL7_OUT),
+ STARFIVE__DIV(SYSCRG_CLK_VOUT_AXI, "sys_clk_vout_axi", 10,
+ SYSCRG_CLK_PLL7_OUT),
+ /* stg2_usb_wrap (se) */
+ STARFIVE__DIV(SYSCRG_CLK_USB_WRAP_625, "sys_clk_usb_wrap_625", 6,
+ SYSCRG_CLK_PLL0_OUT),
+ STARFIVE__DIV(SYSCRG_CLK_USB_WRAP_480, "sys_clk_usb_wrap_480", 8,
+ SYSCRG_CLK_PLL0_OUT),
+ STARFIVE__DIV(SYSCRG_CLK_USB_WRAP_240, "sys_clk_usb_wrap_240", 2,
+ SYSCRG_CLK_USB_WRAP_480),
+ STARFIVE__DIV(SYSCRG_CLK_USB_WRAP_60, "sys_clk_usb_wrap_60", 10,
+ SYSCRG_CLK_USB_WRAP_480),
+ STARFIVE__DIV(SYSCRG_CLK_USB_WRAP_156P25, "sys_clk_usb_wrap_156p25", 4,
+ SYSCRG_CLK_USB_WRAP_625),
+ STARFIVE__DIV(SYSCRG_CLK_USB_WRAP_312P5, "sys_clk_usb_wrap_312p5", 2,
+ SYSCRG_CLK_USB_WRAP_625),
+ /* stg */
+ STARFIVE__DIV(SYSCRG_CLK_USB_125M, "sys_clk_usb_125m", 32,
+ SYSCRG_CLK_PLL0_OUT),
+ /* Flexnoc (se) */
+ STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_APBOOTRAM, "sys_clk_flexnoc_apbootram",
+ CLK_IS_CRITICAL, SYSCRG_CLK_AXI_400_APBOOTRAM),
+ STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_PCIEX1AMST, "sys_clk_flexnoc_pciex1amst",
+ CLK_IS_CRITICAL, SYSCRG_CLK_AXI_500_PCIEX1A),
+ STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_PCIEX1ASLV, "sys_clk_flexnoc_pciex1aslv",
+ CLK_IS_CRITICAL, SYSCRG_CLK_AXI_500_PCIEX1A),
+ STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_PCIEX1BMST, "sys_clk_flexnoc_pciex1bmst",
+ CLK_IS_CRITICAL, SYSCRG_CLK_AXI_500_PCIEX1B),
+ STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_PCIEX1BSLV, "sys_clk_flexnoc_pciex1bslv",
+ CLK_IS_CRITICAL, SYSCRG_CLK_AXI_500_PCIEX1B),
+ STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_PCIEX2MST, "sys_clk_flexnoc_pciex2mst",
+ CLK_IS_CRITICAL, SYSCRG_CLK_AXI_500_PCIEX2),
+ STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_PCIEX2SLV, "sys_clk_flexnoc_pciex2slv",
+ CLK_IS_CRITICAL, SYSCRG_CLK_AXI_500_PCIEX2),
+ STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_PCIEX8MST, "sys_clk_flexnoc_pciex8mst",
+ CLK_IS_CRITICAL, SYSCRG_CLK_AXI_500_PCIEX8),
+ STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_PCIEX8SLV, "sys_clk_flexnoc_pciex8slv",
+ CLK_IS_CRITICAL, SYSCRG_CLK_AXI_500_PCIEX8),
+ STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_GMACSYSSLV, "sys_clk_flexnoc_gmacsysslv",
+ CLK_IS_CRITICAL, SYSCRG_CLK_AXI_200_GMAC),
+ /* gmac1 (se) */
+ STARFIVE__DIV(SYSCRG_CLK_GMAC_SRC, "sys_clk_gmac_src", 7,
+ SYSCRG_CLK_PLL0_OUT),
+ STARFIVE__DIV(SYSCRG_CLK_GMAC1_GTXCLK_TOP, "sys_clk_gmac1_gtxclk_top", 400,
+ SYSCRG_CLK_PLL0_OUT),
+ STARFIVE__DIV(SYSCRG_CLK_GMAC1_PTP, "sys_clk_gmac1_ptp", 31,
+ SYSCRG_CLK_GMAC_SRC),
+ /* hd audio */
+ STARFIVE_GATE(SYSCRG_CLK_HD_AUDIO_SYSTEM_CLOCK, "sys_clk_hd_audio_system_clock",
+ 0, SYSCRG_CLK_APB_BUS_PER7),
+ STARFIVE_GATE(SYSCRG_CLK_HD_AUDIO_CLOCK_48, "sys_clk_hd_audio_clock_48",
+ 0, SYSCRG_CLK_HD_AUDIO_48M),
+ STARFIVE_GATE(SYSCRG_CLK_HD_AUDIO_BCLK_POST_OCC_IN, "sys_clk_hd_audio_bclk_post_occ_in",
+ 0, SYSCRG_CLK_HD_AUDIO_48M),
+ /* nne_vip (se) */
+ STARFIVE_GATE(SYSCRG_CLK_NNE_VIP_ACLK, "sys_clk_nne_vip_aclk",
+ 0, SYSCRG_CLK_AXI_500),
+ STARFIVE_GATE(SYSCRG_CLK_NNE_VIP_HCLK, "sys_clk_nne_vip_hclk",
+ 0, SYSCRG_CLK_AXI_200),
+ STARFIVE_GMUX(SYSCRG_CLK_NNE_VIP_CLKCORE, "sys_clk_nne_vip_clkcore", 0, 2,
+ SYSCRG_CLK_PLL2_OUT,
+ SYSCRG_CLK_PLL0_OUT),
+ /* icg_en */
+ STARFIVE_GATE(SYSCRG_CLK_GPU_ICG_EN, "sys_clk_gpu_en",
+ 0, SYSCRG_CLK_GPU_CORE),
+ STARFIVE_GATE(SYSCRG_CLK_HD_AUDIO_ICG_EN, "sys_clk_hd_audio_en",
+ 0, SYSCRG_CLK_APB_BUS),
+ STARFIVE_GATE(SYSCRG_CLK_NNE_ICG_EN, "sys_clk_nne_en",
+ CLK_IGNORE_UNUSED, SYSCRG_CLK_PLL2_OUT),
+};
+
+static struct clk_hw *jh8100_sysclk_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct starfive_clk_priv *priv = data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx < SYSCRG_CLK_END)
+ return &priv->reg[idx].hw;
+
+ return ERR_PTR(-EINVAL);
+}
+
+static void jh8100_reset_unregister_adev(void *_adev)
+{
+ struct auxiliary_device *adev = _adev;
+
+ auxiliary_device_delete(adev);
+ auxiliary_device_uninit(adev);
+}
+
+static void jh8100_reset_adev_release(struct device *dev)
+{
+ struct auxiliary_device *adev = to_auxiliary_dev(dev);
+ struct starfive_reset_adev *rdev = to_starfive_reset_adev(adev);
+
+ kfree(rdev);
+}
+
+int jh8100_reset_controller_register(struct starfive_clk_priv *priv,
+ const char *adev_name,
+ u32 adev_id)
+{
+ struct starfive_reset_adev *rdev;
+ struct auxiliary_device *adev;
+ int ret;
+
+ rdev = kzalloc(sizeof(*rdev), GFP_KERNEL);
+ if (!rdev)
+ return -ENOMEM;
+
+ rdev->base = priv->base;
+
+ adev = &rdev->adev;
+ adev->name = adev_name;
+ adev->dev.parent = priv->dev;
+ adev->dev.release = jh8100_reset_adev_release;
+ adev->id = adev_id;
+
+ ret = auxiliary_device_init(adev);
+ if (ret)
+ return ret;
+
+ ret = auxiliary_device_add(adev);
+ if (ret) {
+ auxiliary_device_uninit(adev);
+ return ret;
+ }
+
+ return devm_add_action_or_reset(priv->dev,
+ jh8100_reset_unregister_adev, adev);
+}
+EXPORT_SYMBOL_GPL(jh8100_reset_controller_register);
+
+static int __init jh8100_syscrg_probe(struct platform_device *pdev)
+{
+ struct starfive_clk_priv *priv;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, reg, SYSCRG_CLK_END),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ /* 24MHz -> 2000.0MHz */
+ priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "clk_pll0_out",
+ "clk_osc", 0, 250, 3);
+ if (IS_ERR(priv->pll[0]))
+ return PTR_ERR(priv->pll[0]);
+
+ /* 24MHz -> 1782.0MHz */
+ priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "clk_pll1_out",
+ "clk_osc", 0, 445, 6);
+ if (IS_ERR(priv->pll[1]))
+ return PTR_ERR(priv->pll[1]);
+
+ /* 24MHz -> 1843.2MHz */
+ priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "clk_pll2_out",
+ "clk_osc", 0, 767, 10);
+ if (IS_ERR(priv->pll[2]))
+ return PTR_ERR(priv->pll[2]);
+
+ /* 24MHz -> 1866MHz */
+ priv->pll[3] = devm_clk_hw_register_fixed_factor(priv->dev, "clk_pll3_out",
+ "clk_osc", 0, 4665, 60);
+ if (IS_ERR(priv->pll[3]))
+ return PTR_ERR(priv->pll[3]);
+
+ /* 24MHz -> 2000MHz */
+ priv->pll[4] = devm_clk_hw_register_fixed_factor(priv->dev, "clk_pll4_out",
+ "clk_osc", 0, 250, 3);
+ if (IS_ERR(priv->pll[4]))
+ return PTR_ERR(priv->pll[4]);
+
+ /* 24MHz -> 1782MHz */
+ priv->pll[5] = devm_clk_hw_register_fixed_factor(priv->dev, "clk_pll6_out",
+ "clk_osc", 0, 445, 6);
+ if (IS_ERR(priv->pll[5]))
+ return PTR_ERR(priv->pll[5]);
+
+ /* 24MHz -> 2400MHz */
+ priv->pll[6] = devm_clk_hw_register_fixed_factor(priv->dev, "clk_pll7_out",
+ "clk_osc", 0, 100, 1);
+ if (IS_ERR(priv->pll[6]))
+ return PTR_ERR(priv->pll[6]);
+
+ for (idx = 0; idx < SYSCRG_CLK_END; idx++) {
+ u32 max = jh8100_syscrg_clk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jh8100_syscrg_clk_data[idx].name,
+ .ops = starfive_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
+ .flags = jh8100_syscrg_clk_data[idx].flags,
+ };
+ struct starfive_clk *clk = &priv->reg[idx];
+ unsigned int i;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jh8100_syscrg_clk_data[idx].parents[i];
+
+ if (pidx < SYSCRG_CLK_END)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx == SYSCRG_CLK_OSC)
+ parents[i].fw_name = "clk_osc";
+ else if (pidx == SYSCRG_CLK_MCLK_EXT)
+ parents[i].fw_name = "clk_mclk_ext";
+ else if (pidx == SYSCRG_CLK_PLL1_OUT && !priv->pll[1])
+ parents[i].fw_name = "clk_pll1_out";
+ else if (pidx == SYSCRG_CLK_PLL2_OUT && !priv->pll[2])
+ parents[i].fw_name = "clk_pll2_out";
+ else if (pidx == SYSCRG_CLK_PLL6_OUT && !priv->pll[5])
+ parents[i].fw_name = "clk_pll6_out";
+ else
+ parents[i].hw = priv->pll[pidx - SYSCRG_CLK_PLL0_OUT];
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, jh8100_sysclk_get, priv);
+ if (ret)
+ return ret;
+
+ return jh8100_reset_controller_register(priv, "rst-sys", 0);
+}
+
+static const struct of_device_id jh8100_syscrg_match[] = {
+ { .compatible = "starfive,jh8100-syscrg" },
+ { /* sentinel */ }
+};
+
+static struct platform_driver jh8100_syscrg_driver = {
+ .driver = {
+ .name = "clk-starfive-jh8100-sys",
+ .of_match_table = jh8100_syscrg_match,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver_probe(jh8100_syscrg_driver, jh8100_syscrg_probe);
--
2.34.1
StarFive JH8100 shares a similar clock and reset design with JH7110.
To facilitate the reuse of the file and its functionalities, files
containing the "jh71x0" naming convention are renamed to use the
"common" wording.
Signed-off-by: Sia Jee Heng <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
---
drivers/clk/starfive/Kconfig | 8 ++++----
drivers/clk/starfive/Makefile | 2 +-
.../{clk-starfive-jh71x0.c => clk-starfive-common.c} | 4 ++--
.../{clk-starfive-jh71x0.h => clk-starfive-common.h} | 4 ++--
drivers/clk/starfive/clk-starfive-jh7100-audio.c | 2 +-
drivers/clk/starfive/clk-starfive-jh7100.c | 2 +-
drivers/clk/starfive/clk-starfive-jh7110.h | 2 +-
7 files changed, 12 insertions(+), 12 deletions(-)
rename drivers/clk/starfive/{clk-starfive-jh71x0.c => clk-starfive-common.c} (99%)
rename drivers/clk/starfive/{clk-starfive-jh71x0.h => clk-starfive-common.h} (97%)
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index bd29358ffeec..ff8eace36e64 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -1,12 +1,12 @@
# SPDX-License-Identifier: GPL-2.0
-config CLK_STARFIVE_JH71X0
+config CLK_STARFIVE_COMMON
bool
config CLK_STARFIVE_JH7100
bool "StarFive JH7100 clock support"
depends on ARCH_STARFIVE || COMPILE_TEST
- select CLK_STARFIVE_JH71X0
+ select CLK_STARFIVE_COMMON
default ARCH_STARFIVE
help
Say yes here to support the clock controller on the StarFive JH7100
@@ -15,7 +15,7 @@ config CLK_STARFIVE_JH7100
config CLK_STARFIVE_JH7100_AUDIO
tristate "StarFive JH7100 audio clock support"
depends on CLK_STARFIVE_JH7100
- select CLK_STARFIVE_JH71X0
+ select CLK_STARFIVE_COMMON
default m if ARCH_STARFIVE
help
Say Y or M here to support the audio clocks on the StarFive JH7100
@@ -33,7 +33,7 @@ config CLK_STARFIVE_JH7110_SYS
bool "StarFive JH7110 system clock support"
depends on ARCH_STARFIVE || COMPILE_TEST
select AUXILIARY_BUS
- select CLK_STARFIVE_JH71X0
+ select CLK_STARFIVE_COMMON
select RESET_STARFIVE_JH7110 if RESET_CONTROLLER
select CLK_STARFIVE_JH7110_PLL
default ARCH_STARFIVE
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 199ac0f37a2f..012f7ee83f8e 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_CLK_STARFIVE_JH71X0) += clk-starfive-jh71x0.o
+obj-$(CONFIG_CLK_STARFIVE_COMMON) += clk-starfive-common.o
obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o
obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o
diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.c b/drivers/clk/starfive/clk-starfive-common.c
similarity index 99%
rename from drivers/clk/starfive/clk-starfive-jh71x0.c
rename to drivers/clk/starfive/clk-starfive-common.c
index aebc99264a0b..a12490c97957 100644
--- a/drivers/clk/starfive/clk-starfive-jh71x0.c
+++ b/drivers/clk/starfive/clk-starfive-common.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * StarFive JH71X0 Clock Generator Driver
+ * StarFive Clock Generator Driver
*
* Copyright (C) 2021-2022 Emil Renner Berthing <[email protected]>
*/
@@ -10,7 +10,7 @@
#include <linux/device.h>
#include <linux/io.h>
-#include "clk-starfive-jh71x0.h"
+#include "clk-starfive-common.h"
static struct jh71x0_clk *jh71x0_clk_from(struct clk_hw *hw)
{
diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.h b/drivers/clk/starfive/clk-starfive-common.h
similarity index 97%
rename from drivers/clk/starfive/clk-starfive-jh71x0.h
rename to drivers/clk/starfive/clk-starfive-common.h
index 34bb11c72eb7..1f32f7024e9f 100644
--- a/drivers/clk/starfive/clk-starfive-jh71x0.h
+++ b/drivers/clk/starfive/clk-starfive-common.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __CLK_STARFIVE_JH71X0_H
-#define __CLK_STARFIVE_JH71X0_H
+#ifndef __CLK_STARFIVE_COMMON_H
+#define __CLK_STARFIVE_COMMON_H
#include <linux/bits.h>
#include <linux/clk-provider.h>
diff --git a/drivers/clk/starfive/clk-starfive-jh7100-audio.c b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
index ee4bda14a40e..dc4c278606d7 100644
--- a/drivers/clk/starfive/clk-starfive-jh7100-audio.c
+++ b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
@@ -15,7 +15,7 @@
#include <dt-bindings/clock/starfive-jh7100-audio.h>
-#include "clk-starfive-jh71x0.h"
+#include "clk-starfive-common.h"
/* external clocks */
#define JH7100_AUDCLK_AUDIO_SRC (JH7100_AUDCLK_END + 0)
diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c
index 69cc11ea7e33..6bb6a6af9f28 100644
--- a/drivers/clk/starfive/clk-starfive-jh7100.c
+++ b/drivers/clk/starfive/clk-starfive-jh7100.c
@@ -15,7 +15,7 @@
#include <dt-bindings/clock/starfive-jh7100.h>
-#include "clk-starfive-jh71x0.h"
+#include "clk-starfive-common.h"
/* external clocks */
#define JH7100_CLK_OSC_SYS (JH7100_CLK_END + 0)
diff --git a/drivers/clk/starfive/clk-starfive-jh7110.h b/drivers/clk/starfive/clk-starfive-jh7110.h
index 0659adae4d76..6b1bdf860f00 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110.h
+++ b/drivers/clk/starfive/clk-starfive-jh7110.h
@@ -2,7 +2,7 @@
#ifndef __CLK_STARFIVE_JH7110_H
#define __CLK_STARFIVE_JH7110_H
-#include "clk-starfive-jh71x0.h"
+#include "clk-starfive-common.h"
/* top clocks of ISP/VOUT domain from JH7110 SYSCRG */
struct jh7110_top_sysclk {
--
2.34.1
Add support for JH8100 System-North-West clock generator.
Signed-off-by: Sia Jee Heng <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
---
drivers/clk/starfive/Kconfig | 8 +
drivers/clk/starfive/jh8100/Makefile | 1 +
drivers/clk/starfive/jh8100/clk-sys-nw.c | 268 +++++++++++++++++++++++
3 files changed, 277 insertions(+)
create mode 100644 drivers/clk/starfive/jh8100/clk-sys-nw.c
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index d8c7b9bb3895..e55f783d73ac 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -81,3 +81,11 @@ config CLK_STARFIVE_JH8100_SYS
default ARCH_STARFIVE
help
Say yes here to support the System clock controller on the StarFive JH8100 SoC.
+
+config CLK_STARFIVE_JH8100_SYS_NW
+ bool "StarFive JH8100 System-North-West clock support"
+ depends on CLK_STARFIVE_JH8100_SYS
+ default ARCH_STARFIVE
+ help
+ Say yes here to support the System-North-West clock controller on the StarFive JH8100
+ SoC.
diff --git a/drivers/clk/starfive/jh8100/Makefile b/drivers/clk/starfive/jh8100/Makefile
index af6a09e220d3..eca7970a0e45 100644
--- a/drivers/clk/starfive/jh8100/Makefile
+++ b/drivers/clk/starfive/jh8100/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
# StarFive JH8100 Clock
obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS) += clk-sys.o
+obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS_NW) += clk-sys-nw.o
diff --git a/drivers/clk/starfive/jh8100/clk-sys-nw.c b/drivers/clk/starfive/jh8100/clk-sys-nw.c
new file mode 100644
index 000000000000..a200ea4d4020
--- /dev/null
+++ b/drivers/clk/starfive/jh8100/clk-sys-nw.c
@@ -0,0 +1,268 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH8100 System Clock Driver
+ *
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ *
+ * Author: Jee Heng Sia <[email protected]>
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <dt-bindings/clock/starfive,jh8100-crg.h>
+
+#include "clk-starfive-jh8100.h"
+
+/* external clocks */
+#define SYSCRG_NW_CLK_OSC (SYSCRG_NW_CLK_END + 0)
+#define SYSCRG_NW_CLK_APB_BUS (SYSCRG_NW_CLK_END + 1)
+#define SYSCRG_NW_CLK_APB_BUS_PER4 (SYSCRG_NW_CLK_END + 2)
+#define SYSCRG_NW_CLK_SPI_CORE_100 (SYSCRG_NW_CLK_END + 3)
+#define SYSCRG_NW_CLK_ISP_2X (SYSCRG_NW_CLK_END + 4)
+#define SYSCRG_NW_CLK_ISP__AXI (SYSCRG_NW_CLK_END + 5)
+#define SYSCRG_NW_CLK_VOUT_ROOT0 (SYSCRG_NW_CLK_END + 6)
+#define SYSCRG_NW_CLK_VOUT_ROOT1 (SYSCRG_NW_CLK_END + 7)
+#define SYSCRG_NW_CLK_VOUT_SCAN__ATS (SYSCRG_NW_CLK_END + 8)
+#define SYSCRG_NW_CLK_VOUT_DC__CORE (SYSCRG_NW_CLK_END + 9)
+#define SYSCRG_NW_CLK_VOUT__AXI (SYSCRG_NW_CLK_END + 10)
+#define SYSCRG_NW_CLK_AXI_400 (SYSCRG_NW_CLK_END + 11)
+#define SYSCRG_NW_CLK_DVP_EXT (SYSCRG_NW_CLK_END + 12)
+#define SYSCRG_NW_CLK_ISP_DPHY_TAP_TCK_EXT (SYSCRG_NW_CLK_END + 13)
+#define SYSCRG_NW_CLK_GLB_EXT (SYSCRG_NW_CLK_END + 14)
+#define SYSCRG_NW_CLK_VOUT_MIPI_DPHY_TAP_TCK_EXT (SYSCRG_NW_CLK_END + 15)
+#define SYSCRG_NW_CLK_VOUT_EDP_TAP_TCK_EXT (SYSCRG_NW_CLK_END + 16)
+#define SYSCRG_NW_CLK_SPI_IN2_EXT (SYSCRG_NW_CLK_END + 17)
+#define SYSCRG_NW_CLK_PERH_ROOT_PREOSC (SYSCRG_NW_CLK_END + 18)
+#define SYSCRG_NW_CLK_AHB_VOUT (SYSCRG_NW_CLK_END + 19)
+#define SYSCRG_NW_CLK_PLL5_OUT (SYSCRG_NW_CLK_END + 20)
+
+static const struct starfive_clk_data jh8100_syscrg_nw_clk_data[] = {
+ /* root */
+ STARFIVE__DIV(SYSCRG_NW_CLK_PLL5_DIV2, "sys_nw_clk_pll5_div2", 2,
+ SYSCRG_NW_CLK_PLL5_OUT),
+ STARFIVE_GDIV(SYSCRG_NW_CLK_GCLK5, "sys_nw_clk_gclk5", CLK_IS_CRITICAL, 120,
+ SYSCRG_NW_CLK_PLL5_DIV2),
+ /* gpio */
+ STARFIVE_GATE(SYSCRG_NW_CLK_GPIO_100, "sys_nw_clk_gpio_100",
+ CLK_IS_CRITICAL, SYSCRG_NW_CLK_PLL5_OUT),
+ STARFIVE_GATE(SYSCRG_NW_CLK_GPIO_50, "sys_nw_clk_gpio_50",
+ CLK_IS_CRITICAL, SYSCRG_NW_CLK_PLL5_OUT),
+ STARFIVE_GATE(SYSCRG_NW_CLK_GPIO_150, "sys_nw_clk_gpio_150",
+ CLK_IS_CRITICAL, SYSCRG_NW_CLK_PLL5_OUT),
+ STARFIVE_GDIV(SYSCRG_NW_CLK_GPIO_60, "sys_nw_clk_gpio_60", CLK_IS_CRITICAL, 30,
+ SYSCRG_NW_CLK_PLL5_OUT),
+ /* iomux */
+ STARFIVE_GATE(SYSCRG_NW_CLK_IOMUX_WEST_PCLK, "sys_nw_clk_iomux_west_pclk", 0,
+ SYSCRG_NW_CLK_APB_BUS_PER4),
+ /* i2c */
+ STARFIVE_GATE(SYSCRG_NW_CLK_I2C6_APB, "sys_nw_clk_i2c6_apb", 0,
+ SYSCRG_NW_CLK_APB_BUS_PER4),
+ STARFIVE_GATE(SYSCRG_NW_CLK_I2C7_APB, "sys_nw_clk_i2c7_apb", 0,
+ SYSCRG_NW_CLK_APB_BUS_PER4),
+ /* spi */
+ STARFIVE_GATE(SYSCRG_NW_CLK_SPI2_APB, "sys_nw_clk_spi2_apb", 0,
+ SYSCRG_NW_CLK_APB_BUS_PER4),
+ STARFIVE_GATE(SYSCRG_NW_CLK_SPI2_CORE, "sys_nw_clk_spi2_core", 0,
+ SYSCRG_NW_CLK_SPI_CORE_100),
+ STARFIVE__MUX(SYSCRG_NW_CLK_SPI2_SCLK_IN, "sys_nw_clk_spi2_sclk_in", 2,
+ SYSCRG_NW_CLK_SPI_IN2_EXT, SYSCRG_NW_CLK_GPIO_100),
+ /* smbus */
+ STARFIVE_GATE(SYSCRG_NW_CLK_SMBUS1_APB, "sys_nw_clk_smbus1_apb", CLK_IGNORE_UNUSED,
+ SYSCRG_NW_CLK_APB_BUS_PER4),
+ STARFIVE_GDIV(SYSCRG_NW_CLK_SMBUS1_CORE, "sys_nw_clk_smbus1_core", CLK_IGNORE_UNUSED, 120,
+ SYSCRG_NW_CLK_PERH_ROOT_PREOSC),
+ /* isp */
+ STARFIVE__MUX(SYSCRG_NW_CLK_ISP_DVP, "sys_nw_clk_isp_dvp", 2,
+ SYSCRG_NW_CLK_DVP_EXT, SYSCRG_NW_CLK_GPIO_150),
+ STARFIVE_GATE(SYSCRG_NW_CLK_ISP_CORE_2X, "sys_nw_clk_isp_core_2x", 0,
+ SYSCRG_NW_CLK_ISP_2X),
+ STARFIVE_GATE(SYSCRG_NW_CLK_ISP_AXI, "sys_nw_clk_isp_axi", 0,
+ SYSCRG_NW_CLK_ISP__AXI),
+ STARFIVE__MUX(SYSCRG_NW_CLK_ISP_DPHY_TAP_TCK, "sys_nw_clk_isp_dphy_tap_tck", 2,
+ SYSCRG_NW_CLK_ISP_DPHY_TAP_TCK_EXT, SYSCRG_NW_CLK_GLB_EXT),
+ STARFIVE_GATE(SYSCRG_NW_CLK_FLEXNOC_ISPSLV, "sys_nw_clk_flexnoc_ispslv", 0,
+ SYSCRG_NW_CLK_ISP__AXI),
+ /* vout */
+ STARFIVE_GATE(SYSCRG_NW_CLK_VOUT_PIX0, "sys_nw_clk_vout_pix0", CLK_IGNORE_UNUSED,
+ SYSCRG_NW_CLK_VOUT_ROOT0),
+ STARFIVE_GATE(SYSCRG_NW_CLK_VOUT_PIX1, "sys_nw_clk_vout_pix1", CLK_IGNORE_UNUSED,
+ SYSCRG_NW_CLK_VOUT_ROOT1),
+ STARFIVE_GATE(SYSCRG_NW_CLK_VOUT_SCAN_ATS, "sys_nw_clk_vout_scan_ats",
+ CLK_IGNORE_UNUSED, SYSCRG_NW_CLK_VOUT_SCAN__ATS),
+ STARFIVE_GATE(SYSCRG_NW_CLK_VOUT_DC_CORE, "sys_nw_clk_vout_dc_core",
+ CLK_IGNORE_UNUSED, SYSCRG_NW_CLK_VOUT_DC__CORE),
+ STARFIVE_GATE(SYSCRG_NW_CLK_VOUT_APB, "sys_nw_clk_vout_apb", CLK_IGNORE_UNUSED,
+ SYSCRG_NW_CLK_APB_BUS),
+ STARFIVE_GATE(SYSCRG_NW_CLK_VOUT_DSI, "sys_nw_clk_vout_dsi", CLK_IGNORE_UNUSED,
+ SYSCRG_NW_CLK_AXI_400),
+ STARFIVE_GATE(SYSCRG_NW_CLK_VOUT_AHB, "sys_nw_clk_vout_ahb", CLK_IGNORE_UNUSED,
+ SYSCRG_NW_CLK_AHB_VOUT),
+ STARFIVE_GATE(SYSCRG_NW_CLK_VOUT_AXI, "sys_nw_clk_vout_axi", CLK_IGNORE_UNUSED,
+ SYSCRG_NW_CLK_VOUT__AXI),
+ STARFIVE__MUX(SYSCRG_NW_CLK_VOUT_MIPI_DPHY_TAP_TCK,
+ "sys_nw_clk_vout_mipi_dphy_tap_tck", 2,
+ SYSCRG_NW_CLK_VOUT_MIPI_DPHY_TAP_TCK_EXT,
+ SYSCRG_NW_CLK_GLB_EXT),
+ STARFIVE__MUX(SYSCRG_NW_CLK_VOUT_EDP_PHY_TAP_TCK,
+ "sys_nw_clk_vout_edp_phy_tap_tck", 2,
+ SYSCRG_NW_CLK_VOUT_EDP_TAP_TCK_EXT, SYSCRG_NW_CLK_GLB_EXT),
+ /* uart */
+ STARFIVE__DIV(SYSCRG_NW_CLK_UART5_CORE_PREOSC, "sys_nw_clk_uart5_core_preosc",
+ 131071, SYSCRG_NW_CLK_PERH_ROOT_PREOSC),
+ STARFIVE_GATE(SYSCRG_NW_CLK_UART5_APB, "sys_nw_clk_uart5_apb", 0,
+ SYSCRG_NW_CLK_APB_BUS_PER4),
+ STARFIVE_GMUX(SYSCRG_NW_CLK_UART5_CORE, "sys_nw_clk_uart5_core", 0, 2,
+ SYSCRG_NW_CLK_OSC, SYSCRG_NW_CLK_UART5_CORE_PREOSC),
+ STARFIVE__DIV(SYSCRG_NW_CLK_UART6_CORE_PREOSC, "sys_nw_clk_uart6_core_preosc",
+ 131071, SYSCRG_NW_CLK_PERH_ROOT_PREOSC),
+ STARFIVE_GATE(SYSCRG_NW_CLK_UART6_APB, "sys_nw_clk_uart6_apb", 0,
+ SYSCRG_NW_CLK_APB_BUS_PER4),
+ STARFIVE_GMUX(SYSCRG_NW_CLK_UART6_CORE, "sys_nw_clk_uart6_core", 0, 2,
+ SYSCRG_NW_CLK_OSC, SYSCRG_NW_CLK_UART6_CORE_PREOSC),
+ /* icg_en */
+ STARFIVE_GATE(SYSCRG_NW_CLK_SPI2_ICG_EN, "sys_nw_clk_spi2_en", 0,
+ SYSCRG_NW_CLK_APB_BUS_PER4),
+ STARFIVE_GATE(SYSCRG_NW_CLK_SMBUS1_ICG_EN, "sys_nw_clk_smbus1_en", 0,
+ SYSCRG_NW_CLK_APB_BUS_PER4),
+ STARFIVE_GATE(SYSCRG_NW_CLK_ISP_ICG_EN, "sys_nw_clk_isp_en", 0,
+ SYSCRG_NW_CLK_ISP__AXI),
+ STARFIVE_GATE(SYSCRG_NW_CLK_VOUT_ICG_EN, "sys_nw_clk_vout_en", 0,
+ SYSCRG_NW_CLK_VOUT_ROOT0),
+ STARFIVE_GATE(SYSCRG_NW_CLK_UART5_ICG_EN, "sys_nw_clk_uart5_en", 0,
+ SYSCRG_NW_CLK_APB_BUS_PER4),
+ STARFIVE_GATE(SYSCRG_NW_CLK_UART6_ICG_EN, "sys_nw_clk_uart6_en", 0,
+ SYSCRG_NW_CLK_APB_BUS_PER4),
+};
+
+struct clk_hw *jh8100_syscrg_nw_clk_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct starfive_clk_priv *priv = data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx < SYSCRG_NW_CLK_END)
+ return &priv->reg[idx].hw;
+
+ return ERR_PTR(-EINVAL);
+}
+
+static int jh8100_syscrg_nw_probe(struct platform_device *pdev)
+{
+ struct starfive_clk_priv *priv;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, reg, SYSCRG_NW_CLK_END),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ /* 24MHz -> 1500.0MHz */
+ priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "clk_pll5_out",
+ "clk_osc", 0, 125, 2);
+ if (IS_ERR(priv->pll[0]))
+ return PTR_ERR(priv->pll[0]);
+
+ for (idx = 0; idx < SYSCRG_NW_CLK_END; idx++) {
+ u32 max = jh8100_syscrg_nw_clk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jh8100_syscrg_nw_clk_data[idx].name,
+ .ops = starfive_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
+ .flags = jh8100_syscrg_nw_clk_data[idx].flags,
+ };
+ struct starfive_clk *clk = &priv->reg[idx];
+ unsigned int i;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jh8100_syscrg_nw_clk_data[idx].parents[i];
+
+ if (pidx < SYSCRG_NW_CLK_END)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx == SYSCRG_NW_CLK_OSC)
+ parents[i].fw_name = "clk_osc";
+ else if (pidx == SYSCRG_NW_CLK_APB_BUS)
+ parents[i].fw_name = "sys_clk_apb_bus";
+ else if (pidx == SYSCRG_NW_CLK_APB_BUS_PER4)
+ parents[i].fw_name = "sys_clk_apb_bus_per4";
+ else if (pidx == SYSCRG_NW_CLK_SPI_CORE_100)
+ parents[i].fw_name = "sys_clk_spi_core_100";
+ else if (pidx == SYSCRG_NW_CLK_ISP_2X)
+ parents[i].fw_name = "sys_clk_isp_2x";
+ else if (pidx == SYSCRG_NW_CLK_ISP__AXI)
+ parents[i].fw_name = "sys_clk_isp_axi";
+ else if (pidx == SYSCRG_NW_CLK_VOUT_ROOT0)
+ parents[i].fw_name = "sys_clk_vout_root0";
+ else if (pidx == SYSCRG_NW_CLK_VOUT_ROOT1)
+ parents[i].fw_name = "sys_clk_vout_root1";
+ else if (pidx == SYSCRG_NW_CLK_VOUT_SCAN__ATS)
+ parents[i].fw_name = "sys_clk_vout_scan_ats";
+ else if (pidx == SYSCRG_NW_CLK_VOUT_DC__CORE)
+ parents[i].fw_name = "sys_clk_vout_dc_core";
+ else if (pidx == SYSCRG_NW_CLK_VOUT__AXI)
+ parents[i].fw_name = "sys_clk_vout_axi";
+ else if (pidx == SYSCRG_NW_CLK_AXI_400)
+ parents[i].fw_name = "sys_clk_axi_400";
+ else if (pidx == SYSCRG_NW_CLK_DVP_EXT)
+ parents[i].fw_name = "clk_dvp_ext";
+ else if (pidx == SYSCRG_NW_CLK_ISP_DPHY_TAP_TCK_EXT)
+ parents[i].fw_name = "clk_isp_dphy_tap_tck_ext";
+ else if (pidx == SYSCRG_NW_CLK_GLB_EXT)
+ parents[i].fw_name = "clk_glb_ext_clk";
+ else if (pidx == SYSCRG_NW_CLK_VOUT_MIPI_DPHY_TAP_TCK_EXT)
+ parents[i].fw_name = "clk_vout_mipi_dphy_tap_tck_ext";
+ else if (pidx == SYSCRG_NW_CLK_VOUT_EDP_TAP_TCK_EXT)
+ parents[i].fw_name = "clk_vout_edp_tap_tck_ext";
+ else if (pidx == SYSCRG_NW_CLK_SPI_IN2_EXT)
+ parents[i].fw_name = "clk_spi_in2_ext";
+ else if (pidx == SYSCRG_NW_CLK_PERH_ROOT_PREOSC)
+ parents[i].fw_name = "sys_clk_perh_root_preosc";
+ else if (pidx == SYSCRG_NW_CLK_AHB_VOUT)
+ parents[i].fw_name = "sys_clk_ahb_vout";
+ else
+ parents[i].hw = priv->pll[pidx - SYSCRG_NW_CLK_PLL5_OUT];
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, jh8100_syscrg_nw_clk_get, priv);
+ if (ret)
+ return ret;
+
+ return jh8100_reset_controller_register(priv, "rst-sys-nw", 1);
+}
+
+static const struct of_device_id jh8100_syscrg_nw_match[] = {
+ { .compatible = "starfive,jh8100-syscrg-nw" },
+ { /* sentinel */ }
+};
+
+static struct platform_driver jh8100_syscrg_nw_driver = {
+ .driver = {
+ .name = "clk-starfive-jh8100-sys-nw",
+ .of_match_table = jh8100_syscrg_nw_match,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver_probe(jh8100_syscrg_nw_driver, jh8100_syscrg_nw_probe);
--
2.34.1
Add support for JH8100 System-North-East clock generator.
Signed-off-by: Sia Jee Heng <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
---
drivers/clk/starfive/Kconfig | 8 +
drivers/clk/starfive/jh8100/Makefile | 1 +
drivers/clk/starfive/jh8100/clk-sys-ne.c | 566 +++++++++++++++++++++++
3 files changed, 575 insertions(+)
create mode 100644 drivers/clk/starfive/jh8100/clk-sys-ne.c
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index e55f783d73ac..acd530c3897b 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -89,3 +89,11 @@ config CLK_STARFIVE_JH8100_SYS_NW
help
Say yes here to support the System-North-West clock controller on the StarFive JH8100
SoC.
+
+config CLK_STARFIVE_JH8100_SYS_NE
+ bool "StarFive JH8100 System-North-East clock support"
+ depends on CLK_STARFIVE_JH8100_SYS
+ default ARCH_STARFIVE
+ help
+ Say yes here to support the System-North-East clock controller on the StarFive JH8100
+ SoC.
diff --git a/drivers/clk/starfive/jh8100/Makefile b/drivers/clk/starfive/jh8100/Makefile
index eca7970a0e45..164c1d55b97c 100644
--- a/drivers/clk/starfive/jh8100/Makefile
+++ b/drivers/clk/starfive/jh8100/Makefile
@@ -2,3 +2,4 @@
# StarFive JH8100 Clock
obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS) += clk-sys.o
obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS_NW) += clk-sys-nw.o
+obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS_NE) += clk-sys-ne.o
diff --git a/drivers/clk/starfive/jh8100/clk-sys-ne.c b/drivers/clk/starfive/jh8100/clk-sys-ne.c
new file mode 100644
index 000000000000..325571f52c29
--- /dev/null
+++ b/drivers/clk/starfive/jh8100/clk-sys-ne.c
@@ -0,0 +1,566 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH8100 System Clock Driver
+ *
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ *
+ * Author: Jee Heng Sia <[email protected]>
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <dt-bindings/clock/starfive,jh8100-crg.h>
+
+#include "clk-starfive-jh8100.h"
+
+/* external clocks */
+#define SYSCRG_NE_CLK_OSC (SYSCRG_NE_CLK_END + 0)
+#define SYSCRG_NE_CLK_APB_BUS (SYSCRG_NE_CLK_END + 1)
+#define SYSCRG_NE_CLK_AXI_400 (SYSCRG_NE_CLK_END + 3)
+#define SYSCRG_NE_CLK_VOUT_ROOT0 (SYSCRG_NE_CLK_END + 5)
+#define SYSCRG_NE_CLK_VOUT_ROOT1 (SYSCRG_NE_CLK_END + 6)
+#define SYSCRG_NE_CLK_USB_WRAP_480 (SYSCRG_NE_CLK_END + 7)
+#define SYSCRG_NE_CLK_USB_WRAP_625 (SYSCRG_NE_CLK_END + 8)
+#define SYSCRG_NE_CLK_USB_WRAP_240 (SYSCRG_NE_CLK_END + 9)
+#define SYSCRG_NE_CLK_USB_WRAP_60 (SYSCRG_NE_CLK_END + 10)
+#define SYSCRG_NE_CLK_USB_WRAP_156P25 (SYSCRG_NE_CLK_END + 11)
+#define SYSCRG_NE_CLK_USB_WRAP_312P5 (SYSCRG_NE_CLK_END + 12)
+#define SYSCRG_NE_CLK_USB_125M (SYSCRG_NE_CLK_END + 13)
+#define SYSCRG_NE_CLK_GPIO_100 (SYSCRG_NE_CLK_END + 14)
+#define SYSCRG_NE_CLK_PERH_ROOT (SYSCRG_NE_CLK_END + 15)
+#define SYSCRG_NE_CLK_MCLK (SYSCRG_NE_CLK_END + 16)
+#define SYSCRG_NE_CLK_USB3_TAP_TCK_EXT (SYSCRG_NE_CLK_END + 17)
+#define SYSCRG_NE_CLK_GLB_EXT (SYSCRG_NE_CLK_END + 18)
+#define SYSCRG_NE_CLK_USB1_TAP_TCK_EXT (SYSCRG_NE_CLK_END + 19)
+#define SYSCRG_NE_CLK_USB2_TAP_TCK_EXT (SYSCRG_NE_CLK_END + 20)
+#define SYSCRG_NE_CLK_TYPEC_TAP_TCK_EXT (SYSCRG_NE_CLK_END + 22)
+#define SYSCRG_NE_CLK_SPI_IN0_EXT (SYSCRG_NE_CLK_END + 23)
+#define SYSCRG_NE_CLK_SPI_IN1_EXT (SYSCRG_NE_CLK_END + 24)
+#define SYSCRG_NE_CLK_I2STX_BCLK_EXT (SYSCRG_NE_CLK_END + 25)
+#define SYSCRG_NE_CLK_I2STX_LRCK_EXT (SYSCRG_NE_CLK_END + 26)
+#define SYSCRG_NE_CLK_PERH_ROOT_PREOSC (SYSCRG_NE_CLK_END + 27)
+#define SYSCRG_NE_CLK_AHB_DMA (SYSCRG_NE_CLK_END + 28)
+#define SYSCRG_NE_CLK_APB_BUS_PER1 (SYSCRG_NE_CLK_END + 29)
+#define SYSCRG_NE_CLK_APB_BUS_PER2 (SYSCRG_NE_CLK_END + 30)
+#define SYSCRG_NE_CLK_APB_BUS_PER3 (SYSCRG_NE_CLK_END + 31)
+#define SYSCRG_NE_CLK_APB_BUS_PER5 (SYSCRG_NE_CLK_END + 32)
+#define SYSCRG_NE_CLK_VENC_ROOT (SYSCRG_NE_CLK_END + 33)
+#define SYSCRG_NE_CLK_SPI_CORE_100 (SYSCRG_NE_CLK_END + 34)
+
+static const struct starfive_clk_data jh8100_syscrg_ne_clk_data[] = {
+ /* flexnoc */
+ STARFIVE_GATE(SYSCRG_NE_CLK_FLEXNOC_DMASLV, "sys_ne_clk_flexnoc_dmaslv",
+ CLK_IS_CRITICAL, SYSCRG_NE_CLK_AHB_DMA),
+ /* mailbox */
+ STARFIVE_GATE(SYSCRG_NE_CLK_MAILBOX_APB, "sys_ne_clk_mailbox_apb",
+ CLK_IS_CRITICAL, SYSCRG_NE_CLK_APB_BUS_PER1),
+ /* timer */
+ STARFIVE_GATE(SYSCRG_NE_CLK_SR5_TIMER0_APB, "sys_ne_clk_timer0_apb", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER1),
+ STARFIVE_GATE(SYSCRG_NE_CLK_SR5_TIMER0_CH0, "sys_ne_clk_timer0_ch0", 0,
+ SYSCRG_NE_CLK_OSC),
+ STARFIVE_GATE(SYSCRG_NE_CLK_SR5_TIMER0_CH1, "sys_ne_clk_timer0_ch1", 0,
+ SYSCRG_NE_CLK_OSC),
+ STARFIVE_GATE(SYSCRG_NE_CLK_SR5_TIMER0_CH2, "sys_ne_clk_timer0_ch2", 0,
+ SYSCRG_NE_CLK_OSC),
+ STARFIVE_GATE(SYSCRG_NE_CLK_SR5_TIMER0_CH3, "sys_ne_clk_timer0_ch3", 0,
+ SYSCRG_NE_CLK_OSC),
+ STARFIVE_GATE(SYSCRG_NE_CLK_SR5_TIMER1_APB, "sys_ne_clk_timer1_apb", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER1),
+ STARFIVE_GATE(SYSCRG_NE_CLK_SR5_TIMER1_CH0, "sys_ne_clk_timer1_ch0", 0,
+ SYSCRG_NE_CLK_OSC),
+ STARFIVE_GATE(SYSCRG_NE_CLK_SR5_TIMER1_CH1, "sys_ne_clk_timer1_ch1", 0,
+ SYSCRG_NE_CLK_OSC),
+ STARFIVE_GATE(SYSCRG_NE_CLK_SR5_TIMER1_CH2, "sys_ne_clk_timer1_ch2", 0,
+ SYSCRG_NE_CLK_OSC),
+ STARFIVE_GATE(SYSCRG_NE_CLK_SR5_TIMER1_CH3, "sys_ne_clk_timer1_ch3", 0,
+ SYSCRG_NE_CLK_OSC),
+ /* usb3 */
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB3_CMN_SCAN_PLL, "sys_ne_clk_usb3_scan_pll",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_625),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB3_CMN_SCAN_SER, "sys_ne_clk_usb3_scan_ser",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_625),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB3_PIPE_IN_SCAN, "sys_ne_clk_usb3_pipe_in_scan",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_125M),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB3_SCAN_PIPE, "sys_ne_clk_usb3_scan_pipe",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_125M),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB3_SCAN_PSM, "sys_ne_clk_usb3_scan_psm",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_125M),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB3_SCAN_REF, "sys_ne_clk_usb3_scan_ref",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_OSC),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB3_USB2_SCAN, "sys_ne_clk_usb3_usb2_scan",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_APB_BUS_PER3),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB3_HSCLK, "sys_ne_clk_usb3_hsclk",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_480),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB3_HSSICLK, "sys_ne_clk_usb3_hssiclk",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_240),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB3_SIECLK, "sys_ne_clk_usb3_sieclk",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_60),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB3_XCVR_SCAN_PLL, "sys_ne_clk_usb3_xcvr_scan_pll",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_625),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB3_XCVR_SCAN_SER, "sys_ne_clk_usb3_xcvr_scan_ser",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_625),
+ STARFIVE__MUX(SYSCRG_NE_CLK_USB3_TAP_TCK, "sys_ne_clk_usb3_tap_tck", 2,
+ SYSCRG_NE_CLK_USB3_TAP_TCK_EXT, SYSCRG_NE_CLK_GLB_EXT),
+ /* usb1 */
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB1_CMN_SCAN_PLL, "sys_ne_clk_usb1_scan_pll",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_625),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB1_CMN_SCAN_SER, "sys_ne_clk_usb1_scan_ser",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_625),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB1_PIPE_IN_SCAN, "sys_ne_clk_usb1_pipe_in_scan",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_125M),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB1_SCAN_PIPE, "sys_ne_clk_usb1_scan_pipe",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_125M),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB1_SCAN_PSM, "sys_ne_clk_usb1_scan_psm",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_125M),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB1_SCAN_REF, "sys_ne_clk_usb1_scan_ref",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_OSC),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB1_USB2_SCAN, "sys_ne_clk_usb1_usb2_scan",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_APB_BUS_PER3),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB1_HSCLK, "sys_ne_clk_usb1_hsclk",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_480),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB1_HSSICLK, "sys_ne_clk_usb1_hssiclk",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_240),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB1_SIECLK, "sys_ne_clk_usb1_sieclk",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_60),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB1_XCVR_SCAN_PLL, "sys_ne_clk_usb1_xcvr_scan_pll",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_625),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB1_XCVR_SCAN_SER, "sys_ne_clk_usb1_xcvr_scan_ser",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_625),
+ STARFIVE__MUX(SYSCRG_NE_CLK_USB1_TAP_TCK, "sys_ne_clk_usb1_tap_tck", 2,
+ SYSCRG_NE_CLK_USB1_TAP_TCK_EXT, SYSCRG_NE_CLK_GLB_EXT),
+ /* usb2 */
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB2_CMN_SCAN_PLL, "sys_ne_clk_usb2_scan_pll",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_625),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB2_CMN_SCAN_SER, "sys_ne_clk_usb2_scan_ser",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_625),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB2_PIPE_IN_SCAN, "sys_ne_clk_usb2_pipe_in_scan",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_125M),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB2_SCAN_PIPE, "sys_ne_clk_usb2_scan_pipe",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_125M),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB2_SCAN_PSM, "sys_ne_clk_usb2_scan_psm",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_125M),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB2_SCAN_REF, "sys_ne_clk_usb2_scan_ref",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_OSC),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB2_USB2_SCAN, "sys_ne_clk_usb2_usb2_scan",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_APB_BUS_PER3),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB2_HSCLK, "sys_ne_clk_usb2_hsclk",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_480),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB2_HSSICLK, "sys_ne_clk_usb2_hssiclk",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_240),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB2_SIECLK, "sys_ne_clk_usb2_sieclk",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_60),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB2_XCVR_SCAN_PLL, "sys_ne_clk_usb2_xcvr_scan_pll",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_625),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB2_XCVR_SCAN_SER, "sys_ne_clk_usb2_xcvr_scan_ser",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_625),
+ STARFIVE__MUX(SYSCRG_NE_CLK_USB2_TAP_TCK, "sys_ne_clk_usb2_tap_tck", 2,
+ SYSCRG_NE_CLK_USB2_TAP_TCK_EXT, SYSCRG_NE_CLK_GLB_EXT),
+ /* usb typec */
+ STARFIVE_GATE(SYSCRG_NE_CLK_TYPEC_PIPE_DIV_SCAN, "sys_ne_clk_typec_pipe_div_scan",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_156P25),
+ STARFIVE_GATE(SYSCRG_NE_CLK_TYPEC_CMN_SCAN_PLL, "sys_ne_clk_typec_scan_pll",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_625),
+ STARFIVE_GATE(SYSCRG_NE_CLK_TYPEC_CMN_SCAN_SER, "sys_ne_clk_typec_scan_ser",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_625),
+ STARFIVE_GATE(SYSCRG_NE_CLK_TYPEC_SCAN_PIPE, "sys_ne_clk_typec_scan_pipe",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_312P5),
+ STARFIVE_GATE(SYSCRG_NE_CLK_TYPEC_SCAN_PSM, "sys_ne_clk_typec_scan_psm",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_125M),
+ STARFIVE_GATE(SYSCRG_NE_CLK_TYPEC_SCAN_REF, "sys_ne_clk_typec_scan_ref",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_OSC),
+ STARFIVE_GATE(SYSCRG_NE_CLK_TYPEC_USB2_SCAN, "sys_ne_clk_typec_usb2_scan",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_APB_BUS_PER5),
+ STARFIVE_GATE(SYSCRG_NE_CLK_TYPEC_HSCLK, "sys_ne_clk_typec_hsclk", CLK_IGNORE_UNUSED,
+ SYSCRG_NE_CLK_USB_WRAP_480),
+ STARFIVE_GATE(SYSCRG_NE_CLK_TYPEC_HSSICLK, "sys_ne_clk_typec_hssiclk",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_240),
+ STARFIVE_GATE(SYSCRG_NE_CLK_TYPEC_SIECLK, "sys_ne_clk_typec_sieclk",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_60),
+ STARFIVE_GMUX(SYSCRG_NE_CLK_TYPEC_VID0, "sys_ne_clk_typec_vid0", CLK_IGNORE_UNUSED,
+ 2, SYSCRG_NE_CLK_VOUT_ROOT0, SYSCRG_NE_CLK_VOUT_ROOT1),
+ STARFIVE_GMUX(SYSCRG_NE_CLK_TYPEC_VID1, "sys_ne_clk_typec_vid1", CLK_IGNORE_UNUSED,
+ 2, SYSCRG_NE_CLK_VOUT_ROOT0, SYSCRG_NE_CLK_VOUT_ROOT1),
+ STARFIVE_GATE(SYSCRG_NE_CLK_TYPEC_XCVR_SCAN_PLL0, "sys_ne_clk_typec_xcvr_scan_pll0",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_625),
+ STARFIVE_GATE(SYSCRG_NE_CLK_TYPEC_XCVR_SCAN_PLL1, "sys_ne_clk_typec_xcvr_scan_pll1",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_625),
+ STARFIVE_GATE(SYSCRG_NE_CLK_TYPEC_XCVR_SCAN_PLL2, "sys_ne_clk_typec_xcvr_scan_pll2",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_625),
+ STARFIVE_GATE(SYSCRG_NE_CLK_TYPEC_XCVR_SCAN_PLL3, "sys_ne_clk_typec_xcvr_scan_pll3",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_625),
+ STARFIVE_GATE(SYSCRG_NE_CLK_TYPEC_XCVR_SCAN_SER0, "sys_ne_clk_typec_xcvr_scan_ser0",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_625),
+ STARFIVE_GATE(SYSCRG_NE_CLK_TYPEC_XCVR_SCAN_SER1, "sys_ne_clk_typec_xcvr_scan_ser1",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_625),
+ STARFIVE_GATE(SYSCRG_NE_CLK_TYPEC_XCVR_SCAN_SER2, "sys_ne_clk_typec_xcvr_scan_ser2",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_625),
+ STARFIVE_GATE(SYSCRG_NE_CLK_TYPEC_XCVR_SCAN_SER3, "sys_ne_clk_typec_xcvr_scan_ser3",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_USB_WRAP_625),
+ STARFIVE__MUX(SYSCRG_NE_CLK_TYPEC_TAP_TCK, "sys_ne_clk_typec_tap_tck", 2,
+ SYSCRG_NE_CLK_TYPEC_TAP_TCK_EXT, SYSCRG_NE_CLK_GLB_EXT),
+ /* video enc */
+ STARFIVE__DIV(SYSCRG_NE_CLK_VENC_AXI, "sys_ne_clk_venc_axi",
+ 20, SYSCRG_NE_CLK_VENC_ROOT),
+ STARFIVE_GATE(SYSCRG_NE_CLK_VC9000LE_AXI, "sys_ne_clk_vc9000le_axi",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_VENC_AXI),
+ STARFIVE_GATE(SYSCRG_NE_CLK_VC9000LE_APB, "sys_ne_clk_vc9000le_apb",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_APB_BUS_PER5),
+ STARFIVE_GDIV(SYSCRG_NE_CLK_VC9000LE_CORECLK, "sys_ne_clk_vc9000le_coreclk",
+ 0, 40, SYSCRG_NE_CLK_VENC_ROOT),
+ /* intc */
+ STARFIVE_GATE(SYSCRG_NE_CLK_INT_CTRL_APB, "sys_ne_clk_int_ctrl_apb", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER2),
+ /* pwm */
+ STARFIVE_GATE(SYSCRG_NE_CLK_PWM_8CH_APB, "sys_ne_clk_pwm_8ch_apb", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER2),
+ /* wdt */
+ STARFIVE_GATE(SYSCRG_NE_CLK_WDT_APB, "sys_ne_clk_wdt_apb", CLK_IGNORE_UNUSED,
+ SYSCRG_NE_CLK_APB_BUS_PER2),
+ STARFIVE_GATE(SYSCRG_NE_CLK_WDT, "sys_ne_clk_wdt", CLK_IGNORE_UNUSED,
+ SYSCRG_NE_CLK_OSC),
+ /* SPI */
+ STARFIVE_GATE(SYSCRG_NE_CLK_SPI0_APB, "sys_ne_clk_spi0_apb", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER2),
+ STARFIVE_GATE(SYSCRG_NE_CLK_SPI0_CORE, "sys_ne_clk_spi0_core", 0,
+ SYSCRG_NE_CLK_SPI_CORE_100),
+ STARFIVE__MUX(SYSCRG_NE_CLK_SPI0_SCLK_IN, "sys_ne_clk_spi0_sclk_in", 2,
+ SYSCRG_NE_CLK_SPI_IN0_EXT, SYSCRG_NE_CLK_GPIO_100),
+ STARFIVE_GATE(SYSCRG_NE_CLK_SPI1_APB, "sys_ne_clk_spi1_apb", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER2),
+ STARFIVE_GATE(SYSCRG_NE_CLK_SPI1_CORE, "sys_ne_clk_spi1_core", 0,
+ SYSCRG_NE_CLK_SPI_CORE_100),
+ STARFIVE__MUX(SYSCRG_NE_CLK_SPI1_SCLK_IN, "sys_ne_clk_spi1_sclk_in", 2,
+ SYSCRG_NE_CLK_SPI_IN1_EXT, SYSCRG_NE_CLK_GPIO_100),
+ /* i2c */
+ STARFIVE_GATE(SYSCRG_NE_CLK_I2C0_APB, "sys_ne_clk_i2c0_apb", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER1),
+ STARFIVE_GATE(SYSCRG_NE_CLK_I2C1_APB, "sys_ne_clk_i2c1_apb", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER1),
+ STARFIVE_GATE(SYSCRG_NE_CLK_I2C2_APB, "sys_ne_clk_i2c2_apb", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER1),
+ STARFIVE_GATE(SYSCRG_NE_CLK_I2C3_APB, "sys_ne_clk_i2c3_apb", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER1),
+ STARFIVE_GATE(SYSCRG_NE_CLK_I2C4_APB, "sys_ne_clk_i2c4_apb", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER1),
+ STARFIVE_GATE(SYSCRG_NE_CLK_I2C5_APB, "sys_ne_clk_i2c5_apb", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER1),
+ /* uart */
+ STARFIVE_GATE(SYSCRG_NE_CLK_UART0_APB, "sys_ne_clk_uart0_apb", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER1),
+ STARFIVE_GATE(SYSCRG_NE_CLK_UART0_CORE, "sys_ne_clk_uart0_core", 0,
+ SYSCRG_NE_CLK_OSC),
+ STARFIVE__DIV(SYSCRG_NE_CLK_UART1_CORE_PREOSC, "sys_ne_clk_uart1_core_preosc",
+ 131071, SYSCRG_NE_CLK_PERH_ROOT_PREOSC),
+ STARFIVE_GATE(SYSCRG_NE_CLK_UART1_APB, "sys_ne_clk_uart1_apb", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER1),
+ STARFIVE_GMUX(SYSCRG_NE_CLK_UART1_CORE, "sys_ne_clk_uart1_core", 0, 2,
+ SYSCRG_NE_CLK_OSC, SYSCRG_NE_CLK_UART1_CORE_PREOSC),
+ STARFIVE__DIV(SYSCRG_NE_CLK_UART2_CORE_PREOSC, "sys_ne_clk_uart2_core_preosc",
+ 131071, SYSCRG_NE_CLK_PERH_ROOT_PREOSC),
+ STARFIVE_GATE(SYSCRG_NE_CLK_UART2_APB, "sys_ne_clk_uart2_apb", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER1),
+ STARFIVE_GMUX(SYSCRG_NE_CLK_UART2_CORE, "sys_ne_clk_uart2_core", 0, 2,
+ SYSCRG_NE_CLK_OSC, SYSCRG_NE_CLK_UART2_CORE_PREOSC),
+ STARFIVE__DIV(SYSCRG_NE_CLK_UART3_CORE_PREOSC, "sys_ne_clk_uart3_core_preosc",
+ 131071, SYSCRG_NE_CLK_PERH_ROOT_PREOSC),
+ STARFIVE_GATE(SYSCRG_NE_CLK_UART3_APB, "sys_ne_clk_uart3_apb", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER1),
+ STARFIVE_GMUX(SYSCRG_NE_CLK_UART3_CORE, "sys_ne_clk_uart3_core", 0, 2,
+ SYSCRG_NE_CLK_OSC, SYSCRG_NE_CLK_UART3_CORE_PREOSC),
+ STARFIVE__DIV(SYSCRG_NE_CLK_UART4_CORE_PREOSC, "sys_ne_clk_uart4_core_preosc",
+ 131071, SYSCRG_NE_CLK_PERH_ROOT_PREOSC),
+ STARFIVE_GATE(SYSCRG_NE_CLK_UART4_APB, "sys_ne_clk_uart4_apb", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER1),
+ STARFIVE_GMUX(SYSCRG_NE_CLK_UART4_CORE, "sys_ne_clk_uart4_core", 0, 2,
+ SYSCRG_NE_CLK_OSC, SYSCRG_NE_CLK_UART4_CORE_PREOSC),
+ /* i2s */
+ STARFIVE__DIV(SYSCRG_NE_CLK_I2S0_BCLK, "sys_ne_clk_i2s0_bclk", 32,
+ SYSCRG_NE_CLK_MCLK),
+ STARFIVE__DIV(SYSCRG_NE_CLK_I2S0_LRCK, "sys_ne_clk_i2s0_lrck", 128,
+ SYSCRG_NE_CLK_I2S0_BCLK),
+ STARFIVE_GATE(SYSCRG_NE_CLK_I2S0_APB, "sys_ne_clk_i2s0_apb", CLK_IGNORE_UNUSED,
+ SYSCRG_NE_CLK_APB_BUS_PER2),
+ STARFIVE_GATE(SYSCRG_NE_CLK_I2S0, "sys_ne_clk_i2s0", CLK_IGNORE_UNUSED,
+ SYSCRG_NE_CLK_MCLK),
+ STARFIVE_GINV(SYSCRG_NE_CLK_I2S0_N, "sys_ne_clk_i2s0_n",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_MCLK),
+ STARFIVE__MUX(SYSCRG_NE_CLK_I2S0_BCLK_TX, "sys_ne_clk_i2s0_bclk_tx", 2,
+ SYSCRG_NE_CLK_I2S0_BCLK, SYSCRG_NE_CLK_I2STX_BCLK_EXT),
+ STARFIVE__MUX(SYSCRG_NE_CLK_I2S0_LRCK_TX, "sys_ne_clk_i2s0_lrck_tx", 2,
+ SYSCRG_NE_CLK_I2S0_LRCK, SYSCRG_NE_CLK_I2STX_LRCK_EXT),
+ STARFIVE__MUX(SYSCRG_NE_CLK_I2S0_BCLK_RX, "sys_ne_clk_i2s0_bclk_rx", 2,
+ SYSCRG_NE_CLK_I2S0_BCLK, SYSCRG_NE_CLK_I2STX_BCLK_EXT),
+ STARFIVE__MUX(SYSCRG_NE_CLK_I2S0_LRCK_RX, "sys_ne_clk_i2s0_lrck_rx", 2,
+ SYSCRG_NE_CLK_I2S0_LRCK, SYSCRG_NE_CLK_I2STX_LRCK_EXT),
+ STARFIVE__DIV(SYSCRG_NE_CLK_I2S1_BCLK, "sys_ne_clk_i2s1_bclk", 32,
+ SYSCRG_NE_CLK_MCLK),
+ STARFIVE__DIV(SYSCRG_NE_CLK_I2S1_LRCK, "sys_ne_clk_i2s1_lrck", 128,
+ SYSCRG_NE_CLK_I2S1_BCLK),
+ STARFIVE_GATE(SYSCRG_NE_CLK_I2S1_APB, "sys_ne_clk_i2s1_apb", CLK_IGNORE_UNUSED,
+ SYSCRG_NE_CLK_APB_BUS_PER2),
+ STARFIVE_GATE(SYSCRG_NE_CLK_I2S1, "sys_ne_clk_i2s1", CLK_IGNORE_UNUSED,
+ SYSCRG_NE_CLK_MCLK),
+ STARFIVE_GINV(SYSCRG_NE_CLK_I2S1_N, "sys_ne_clk_i2s1_n",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_MCLK),
+ STARFIVE__MUX(SYSCRG_NE_CLK_I2S1_BCLK_TX, "sys_ne_clk_i2s1_bclk_tx", 2,
+ SYSCRG_NE_CLK_I2S1_BCLK, SYSCRG_NE_CLK_I2STX_BCLK_EXT),
+ STARFIVE__MUX(SYSCRG_NE_CLK_I2S1_LRCK_TX, "sys_ne_clk_i2s1_lrck_tx", 2,
+ SYSCRG_NE_CLK_I2S1_LRCK, SYSCRG_NE_CLK_I2STX_LRCK_EXT),
+ STARFIVE__MUX(SYSCRG_NE_CLK_I2S1_BCLK_RX, "sys_ne_clk_i2s1_bclk_rx", 2,
+ SYSCRG_NE_CLK_I2S1_BCLK, SYSCRG_NE_CLK_I2STX_BCLK_EXT),
+ STARFIVE__MUX(SYSCRG_NE_CLK_I2S1_LRCK_RX, "sys_ne_clk_i2s1_lrck_rx", 2,
+ SYSCRG_NE_CLK_I2S1_LRCK, SYSCRG_NE_CLK_I2STX_LRCK_EXT),
+ STARFIVE__DIV(SYSCRG_NE_CLK_I2S2_BCLK, "sys_ne_clk_i2s2_bclk", 32,
+ SYSCRG_NE_CLK_MCLK),
+ STARFIVE__DIV(SYSCRG_NE_CLK_I2S2_LRCK, "sys_ne_clk_i2s2_lrck", 128,
+ SYSCRG_NE_CLK_I2S2_BCLK),
+ STARFIVE_GATE(SYSCRG_NE_CLK_I2S2_APB, "sys_ne_clk_i2s2_apb", CLK_IGNORE_UNUSED,
+ SYSCRG_NE_CLK_APB_BUS_PER2),
+ STARFIVE_GATE(SYSCRG_NE_CLK_I2S2, "sys_ne_clk_i2s2", CLK_IGNORE_UNUSED,
+ SYSCRG_NE_CLK_MCLK),
+ STARFIVE_GINV(SYSCRG_NE_CLK_I2S2_N, "sys_ne_clk_i2s2_n",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_MCLK),
+ STARFIVE__MUX(SYSCRG_NE_CLK_I2S2_BCLK_TX, "sys_ne_clk_i2s2_bclk_tx", 2,
+ SYSCRG_NE_CLK_I2S2_BCLK, SYSCRG_NE_CLK_I2STX_BCLK_EXT),
+ STARFIVE__MUX(SYSCRG_NE_CLK_I2S2_LRCK_TX, "sys_ne_clk_i2s2_lrck_tx", 2,
+ SYSCRG_NE_CLK_I2S2_LRCK, SYSCRG_NE_CLK_I2STX_LRCK_EXT),
+ STARFIVE__MUX(SYSCRG_NE_CLK_I2S2_BCLK_RX, "sys_ne_clk_i2s2_bclk_rx", 2,
+ SYSCRG_NE_CLK_I2S2_BCLK, SYSCRG_NE_CLK_I2STX_BCLK_EXT),
+ STARFIVE__MUX(SYSCRG_NE_CLK_I2S2_LRCK_RX, "sys_ne_clk_i2s2_lrck_rx", 2,
+ SYSCRG_NE_CLK_I2S2_LRCK, SYSCRG_NE_CLK_I2STX_LRCK_EXT),
+ STARFIVE__DIV(SYSCRG_NE_CLK_I2S3_BCLK, "sys_ne_clk_i2s3_bclk", 32,
+ SYSCRG_NE_CLK_MCLK),
+ STARFIVE__DIV(SYSCRG_NE_CLK_I2S3_LRCK, "sys_ne_clk_i2s3_lrck", 128,
+ SYSCRG_NE_CLK_I2S3_BCLK),
+ STARFIVE_GATE(SYSCRG_NE_CLK_I2S0_STEREO_APB, "sys_ne_clk_i2s0_stereo_apb",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_APB_BUS_PER2),
+ STARFIVE_GATE(SYSCRG_NE_CLK_I2S0_STEREO, "sys_ne_clk_i2s0_stereo", CLK_IGNORE_UNUSED,
+ SYSCRG_NE_CLK_MCLK),
+ STARFIVE_GINV(SYSCRG_NE_CLK_I2S0_STEREO_N, "sys_ne_clk_i2s0_stereo_n",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_MCLK),
+ STARFIVE__MUX(SYSCRG_NE_CLK_I2S0_STEREO_BCLK_TX, "sys_ne_clk_i2s0_stereo_bclk_tx", 2,
+ SYSCRG_NE_CLK_I2S3_BCLK, SYSCRG_NE_CLK_I2STX_BCLK_EXT),
+ STARFIVE__MUX(SYSCRG_NE_CLK_I2S0_STEREO_LRCK_TX, "sys_ne_clk_i2s0_stereo_lrck_tx", 2,
+ SYSCRG_NE_CLK_I2S3_LRCK, SYSCRG_NE_CLK_I2STX_LRCK_EXT),
+ STARFIVE__MUX(SYSCRG_NE_CLK_I2S0_STEREO_BCLK_RX_ICG, "sys_ne_clk_i2s0_stereo_bclk_rx_icg",
+ 2, SYSCRG_NE_CLK_I2S3_BCLK, SYSCRG_NE_CLK_I2STX_BCLK_EXT),
+ STARFIVE__MUX(SYSCRG_NE_CLK_I2S0_STEREO_LRCK_RX, "sys_ne_clk_i2s0_stereo_lrck_rx", 2,
+ SYSCRG_NE_CLK_I2S3_LRCK, SYSCRG_NE_CLK_I2STX_LRCK_EXT),
+ STARFIVE_GDIV(SYSCRG_NE_CLK_PDM_4MIC_DMIC, "sys_ne_clk_pdm_4mic_dmic",
+ 0, 64, SYSCRG_NE_CLK_MCLK),
+ STARFIVE_GATE(SYSCRG_NE_CLK_PDM_4MIC_APB, "sys_ne_clk_pdm_4mic_apb", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER2),
+ STARFIVE_GATE(SYSCRG_NE_CLK_PDM_4MIC_SCAN, "sys_ne_clk_pdm_4mic_scan", 0,
+ SYSCRG_NE_CLK_I2S3_BCLK),
+ STARFIVE_GATE(SYSCRG_NE_CLK_CAN0_CTRL_PCLK, "sys_ne_clk_can0_ctrl_pclk",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_APB_BUS_PER2),
+ STARFIVE_GDIV(SYSCRG_NE_CLK_CAN0_CTRL, "sys_ne_clk_can0_ctrl", CLK_IGNORE_UNUSED, 50,
+ SYSCRG_NE_CLK_AXI_400),
+ STARFIVE_GATE(SYSCRG_NE_CLK_CAN0_CTRL_TIMER, "sys_ne_clk_can0_ctrl_timer",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_OSC),
+ STARFIVE_GATE(SYSCRG_NE_CLK_CAN1_CTRL_PCLK, "sys_ne_clk_can1_ctrl_pclk",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_APB_BUS_PER2),
+ STARFIVE_GDIV(SYSCRG_NE_CLK_CAN1_CTRL, "sys_ne_clk_can1_ctrl", CLK_IGNORE_UNUSED, 50,
+ SYSCRG_NE_CLK_AXI_400),
+ STARFIVE_GATE(SYSCRG_NE_CLK_CAN1_CTRL_TIMER, "sys_ne_clk_can1_ctrl_timer",
+ CLK_IGNORE_UNUSED, SYSCRG_NE_CLK_OSC),
+ /* smbus */
+ STARFIVE_GATE(SYSCRG_NE_CLK_SMBUS0_APB, "sys_ne_clk_smbus0_apb", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER2),
+ STARFIVE_GDIV(SYSCRG_NE_CLK_SMBUS0_CORE, "sys_ne_clk_smbus0_core", 0, 120,
+ SYSCRG_NE_CLK_PERH_ROOT_PREOSC),
+ /* iomux */
+ STARFIVE_GATE(SYSCRG_NE_CLK_IOMUX_EAST_PCLK, "sys_ne_clk_iomux_east_pclk", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER2),
+ /* icg_en */
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB3_ICG_EN, "sys_ne_clk_usb3_en", 0,
+ SYSCRG_NE_CLK_USB_WRAP_625),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB1_ICG_EN, "sys_ne_clk_usb1_en", 0,
+ SYSCRG_NE_CLK_USB_WRAP_625),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USB2_ICG_EN, "sys_ne_clk_usb2_en", 0,
+ SYSCRG_NE_CLK_USB_WRAP_625),
+ STARFIVE_GATE(SYSCRG_NE_CLK_USBC_ICG_EN, "sys_ne_clk_usbc_en", 0,
+ SYSCRG_NE_CLK_USB_WRAP_625),
+ STARFIVE_GATE(SYSCRG_NE_CLK_VENC_ICG_EN, "sys_ne_clk_venc_en", 0,
+ SYSCRG_NE_CLK_AXI_400),
+ STARFIVE_GATE(SYSCRG_NE_CLK_WDT0_ICG_EN, "sys_ne_clk_wdt0_en", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER2),
+ STARFIVE_GATE(SYSCRG_NE_CLK_SPI0_ICG_EN, "sys_ne_clk_spi0_en", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER2),
+ STARFIVE_GATE(SYSCRG_NE_CLK_SPI1_ICG_EN, "sys_ne_clk_spi1_en", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER2),
+ STARFIVE_GATE(SYSCRG_NE_CLK_UART0_ICG_EN, "sys_ne_clk_uart0_en", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER1),
+ STARFIVE_GATE(SYSCRG_NE_CLK_UART1_ICG_EN, "sys_ne_clk_uart1_en", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER1),
+ STARFIVE_GATE(SYSCRG_NE_CLK_UART2_ICG_EN, "sys_ne_clk_uart2_en", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER1),
+ STARFIVE_GATE(SYSCRG_NE_CLK_UART3_ICG_EN, "sys_ne_clk_uart3_en", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER1),
+ STARFIVE_GATE(SYSCRG_NE_CLK_UART4_ICG_EN, "sys_ne_clk_uart4_en", 0,
+ SYSCRG_NE_CLK_APB_BUS_PER1),
+ STARFIVE_GATE(SYSCRG_NE_CLK_I2S0_ICG_EN, "sys_ne_clk_i2s0_en", 0,
+ SYSCRG_NE_CLK_MCLK),
+ STARFIVE_GATE(SYSCRG_NE_CLK_I2S1_ICG_EN, "sys_ne_clk_i2s1_en", 0,
+ SYSCRG_NE_CLK_MCLK),
+ STARFIVE_GATE(SYSCRG_NE_CLK_I2S2_ICG_EN, "sys_ne_clk_i2s2_en", 0,
+ SYSCRG_NE_CLK_MCLK),
+ STARFIVE_GATE(SYSCRG_NE_CLK_I2S_STEREO_ICG_EN, "sys_ne_clk_i2s_stereo_en", 0,
+ SYSCRG_NE_CLK_MCLK),
+ STARFIVE_GATE(SYSCRG_NE_CLK_PDM_4MIC_ICG_EN, "sys_ne_clk_pdm_4mic_en", 0,
+ SYSCRG_NE_CLK_MCLK),
+ STARFIVE_GATE(SYSCRG_NE_CLK_CAN0_ICG_EN, "sys_ne_clk_can0_en", 0,
+ SYSCRG_NE_CLK_AXI_400),
+ STARFIVE_GATE(SYSCRG_NE_CLK_CAN1_ICG_EN, "sys_ne_clk_can1_en", 0,
+ SYSCRG_NE_CLK_AXI_400),
+ STARFIVE_GATE(SYSCRG_NE_CLK_SMBUS0_ICG_EN, "sys_ne_clk_smbus0_en", 0,
+ SYSCRG_NE_CLK_PERH_ROOT_PREOSC),
+};
+
+static struct clk_hw *jh8100_syscrg_ne_clk_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct starfive_clk_priv *priv = data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx < SYSCRG_NE_CLK_END)
+ return &priv->reg[idx].hw;
+
+ return ERR_PTR(-EINVAL);
+}
+
+static int jh8100_syscrg_ne_probe(struct platform_device *pdev)
+{
+ struct starfive_clk_priv *priv;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, reg, SYSCRG_NE_CLK_END),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ for (idx = 0; idx < SYSCRG_NE_CLK_END; idx++) {
+ u32 max = jh8100_syscrg_ne_clk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jh8100_syscrg_ne_clk_data[idx].name,
+ .ops = starfive_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
+ .flags = jh8100_syscrg_ne_clk_data[idx].flags,
+ };
+ struct starfive_clk *clk = &priv->reg[idx];
+ unsigned int i;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jh8100_syscrg_ne_clk_data[idx].parents[i];
+
+ if (pidx < SYSCRG_NE_CLK_END)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx == SYSCRG_NE_CLK_OSC)
+ parents[i].fw_name = "clk_osc";
+ else if (pidx == SYSCRG_NE_CLK_AXI_400)
+ parents[i].fw_name = "sys_clk_axi_400";
+ else if (pidx == SYSCRG_NE_CLK_VOUT_ROOT0)
+ parents[i].fw_name = "sys_clk_vout_root0";
+ else if (pidx == SYSCRG_NE_CLK_VOUT_ROOT1)
+ parents[i].fw_name = "sys_clk_vout_root1";
+ else if (pidx == SYSCRG_NE_CLK_USB_WRAP_480)
+ parents[i].fw_name = "sys_clk_usb_wrap_480";
+ else if (pidx == SYSCRG_NE_CLK_USB_WRAP_625)
+ parents[i].fw_name = "sys_clk_usb_wrap_625";
+ else if (pidx == SYSCRG_NE_CLK_USB_WRAP_240)
+ parents[i].fw_name = "sys_clk_usb_wrap_240";
+ else if (pidx == SYSCRG_NE_CLK_USB_WRAP_60)
+ parents[i].fw_name = "sys_clk_usb_wrap_60";
+ else if (pidx == SYSCRG_NE_CLK_USB_WRAP_156P25)
+ parents[i].fw_name = "sys_clk_usb_wrap_156p25";
+ else if (pidx == SYSCRG_NE_CLK_USB_WRAP_312P5)
+ parents[i].fw_name = "sys_clk_usb_wrap_312p5";
+ else if (pidx == SYSCRG_NE_CLK_USB_125M)
+ parents[i].fw_name = "sys_clk_usb_125m";
+ else if (pidx == SYSCRG_NE_CLK_GPIO_100)
+ parents[i].fw_name = "sys_nw_clk_gpio_100";
+ else if (pidx == SYSCRG_NE_CLK_PERH_ROOT)
+ parents[i].fw_name = "sys_clk_perh_root";
+ else if (pidx == SYSCRG_NE_CLK_MCLK)
+ parents[i].fw_name = "sys_clk_mclk";
+ else if (pidx == SYSCRG_NE_CLK_USB3_TAP_TCK_EXT)
+ parents[i].fw_name = "clk_usb3_tap_tck_ext";
+ else if (pidx == SYSCRG_NE_CLK_GLB_EXT)
+ parents[i].fw_name = "clk_glb_ext_clk";
+ else if (pidx == SYSCRG_NE_CLK_USB1_TAP_TCK_EXT)
+ parents[i].fw_name = "clk_usb1_tap_tck_ext";
+ else if (pidx == SYSCRG_NE_CLK_USB2_TAP_TCK_EXT)
+ parents[i].fw_name = "clk_usb2_tap_tck_ext";
+ else if (pidx == SYSCRG_NE_CLK_TYPEC_TAP_TCK_EXT)
+ parents[i].fw_name = "clk_typec_tap_tck_ext";
+ else if (pidx == SYSCRG_NE_CLK_SPI_IN0_EXT)
+ parents[i].fw_name = "clk_spi_in0_ext";
+ else if (pidx == SYSCRG_NE_CLK_SPI_IN1_EXT)
+ parents[i].fw_name = "clk_spi_in1_ext";
+ else if (pidx == SYSCRG_NE_CLK_I2STX_BCLK_EXT)
+ parents[i].fw_name = "clk_i2stx_bclk_ext";
+ else if (pidx == SYSCRG_NE_CLK_I2STX_LRCK_EXT)
+ parents[i].fw_name = "clk_i2stx_lrck_ext";
+ else if (pidx == SYSCRG_NE_CLK_PERH_ROOT_PREOSC)
+ parents[i].fw_name = "sys_clk_perh_root_preosc";
+ else if (pidx == SYSCRG_NE_CLK_AHB_DMA)
+ parents[i].fw_name = "sys_clk_ahb0";
+ else if (pidx == SYSCRG_NE_CLK_APB_BUS_PER1)
+ parents[i].fw_name = "sys_clk_apb_bus_per1";
+ else if (pidx == SYSCRG_NE_CLK_APB_BUS_PER2)
+ parents[i].fw_name = "sys_clk_apb_bus_per2";
+ else if (pidx == SYSCRG_NE_CLK_APB_BUS_PER3)
+ parents[i].fw_name = "sys_clk_apb_bus_per3";
+ else if (pidx == SYSCRG_NE_CLK_APB_BUS_PER5)
+ parents[i].fw_name = "sys_clk_apb_bus_per5";
+ else if (pidx == SYSCRG_NE_CLK_VENC_ROOT)
+ parents[i].fw_name = "sys_clk_venc_root";
+ else if (pidx == SYSCRG_NE_CLK_SPI_CORE_100)
+ parents[i].fw_name = "sys_clk_spi_core_100";
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, jh8100_syscrg_ne_clk_get, priv);
+ if (ret)
+ return ret;
+
+ return jh8100_reset_controller_register(priv, "rst-sys-ne", 2);
+}
+
+static const struct of_device_id jh8100_syscrg_ne_match[] = {
+ { .compatible = "starfive,jh8100-syscrg-ne" },
+ { /* sentinel */ }
+};
+
+static struct platform_driver jh8100_syscrg_ne_driver = {
+ .driver = {
+ .name = "clk-starfive-jh8100-sys-ne",
+ .of_match_table = jh8100_syscrg_ne_match,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver_probe(jh8100_syscrg_ne_driver, jh8100_syscrg_ne_probe);
--
2.34.1
Add bindings for the System-South-West clock and reset generator
(SYSCRG-SW) on JH8100 SoC.
Signed-off-by: Sia Jee Heng <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
---
.../clock/starfive,jh8100-syscrg-sw.yaml | 66 +++++++++++++++++++
.../dt-bindings/clock/starfive,jh8100-crg.h | 14 ++++
.../dt-bindings/reset/starfive,jh8100-crg.h | 10 +++
3 files changed, 90 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-sw.yaml
diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-sw.yaml b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-sw.yaml
new file mode 100644
index 000000000000..8bd41af040b7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-sw.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh8100-syscrg-sw.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH8100 System-South-West Clock And Reset Generator
+
+maintainers:
+ - Sia Jee Heng <[email protected]>
+
+properties:
+ compatible:
+ const: starfive,jh8100-syscrg-sw
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: APB_BUS clock from SYSCRG
+ - description: VDEC_ROOT clock from SYSCRG
+ - description: FLEXNOC1 clock from SYSCRG
+
+ clock-names:
+ items:
+ - const: sys_clk_apb_bus
+ - const: sys_clk_vdec_root
+ - const: sys_clk_flexnoc1
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive,jh8100-crg.h> for valid indices.
+
+ '#reset-cells':
+ const: 1
+ description:
+ See <dt-bindings/reset/starfive-jh8100-crg.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/starfive,jh8100-crg.h>
+
+ clock-controller@12720000 {
+ compatible = "starfive,jh8100-syscrg-sw";
+ reg = <0x12720000 0x10000>;
+ clocks = <&syscrg SYSCRG_CLK_APB_BUS>,
+ <&syscrg SYSCRG_CLK_VDEC_ROOT>,
+ <&syscrg SYSCRG_CLK_FLEXNOC1>;
+ clock-names = "sys_clk_apb_bus",
+ "sys_clk_vdec_root",
+ "sys_clk_flexnoc1";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h
index b30ccd16a802..3ce0b9ec66be 100644
--- a/include/dt-bindings/clock/starfive,jh8100-crg.h
+++ b/include/dt-bindings/clock/starfive,jh8100-crg.h
@@ -344,4 +344,18 @@
#define SYSCRG_NE_CLK_SMBUS0_ICG_EN 174
#define SYSCRG_NE_CLK_END 175
+
+/* SYSCRG_SW_CLK */
+#define SYSCRG_SW_CLK_JPEG_AXI 0
+#define SYSCRG_SW_CLK_VC9000DJ_AXI 1
+#define SYSCRG_SW_CLK_VC9000DJ_VDEC 2
+#define SYSCRG_SW_CLK_VC9000DJ_APB 3
+#define SYSCRG_SW_CLK_VDEC_AXI 4
+#define SYSCRG_SW_CLK_VC9000D_AXI 5
+#define SYSCRG_SW_CLK_VC9000D_VDEC 6
+#define SYSCRG_SW_CLK_VC9000D_APB 7
+#define SYSCRG_SW_CLK_JPEG_ICG_EN 8
+#define SYSCRG_SW_CLK_VDEC_ICG_EN 9
+
+#define SYSCRG_SW_CLK_END 10
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */
diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h
index 7626da648686..55209382e00e 100644
--- a/include/dt-bindings/reset/starfive,jh8100-crg.h
+++ b/include/dt-bindings/reset/starfive,jh8100-crg.h
@@ -96,4 +96,14 @@
#define SYSCRG_NE_RSTN_DUBHE_TVSENSOR 49
#define SYSCRG_NE_RESET_NR_RESETS 50
+
+/*
+ * syscrg_sw: assert0
+ */
+#define SYSCRG_SW_RSTN_PRESETN 0
+#define SYSCRG_SW_RSTN_VC9000DJ 1
+#define SYSCRG_SW_RSTN_VC9000D 2
+#define SYSCRG_SW_RSTN_DDR_TVSENSOR 3
+
+#define SYSCRG_SW_RESET_NR_RESETS 4
#endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */
--
2.34.1
Add SYSCRG/SYSCRG-NE/SYSCRG-NW/SYSCRG-SW/AONCRG clock and reset
nodes for JH8100 RISC-V SoC.
Signed-off-by: Sia Jee Heng <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
---
arch/riscv/boot/dts/starfive/jh8100-clk.dtsi | 180 +++++++++++++++++++
arch/riscv/boot/dts/starfive/jh8100.dtsi | 115 ++++++++++++
2 files changed, 295 insertions(+)
create mode 100644 arch/riscv/boot/dts/starfive/jh8100-clk.dtsi
diff --git a/arch/riscv/boot/dts/starfive/jh8100-clk.dtsi b/arch/riscv/boot/dts/starfive/jh8100-clk.dtsi
new file mode 100644
index 000000000000..27ba249f523e
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh8100-clk.dtsi
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ */
+
+/ {
+ clk_osc: clk_osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ clk_i2srx_bclk_ext: clk_i2srx_bclk_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12288000>;
+ };
+
+ clk_i2srx_lrck_ext: clk_i2srx_lrck_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <192000>;
+ };
+
+ clk_mclk_ext: clk_mclk_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <49152000>;
+ };
+ /* sys-ne */
+ clk_usb3_tap_tck_ext: clk_usb3_tap_tck_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ clk_glb_ext_clk: clk_glb_ext_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <30000000>;
+ };
+
+ clk_usb1_tap_tck_ext: clk_usb1_tap_tck_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ clk_usb2_tap_tck_ext: clk_usb2_tap_tck_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ clk_i2s_tscko: clk_i2s_tscko {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12800000>;
+ };
+
+ clk_typec_tap_tck_ext: clk_typec_tap_tck_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ clk_spi_in0_ext: clk_spi_in0_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ clk_spi_in1_ext: clk_spi_in1_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ clk_spi_in2_ext: clk_spi_in2_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ clk_i2stx_bclk_ext: clk_i2stx_bclk_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12288000>;
+ };
+
+ clk_i2stx_lrck_ext: clk_i2stx_lrck_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <192000>;
+ };
+ /* sys-nw */
+ clk_dvp_ext: clk_dvp_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <150000000>;
+ };
+
+ clk_isp_dphy_tap_tck_ext: clk_isp_dphy_tap_tck_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ clk_vout_mipi_dphy_tap_tck_ext: clk_vout_mipi_dphy_tap_tck_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ clk_vout_edp_tap_tck_ext: clk_vout_edp_tap_tck_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ clk_rtc: clk_rtc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ /* aon */
+ clk_gmac0_rmii_func: clk_gmac0_rmii_func {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+
+ clk_gmac0_rgmii_func: clk_gmac0_rgmii_func {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ clk_aon50: clk_aon50 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+
+ clk_aon125: clk_aon125 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ clk_aon2000: clk_aon2000 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2000000000>;
+ };
+
+ clk_aon200: clk_aon200 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+
+ clk_aon667: clk_isp_aon667 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <667000000>;
+ };
+
+ clk_i3c_ext: clk_i3c_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12500000>;
+ };
+
+ clk_espi_ext: clk_espi_ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <60000000>;
+ };
+};
diff --git a/arch/riscv/boot/dts/starfive/jh8100.dtsi b/arch/riscv/boot/dts/starfive/jh8100.dtsi
index f26aff5c1ddf..9863c61324a0 100644
--- a/arch/riscv/boot/dts/starfive/jh8100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh8100.dtsi
@@ -4,6 +4,9 @@
*/
/dts-v1/;
+#include <dt-bindings/clock/starfive,jh8100-crg.h>
+#include <dt-bindings/reset/starfive,jh8100-crg.h>
+#include "jh8100-clk.dtsi"
/ {
compatible = "starfive,jh8100";
@@ -357,6 +360,104 @@ uart4: serial@121a0000 {
status = "disabled";
};
+ syscrg_ne: syscrg_ne@12320000 {
+ compatible = "starfive,jh8100-syscrg-ne";
+ reg = <0x0 0x12320000 0x0 0x10000>;
+ clocks = <&clk_osc>, <&syscrg SYSCRG_CLK_AXI_400>,
+ <&syscrg SYSCRG_CLK_VOUT_ROOT0>,
+ <&syscrg SYSCRG_CLK_VOUT_ROOT1>,
+ <&syscrg SYSCRG_CLK_USB_WRAP_480>,
+ <&syscrg SYSCRG_CLK_USB_WRAP_625>,
+ <&syscrg SYSCRG_CLK_USB_WRAP_240>,
+ <&syscrg SYSCRG_CLK_USB_WRAP_60>,
+ <&syscrg SYSCRG_CLK_USB_WRAP_156P25>,
+ <&syscrg SYSCRG_CLK_USB_WRAP_312P5>,
+ <&syscrg SYSCRG_CLK_USB_125M>,
+ <&syscrg_nw SYSCRG_NW_CLK_GPIO_100>,
+ <&syscrg SYSCRG_CLK_PERH_ROOT>, <&syscrg SYSCRG_CLK_MCLK>,
+ <&syscrg SYSCRG_CLK_PERH_ROOT_PREOSC>,
+ <&syscrg SYSCRG_CLK_AHB0>,
+ <&syscrg SYSCRG_CLK_APB_BUS_PER1>,
+ <&syscrg SYSCRG_CLK_APB_BUS_PER2>,
+ <&syscrg SYSCRG_CLK_APB_BUS_PER3>,
+ <&syscrg SYSCRG_CLK_APB_BUS_PER5>,
+ <&syscrg SYSCRG_CLK_VENC_ROOT>,
+ <&syscrg SYSCRG_CLK_SPI_CORE_100>,
+ <&clk_glb_ext_clk>, <&clk_usb3_tap_tck_ext>,
+ <&clk_usb1_tap_tck_ext>, <&clk_usb2_tap_tck_ext>,
+ <&clk_typec_tap_tck_ext>, <&clk_spi_in0_ext>,
+ <&clk_spi_in1_ext>, <&clk_i2stx_bclk_ext>, <&clk_i2stx_lrck_ext>;
+ clock-names = "clk_osc", "sys_clk_axi_400",
+ "sys_clk_vout_root0", "sys_clk_vout_root1",
+ "sys_clk_usb_wrap_480", "sys_clk_usb_wrap_625",
+ "sys_clk_usb_wrap_240", "sys_clk_usb_wrap_60",
+ "sys_clk_usb_wrap_156p25", "sys_clk_usb_wrap_312p5",
+ "sys_clk_usb_125m", "sys_nw_clk_gpio_100",
+ "sys_clk_perh_root", "sys_clk_mclk",
+ "sys_clk_perh_root_preosc", "sys_clk_ahb0",
+ "sys_clk_apb_bus_per1", "sys_clk_apb_bus_per2",
+ "sys_clk_apb_bus_per3", "sys_clk_apb_bus_per5",
+ "sys_clk_venc_root", "sys_clk_spi_core_100",
+ "clk_glb_ext_clk", "clk_usb3_tap_tck_ext",
+ "clk_usb1_tap_tck_ext", "clk_usb2_tap_tck_ext",
+ "clk_typec_tap_tck_ext", "clk_spi_in0_ext",
+ "clk_spi_in1_ext", "clk_i2stx_bclk_ext",
+ "clk_i2stx_lrck_ext";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ syscrg_nw: syscrg_nw@123c0000 {
+ compatible = "starfive,jh8100-syscrg-nw";
+ reg = <0x0 0x123c0000 0x0 0x10000>;
+ clocks = <&clk_osc>, <&syscrg SYSCRG_CLK_APB_BUS>,
+ <&syscrg SYSCRG_CLK_ISP_2X>, <&syscrg SYSCRG_CLK_ISP_AXI>,
+ <&syscrg SYSCRG_CLK_VOUT_ROOT0>, <&syscrg SYSCRG_CLK_VOUT_ROOT1>,
+ <&syscrg SYSCRG_CLK_VOUT_SCAN_ATS>,
+ <&syscrg SYSCRG_CLK_VOUT_DC_CORE>, <&syscrg SYSCRG_CLK_VOUT_AXI>,
+ <&syscrg SYSCRG_CLK_AXI_400>, <&syscrg SYSCRG_CLK_AXI_200>,
+ <&syscrg SYSCRG_CLK_PERH_ROOT_PREOSC>,
+ <&clk_dvp_ext>, <&clk_isp_dphy_tap_tck_ext>,
+ <&clk_glb_ext_clk>, <&clk_i2s_tscko>,
+ <&clk_vout_mipi_dphy_tap_tck_ext>, <&clk_vout_edp_tap_tck_ext>,
+ <&clk_spi_in2_ext>;
+ clock-names = "clk_osc", "sys_clk_apb_bus",
+ "sys_clk_isp_2x", "sys_clk_isp_axi",
+ "sys_clk_vout_root0", "sys_clk_vout_root1",
+ "sys_clk_vout_scan_ats", "sys_clk_vout_dc_core",
+ "sys_clk_vout_axi", "sys_clk_axi_400",
+ "sys_clk_axi_200", "sys_clk_perh_root_preosc", "clk_dvp_ext",
+ "clk_isp_dphy_tap_tck_ext", "clk_glb_ext_clk",
+ "clk_i2s_tscko", "clk_vout_mipi_dphy_tap_tck_ext",
+ "clk_vout_edp_tap_tck_ext", "clk_spi_in2_ext";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ syscrg: syscrg@126d0000 {
+ compatible = "starfive,jh8100-syscrg";
+ reg = <0x0 0x126d0000 0x0 0x10000>;
+ clocks = <&clk_osc>, <&clk_i2srx_bclk_ext>,
+ <&clk_i2srx_lrck_ext>, <&clk_mclk_ext>;
+ clock-names = "clk_osc", "clk_i2srx_bclk_ext",
+ "clk_i2srx_lrck_ext", "clk_mclk_ext";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ syscrg_sw: syscrg_sw@12720000 {
+ compatible = "starfive,jh8100-syscrg-sw";
+ reg = <0x0 0x12720000 0x0 0x10000>;
+ clocks = <&syscrg SYSCRG_CLK_APB_BUS>,
+ <&syscrg SYSCRG_CLK_VDEC_ROOT>,
+ <&syscrg SYSCRG_CLK_FLEXNOC1>;
+ clock-names = "sys_clk_apb_bus",
+ "sys_clk_vdec_root",
+ "sys_clk_flexnoc1";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
uart5: serial@127d0000 {
compatible = "starfive,jh8100-uart", "cdns,uart-r1p8";
reg = <0x0 0x127d0000 0x0 0x10000>;
@@ -374,5 +475,19 @@ uart6: serial@127e0000 {
interrupts = <73>;
status = "disabled";
};
+
+ aoncrg: aoncrg@1f310000 {
+ compatible = "starfive,jh8100-aoncrg";
+ reg = <0x0 0x1f310000 0x0 0x10000>;
+ clocks = <&clk_osc>, <&clk_gmac0_rmii_func>,
+ <&clk_gmac0_rgmii_func>, <&clk_aon125>,
+ <&clk_aon2000>, <&clk_aon200>,
+ <&clk_aon667>, <&clk_rtc>;
+ clock-names = "clk_osc", "clk_gmac0_rmii_func", "clk_gmac0_rgmii_func",
+ "clk_aon125", "clk_aon2000", "clk_aon200",
+ "clk_aon667", "clk_rtc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
};
};
--
2.34.1
Add auxiliary reset driver to support StarFive JH8100 SoC.
Co-developed-by: Joshua Yeong <[email protected]>
Signed-off-by: Joshua Yeong <[email protected]>
Signed-off-by: Sia Jee Heng <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
---
MAINTAINERS | 7 ++
drivers/reset/starfive/Kconfig | 8 ++
drivers/reset/starfive/Makefile | 2 +
.../reset/starfive/reset-starfive-jh8100.c | 102 ++++++++++++++++++
4 files changed, 119 insertions(+)
create mode 100644 drivers/reset/starfive/reset-starfive-jh8100.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 87bcb25becc1..ed728f013d32 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20771,6 +20771,13 @@ F: Documentation/devicetree/bindings/clock/starfive,jh81*.yaml
F: drivers/clk/starfive/jh8100
F: include/dt-bindings/clock/starfive?jh81*.h
+STARFIVE JH8100 RESET CONTROLLER DRIVERS
+M: Sia Jee Heng <[email protected]>
+M: Ley Foon Tan <[email protected]>
+S: Maintained
+F: drivers/reset/starfive/reset-starfive-jh81*
+F: include/dt-bindings/reset/starfive?jh81*.h
+
STATIC BRANCH/CALL
M: Peter Zijlstra <[email protected]>
M: Josh Poimboeuf <[email protected]>
diff --git a/drivers/reset/starfive/Kconfig b/drivers/reset/starfive/Kconfig
index 29fbcf1a7d83..88d050044d52 100644
--- a/drivers/reset/starfive/Kconfig
+++ b/drivers/reset/starfive/Kconfig
@@ -19,3 +19,11 @@ config RESET_STARFIVE_JH7110
default ARCH_STARFIVE
help
This enables the reset controller driver for the StarFive JH7110 SoC.
+
+config RESET_STARFIVE_JH8100
+ bool "StarFive JH8100 Reset Driver"
+ depends on AUXILIARY_BUS && CLK_STARFIVE_JH8100_SYS
+ select RESET_STARFIVE_COMMON
+ default ARCH_STARFIVE
+ help
+ This enables the reset controller driver for the StarFive JH8100 SoC.
diff --git a/drivers/reset/starfive/Makefile b/drivers/reset/starfive/Makefile
index 582e4c160bd4..ede1fc1c9601 100644
--- a/drivers/reset/starfive/Makefile
+++ b/drivers/reset/starfive/Makefile
@@ -3,3 +3,5 @@ obj-$(CONFIG_RESET_STARFIVE_COMMON) += reset-starfive-common.o
obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
obj-$(CONFIG_RESET_STARFIVE_JH7110) += reset-starfive-jh7110.o
+
+obj-$(CONFIG_RESET_STARFIVE_JH8100) += reset-starfive-jh8100.o
diff --git a/drivers/reset/starfive/reset-starfive-jh8100.c b/drivers/reset/starfive/reset-starfive-jh8100.c
new file mode 100644
index 000000000000..84f3781a22a5
--- /dev/null
+++ b/drivers/reset/starfive/reset-starfive-jh8100.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Reset driver for the StarFive JH8100 SoC
+ *
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ */
+
+#include <dt-bindings/reset/starfive,jh8100-crg.h>
+#include <linux/auxiliary_bus.h>
+#include <soc/starfive/reset-starfive-common.h>
+
+#include "reset-starfive-common.h"
+
+struct jh8100_reset_info {
+ unsigned int nr_resets;
+ unsigned int assert_offset;
+ unsigned int status_offset;
+};
+
+static const struct jh8100_reset_info jh8100_sys_info = {
+ .nr_resets = SYSCRG_RESET_NR_RESETS,
+ .assert_offset = 0x1B4,
+ .status_offset = 0x1B8,
+};
+
+static const struct jh8100_reset_info jh8100_sys_nw_info = {
+ .nr_resets = SYSCRG_NW_RESET_NR_RESETS,
+ .assert_offset = 0xA4,
+ .status_offset = 0xA8,
+};
+
+static const struct jh8100_reset_info jh8100_sys_ne_info = {
+ .nr_resets = SYSCRG_NE_RESET_NR_RESETS,
+ .assert_offset = 0x2BC,
+ .status_offset = 0x2C4,
+};
+
+static const struct jh8100_reset_info jh8100_sys_sw_info = {
+ .nr_resets = SYSCRG_SW_RESET_NR_RESETS,
+ .assert_offset = 0x28,
+ .status_offset = 0x2C,
+};
+
+static const struct jh8100_reset_info jh8100_aon_info = {
+ .nr_resets = AONCRG_RESET_NR_RESETS,
+ .assert_offset = 0x104,
+ .status_offset = 0x108,
+};
+
+static int jh8100_reset_probe(struct auxiliary_device *adev,
+ const struct auxiliary_device_id *id)
+{
+ struct jh8100_reset_info *info = (struct jh8100_reset_info *)
+ (id->driver_data);
+ struct starfive_reset_adev *rdev = to_starfive_reset_adev(adev);
+ void __iomem *base = rdev->base;
+
+ if (!info || !base)
+ return -ENODEV;
+
+ return reset_starfive_register(&adev->dev,
+ adev->dev.parent->of_node,
+ base + info->assert_offset,
+ base + info->status_offset, NULL,
+ info->nr_resets, NULL);
+}
+
+static const struct auxiliary_device_id jh8100_reset_ids[] = {
+ {
+ .name = "clk_sys.rst-sys",
+ .driver_data = (kernel_ulong_t)&jh8100_sys_info,
+ },
+ {
+ .name = "clk_sys.rst-sys-nw",
+ .driver_data = (kernel_ulong_t)&jh8100_sys_nw_info,
+ },
+ {
+ .name = "clk_sys.rst-sys-ne",
+ .driver_data = (kernel_ulong_t)&jh8100_sys_ne_info,
+ },
+ {
+ .name = "clk_sys.rst-sys-sw",
+ .driver_data = (kernel_ulong_t)&jh8100_sys_sw_info,
+ },
+ {
+ .name = "clk_sys.rst-aon",
+ .driver_data = (kernel_ulong_t)&jh8100_aon_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(auxiliary, jh8100_reset_ids);
+
+static struct auxiliary_driver jh8100_reset_driver = {
+ .probe = jh8100_reset_probe,
+ .id_table = jh8100_reset_ids,
+};
+module_auxiliary_driver(jh8100_reset_driver);
+
+MODULE_AUTHOR("Joshua Yeong <[email protected]>");
+MODULE_AUTHOR("Sia Jee Heng <[email protected]>");
+MODULE_DESCRIPTION("StarFive JH8100 reset driver");
+MODULE_LICENSE("GPL");
--
2.34.1
Add support for JH8100 System-South-West clock generator.
Signed-off-by: Sia Jee Heng <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
---
drivers/clk/starfive/Kconfig | 8 ++
drivers/clk/starfive/jh8100/Makefile | 1 +
drivers/clk/starfive/jh8100/clk-sys-sw.c | 136 +++++++++++++++++++++++
3 files changed, 145 insertions(+)
create mode 100644 drivers/clk/starfive/jh8100/clk-sys-sw.c
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index acd530c3897b..2d8a1e0fae8a 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -97,3 +97,11 @@ config CLK_STARFIVE_JH8100_SYS_NE
help
Say yes here to support the System-North-East clock controller on the StarFive JH8100
SoC.
+
+config CLK_STARFIVE_JH8100_SYS_SW
+ bool "StarFive JH8100 System-South-West clock support"
+ depends on CLK_STARFIVE_JH8100_SYS
+ default ARCH_STARFIVE
+ help
+ Say yes here to support the System-South-West clock controller on the StarFive JH8100
+ SoC.
diff --git a/drivers/clk/starfive/jh8100/Makefile b/drivers/clk/starfive/jh8100/Makefile
index 164c1d55b97c..5c14bff5c541 100644
--- a/drivers/clk/starfive/jh8100/Makefile
+++ b/drivers/clk/starfive/jh8100/Makefile
@@ -3,3 +3,4 @@
obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS) += clk-sys.o
obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS_NW) += clk-sys-nw.o
obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS_NE) += clk-sys-ne.o
+obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS_SW) += clk-sys-sw.o
diff --git a/drivers/clk/starfive/jh8100/clk-sys-sw.c b/drivers/clk/starfive/jh8100/clk-sys-sw.c
new file mode 100644
index 000000000000..d88dd8741b5d
--- /dev/null
+++ b/drivers/clk/starfive/jh8100/clk-sys-sw.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH8100 System Clock Driver
+ *
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ *
+ * Author: Jee Heng Sia <[email protected]>
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <dt-bindings/clock/starfive,jh8100-crg.h>
+
+#include "clk-starfive-jh8100.h"
+
+/* external clocks */
+#define SYSCRG_SW_CLK_APB_BUS (SYSCRG_SW_CLK_END + 0)
+#define SYSCRG_SW_CLK_VDEC_ROOT (SYSCRG_SW_CLK_END + 1)
+#define SYSCRG_SW_CLK_FLEXNOC1 (SYSCRG_SW_CLK_END + 2)
+
+static const struct starfive_clk_data jh8100_syscrg_sw_clk_data[] = {
+ /* jpeg */
+ STARFIVE__DIV(SYSCRG_SW_CLK_JPEG_AXI, "sys_sw_clk_jpeg_axi", 20,
+ SYSCRG_SW_CLK_VDEC_ROOT),
+ STARFIVE_GATE(SYSCRG_SW_CLK_VC9000DJ_AXI, "sys_sw_clk_vc9000dj_axi",
+ CLK_IGNORE_UNUSED, SYSCRG_SW_CLK_JPEG_AXI),
+ STARFIVE_GDIV(SYSCRG_SW_CLK_VC9000DJ_VDEC, "sys_sw_clk_vc9000dj_vdec",
+ CLK_IGNORE_UNUSED, 40, SYSCRG_SW_CLK_VDEC_ROOT),
+ STARFIVE_GATE(SYSCRG_SW_CLK_VC9000DJ_APB, "sys_sw_clk_vc9000dj_apb",
+ CLK_IGNORE_UNUSED, SYSCRG_SW_CLK_APB_BUS),
+ /* video dec */
+ STARFIVE__DIV(SYSCRG_SW_CLK_VDEC_AXI, "sys_sw_clk_vdec_axi", 20,
+ SYSCRG_SW_CLK_VDEC_ROOT),
+ STARFIVE_GATE(SYSCRG_SW_CLK_VC9000D_AXI, "sys_sw_clk_vc9000d_axi", CLK_IGNORE_UNUSED,
+ SYSCRG_SW_CLK_VDEC_AXI),
+ STARFIVE_GDIV(SYSCRG_SW_CLK_VC9000D_VDEC, "sys_sw_clk_vc9000d_vdec",
+ CLK_IGNORE_UNUSED, 40, SYSCRG_SW_CLK_FLEXNOC1),
+ STARFIVE_GATE(SYSCRG_SW_CLK_VC9000D_APB, "sys_sw_clk_vc9000d_apb", CLK_IGNORE_UNUSED,
+ SYSCRG_SW_CLK_APB_BUS),
+ /* icg_en */
+ STARFIVE_GATE(SYSCRG_SW_CLK_JPEG_ICG_EN, "sys_sw_clk_jpeg_en", 0,
+ SYSCRG_SW_CLK_VDEC_ROOT),
+ STARFIVE_GATE(SYSCRG_SW_CLK_VDEC_ICG_EN, "sys_sw_clk_vdec_en", 0,
+ SYSCRG_SW_CLK_VDEC_AXI),
+};
+
+static struct clk_hw *jh8100_syscrg_sw_clk_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct starfive_clk_priv *priv = data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx < SYSCRG_SW_CLK_END)
+ return &priv->reg[idx].hw;
+
+ return ERR_PTR(-EINVAL);
+}
+
+static int jh8100_syscrg_sw_probe(struct platform_device *pdev)
+{
+ struct starfive_clk_priv *priv;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, reg, SYSCRG_SW_CLK_END),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ for (idx = 0; idx < SYSCRG_SW_CLK_END; idx++) {
+ u32 max = jh8100_syscrg_sw_clk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jh8100_syscrg_sw_clk_data[idx].name,
+ .ops = starfive_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
+ .flags = jh8100_syscrg_sw_clk_data[idx].flags,
+ };
+ struct starfive_clk *clk = &priv->reg[idx];
+ unsigned int i;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jh8100_syscrg_sw_clk_data[idx].parents[i];
+
+ if (pidx < SYSCRG_SW_CLK_END)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx == SYSCRG_SW_CLK_APB_BUS)
+ parents[i].fw_name = "sys_clk_apb_bus";
+ else if (pidx == SYSCRG_SW_CLK_VDEC_ROOT)
+ parents[i].fw_name = "sys_clk_vdec_root";
+ else if (pidx == SYSCRG_SW_CLK_FLEXNOC1)
+ parents[i].fw_name = "sys_clk_flexnoc1";
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, jh8100_syscrg_sw_clk_get, priv);
+ if (ret)
+ return ret;
+
+ return jh8100_reset_controller_register(priv, "rst-sys-sw", 3);
+}
+
+static const struct of_device_id jh8100_syscrg_sw_match[] = {
+ { .compatible = "starfive,jh8100-syscrg-sw" },
+ { /* sentinel */ }
+};
+
+static struct platform_driver jh8100_syscrg_sw_driver = {
+ .driver = {
+ .name = "clk-starfive-jh8100-sys-sw",
+ .of_match_table = jh8100_syscrg_sw_match,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver_probe(jh8100_syscrg_sw_driver, jh8100_syscrg_sw_probe);
--
2.34.1
Add support for JH8100 Always-On clock generator.
Signed-off-by: Sia Jee Heng <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
---
drivers/clk/starfive/Kconfig | 8 +
drivers/clk/starfive/jh8100/Makefile | 1 +
drivers/clk/starfive/jh8100/clk-aon.c | 275 ++++++++++++++++++++++++++
3 files changed, 284 insertions(+)
create mode 100644 drivers/clk/starfive/jh8100/clk-aon.c
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 2d8a1e0fae8a..7a8bb958f915 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -105,3 +105,11 @@ config CLK_STARFIVE_JH8100_SYS_SW
help
Say yes here to support the System-South-West clock controller on the StarFive JH8100
SoC.
+
+config CLK_STARFIVE_JH8100_AON
+ bool "StarFive JH8100 Always-On clock support"
+ depends on CLK_STARFIVE_JH8100_SYS
+ default ARCH_STARFIVE
+ help
+ Say yes here to support the Always-On clock controller on the StarFive JH8100
+ SoC.
diff --git a/drivers/clk/starfive/jh8100/Makefile b/drivers/clk/starfive/jh8100/Makefile
index 5c14bff5c541..1decc43de0d3 100644
--- a/drivers/clk/starfive/jh8100/Makefile
+++ b/drivers/clk/starfive/jh8100/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS) += clk-sys.o
obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS_NW) += clk-sys-nw.o
obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS_NE) += clk-sys-ne.o
obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS_SW) += clk-sys-sw.o
+obj-$(CONFIG_CLK_STARFIVE_JH8100_AON) += clk-aon.o
diff --git a/drivers/clk/starfive/jh8100/clk-aon.c b/drivers/clk/starfive/jh8100/clk-aon.c
new file mode 100644
index 000000000000..95c10d5a9552
--- /dev/null
+++ b/drivers/clk/starfive/jh8100/clk-aon.c
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH8100 System Clock Driver
+ *
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ *
+ * Author: Jee Heng Sia <[email protected]>
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <dt-bindings/clock/starfive,jh8100-crg.h>
+
+#include "clk-starfive-jh8100.h"
+
+/* external clocks */
+#define AONCRG_CLK_OSC (AONCRG_CLK_END + 0)
+#define AONCRG_CLK_GMAC0_RMII_FUNC (AONCRG_CLK_END + 1)
+#define AONCRG_CLK_AON_50 (AONCRG_CLK_END + 2)
+#define AONCRG_CLK_GMAC0_RGMII_FUNC (AONCRG_CLK_END + 3)
+#define AONCRG_CLK_AON_125 (AONCRG_CLK_END + 4)
+#define AONCRG_CLK_AON_2000 (AONCRG_CLK_END + 5)
+#define AONCRG_CLK_AON_200 (AONCRG_CLK_END + 6)
+#define AONCRG_CLK_AON_667 (AONCRG_CLK_END + 7)
+#define AONCRG_CLK_RTC (AONCRG_CLK_END + 8)
+
+static const struct starfive_clk_data jh8100_aoncrg_clk_data[] = {
+ /* source */
+ STARFIVE__MUX(AONCRG_CLK_GMAC0_RMII_REFIN, "aon_clk_gmac0_rmii_refin", 2,
+ AONCRG_CLK_GMAC0_RMII_FUNC, AONCRG_CLK_AON_50),
+ STARFIVE__MUX(AONCRG_CLK_GMAC0_RGMII_RXIN, "aon_clk_gmac0_rgmii_rxin", 2,
+ AONCRG_CLK_GMAC0_RGMII_FUNC, AONCRG_CLK_AON_125),
+ STARFIVE__DIV(AONCRG_CLK_GMAC0_GTXCLK, "aon_clk_gmac0_gtxclk", 50,
+ AONCRG_CLK_AON_125),
+ STARFIVE__DIV(AONCRG_CLK_AON_1000, "aon_clk_aon_1000", 2,
+ AONCRG_CLK_AON_2000),
+ STARFIVE__DIV(AONCRG_CLK_AON_400, "aon_clk_aon_400", 5,
+ AONCRG_CLK_AON_2000),
+ STARFIVE__MUX(AONCRG_CLK_AON_400_POSTOSC, "aon_clk_aon_400_postosc", 2,
+ AONCRG_CLK_OSC, AONCRG_CLK_AON_400),
+ STARFIVE__DIV(AONCRG_CLK_AON_500, "aon_clk_aon_500", 4,
+ AONCRG_CLK_AON_2000),
+ STARFIVE__MUX(AONCRG_CLK_AON_500_POSTOSC, "aon_clk_aon_500_postosc", 2,
+ AONCRG_CLK_OSC, AONCRG_CLK_AON_500),
+ STARFIVE__DIV(AONCRG_CLK_XSPI_PHY, "aon_clk_xspi_phy", 4,
+ AONCRG_CLK_AON_200),
+ STARFIVE__DIV(AONCRG_CLK_AON_100, "aon_clk_aon_100", 2,
+ AONCRG_CLK_AON_200),
+ STARFIVE__MUX(AONCRG_CLK_AON_100_POSTOSC, "aon_clk_aon_100_postosc", 2,
+ AONCRG_CLK_OSC, AONCRG_CLK_AON_100),
+ STARFIVE__MUX(AONCRG_CLK_AON_50_POSTOSC, "aon_clk_aon_50_postosc", 2,
+ AONCRG_CLK_OSC, AONCRG_CLK_AON_50),
+ STARFIVE_GATE(AONCRG_CLK_DDR50_POSTOCC_ICG, "aon_clk_ddr50_postocc", CLK_IS_CRITICAL,
+ AONCRG_CLK_AON_50_POSTOSC),
+ STARFIVE_GATE(AONCRG_CLK_DDR100_POSTOCC_ICG, "aon_clk_ddr100_postocc", CLK_IS_CRITICAL,
+ AONCRG_CLK_AON_100),
+ /* pufrt */
+ STARFIVE_GATE(AONCRG_CLK_PUFRT_APB, "aon_clk_pufrt_apb", CLK_IS_CRITICAL,
+ AONCRG_CLK_OSC),
+ /* rtc hms */
+ STARFIVE_GATE(AONCRG_CLK_RTC_HMS_APB, "aon_clk_rtc_hms_apb", 0,
+ AONCRG_CLK_OSC),
+ STARFIVE__DIV(AONCRG_CLK_RTC_INTERNAL, "aon_clk_rtc_internal", 1020,
+ AONCRG_CLK_OSC),
+ STARFIVE__MUX(AONCRG_CLK_RTC_HMS_OSC32K, "aon_clk_rtc_hms_osc32k", 2,
+ AONCRG_CLK_RTC, AONCRG_CLK_RTC_INTERNAL),
+ STARFIVE_GATE(AONCRG_CLK_RTC_HMS_CAL, "aon_clk_rtc_hms_cal", 0,
+ AONCRG_CLK_OSC),
+ /* gmac5_axi128 */
+ STARFIVE_GATE(AONCRG_CLK_GMAC0_AXI128_AHB, "aon_clk_gmac0_axi128_ahb",
+ CLK_IGNORE_UNUSED, AONCRG_CLK_AON_200),
+ STARFIVE_GATE(AONCRG_CLK_GMAC0_AXI128_MSTRCLK, "aon_clk_gmac0_axi128_mstrclk",
+ CLK_IGNORE_UNUSED, AONCRG_CLK_AON_667),
+ STARFIVE_GATE(AONCRG_CLK_GMAC0_AXI128_AXI, "aon_clk_gmac0_axi128_axi",
+ CLK_IGNORE_UNUSED, AONCRG_CLK_AON_400_POSTOSC),
+ STARFIVE__DIV(AONCRG_CLK_GMAC0_RMII_RTX, "aon_clk_gmac0_rmii_rtx", 30,
+ AONCRG_CLK_GMAC0_RMII_REFIN),
+ STARFIVE_GMUX(AONCRG_CLK_GMAC0_AXI128_TX, "aon_clk_gmac0_axi128_tx",
+ CLK_IGNORE_UNUSED, 2, AONCRG_CLK_GMAC0_GTXCLK,
+ AONCRG_CLK_GMAC0_RMII_RTX),
+ STARFIVE_GINV(AONCRG_CLK_GMAC0_AXI128_TX_INV, "aon_clk_gmac0_axi128_tx_inv",
+ CLK_IGNORE_UNUSED, AONCRG_CLK_GMAC0_AXI128_TX),
+ STARFIVE__MUX(AONCRG_CLK_GMAC0_AXI128_RX, "aon_clk_gmac0_axi128_rx", 2,
+ AONCRG_CLK_GMAC0_RGMII_RXIN, AONCRG_CLK_GMAC0_RMII_RTX),
+ STARFIVE__INV(AONCRG_CLK_GMAC0_AXI128_RX_INV, "aon_clk_gmac0_axi128_rx_inv",
+ AONCRG_CLK_GMAC0_AXI128_RX),
+ STARFIVE_GATE(AONCRG_CLK_GMAC0_GTXC, "aon_clk_gmac0_gtxc", CLK_IGNORE_UNUSED,
+ AONCRG_CLK_GMAC0_GTXCLK),
+ /* xspi */
+ STARFIVE_GATE(AONCRG_CLK_XSPI_AXI, "aon_clk_xspi_axi", CLK_IGNORE_UNUSED,
+ AONCRG_CLK_AON_200),
+ STARFIVE_GATE(AONCRG_CLK_XSPI_APB, "aon_clk_xspi_apb", CLK_IGNORE_UNUSED,
+ AONCRG_CLK_OSC),
+ STARFIVE_GMUX(AONCRG_CLK_XSPI_XSPI_PHY, "aon_clk_xspi_xspi_phy", CLK_IGNORE_UNUSED, 2,
+ AONCRG_CLK_OSC, AONCRG_CLK_XSPI_PHY),
+ /* tvsensor */
+ STARFIVE_GATE(AONCRG_CLK_TVSENSOR_PCLK, "aon_clk_tvsensor_pclk", CLK_IGNORE_UNUSED,
+ AONCRG_CLK_OSC),
+ STARFIVE_GATE(AONCRG_CLK_TVSENSOR_TSADC, "aon_clk_tvsensor_tsadc", CLK_IGNORE_UNUSED,
+ AONCRG_CLK_OSC),
+ STARFIVE_GDIV(AONCRG_CLK_TVSENSOR_BG, "aon_clk_tvsensor_bg",
+ CLK_IGNORE_UNUSED, 3, AONCRG_CLK_OSC),
+ /* meu */
+ STARFIVE_GATE(AONCRG_CLK_MEU_PCLK_AP, "aon_clk_meu_pclk_ap", CLK_IGNORE_UNUSED,
+ AONCRG_CLK_OSC),
+ STARFIVE_GATE(AONCRG_CLK_MEU_PCLK_SCP, "aon_clk_meu_pclk_scp", CLK_IGNORE_UNUSED,
+ AONCRG_CLK_OSC),
+ STARFIVE_GATE(AONCRG_CLK_MEU_MEM_AXI, "aon_clk_meu_mem_axi", CLK_IGNORE_UNUSED,
+ AONCRG_CLK_AON_200),
+ /* aximem_128b */
+ STARFIVE_GATE(AONCRG_CLK_AXIMEM_128B_ACLK, "aon_clk_aximem_128b_aclk", CLK_IS_CRITICAL,
+ AONCRG_CLK_AON_200),
+ /* apb2bisr */
+ STARFIVE_GATE(AONCRG_CLK_APB2BISR_APB, "aon_clk_apb2bisr_apb", CLK_IGNORE_UNUSED,
+ AONCRG_CLK_OSC),
+ STARFIVE_GATE(AONCRG_CLK_APB2BISR_BISR, "aon_clk_apb2bisr_bisr", CLK_IGNORE_UNUSED,
+ AONCRG_CLK_OSC),
+ /* emmc */
+ STARFIVE_GATE(AONCRG_CLK_EMMC_S_PCLK, "aon_clk_emmc_s_pclk",
+ CLK_IGNORE_UNUSED, AONCRG_CLK_AON_50_POSTOSC),
+ STARFIVE_GATE(AONCRG_CLK_EMMC_MSTRCLK, "aon_clk_emmc_mstrclk",
+ CLK_IGNORE_UNUSED, AONCRG_CLK_AON_667),
+ STARFIVE_GATE(AONCRG_CLK_EMMC, "aon_clk_emmc",
+ CLK_IGNORE_UNUSED, AONCRG_CLK_AON_200),
+ STARFIVE_GATE(AONCRG_CLK_EMMC_SDMCLK, "aon_clk_emmc_sdmclk",
+ CLK_IGNORE_UNUSED, AONCRG_CLK_AON_200),
+ STARFIVE_GATE(AONCRG_CLK_EMMC_SDPHY_PCLK, "aon_clk_emmc_sdphy_pclk",
+ CLK_IGNORE_UNUSED, AONCRG_CLK_AON_50_POSTOSC),
+ /* sdio */
+ STARFIVE_GATE(AONCRG_CLK_SDIO0_PCLK, "aon_clk_sdio0_pclk",
+ CLK_IGNORE_UNUSED, AONCRG_CLK_AON_50_POSTOSC),
+ STARFIVE_GATE(AONCRG_CLK_SDIO0_MSTRCLK, "aon_clk_sdio0_mstrclk",
+ CLK_IGNORE_UNUSED, AONCRG_CLK_AON_667),
+ STARFIVE_GATE(AONCRG_CLK_SDIO0, "aon_clk_sdio0",
+ CLK_IGNORE_UNUSED, AONCRG_CLK_AON_200),
+ STARFIVE_GATE(AONCRG_CLK_SDIO0_SDMCLK, "aon_clk_sdio0_sdmclk",
+ CLK_IGNORE_UNUSED, AONCRG_CLK_AON_200),
+ STARFIVE_GATE(AONCRG_CLK_SDIO0_SDPHY_PCLK, "aon_clk_sdio0_sdphy_pclk",
+ CLK_IGNORE_UNUSED, AONCRG_CLK_AON_50_POSTOSC),
+ /* top */
+ STARFIVE_GATE(AONCRG_CLK_HCLK, "aon_clk_hclk", CLK_IS_CRITICAL,
+ AONCRG_CLK_AON_200),
+ STARFIVE_GATE(AONCRG_CLK_ACLK, "aon_clk_aclk", CLK_IS_CRITICAL,
+ AONCRG_CLK_AON_500_POSTOSC),
+ STARFIVE_GATE(AONCRG_CLK_PERF_MSTRCLK, "aon_clk_perf_mstrclk", CLK_IS_CRITICAL,
+ AONCRG_CLK_AON_667),
+ STARFIVE_GATE(AONCRG_CLK_PERF_SLVCLK, "aon_clk_perf_slvclk", CLK_IS_CRITICAL,
+ AONCRG_CLK_AON_500_POSTOSC),
+ STARFIVE_GDIV(AONCRG_CLK_GCLK0, "aon_clk_gclk0",
+ CLK_IS_CRITICAL, 100, AONCRG_CLK_AON_1000),
+ STARFIVE_GATE(AONCRG_CLK_GCLK_OSC, "aon_clk_gclk_osc", CLK_IS_CRITICAL,
+ AONCRG_CLK_OSC),
+ /* icg_en */
+ STARFIVE_GATE(AONCRG_CLK_RTC_ICG_EN, "aon_clk_rtc_en", CLK_IGNORE_UNUSED,
+ AONCRG_CLK_OSC),
+ STARFIVE_GATE(AONCRG_CLK_GMAC0_ICG_EN, "aon_clk_gmac0_en", 0,
+ AONCRG_CLK_GMAC0_GTXCLK),
+ STARFIVE_GATE(AONCRG_CLK_XSPI_ICG_EN, "aon_clk_xspi_en", 0,
+ AONCRG_CLK_OSC),
+ STARFIVE_GATE(AONCRG_CLK_TVSENSOR0_ICG_EN, "aon_clk_tvsensor0_en", 0,
+ AONCRG_CLK_OSC),
+ STARFIVE_GATE(AONCRG_CLK_MEU_ICG_EN, "aon_clk_meu_en", CLK_IGNORE_UNUSED,
+ AONCRG_CLK_OSC),
+ STARFIVE_GATE(AONCRG_CLK_APB2BISR_ICG_EN, "aon_clk_apb2bisr_en", CLK_IGNORE_UNUSED,
+ AONCRG_CLK_OSC),
+ STARFIVE_GATE(AONCRG_CLK_EMMC_ICG_EN, "aon_clk_emmc_en", 0,
+ AONCRG_CLK_AON_50_POSTOSC),
+ STARFIVE_GATE(AONCRG_CLK_SDIO0_ICG_EN, "aon_clk_sdio0_en", 0,
+ AONCRG_CLK_AON_50_POSTOSC),
+ STARFIVE_GATE(AONCRG_CLK_TOP_ICG_EN, "aon_clk_top_en", CLK_IGNORE_UNUSED,
+ AONCRG_CLK_AON_500_POSTOSC),
+};
+
+static struct clk_hw *jh8100_aoncrg_clk_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct starfive_clk_priv *priv = data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx < AONCRG_CLK_END)
+ return &priv->reg[idx].hw;
+
+ return ERR_PTR(-EINVAL);
+}
+
+static int __init jh8100_aoncrg_probe(struct platform_device *pdev)
+{
+ struct starfive_clk_priv *priv;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, reg, AONCRG_CLK_END),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ for (idx = 0; idx < AONCRG_CLK_END; idx++) {
+ u32 max = jh8100_aoncrg_clk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jh8100_aoncrg_clk_data[idx].name,
+ .ops = starfive_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
+ .flags = jh8100_aoncrg_clk_data[idx].flags,
+ };
+ struct starfive_clk *clk = &priv->reg[idx];
+ unsigned int i;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jh8100_aoncrg_clk_data[idx].parents[i];
+
+ if (pidx < AONCRG_CLK_END)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx == AONCRG_CLK_OSC)
+ parents[i].fw_name = "clk_osc";
+ else if (pidx == AONCRG_CLK_GMAC0_RMII_FUNC)
+ parents[i].fw_name = "clk_gmac0_rmii_func";
+ else if (pidx == AONCRG_CLK_AON_50)
+ parents[i].fw_name = "clk_aon50";
+ else if (pidx == AONCRG_CLK_GMAC0_RGMII_FUNC)
+ parents[i].fw_name = "clk_gmac0_rgmii_func";
+ else if (pidx == AONCRG_CLK_AON_125)
+ parents[i].fw_name = "clk_aon125";
+ else if (pidx == AONCRG_CLK_AON_2000)
+ parents[i].fw_name = "clk_aon2000";
+ else if (pidx == AONCRG_CLK_AON_200)
+ parents[i].fw_name = "clk_aon200";
+ else if (pidx == AONCRG_CLK_AON_667)
+ parents[i].fw_name = "clk_aon667";
+ else if (pidx == AONCRG_CLK_RTC)
+ parents[i].fw_name = "clk_rtc";
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & STARFIVE_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, jh8100_aoncrg_clk_get, priv);
+ if (ret)
+ return ret;
+
+ return jh8100_reset_controller_register(priv, "rst-aon", 4);
+}
+
+static const struct of_device_id jh8100_aoncrg_match[] = {
+ { .compatible = "starfive,jh8100-aoncrg" },
+ { /* sentinel */ }
+};
+
+static struct platform_driver jh8100_aoncrg_driver = {
+ .driver = {
+ .name = "clk-starfive-jh8100-aon",
+ .of_match_table = jh8100_aoncrg_match,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver_probe(jh8100_aoncrg_driver, jh8100_aoncrg_probe);
--
2.34.1
Add bindings for the System-North-West clock and reset generator
(SYSCRG-NW) on JH8100 SoC.
Signed-off-by: Sia Jee Heng <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
---
.../clock/starfive,jh8100-syscrg-nw.yaml | 119 ++++++++++++++++++
.../dt-bindings/clock/starfive,jh8100-crg.h | 45 +++++++
.../dt-bindings/reset/starfive,jh8100-crg.h | 15 +++
3 files changed, 179 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-nw.yaml
diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-nw.yaml b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-nw.yaml
new file mode 100644
index 000000000000..b16a874828dd
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-nw.yaml
@@ -0,0 +1,119 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh8100-syscrg-nw.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH8100 System-North-West Clock and Reset Generator
+
+maintainers:
+ - Sia Jee Heng <[email protected]>
+
+properties:
+ compatible:
+ const: starfive,jh8100-syscrg-nw
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Main Oscillator (24 MHz)
+ - description: APB_BUS clock from SYSCRG
+ - description: ISP_2X clock from SYSCRG
+ - description: ISP_AXI clock from SYSCRG
+ - description: VOUT_ROOT0 clock from SYSCRG
+ - description: VOUT_ROOT1 clock from SYSCRG
+ - description: VOUT_SCAN_ATS clock from SYSCRG
+ - description: VOUT_DC_CORE clock from SYSCRG
+ - description: VOUT_AXI clock from SYSCRG
+ - description: AXI_400 clock from SYSCRG
+ - description: AXI_200 clock from SYSCRG
+ - description: Peripheral clock from SYSCRG
+ - description: External DVP clock
+ - description: External ISP DPHY TAP TCK clock
+ - description: External golbal clock
+ - description: External i2s_tscko clock
+ - description: External VOUT MIPI DPHY TAP TCK
+ - description: External VOUT eDP TAP TCK
+ - description: External SPI In2 clock
+
+ clock-names:
+ items:
+ - const: clk_osc
+ - const: sys_clk_apb_bus
+ - const: sys_clk_isp_2x
+ - const: sys_clk_isp_axi
+ - const: sys_clk_vout_root0
+ - const: sys_clk_vout_root1
+ - const: sys_clk_vout_scan_ats
+ - const: sys_clk_vout_dc_core
+ - const: sys_clk_vout_axi
+ - const: sys_clk_axi_400
+ - const: sys_clk_axi_200
+ - const: sys_clk_perh_root_preosc
+ - const: clk_dvp_ext
+ - const: clk_isp_dphy_tap_tck_ext
+ - const: clk_glb_ext_clk
+ - const: clk_i2s_tscko
+ - const: clk_vout_mipi_dphy_tap_tck_ext
+ - const: clk_vout_edp_tap_tck_ext
+ - const: clk_spi_in2_ext
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive,jh8100-crg.h> for valid indices.
+
+ '#reset-cells':
+ const: 1
+ description:
+ See <dt-bindings/reset/starfive,jh8100-crg.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/starfive,jh8100-crg.h>
+
+ clock-controller@123c0000 {
+ compatible = "starfive,jh8100-syscrg-nw";
+ reg = <0x123c0000 0x10000>;
+ clocks = <&clk_osc>, <&syscrg SYSCRG_CLK_APB_BUS>,
+ <&syscrg SYSCRG_CLK_ISP_2X>,
+ <&syscrg SYSCRG_CLK_ISP_AXI>,
+ <&syscrg SYSCRG_CLK_VOUT_ROOT0>,
+ <&syscrg SYSCRG_CLK_VOUT_ROOT1>,
+ <&syscrg SYSCRG_CLK_VOUT_SCAN_ATS>,
+ <&syscrg SYSCRG_CLK_VOUT_DC_CORE>,
+ <&syscrg SYSCRG_CLK_VOUT_AXI>,
+ <&syscrg SYSCRG_CLK_AXI_400>,
+ <&syscrg SYSCRG_CLK_AXI_200>,
+ <&syscrg SYSCRG_CLK_PERH_ROOT_PREOSC>,
+ <&clk_dvp_ext>,
+ <&clk_isp_dphy_tap_tck_ext>,
+ <&clk_glb_ext_clk>,
+ <&clk_i2s_tscko>,
+ <&clk_vout_mipi_dphy_tap_tck_ext>,
+ <&clk_vout_edp_tap_tck_ext>,
+ <&clk_spi_in2_ext>;
+ clock-names = "clk_osc", "sys_clk_apb_bus", "sys_clk_isp_2x",
+ "sys_clk_isp_axi", "sys_clk_vout_root0",
+ "sys_clk_vout_root1", "sys_clk_vout_scan_ats",
+ "sys_clk_vout_dc_core", "sys_clk_vout_axi",
+ "sys_clk_axi_400", "sys_clk_axi_200",
+ "sys_clk_perh_root_preosc", "clk_dvp_ext",
+ "clk_isp_dphy_tap_tck_ext", "clk_glb_ext_clk",
+ "clk_i2s_tscko", "clk_vout_mipi_dphy_tap_tck_ext",
+ "clk_vout_edp_tap_tck_ext", "clk_spi_in2_ext";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h
index e5bb588ce798..8417455c2409 100644
--- a/include/dt-bindings/clock/starfive,jh8100-crg.h
+++ b/include/dt-bindings/clock/starfive,jh8100-crg.h
@@ -120,4 +120,49 @@
#define SYSCRG_CLK_NNE_ICG_EN 108
#define SYSCRG_CLK_END 109
+
+/* SYSCRG_NW_CLK */
+#define SYSCRG_NW_CLK_PLL5_DIV2 0
+#define SYSCRG_NW_CLK_GCLK5 1
+#define SYSCRG_NW_CLK_GPIO_100 2
+#define SYSCRG_NW_CLK_GPIO_50 3
+#define SYSCRG_NW_CLK_GPIO_150 4
+#define SYSCRG_NW_CLK_GPIO_60 5
+#define SYSCRG_NW_CLK_IOMUX_WEST_PCLK 6
+#define SYSCRG_NW_CLK_I2C6_APB 7
+#define SYSCRG_NW_CLK_I2C7_APB 8
+#define SYSCRG_NW_CLK_SPI2_APB 9
+#define SYSCRG_NW_CLK_SPI2_CORE 10
+#define SYSCRG_NW_CLK_SPI2_SCLK_IN 11
+#define SYSCRG_NW_CLK_SMBUS1_APB 12
+#define SYSCRG_NW_CLK_SMBUS1_CORE 13
+#define SYSCRG_NW_CLK_ISP_DVP 14
+#define SYSCRG_NW_CLK_ISP_CORE_2X 15
+#define SYSCRG_NW_CLK_ISP_AXI 16
+#define SYSCRG_NW_CLK_ISP_DPHY_TAP_TCK 17
+#define SYSCRG_NW_CLK_FLEXNOC_ISPSLV 18
+#define SYSCRG_NW_CLK_VOUT_PIX0 19
+#define SYSCRG_NW_CLK_VOUT_PIX1 20
+#define SYSCRG_NW_CLK_VOUT_SCAN_ATS 21
+#define SYSCRG_NW_CLK_VOUT_DC_CORE 22
+#define SYSCRG_NW_CLK_VOUT_APB 23
+#define SYSCRG_NW_CLK_VOUT_DSI 24
+#define SYSCRG_NW_CLK_VOUT_AHB 25
+#define SYSCRG_NW_CLK_VOUT_AXI 26
+#define SYSCRG_NW_CLK_VOUT_MIPI_DPHY_TAP_TCK 27
+#define SYSCRG_NW_CLK_VOUT_EDP_PHY_TAP_TCK 28
+#define SYSCRG_NW_CLK_UART5_CORE_PREOSC 29
+#define SYSCRG_NW_CLK_UART5_APB 30
+#define SYSCRG_NW_CLK_UART5_CORE 31
+#define SYSCRG_NW_CLK_UART6_CORE_PREOSC 32
+#define SYSCRG_NW_CLK_UART6_APB 33
+#define SYSCRG_NW_CLK_UART6_CORE 34
+#define SYSCRG_NW_CLK_SPI2_ICG_EN 35
+#define SYSCRG_NW_CLK_SMBUS1_ICG_EN 36
+#define SYSCRG_NW_CLK_ISP_ICG_EN 37
+#define SYSCRG_NW_CLK_VOUT_ICG_EN 38
+#define SYSCRG_NW_CLK_UART5_ICG_EN 39
+#define SYSCRG_NW_CLK_UART6_ICG_EN 40
+
+#define SYSCRG_NW_CLK_END 41
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */
diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h
index 3b7b92488e76..8c3a858bdf6a 100644
--- a/include/dt-bindings/reset/starfive,jh8100-crg.h
+++ b/include/dt-bindings/reset/starfive,jh8100-crg.h
@@ -20,4 +20,19 @@
#define SYSCRG_RESET_NR_RESETS 8
+/*
+ * syscrg_nw: assert0
+ */
+#define SYSCRG_NW_RSTN_PRESETN 0
+#define SYSCRG_NW_RSTN_SYS_IOMUX_W 1
+#define SYSCRG_NW_RSTN_I2C6 2
+#define SYSCRG_NW_RSTN_I2C7 3
+#define SYSCRG_NW_RSTN_SPI2 4
+#define SYSCRG_NW_RSTN_SMBUS1 5
+#define SYSCRG_NW_RSTN_UART5 6
+#define SYSCRG_NW_RSTN_UART6 7
+#define SYSCRG_NW_RSTN_MERAK0_TVSENSOR 8
+#define SYSCRG_NW_RSTN_MERAK1_TVSENSOR 9
+
+#define SYSCRG_NW_RESET_NR_RESETS 10
#endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */
--
2.34.1
Add bindings for the System-North-East clock and reset generator
(SYSCRG-NE) on JH8100 SoC.
Signed-off-by: Sia Jee Heng <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
---
.../clock/starfive,jh8100-syscrg-ne.yaml | 158 ++++++++++++++++
.../dt-bindings/clock/starfive,jh8100-crg.h | 179 ++++++++++++++++++
.../dt-bindings/reset/starfive,jh8100-crg.h | 61 ++++++
3 files changed, 398 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-ne.yaml
diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-ne.yaml b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-ne.yaml
new file mode 100644
index 000000000000..e9c1156489b2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-ne.yaml
@@ -0,0 +1,158 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh8100-syscrg-ne.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH8100 System-North-East Clock and Reset Generator
+
+maintainers:
+ - Sia Jee Heng <[email protected]>
+
+properties:
+ compatible:
+ const: starfive,jh8100-syscrg-ne
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Main Oscillator (24 MHz)
+ - description: AXI_400 clock from SYSCRG
+ - description: VOUT_ROOT0 clock from SYSCRG
+ - description: VOUT_ROOT1 clock from SYSCRG
+ - description: USB_WRAP_480 clock from SYSCRG
+ - description: USB_WRAP_625 clock from SYSCRG
+ - description: USB_WRAP_240 clock from SYSCRG
+ - description: USB_WRAP_60 clock from SYSCRG
+ - description: USB_WRAP_156P25 clock from SYSCRG
+ - description: USB_WRAP_312P5 clock from SYSCRG
+ - description: USB_125M clock from SYSCRG
+ - description: GPIO_100 clock from SYSCRG_NW
+ - description: PERH_ROOT clock from SYSCRG
+ - description: Master clock from SYSCRG
+ - description: PERH_ROOT_PREOSC clock from SYSCRG
+ - description: AHB0 clock from SYSCRG
+ - description: APB_BUS_PER1 clock from SYSCRG
+ - description: APB_BUS PER2 clock from SYSCRG
+ - description: APB_BUS_PER3 clock from SYSCRG
+ - description: APB_BUS_PER5 clock from SYSCRG
+ - description: VENC_ROOT clock from SYSCRG
+ - description: SPI_CORE_100 clock from SYSCRG
+ - description: External global clock
+ - description: External USB3_TAP_TCK clock
+ - description: External USB1_TAP_TCK clock
+ - description: External USB2_TAP_TCK clock
+ - description: External TYPEC_TAP_TCK clock
+ - description: External SPI_IN0 clock
+ - description: External SPI_IN1 clock
+ - description: External I2STX_BCLK clock
+ - description: External I2STX_LRCK clock
+
+ clock-names:
+ items:
+ - const: clk_osc
+ - const: sys_clk_axi_400
+ - const: sys_clk_vout_root0
+ - const: sys_clk_vout_root1
+ - const: sys_clk_usb_wrap_480
+ - const: sys_clk_usb_wrap_625
+ - const: sys_clk_usb_wrap_240
+ - const: sys_clk_usb_wrap_60
+ - const: sys_clk_usb_wrap_156p25
+ - const: sys_clk_usb_wrap_312p5
+ - const: sys_clk_usb_125m
+ - const: sys_nw_clk_gpio_100
+ - const: sys_clk_perh_root
+ - const: sys_clk_mclk
+ - const: sys_clk_perh_root_preosc
+ - const: sys_clk_ahb0
+ - const: sys_clk_apb_bus_per1
+ - const: sys_clk_apb_bus_per2
+ - const: sys_clk_apb_bus_per3
+ - const: sys_clk_apb_bus_per5
+ - const: sys_clk_venc_root
+ - const: sys_clk_spi_core_100
+ - const: clk_glb_ext_clk
+ - const: clk_usb3_tap_tck_ext
+ - const: clk_usb1_tap_tck_ext
+ - const: clk_usb2_tap_tck_ext
+ - const: clk_typec_tap_tck_ext
+ - const: clk_spi_in0_ext
+ - const: clk_spi_in1_ext
+ - const: clk_i2stx_bclk_ext
+ - const: clk_i2stx_lrck_ext
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive,jh8100-crg.h> for valid indices.
+
+ '#reset-cells':
+ const: 1
+ description:
+ See <dt-bindings/reset/starfive-jh8100-crg.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/starfive,jh8100-crg.h>
+
+ clock-controller@12320000 {
+ compatible = "starfive,jh8100-syscrg-ne";
+ reg = <0x12320000 0x10000>;
+ clocks = <&clk_osc>, <&syscrg SYSCRG_CLK_AXI_400>,
+ <&syscrg SYSCRG_CLK_VOUT_ROOT0>,
+ <&syscrg SYSCRG_CLK_VOUT_ROOT1>,
+ <&syscrg SYSCRG_CLK_USB_WRAP_480>,
+ <&syscrg SYSCRG_CLK_USB_WRAP_625>,
+ <&syscrg SYSCRG_CLK_USB_WRAP_240>,
+ <&syscrg SYSCRG_CLK_USB_WRAP_60>,
+ <&syscrg SYSCRG_CLK_USB_WRAP_156P25>,
+ <&syscrg SYSCRG_CLK_USB_WRAP_312P5>,
+ <&syscrg SYSCRG_CLK_USB_125M>,
+ <&syscrg_nw SYSCRG_NW_CLK_GPIO_100>,
+ <&syscrg SYSCRG_CLK_PERH_ROOT>,
+ <&syscrg SYSCRG_CLK_MCLK>,
+ <&syscrg SYSCRG_CLK_PERH_ROOT_PREOSC>,
+ <&syscrg SYSCRG_CLK_AHB0>,
+ <&syscrg SYSCRG_CLK_APB_BUS_PER1>,
+ <&syscrg SYSCRG_CLK_APB_BUS_PER2>,
+ <&syscrg SYSCRG_CLK_APB_BUS_PER3>,
+ <&syscrg SYSCRG_CLK_APB_BUS_PER5>,
+ <&syscrg SYSCRG_CLK_VENC_ROOT>,
+ <&syscrg SYSCRG_CLK_SPI_CORE_100>,
+ <&clk_glb_ext_clk>, <&clk_usb3_tap_tck_ext>,
+ <&clk_usb1_tap_tck_ext>, <&clk_usb2_tap_tck_ext>,
+ <&clk_typec_tap_tck_ext>, <&clk_spi_in0_ext>,
+ <&clk_spi_in1_ext>, <&clk_i2stx_bclk_ext>,
+ <&clk_i2stx_lrck_ext>;
+ clock-names = "clk_osc", "sys_clk_axi_400",
+ "sys_clk_vout_root0", "sys_clk_vout_root1",
+ "sys_clk_usb_wrap_480", "sys_clk_usb_wrap_625",
+ "sys_clk_usb_wrap_240", "sys_clk_usb_wrap_60",
+ "sys_clk_usb_wrap_156p25", "sys_clk_usb_wrap_312p5",
+ "sys_clk_usb_125m", "sys_nw_clk_gpio_100",
+ "sys_clk_perh_root", "sys_clk_mclk",
+ "sys_clk_perh_root_preosc",
+ "sys_clk_ahb0", "sys_clk_apb_bus_per1",
+ "sys_clk_apb_bus_per2", "sys_clk_apb_bus_per3",
+ "sys_clk_apb_bus_per5", "sys_clk_venc_root",
+ "sys_clk_spi_core_100", "clk_glb_ext_clk",
+ "clk_usb3_tap_tck_ext", "clk_usb1_tap_tck_ext",
+ "clk_usb2_tap_tck_ext", "clk_typec_tap_tck_ext",
+ "clk_spi_in0_ext", "clk_spi_in1_ext",
+ "clk_i2stx_bclk_ext", "clk_i2stx_lrck_ext";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h
index 8417455c2409..b30ccd16a802 100644
--- a/include/dt-bindings/clock/starfive,jh8100-crg.h
+++ b/include/dt-bindings/clock/starfive,jh8100-crg.h
@@ -165,4 +165,183 @@
#define SYSCRG_NW_CLK_UART6_ICG_EN 40
#define SYSCRG_NW_CLK_END 41
+
+/* SYSCRG_NE_CLK */
+#define SYSCRG_NE_CLK_FLEXNOC_DMASLV 0
+#define SYSCRG_NE_CLK_MAILBOX_APB 1
+#define SYSCRG_NE_CLK_SR5_TIMER0_APB 2
+#define SYSCRG_NE_CLK_SR5_TIMER0_CH0 3
+#define SYSCRG_NE_CLK_SR5_TIMER0_CH1 4
+#define SYSCRG_NE_CLK_SR5_TIMER0_CH2 5
+#define SYSCRG_NE_CLK_SR5_TIMER0_CH3 6
+#define SYSCRG_NE_CLK_SR5_TIMER1_APB 7
+#define SYSCRG_NE_CLK_SR5_TIMER1_CH0 8
+#define SYSCRG_NE_CLK_SR5_TIMER1_CH1 9
+#define SYSCRG_NE_CLK_SR5_TIMER1_CH2 10
+#define SYSCRG_NE_CLK_SR5_TIMER1_CH3 11
+#define SYSCRG_NE_CLK_USB3_CMN_SCAN_PLL 12
+#define SYSCRG_NE_CLK_USB3_CMN_SCAN_SER 13
+#define SYSCRG_NE_CLK_USB3_PIPE_IN_SCAN 14
+#define SYSCRG_NE_CLK_USB3_SCAN_PIPE 15
+#define SYSCRG_NE_CLK_USB3_SCAN_PSM 16
+#define SYSCRG_NE_CLK_USB3_SCAN_REF 17
+#define SYSCRG_NE_CLK_USB3_USB2_SCAN 18
+#define SYSCRG_NE_CLK_USB3_HSCLK 19
+#define SYSCRG_NE_CLK_USB3_HSSICLK 20
+#define SYSCRG_NE_CLK_USB3_SIECLK 21
+#define SYSCRG_NE_CLK_USB3_XCVR_SCAN_PLL 22
+#define SYSCRG_NE_CLK_USB3_XCVR_SCAN_SER 23
+#define SYSCRG_NE_CLK_USB3_TAP_TCK 24
+#define SYSCRG_NE_CLK_USB1_CMN_SCAN_PLL 25
+#define SYSCRG_NE_CLK_USB1_CMN_SCAN_SER 26
+#define SYSCRG_NE_CLK_USB1_PIPE_IN_SCAN 27
+#define SYSCRG_NE_CLK_USB1_SCAN_PIPE 28
+#define SYSCRG_NE_CLK_USB1_SCAN_PSM 29
+#define SYSCRG_NE_CLK_USB1_SCAN_REF 30
+#define SYSCRG_NE_CLK_USB1_USB2_SCAN 31
+#define SYSCRG_NE_CLK_USB1_HSCLK 32
+#define SYSCRG_NE_CLK_USB1_HSSICLK 33
+#define SYSCRG_NE_CLK_USB1_SIECLK 34
+#define SYSCRG_NE_CLK_USB1_XCVR_SCAN_PLL 35
+#define SYSCRG_NE_CLK_USB1_XCVR_SCAN_SER 36
+#define SYSCRG_NE_CLK_USB1_TAP_TCK 37
+#define SYSCRG_NE_CLK_USB2_CMN_SCAN_PLL 38
+#define SYSCRG_NE_CLK_USB2_CMN_SCAN_SER 39
+#define SYSCRG_NE_CLK_USB2_PIPE_IN_SCAN 40
+#define SYSCRG_NE_CLK_USB2_SCAN_PIPE 41
+#define SYSCRG_NE_CLK_USB2_SCAN_PSM 42
+#define SYSCRG_NE_CLK_USB2_SCAN_REF 43
+#define SYSCRG_NE_CLK_USB2_USB2_SCAN 44
+#define SYSCRG_NE_CLK_USB2_HSCLK 45
+#define SYSCRG_NE_CLK_USB2_HSSICLK 46
+#define SYSCRG_NE_CLK_USB2_SIECLK 47
+#define SYSCRG_NE_CLK_USB2_XCVR_SCAN_PLL 48
+#define SYSCRG_NE_CLK_USB2_XCVR_SCAN_SER 49
+#define SYSCRG_NE_CLK_USB2_TAP_TCK 50
+#define SYSCRG_NE_CLK_TYPEC_PIPE_DIV_SCAN 51
+#define SYSCRG_NE_CLK_TYPEC_CMN_SCAN_PLL 52
+#define SYSCRG_NE_CLK_TYPEC_CMN_SCAN_SER 53
+#define SYSCRG_NE_CLK_TYPEC_SCAN_PIPE 54
+#define SYSCRG_NE_CLK_TYPEC_SCAN_PSM 55
+#define SYSCRG_NE_CLK_TYPEC_SCAN_REF 56
+#define SYSCRG_NE_CLK_TYPEC_USB2_SCAN 57
+#define SYSCRG_NE_CLK_TYPEC_HSCLK 58
+#define SYSCRG_NE_CLK_TYPEC_HSSICLK 59
+#define SYSCRG_NE_CLK_TYPEC_SIECLK 60
+#define SYSCRG_NE_CLK_TYPEC_VID0 61
+#define SYSCRG_NE_CLK_TYPEC_VID1 62
+#define SYSCRG_NE_CLK_TYPEC_XCVR_SCAN_PLL0 63
+#define SYSCRG_NE_CLK_TYPEC_XCVR_SCAN_PLL1 64
+#define SYSCRG_NE_CLK_TYPEC_XCVR_SCAN_PLL2 65
+#define SYSCRG_NE_CLK_TYPEC_XCVR_SCAN_PLL3 66
+#define SYSCRG_NE_CLK_TYPEC_XCVR_SCAN_SER0 67
+#define SYSCRG_NE_CLK_TYPEC_XCVR_SCAN_SER1 68
+#define SYSCRG_NE_CLK_TYPEC_XCVR_SCAN_SER2 69
+#define SYSCRG_NE_CLK_TYPEC_XCVR_SCAN_SER3 70
+#define SYSCRG_NE_CLK_TYPEC_TAP_TCK 71
+#define SYSCRG_NE_CLK_VENC_AXI 72
+#define SYSCRG_NE_CLK_VC9000LE_AXI 73
+#define SYSCRG_NE_CLK_VC9000LE_APB 74
+#define SYSCRG_NE_CLK_VC9000LE_CORECLK 75
+#define SYSCRG_NE_CLK_INT_CTRL_APB 76
+#define SYSCRG_NE_CLK_PWM_8CH_APB 77
+#define SYSCRG_NE_CLK_WDT_APB 78
+#define SYSCRG_NE_CLK_WDT 79
+#define SYSCRG_NE_CLK_SPI0_APB 80
+#define SYSCRG_NE_CLK_SPI0_CORE 81
+#define SYSCRG_NE_CLK_SPI0_SCLK_IN 82
+#define SYSCRG_NE_CLK_SPI1_APB 83
+#define SYSCRG_NE_CLK_SPI1_CORE 84
+#define SYSCRG_NE_CLK_SPI1_SCLK_IN 85
+#define SYSCRG_NE_CLK_I2C0_APB 86
+#define SYSCRG_NE_CLK_I2C1_APB 87
+#define SYSCRG_NE_CLK_I2C2_APB 88
+#define SYSCRG_NE_CLK_I2C3_APB 89
+#define SYSCRG_NE_CLK_I2C4_APB 90
+#define SYSCRG_NE_CLK_I2C5_APB 91
+#define SYSCRG_NE_CLK_UART0_APB 92
+#define SYSCRG_NE_CLK_UART0_CORE 93
+#define SYSCRG_NE_CLK_UART1_CORE_PREOSC 94
+#define SYSCRG_NE_CLK_UART1_APB 95
+#define SYSCRG_NE_CLK_UART1_CORE 96
+#define SYSCRG_NE_CLK_UART2_CORE_PREOSC 97
+#define SYSCRG_NE_CLK_UART2_APB 98
+#define SYSCRG_NE_CLK_UART2_CORE 99
+#define SYSCRG_NE_CLK_UART3_CORE_PREOSC 100
+#define SYSCRG_NE_CLK_UART3_APB 101
+#define SYSCRG_NE_CLK_UART3_CORE 102
+#define SYSCRG_NE_CLK_UART4_CORE_PREOSC 103
+#define SYSCRG_NE_CLK_UART4_APB 104
+#define SYSCRG_NE_CLK_UART4_CORE 105
+#define SYSCRG_NE_CLK_I2S0_BCLK 106
+#define SYSCRG_NE_CLK_I2S0_LRCK 107
+#define SYSCRG_NE_CLK_I2S0_APB 108
+#define SYSCRG_NE_CLK_I2S0 109
+#define SYSCRG_NE_CLK_I2S0_N 110
+#define SYSCRG_NE_CLK_I2S0_BCLK_TX 111
+#define SYSCRG_NE_CLK_I2S0_LRCK_TX 112
+#define SYSCRG_NE_CLK_I2S0_BCLK_RX 113
+#define SYSCRG_NE_CLK_I2S0_LRCK_RX 114
+#define SYSCRG_NE_CLK_I2S1_BCLK 115
+#define SYSCRG_NE_CLK_I2S1_LRCK 116
+#define SYSCRG_NE_CLK_I2S1_APB 117
+#define SYSCRG_NE_CLK_I2S1 118
+#define SYSCRG_NE_CLK_I2S1_N 119
+#define SYSCRG_NE_CLK_I2S1_BCLK_TX 120
+#define SYSCRG_NE_CLK_I2S1_LRCK_TX 121
+#define SYSCRG_NE_CLK_I2S1_BCLK_RX 122
+#define SYSCRG_NE_CLK_I2S1_LRCK_RX 123
+#define SYSCRG_NE_CLK_I2S2_BCLK 124
+#define SYSCRG_NE_CLK_I2S2_LRCK 125
+#define SYSCRG_NE_CLK_I2S2_APB 126
+#define SYSCRG_NE_CLK_I2S2 127
+#define SYSCRG_NE_CLK_I2S2_N 128
+#define SYSCRG_NE_CLK_I2S2_BCLK_TX 129
+#define SYSCRG_NE_CLK_I2S2_LRCK_TX 130
+#define SYSCRG_NE_CLK_I2S2_BCLK_RX 131
+#define SYSCRG_NE_CLK_I2S2_LRCK_RX 132
+#define SYSCRG_NE_CLK_I2S3_BCLK 133
+#define SYSCRG_NE_CLK_I2S3_LRCK 134
+#define SYSCRG_NE_CLK_I2S0_STEREO_APB 135
+#define SYSCRG_NE_CLK_I2S0_STEREO 136
+#define SYSCRG_NE_CLK_I2S0_STEREO_N 137
+#define SYSCRG_NE_CLK_I2S0_STEREO_BCLK_TX 138
+#define SYSCRG_NE_CLK_I2S0_STEREO_LRCK_TX 139
+#define SYSCRG_NE_CLK_I2S0_STEREO_BCLK_RX_ICG 140
+#define SYSCRG_NE_CLK_I2S0_STEREO_LRCK_RX 141
+#define SYSCRG_NE_CLK_PDM_4MIC_DMIC 142
+#define SYSCRG_NE_CLK_PDM_4MIC_APB 143
+#define SYSCRG_NE_CLK_PDM_4MIC_SCAN 144
+#define SYSCRG_NE_CLK_CAN0_CTRL_PCLK 145
+#define SYSCRG_NE_CLK_CAN0_CTRL 146
+#define SYSCRG_NE_CLK_CAN0_CTRL_TIMER 147
+#define SYSCRG_NE_CLK_CAN1_CTRL_PCLK 148
+#define SYSCRG_NE_CLK_CAN1_CTRL 149
+#define SYSCRG_NE_CLK_CAN1_CTRL_TIMER 150
+#define SYSCRG_NE_CLK_SMBUS0_APB 151
+#define SYSCRG_NE_CLK_SMBUS0_CORE 152
+#define SYSCRG_NE_CLK_IOMUX_EAST_PCLK 153
+#define SYSCRG_NE_CLK_USB3_ICG_EN 154
+#define SYSCRG_NE_CLK_USB1_ICG_EN 155
+#define SYSCRG_NE_CLK_USB2_ICG_EN 156
+#define SYSCRG_NE_CLK_USBC_ICG_EN 157
+#define SYSCRG_NE_CLK_VENC_ICG_EN 158
+#define SYSCRG_NE_CLK_WDT0_ICG_EN 159
+#define SYSCRG_NE_CLK_SPI0_ICG_EN 160
+#define SYSCRG_NE_CLK_SPI1_ICG_EN 161
+#define SYSCRG_NE_CLK_UART0_ICG_EN 162
+#define SYSCRG_NE_CLK_UART1_ICG_EN 163
+#define SYSCRG_NE_CLK_UART2_ICG_EN 164
+#define SYSCRG_NE_CLK_UART3_ICG_EN 165
+#define SYSCRG_NE_CLK_UART4_ICG_EN 166
+#define SYSCRG_NE_CLK_I2S0_ICG_EN 167
+#define SYSCRG_NE_CLK_I2S1_ICG_EN 168
+#define SYSCRG_NE_CLK_I2S2_ICG_EN 169
+#define SYSCRG_NE_CLK_I2S_STEREO_ICG_EN 170
+#define SYSCRG_NE_CLK_PDM_4MIC_ICG_EN 171
+#define SYSCRG_NE_CLK_CAN0_ICG_EN 172
+#define SYSCRG_NE_CLK_CAN1_ICG_EN 173
+#define SYSCRG_NE_CLK_SMBUS0_ICG_EN 174
+
+#define SYSCRG_NE_CLK_END 175
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */
diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h
index 8c3a858bdf6a..7626da648686 100644
--- a/include/dt-bindings/reset/starfive,jh8100-crg.h
+++ b/include/dt-bindings/reset/starfive,jh8100-crg.h
@@ -35,4 +35,65 @@
#define SYSCRG_NW_RSTN_MERAK1_TVSENSOR 9
#define SYSCRG_NW_RESET_NR_RESETS 10
+
+/*
+ * syscrg_ne: assert0
+ */
+#define SYSCRG_NE_RSTN_PRESETN 0
+#define SYSCRG_NE_RSTN_USB3_APB 1
+#define SYSCRG_NE_RSTN_USB3_TORR_PHY 2
+#define SYSCRG_NE_RSTN_USB3_CONFIG 3
+#define SYSCRG_NE_RSTN_USB1_APB 4
+#define SYSCRG_NE_RSTN_USB1_TORRENT_PHY 5
+#define SYSCRG_NE_RSTN_USB1_CONFIG 6
+#define SYSCRG_NE_RSTN_USB2_APB 7
+#define SYSCRG_NE_RSTN_USB2_TORRENT_PHY 8
+#define SYSCRG_NE_RSTN_USB2_CONFIG 9
+#define SYSCRG_NE_RSTN_USBC_APB 10
+#define SYSCRG_NE_RSTN_USBC_CONFIG 11
+#define SYSCRG_NE_RSTN_VC9000LE 12
+#define SYSCRG_NE_RSTN_INT_CTRL_APB 13
+#define SYSCRG_NE_RSTN_PWM_8CH_APB 14
+#define SYSCRG_NE_RSTN_WDT0 15
+#define SYSCRG_NE_RSTN_SPI0 16
+#define SYSCRG_NE_RSTN_SPI1 17
+#define SYSCRG_NE_RSTN_I2C0 18
+#define SYSCRG_NE_RSTN_I2C1 19
+#define SYSCRG_NE_RSTN_I2C2 20
+#define SYSCRG_NE_RSTN_I2C3 21
+#define SYSCRG_NE_RSTN_I2C4 22
+#define SYSCRG_NE_RSTN_I2C5 23
+#define SYSCRG_NE_RSTN_UART0 24
+#define SYSCRG_NE_RSTN_UART1 25
+#define SYSCRG_NE_RSTN_UART2 26
+#define SYSCRG_NE_RSTN_UART3 27
+#define SYSCRG_NE_RSTN_UART4 28
+#define SYSCRG_NE_RSTN_MAILBOX_PRESETN 29
+#define SYSCRG_NE_RSTN_TIMER0_APB 30
+#define SYSCRG_NE_RSTN_TIMER0_CH0 31
+
+/*
+ * syscrg_ne: assert1
+ */
+
+#define SYSCRG_NE_RSTN_TIMER0_CH1 32
+#define SYSCRG_NE_RSTN_TIMER0_CH2 33
+#define SYSCRG_NE_RSTN_TIMER0_CH3 34
+#define SYSCRG_NE_RSTN_TIMER1_APB 35
+#define SYSCRG_NE_RSTN_TIMER1_CH0 36
+#define SYSCRG_NE_RSTN_TIMER1_CH1 37
+#define SYSCRG_NE_RSTN_TIMER1_CH2 38
+#define SYSCRG_NE_RSTN_TIMER1_CH3 39
+#define SYSCRG_NE_RSTN_I2S0_RSTN_APB 40
+#define SYSCRG_NE_RSTN_I2S1_RSTN_APB 41
+#define SYSCRG_NE_RSTN_I2S2_RSTN_APB 42
+#define SYSCRG_NE_RSTN_I2S0_STEREO_APB 43
+#define SYSCRG_NE_RSTN_PDM 44
+#define SYSCRG_NE_RSTN_CAN0 45
+#define SYSCRG_NE_RSTN_CAN1 46
+#define SYSCRG_NE_RSTN_SMBUS0 47
+#define SYSCRG_NE_RSTN_SYS_IOMUX_E 48
+#define SYSCRG_NE_RSTN_DUBHE_TVSENSOR 49
+
+#define SYSCRG_NE_RESET_NR_RESETS 50
#endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */
--
2.34.1
Add bindings for the Always-On clock and reset generator
(AONCRG) on JH8100 SoC.
Signed-off-by: Sia Jee Heng <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
---
.../clock/starfive,jh8100-aoncrg.yaml | 77 +++++++++++++++++++
.../dt-bindings/clock/starfive,jh8100-crg.h | 69 +++++++++++++++++
.../dt-bindings/reset/starfive,jh8100-crg.h | 18 +++++
3 files changed, 164 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-aoncrg.yaml
diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-aoncrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh8100-aoncrg.yaml
new file mode 100644
index 000000000000..fd55bf212259
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-aoncrg.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh8100-aoncrg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH8100 Always-On Clock and Reset Generator
+
+maintainers:
+ - Sia Jee Heng <[email protected]>
+
+properties:
+ compatible:
+ const: starfive,jh8100-aoncrg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Main Oscillator (24 MHz)
+ - description: GMAC0 RMII func
+ - description: GMAC0 RGMII func
+ - description: AON 125MHz clock
+ - description: AON 2000MHz clock
+ - description: AON 200MHz clock
+ - description: AON 667MHz clock
+ - description: RTC clock
+
+ clock-names:
+ items:
+ - const: clk_osc
+ - const: clk_gmac0_rmii_func
+ - const: clk_gmac0_rgmii_func
+ - const: clk_aon125
+ - const: clk_aon2000
+ - const: clk_aon200
+ - const: clk_aon667
+ - const: clk_rtc
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive,jh8100-crg.h> for valid indices.
+
+ '#reset-cells':
+ const: 1
+ description:
+ See <dt-bindings/reset/starfive-jh8100-crg.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/starfive,jh8100-crg.h>
+
+ clock-controller@1f310000 {
+ compatible = "starfive,jh8100-aoncrg";
+ reg = <0x1f310000 0x10000>;
+ clocks = <&clk_osc>, <&clk_gmac0_rmii_func>,
+ <&clk_gmac0_rgmii_func>, <&clk_aon125>,
+ <&clk_aon2000>, <&clk_aon200>,
+ <&clk_aon667>, <&clk_rtc>;
+ clock-names = "clk_osc", "clk_gmac0_rmii_func", "clk_gmac0_rgmii_func",
+ "clk_aon125", "clk_aon2000", "clk_aon200",
+ "clk_aon667", "clk_rtc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h
index 3ce0b9ec66be..65e719bd51a5 100644
--- a/include/dt-bindings/clock/starfive,jh8100-crg.h
+++ b/include/dt-bindings/clock/starfive,jh8100-crg.h
@@ -358,4 +358,73 @@
#define SYSCRG_SW_CLK_VDEC_ICG_EN 9
#define SYSCRG_SW_CLK_END 10
+
+/* AONCRG_CLK */
+#define AONCRG_CLK_GMAC0_RMII_REFIN 0
+#define AONCRG_CLK_GMAC0_RGMII_RXIN 1
+#define AONCRG_CLK_GMAC0_GTXCLK 2
+#define AONCRG_CLK_AON_1000 3
+#define AONCRG_CLK_AON_400 4
+#define AONCRG_CLK_AON_400_POSTOSC 5
+#define AONCRG_CLK_AON_500 6
+#define AONCRG_CLK_AON_500_POSTOSC 7
+#define AONCRG_CLK_XSPI_PHY 8
+#define AONCRG_CLK_AON_100 9
+#define AONCRG_CLK_AON_100_POSTOSC 10
+#define AONCRG_CLK_AON_50_POSTOSC 11
+#define AONCRG_CLK_DDR50_POSTOCC_ICG 12
+#define AONCRG_CLK_DDR100_POSTOCC_ICG 13
+#define AONCRG_CLK_PUFRT_APB 14
+#define AONCRG_CLK_RTC_HMS_APB 15
+#define AONCRG_CLK_RTC_INTERNAL 16
+#define AONCRG_CLK_RTC_HMS_OSC32K 17
+#define AONCRG_CLK_RTC_HMS_CAL 18
+#define AONCRG_CLK_GMAC0_AXI128_AHB 19
+#define AONCRG_CLK_GMAC0_AXI128_MSTRCLK 20
+#define AONCRG_CLK_GMAC0_AXI128_AXI 21
+#define AONCRG_CLK_GMAC0_RMII_RTX 22
+#define AONCRG_CLK_GMAC0_AXI128_TX 23
+#define AONCRG_CLK_GMAC0_AXI128_TX_INV 24
+#define AONCRG_CLK_GMAC0_AXI128_RX 25
+#define AONCRG_CLK_GMAC0_AXI128_RX_INV 26
+#define AONCRG_CLK_GMAC0_GTXC 27
+#define AONCRG_CLK_XSPI_AXI 28
+#define AONCRG_CLK_XSPI_APB 29
+#define AONCRG_CLK_XSPI_XSPI_PHY 30
+#define AONCRG_CLK_TVSENSOR_PCLK 31
+#define AONCRG_CLK_TVSENSOR_TSADC 32
+#define AONCRG_CLK_TVSENSOR_BG 33
+#define AONCRG_CLK_MEU_PCLK_AP 34
+#define AONCRG_CLK_MEU_PCLK_SCP 35
+#define AONCRG_CLK_MEU_MEM_AXI 36
+#define AONCRG_CLK_AXIMEM_128B_ACLK 37
+#define AONCRG_CLK_APB2BISR_APB 38
+#define AONCRG_CLK_APB2BISR_BISR 39
+#define AONCRG_CLK_EMMC_S_PCLK 40
+#define AONCRG_CLK_EMMC_MSTRCLK 41
+#define AONCRG_CLK_EMMC 42
+#define AONCRG_CLK_EMMC_SDMCLK 43
+#define AONCRG_CLK_EMMC_SDPHY_PCLK 44
+#define AONCRG_CLK_SDIO0_PCLK 45
+#define AONCRG_CLK_SDIO0_MSTRCLK 46
+#define AONCRG_CLK_SDIO0 47
+#define AONCRG_CLK_SDIO0_SDMCLK 48
+#define AONCRG_CLK_SDIO0_SDPHY_PCLK 49
+#define AONCRG_CLK_HCLK 50
+#define AONCRG_CLK_ACLK 51
+#define AONCRG_CLK_PERF_MSTRCLK 52
+#define AONCRG_CLK_PERF_SLVCLK 53
+#define AONCRG_CLK_GCLK0 54
+#define AONCRG_CLK_GCLK_OSC 55
+#define AONCRG_CLK_RTC_ICG_EN 56
+#define AONCRG_CLK_GMAC0_ICG_EN 57
+#define AONCRG_CLK_XSPI_ICG_EN 58
+#define AONCRG_CLK_TVSENSOR0_ICG_EN 59
+#define AONCRG_CLK_MEU_ICG_EN 60
+#define AONCRG_CLK_APB2BISR_ICG_EN 61
+#define AONCRG_CLK_EMMC_ICG_EN 62
+#define AONCRG_CLK_SDIO0_ICG_EN 63
+#define AONCRG_CLK_TOP_ICG_EN 64
+
+#define AONCRG_CLK_END 65
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */
diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h
index 55209382e00e..a89ba78b9bf8 100644
--- a/include/dt-bindings/reset/starfive,jh8100-crg.h
+++ b/include/dt-bindings/reset/starfive,jh8100-crg.h
@@ -106,4 +106,22 @@
#define SYSCRG_SW_RSTN_DDR_TVSENSOR 3
#define SYSCRG_SW_RESET_NR_RESETS 4
+
+/*
+ * aoncrg
+ */
+#define AONCRG_RSTN_AON_IOMUX_PRESETN 0
+#define AONCRG_RSTN_RTC 1
+#define AONCRG_RSTN_GMAC0 2
+#define AONCRG_RSTN_XSPI 3
+#define AONCRG_RSTN_TVSENSOR 4
+#define AONCRG_RSTN_MEU 5
+#define AONCRG_RSTN_AXIMEM_128B_ARESET 6
+#define AONCRG_RSTN_APB2BISR_APB 7
+#define AONCRG_RSTN_SDIO0 8
+#define AONCRG_RSTN_EMMC 9
+#define AONCRG_RSTN_TOP 10
+#define AONCRG_RSTN_IRQ_CTRL 11
+
+#define AONCRG_RESET_NR_RESETS 12
#endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */
--
2.34.1
Sia Jee Heng wrote:
> StarFive JH8100 shares a similar clock and reset design with JH7110.
> To facilitate the reuse of the file and its functionalities, files
> containing the "jh71x0" naming convention are renamed to use the
> "common" wording.
>
> Signed-off-by: Sia Jee Heng <[email protected]>
> Reviewed-by: Ley Foon Tan <[email protected]>
Reviewed-by: Emil Renner Berthing <[email protected]>
> ---
> drivers/clk/starfive/clk-starfive-jh7110-sys.c | 2 +-
> drivers/reset/starfive/Kconfig | 6 +++---
> drivers/reset/starfive/Makefile | 2 +-
> .../{reset-starfive-jh71x0.c => reset-starfive-common.c} | 4 ++--
> .../{reset-starfive-jh71x0.h => reset-starfive-common.h} | 6 +++---
> drivers/reset/starfive/reset-starfive-jh7100.c | 2 +-
> drivers/reset/starfive/reset-starfive-jh7110.c | 4 ++--
> .../{reset-starfive-jh71x0.h => reset-starfive-common.h} | 4 ++--
> 8 files changed, 15 insertions(+), 15 deletions(-)
> rename drivers/reset/starfive/{reset-starfive-jh71x0.c => reset-starfive-common.c} (97%)
> rename drivers/reset/starfive/{reset-starfive-jh71x0.h => reset-starfive-common.h} (75%)
> rename include/soc/starfive/{reset-starfive-jh71x0.h => reset-starfive-common.h} (81%)
>
> diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> index 3884eff9fe93..6e45c580c9ba 100644
> --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> @@ -14,7 +14,7 @@
> #include <linux/platform_device.h>
> #include <linux/slab.h>
>
> -#include <soc/starfive/reset-starfive-jh71x0.h>
> +#include <soc/starfive/reset-starfive-common.h>
>
> #include <dt-bindings/clock/starfive,jh7110-crg.h>
>
> diff --git a/drivers/reset/starfive/Kconfig b/drivers/reset/starfive/Kconfig
> index d832339f61bc..29fbcf1a7d83 100644
> --- a/drivers/reset/starfive/Kconfig
> +++ b/drivers/reset/starfive/Kconfig
> @@ -1,12 +1,12 @@
> # SPDX-License-Identifier: GPL-2.0-only
>
> -config RESET_STARFIVE_JH71X0
> +config RESET_STARFIVE_COMMON
> bool
>
> config RESET_STARFIVE_JH7100
> bool "StarFive JH7100 Reset Driver"
> depends on ARCH_STARFIVE || COMPILE_TEST
> - select RESET_STARFIVE_JH71X0
> + select RESET_STARFIVE_COMMON
> default ARCH_STARFIVE
> help
> This enables the reset controller driver for the StarFive JH7100 SoC.
> @@ -15,7 +15,7 @@ config RESET_STARFIVE_JH7110
> bool "StarFive JH7110 Reset Driver"
> depends on CLK_STARFIVE_JH7110_SYS
> select AUXILIARY_BUS
> - select RESET_STARFIVE_JH71X0
> + select RESET_STARFIVE_COMMON
> default ARCH_STARFIVE
> help
> This enables the reset controller driver for the StarFive JH7110 SoC.
> diff --git a/drivers/reset/starfive/Makefile b/drivers/reset/starfive/Makefile
> index 7a44b66fb9d5..582e4c160bd4 100644
> --- a/drivers/reset/starfive/Makefile
> +++ b/drivers/reset/starfive/Makefile
> @@ -1,5 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0
> -obj-$(CONFIG_RESET_STARFIVE_JH71X0) += reset-starfive-jh71x0.o
> +obj-$(CONFIG_RESET_STARFIVE_COMMON) += reset-starfive-common.o
>
> obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
> obj-$(CONFIG_RESET_STARFIVE_JH7110) += reset-starfive-jh7110.o
> diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.c b/drivers/reset/starfive/reset-starfive-common.c
> similarity index 97%
> rename from drivers/reset/starfive/reset-starfive-jh71x0.c
> rename to drivers/reset/starfive/reset-starfive-common.c
> index 55bbbd2de52c..dab454e46bbf 100644
> --- a/drivers/reset/starfive/reset-starfive-jh71x0.c
> +++ b/drivers/reset/starfive/reset-starfive-common.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0-or-later
> /*
> - * Reset driver for the StarFive JH71X0 SoCs
> + * Reset driver for the StarFive SoCs
> *
> * Copyright (C) 2021 Emil Renner Berthing <[email protected]>
> */
> @@ -12,7 +12,7 @@
> #include <linux/reset-controller.h>
> #include <linux/spinlock.h>
>
> -#include "reset-starfive-jh71x0.h"
> +#include "reset-starfive-common.h"
>
> struct jh71x0_reset {
> struct reset_controller_dev rcdev;
> diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.h b/drivers/reset/starfive/reset-starfive-common.h
> similarity index 75%
> rename from drivers/reset/starfive/reset-starfive-jh71x0.h
> rename to drivers/reset/starfive/reset-starfive-common.h
> index db7d39a87f87..266acc4b2caf 100644
> --- a/drivers/reset/starfive/reset-starfive-jh71x0.h
> +++ b/drivers/reset/starfive/reset-starfive-common.h
> @@ -3,12 +3,12 @@
> * Copyright (C) 2021 Emil Renner Berthing <[email protected]>
> */
>
> -#ifndef __RESET_STARFIVE_JH71X0_H
> -#define __RESET_STARFIVE_JH71X0_H
> +#ifndef __RESET_STARFIVE_COMMON_H
> +#define __RESET_STARFIVE_COMMON_H
>
> int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
> void __iomem *assert, void __iomem *status,
> const u32 *asserted, unsigned int nr_resets,
> struct module *owner);
>
> -#endif /* __RESET_STARFIVE_JH71X0_H */
> +#endif /* __RESET_STARFIVE_COMMON_H */
> diff --git a/drivers/reset/starfive/reset-starfive-jh7100.c b/drivers/reset/starfive/reset-starfive-jh7100.c
> index 2a56f7fd4ba7..546dea2e5811 100644
> --- a/drivers/reset/starfive/reset-starfive-jh7100.c
> +++ b/drivers/reset/starfive/reset-starfive-jh7100.c
> @@ -8,7 +8,7 @@
> #include <linux/mod_devicetable.h>
> #include <linux/platform_device.h>
>
> -#include "reset-starfive-jh71x0.h"
> +#include "reset-starfive-common.h"
>
> #include <dt-bindings/reset/starfive-jh7100.h>
>
> diff --git a/drivers/reset/starfive/reset-starfive-jh7110.c b/drivers/reset/starfive/reset-starfive-jh7110.c
> index 29a43f0f2ad6..87dba01491ae 100644
> --- a/drivers/reset/starfive/reset-starfive-jh7110.c
> +++ b/drivers/reset/starfive/reset-starfive-jh7110.c
> @@ -7,9 +7,9 @@
>
> #include <linux/auxiliary_bus.h>
>
> -#include <soc/starfive/reset-starfive-jh71x0.h>
> +#include <soc/starfive/reset-starfive-common.h>
>
> -#include "reset-starfive-jh71x0.h"
> +#include "reset-starfive-common.h"
>
> #include <dt-bindings/reset/starfive,jh7110-crg.h>
>
> diff --git a/include/soc/starfive/reset-starfive-jh71x0.h b/include/soc/starfive/reset-starfive-common.h
> similarity index 81%
> rename from include/soc/starfive/reset-starfive-jh71x0.h
> rename to include/soc/starfive/reset-starfive-common.h
> index 47b486ececc5..56d8f413cf18 100644
> --- a/include/soc/starfive/reset-starfive-jh71x0.h
> +++ b/include/soc/starfive/reset-starfive-common.h
> @@ -1,6 +1,6 @@
> /* SPDX-License-Identifier: GPL-2.0 */
> -#ifndef __SOC_STARFIVE_RESET_JH71X0_H
> -#define __SOC_STARFIVE_RESET_JH71X0_H
> +#ifndef __SOC_STARFIVE_RESET_COMMON_H
> +#define __SOC_STARFIVE_RESET_COMMON_H
>
> #include <linux/auxiliary_bus.h>
> #include <linux/compiler_types.h>
> --
> 2.34.1
>
Sia Jee Heng wrote:
> StarFive JH8100 shares a similar clock and reset design with JH7110.
> To facilitate the reuse of the file and its functionalities, files
> containing the "jh71x0" naming convention are renamed to use the
> "common" wording.
>
> Signed-off-by: Sia Jee Heng <[email protected]>
> Reviewed-by: Ley Foon Tan <[email protected]>
Reviewed-by: Emil Renner Berthing <[email protected]>
> ---
> drivers/clk/starfive/Kconfig | 8 ++++----
> drivers/clk/starfive/Makefile | 2 +-
> .../{clk-starfive-jh71x0.c => clk-starfive-common.c} | 4 ++--
> .../{clk-starfive-jh71x0.h => clk-starfive-common.h} | 4 ++--
> drivers/clk/starfive/clk-starfive-jh7100-audio.c | 2 +-
> drivers/clk/starfive/clk-starfive-jh7100.c | 2 +-
> drivers/clk/starfive/clk-starfive-jh7110.h | 2 +-
> 7 files changed, 12 insertions(+), 12 deletions(-)
> rename drivers/clk/starfive/{clk-starfive-jh71x0.c => clk-starfive-common.c} (99%)
> rename drivers/clk/starfive/{clk-starfive-jh71x0.h => clk-starfive-common.h} (97%)
>
> diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
> index bd29358ffeec..ff8eace36e64 100644
> --- a/drivers/clk/starfive/Kconfig
> +++ b/drivers/clk/starfive/Kconfig
> @@ -1,12 +1,12 @@
> # SPDX-License-Identifier: GPL-2.0
>
> -config CLK_STARFIVE_JH71X0
> +config CLK_STARFIVE_COMMON
> bool
>
> config CLK_STARFIVE_JH7100
> bool "StarFive JH7100 clock support"
> depends on ARCH_STARFIVE || COMPILE_TEST
> - select CLK_STARFIVE_JH71X0
> + select CLK_STARFIVE_COMMON
> default ARCH_STARFIVE
> help
> Say yes here to support the clock controller on the StarFive JH7100
> @@ -15,7 +15,7 @@ config CLK_STARFIVE_JH7100
> config CLK_STARFIVE_JH7100_AUDIO
> tristate "StarFive JH7100 audio clock support"
> depends on CLK_STARFIVE_JH7100
> - select CLK_STARFIVE_JH71X0
> + select CLK_STARFIVE_COMMON
> default m if ARCH_STARFIVE
> help
> Say Y or M here to support the audio clocks on the StarFive JH7100
> @@ -33,7 +33,7 @@ config CLK_STARFIVE_JH7110_SYS
> bool "StarFive JH7110 system clock support"
> depends on ARCH_STARFIVE || COMPILE_TEST
> select AUXILIARY_BUS
> - select CLK_STARFIVE_JH71X0
> + select CLK_STARFIVE_COMMON
> select RESET_STARFIVE_JH7110 if RESET_CONTROLLER
> select CLK_STARFIVE_JH7110_PLL
> default ARCH_STARFIVE
> diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
> index 199ac0f37a2f..012f7ee83f8e 100644
> --- a/drivers/clk/starfive/Makefile
> +++ b/drivers/clk/starfive/Makefile
> @@ -1,5 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0
> -obj-$(CONFIG_CLK_STARFIVE_JH71X0) += clk-starfive-jh71x0.o
> +obj-$(CONFIG_CLK_STARFIVE_COMMON) += clk-starfive-common.o
>
> obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o
> obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o
> diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.c b/drivers/clk/starfive/clk-starfive-common.c
> similarity index 99%
> rename from drivers/clk/starfive/clk-starfive-jh71x0.c
> rename to drivers/clk/starfive/clk-starfive-common.c
> index aebc99264a0b..a12490c97957 100644
> --- a/drivers/clk/starfive/clk-starfive-jh71x0.c
> +++ b/drivers/clk/starfive/clk-starfive-common.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> - * StarFive JH71X0 Clock Generator Driver
> + * StarFive Clock Generator Driver
> *
> * Copyright (C) 2021-2022 Emil Renner Berthing <[email protected]>
> */
> @@ -10,7 +10,7 @@
> #include <linux/device.h>
> #include <linux/io.h>
>
> -#include "clk-starfive-jh71x0.h"
> +#include "clk-starfive-common.h"
>
> static struct jh71x0_clk *jh71x0_clk_from(struct clk_hw *hw)
> {
> diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.h b/drivers/clk/starfive/clk-starfive-common.h
> similarity index 97%
> rename from drivers/clk/starfive/clk-starfive-jh71x0.h
> rename to drivers/clk/starfive/clk-starfive-common.h
> index 34bb11c72eb7..1f32f7024e9f 100644
> --- a/drivers/clk/starfive/clk-starfive-jh71x0.h
> +++ b/drivers/clk/starfive/clk-starfive-common.h
> @@ -1,6 +1,6 @@
> /* SPDX-License-Identifier: GPL-2.0 */
> -#ifndef __CLK_STARFIVE_JH71X0_H
> -#define __CLK_STARFIVE_JH71X0_H
> +#ifndef __CLK_STARFIVE_COMMON_H
> +#define __CLK_STARFIVE_COMMON_H
>
> #include <linux/bits.h>
> #include <linux/clk-provider.h>
> diff --git a/drivers/clk/starfive/clk-starfive-jh7100-audio.c b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
> index ee4bda14a40e..dc4c278606d7 100644
> --- a/drivers/clk/starfive/clk-starfive-jh7100-audio.c
> +++ b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
> @@ -15,7 +15,7 @@
>
> #include <dt-bindings/clock/starfive-jh7100-audio.h>
>
> -#include "clk-starfive-jh71x0.h"
> +#include "clk-starfive-common.h"
>
> /* external clocks */
> #define JH7100_AUDCLK_AUDIO_SRC (JH7100_AUDCLK_END + 0)
> diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c
> index 69cc11ea7e33..6bb6a6af9f28 100644
> --- a/drivers/clk/starfive/clk-starfive-jh7100.c
> +++ b/drivers/clk/starfive/clk-starfive-jh7100.c
> @@ -15,7 +15,7 @@
>
> #include <dt-bindings/clock/starfive-jh7100.h>
>
> -#include "clk-starfive-jh71x0.h"
> +#include "clk-starfive-common.h"
>
> /* external clocks */
> #define JH7100_CLK_OSC_SYS (JH7100_CLK_END + 0)
> diff --git a/drivers/clk/starfive/clk-starfive-jh7110.h b/drivers/clk/starfive/clk-starfive-jh7110.h
> index 0659adae4d76..6b1bdf860f00 100644
> --- a/drivers/clk/starfive/clk-starfive-jh7110.h
> +++ b/drivers/clk/starfive/clk-starfive-jh7110.h
> @@ -2,7 +2,7 @@
> #ifndef __CLK_STARFIVE_JH7110_H
> #define __CLK_STARFIVE_JH7110_H
>
> -#include "clk-starfive-jh71x0.h"
> +#include "clk-starfive-common.h"
>
> /* top clocks of ISP/VOUT domain from JH7110 SYSCRG */
> struct jh7110_top_sysclk {
> --
> 2.34.1
>
Sia Jee Heng wrote:
> Function names that consist of the 'jh71x0' naming convention are
> renamed to use the 'starfive' wording.
>
> Signed-off-by: Sia Jee Heng <[email protected]>
> Reviewed-by: Ley Foon Tan <[email protected]>
Reviewed-by: Emil Renner Berthing <[email protected]>
> ---
> drivers/clk/starfive/clk-starfive-common.c | 290 +++++-----
> drivers/clk/starfive/clk-starfive-common.h | 68 +--
> .../clk/starfive/clk-starfive-jh7100-audio.c | 125 ++---
> drivers/clk/starfive/clk-starfive-jh7100.c | 501 ++++++++---------
> .../clk/starfive/clk-starfive-jh7110-aon.c | 62 +--
> .../clk/starfive/clk-starfive-jh7110-isp.c | 72 +--
> .../clk/starfive/clk-starfive-jh7110-stg.c | 94 ++--
> .../clk/starfive/clk-starfive-jh7110-sys.c | 517 +++++++++---------
> .../clk/starfive/clk-starfive-jh7110-vout.c | 74 +--
> drivers/clk/starfive/clk-starfive-jh7110.h | 2 +-
> 10 files changed, 908 insertions(+), 897 deletions(-)
>
> diff --git a/drivers/clk/starfive/clk-starfive-common.c b/drivers/clk/starfive/clk-starfive-common.c
> index a12490c97957..fd608286ca13 100644
> --- a/drivers/clk/starfive/clk-starfive-common.c
> +++ b/drivers/clk/starfive/clk-starfive-common.c
> @@ -12,27 +12,27 @@
>
> #include "clk-starfive-common.h"
>
> -static struct jh71x0_clk *jh71x0_clk_from(struct clk_hw *hw)
> +static struct starfive_clk *starfive_clk_from(struct clk_hw *hw)
> {
> - return container_of(hw, struct jh71x0_clk, hw);
> + return container_of(hw, struct starfive_clk, hw);
> }
>
> -static struct jh71x0_clk_priv *jh71x0_priv_from(struct jh71x0_clk *clk)
> +static struct starfive_clk_priv *starfive_priv_from(struct starfive_clk *clk)
> {
> - return container_of(clk, struct jh71x0_clk_priv, reg[clk->idx]);
> + return container_of(clk, struct starfive_clk_priv, reg[clk->idx]);
> }
>
> -static u32 jh71x0_clk_reg_get(struct jh71x0_clk *clk)
> +static u32 starfive_clk_reg_get(struct starfive_clk *clk)
> {
> - struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);
> + struct starfive_clk_priv *priv = starfive_priv_from(clk);
> void __iomem *reg = priv->base + 4 * clk->idx;
>
> return readl_relaxed(reg);
> }
>
> -static void jh71x0_clk_reg_rmw(struct jh71x0_clk *clk, u32 mask, u32 value)
> +static void starfive_clk_reg_rmw(struct starfive_clk *clk, u32 mask, u32 value)
> {
> - struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);
> + struct starfive_clk_priv *priv = starfive_priv_from(clk);
> void __iomem *reg = priv->base + 4 * clk->idx;
> unsigned long flags;
>
> @@ -42,41 +42,41 @@ static void jh71x0_clk_reg_rmw(struct jh71x0_clk *clk, u32 mask, u32 value)
> spin_unlock_irqrestore(&priv->rmw_lock, flags);
> }
>
> -static int jh71x0_clk_enable(struct clk_hw *hw)
> +static int starfive_clk_enable(struct clk_hw *hw)
> {
> - struct jh71x0_clk *clk = jh71x0_clk_from(hw);
> + struct starfive_clk *clk = starfive_clk_from(hw);
>
> - jh71x0_clk_reg_rmw(clk, JH71X0_CLK_ENABLE, JH71X0_CLK_ENABLE);
> + starfive_clk_reg_rmw(clk, STARFIVE_CLK_ENABLE, STARFIVE_CLK_ENABLE);
> return 0;
> }
>
> -static void jh71x0_clk_disable(struct clk_hw *hw)
> +static void starfive_clk_disable(struct clk_hw *hw)
> {
> - struct jh71x0_clk *clk = jh71x0_clk_from(hw);
> + struct starfive_clk *clk = starfive_clk_from(hw);
>
> - jh71x0_clk_reg_rmw(clk, JH71X0_CLK_ENABLE, 0);
> + starfive_clk_reg_rmw(clk, STARFIVE_CLK_ENABLE, 0);
> }
>
> -static int jh71x0_clk_is_enabled(struct clk_hw *hw)
> +static int starfive_clk_is_enabled(struct clk_hw *hw)
> {
> - struct jh71x0_clk *clk = jh71x0_clk_from(hw);
> + struct starfive_clk *clk = starfive_clk_from(hw);
>
> - return !!(jh71x0_clk_reg_get(clk) & JH71X0_CLK_ENABLE);
> + return !!(starfive_clk_reg_get(clk) & STARFIVE_CLK_ENABLE);
> }
>
> -static unsigned long jh71x0_clk_recalc_rate(struct clk_hw *hw,
> - unsigned long parent_rate)
> +static unsigned long starfive_clk_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> {
> - struct jh71x0_clk *clk = jh71x0_clk_from(hw);
> - u32 div = jh71x0_clk_reg_get(clk) & JH71X0_CLK_DIV_MASK;
> + struct starfive_clk *clk = starfive_clk_from(hw);
> + u32 div = starfive_clk_reg_get(clk) & STARFIVE_CLK_DIV_MASK;
>
> return div ? parent_rate / div : 0;
> }
>
> -static int jh71x0_clk_determine_rate(struct clk_hw *hw,
> - struct clk_rate_request *req)
> +static int starfive_clk_determine_rate(struct clk_hw *hw,
> + struct clk_rate_request *req)
> {
> - struct jh71x0_clk *clk = jh71x0_clk_from(hw);
> + struct starfive_clk *clk = starfive_clk_from(hw);
> unsigned long parent = req->best_parent_rate;
> unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
> unsigned long div = min_t(unsigned long, DIV_ROUND_UP(parent, rate), clk->max_div);
> @@ -102,226 +102,226 @@ static int jh71x0_clk_determine_rate(struct clk_hw *hw,
> return 0;
> }
>
> -static int jh71x0_clk_set_rate(struct clk_hw *hw,
> - unsigned long rate,
> - unsigned long parent_rate)
> +static int starfive_clk_set_rate(struct clk_hw *hw,
> + unsigned long rate,
> + unsigned long parent_rate)
> {
> - struct jh71x0_clk *clk = jh71x0_clk_from(hw);
> + struct starfive_clk *clk = starfive_clk_from(hw);
> unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate),
> 1UL, (unsigned long)clk->max_div);
>
> - jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, div);
> + starfive_clk_reg_rmw(clk, STARFIVE_CLK_DIV_MASK, div);
> return 0;
> }
>
> -static unsigned long jh71x0_clk_frac_recalc_rate(struct clk_hw *hw,
> - unsigned long parent_rate)
> +static unsigned long starfive_clk_frac_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> {
> - struct jh71x0_clk *clk = jh71x0_clk_from(hw);
> - u32 reg = jh71x0_clk_reg_get(clk);
> - unsigned long div100 = 100 * (reg & JH71X0_CLK_INT_MASK) +
> - ((reg & JH71X0_CLK_FRAC_MASK) >> JH71X0_CLK_FRAC_SHIFT);
> + struct starfive_clk *clk = starfive_clk_from(hw);
> + u32 reg = starfive_clk_reg_get(clk);
> + unsigned long div100 = 100 * (reg & STARFIVE_CLK_INT_MASK) +
> + ((reg & STARFIVE_CLK_FRAC_MASK) >> STARFIVE_CLK_FRAC_SHIFT);
>
> - return (div100 >= JH71X0_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0;
> + return (div100 >= STARFIVE_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0;
> }
>
> -static int jh71x0_clk_frac_determine_rate(struct clk_hw *hw,
> - struct clk_rate_request *req)
> +static int starfive_clk_frac_determine_rate(struct clk_hw *hw,
> + struct clk_rate_request *req)
> {
> unsigned long parent100 = 100 * req->best_parent_rate;
> unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
> unsigned long div100 = clamp(DIV_ROUND_CLOSEST(parent100, rate),
> - JH71X0_CLK_FRAC_MIN, JH71X0_CLK_FRAC_MAX);
> + STARFIVE_CLK_FRAC_MIN, STARFIVE_CLK_FRAC_MAX);
> unsigned long result = parent100 / div100;
>
> - /* clamp the result as in jh71x0_clk_determine_rate() above */
> - if (result > req->max_rate && div100 < JH71X0_CLK_FRAC_MAX)
> + /* clamp the result as in starfive_clk_determine_rate() above */
> + if (result > req->max_rate && div100 < STARFIVE_CLK_FRAC_MAX)
> result = parent100 / (div100 + 1);
> - if (result < req->min_rate && div100 > JH71X0_CLK_FRAC_MIN)
> + if (result < req->min_rate && div100 > STARFIVE_CLK_FRAC_MIN)
> result = parent100 / (div100 - 1);
>
> req->rate = result;
> return 0;
> }
>
> -static int jh71x0_clk_frac_set_rate(struct clk_hw *hw,
> - unsigned long rate,
> - unsigned long parent_rate)
> +static int starfive_clk_frac_set_rate(struct clk_hw *hw,
> + unsigned long rate,
> + unsigned long parent_rate)
> {
> - struct jh71x0_clk *clk = jh71x0_clk_from(hw);
> + struct starfive_clk *clk = starfive_clk_from(hw);
> unsigned long div100 = clamp(DIV_ROUND_CLOSEST(100 * parent_rate, rate),
> - JH71X0_CLK_FRAC_MIN, JH71X0_CLK_FRAC_MAX);
> - u32 value = ((div100 % 100) << JH71X0_CLK_FRAC_SHIFT) | (div100 / 100);
> + STARFIVE_CLK_FRAC_MIN, STARFIVE_CLK_FRAC_MAX);
> + u32 value = ((div100 % 100) << STARFIVE_CLK_FRAC_SHIFT) | (div100 / 100);
>
> - jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, value);
> + starfive_clk_reg_rmw(clk, STARFIVE_CLK_DIV_MASK, value);
> return 0;
> }
>
> -static u8 jh71x0_clk_get_parent(struct clk_hw *hw)
> +static u8 starfive_clk_get_parent(struct clk_hw *hw)
> {
> - struct jh71x0_clk *clk = jh71x0_clk_from(hw);
> - u32 value = jh71x0_clk_reg_get(clk);
> + struct starfive_clk *clk = starfive_clk_from(hw);
> + u32 value = starfive_clk_reg_get(clk);
>
> - return (value & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT;
> + return (value & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT;
> }
>
> -static int jh71x0_clk_set_parent(struct clk_hw *hw, u8 index)
> +static int starfive_clk_set_parent(struct clk_hw *hw, u8 index)
> {
> - struct jh71x0_clk *clk = jh71x0_clk_from(hw);
> - u32 value = (u32)index << JH71X0_CLK_MUX_SHIFT;
> + struct starfive_clk *clk = starfive_clk_from(hw);
> + u32 value = (u32)index << STARFIVE_CLK_MUX_SHIFT;
>
> - jh71x0_clk_reg_rmw(clk, JH71X0_CLK_MUX_MASK, value);
> + starfive_clk_reg_rmw(clk, STARFIVE_CLK_MUX_MASK, value);
> return 0;
> }
>
> -static int jh71x0_clk_get_phase(struct clk_hw *hw)
> +static int starfive_clk_get_phase(struct clk_hw *hw)
> {
> - struct jh71x0_clk *clk = jh71x0_clk_from(hw);
> - u32 value = jh71x0_clk_reg_get(clk);
> + struct starfive_clk *clk = starfive_clk_from(hw);
> + u32 value = starfive_clk_reg_get(clk);
>
> - return (value & JH71X0_CLK_INVERT) ? 180 : 0;
> + return (value & STARFIVE_CLK_INVERT) ? 180 : 0;
> }
>
> -static int jh71x0_clk_set_phase(struct clk_hw *hw, int degrees)
> +static int starfive_clk_set_phase(struct clk_hw *hw, int degrees)
> {
> - struct jh71x0_clk *clk = jh71x0_clk_from(hw);
> + struct starfive_clk *clk = starfive_clk_from(hw);
> u32 value;
>
> if (degrees == 0)
> value = 0;
> else if (degrees == 180)
> - value = JH71X0_CLK_INVERT;
> + value = STARFIVE_CLK_INVERT;
> else
> return -EINVAL;
>
> - jh71x0_clk_reg_rmw(clk, JH71X0_CLK_INVERT, value);
> + starfive_clk_reg_rmw(clk, STARFIVE_CLK_INVERT, value);
> return 0;
> }
>
> #ifdef CONFIG_DEBUG_FS
> -static void jh71x0_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
> +static void starfive_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
> {
> - static const struct debugfs_reg32 jh71x0_clk_reg = {
> + static const struct debugfs_reg32 starfive_clk_reg = {
> .name = "CTRL",
> .offset = 0,
> };
> - struct jh71x0_clk *clk = jh71x0_clk_from(hw);
> - struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);
> + struct starfive_clk *clk = starfive_clk_from(hw);
> + struct starfive_clk_priv *priv = starfive_priv_from(clk);
> struct debugfs_regset32 *regset;
>
> regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);
> if (!regset)
> return;
>
> - regset->regs = &jh71x0_clk_reg;
> + regset->regs = &starfive_clk_reg;
> regset->nregs = 1;
> regset->base = priv->base + 4 * clk->idx;
>
> debugfs_create_regset32("registers", 0400, dentry, regset);
> }
> #else
> -#define jh71x0_clk_debug_init NULL
> +#define starfive_clk_debug_init NULL
> #endif
>
> -static const struct clk_ops jh71x0_clk_gate_ops = {
> - .enable = jh71x0_clk_enable,
> - .disable = jh71x0_clk_disable,
> - .is_enabled = jh71x0_clk_is_enabled,
> - .debug_init = jh71x0_clk_debug_init,
> +static const struct clk_ops starfive_clk_gate_ops = {
> + .enable = starfive_clk_enable,
> + .disable = starfive_clk_disable,
> + .is_enabled = starfive_clk_is_enabled,
> + .debug_init = starfive_clk_debug_init,
> };
>
> -static const struct clk_ops jh71x0_clk_div_ops = {
> - .recalc_rate = jh71x0_clk_recalc_rate,
> - .determine_rate = jh71x0_clk_determine_rate,
> - .set_rate = jh71x0_clk_set_rate,
> - .debug_init = jh71x0_clk_debug_init,
> +static const struct clk_ops starfive_clk_div_ops = {
> + .recalc_rate = starfive_clk_recalc_rate,
> + .determine_rate = starfive_clk_determine_rate,
> + .set_rate = starfive_clk_set_rate,
> + .debug_init = starfive_clk_debug_init,
> };
>
> -static const struct clk_ops jh71x0_clk_fdiv_ops = {
> - .recalc_rate = jh71x0_clk_frac_recalc_rate,
> - .determine_rate = jh71x0_clk_frac_determine_rate,
> - .set_rate = jh71x0_clk_frac_set_rate,
> - .debug_init = jh71x0_clk_debug_init,
> +static const struct clk_ops starfive_clk_fdiv_ops = {
> + .recalc_rate = starfive_clk_frac_recalc_rate,
> + .determine_rate = starfive_clk_frac_determine_rate,
> + .set_rate = starfive_clk_frac_set_rate,
> + .debug_init = starfive_clk_debug_init,
> };
>
> -static const struct clk_ops jh71x0_clk_gdiv_ops = {
> - .enable = jh71x0_clk_enable,
> - .disable = jh71x0_clk_disable,
> - .is_enabled = jh71x0_clk_is_enabled,
> - .recalc_rate = jh71x0_clk_recalc_rate,
> - .determine_rate = jh71x0_clk_determine_rate,
> - .set_rate = jh71x0_clk_set_rate,
> - .debug_init = jh71x0_clk_debug_init,
> +static const struct clk_ops starfive_clk_gdiv_ops = {
> + .enable = starfive_clk_enable,
> + .disable = starfive_clk_disable,
> + .is_enabled = starfive_clk_is_enabled,
> + .recalc_rate = starfive_clk_recalc_rate,
> + .determine_rate = starfive_clk_determine_rate,
> + .set_rate = starfive_clk_set_rate,
> + .debug_init = starfive_clk_debug_init,
> };
>
> -static const struct clk_ops jh71x0_clk_mux_ops = {
> +static const struct clk_ops starfive_clk_mux_ops = {
> .determine_rate = __clk_mux_determine_rate,
> - .set_parent = jh71x0_clk_set_parent,
> - .get_parent = jh71x0_clk_get_parent,
> - .debug_init = jh71x0_clk_debug_init,
> + .set_parent = starfive_clk_set_parent,
> + .get_parent = starfive_clk_get_parent,
> + .debug_init = starfive_clk_debug_init,
> };
>
> -static const struct clk_ops jh71x0_clk_gmux_ops = {
> - .enable = jh71x0_clk_enable,
> - .disable = jh71x0_clk_disable,
> - .is_enabled = jh71x0_clk_is_enabled,
> +static const struct clk_ops starfive_clk_gmux_ops = {
> + .enable = starfive_clk_enable,
> + .disable = starfive_clk_disable,
> + .is_enabled = starfive_clk_is_enabled,
> .determine_rate = __clk_mux_determine_rate,
> - .set_parent = jh71x0_clk_set_parent,
> - .get_parent = jh71x0_clk_get_parent,
> - .debug_init = jh71x0_clk_debug_init,
> + .set_parent = starfive_clk_set_parent,
> + .get_parent = starfive_clk_get_parent,
> + .debug_init = starfive_clk_debug_init,
> };
>
> -static const struct clk_ops jh71x0_clk_mdiv_ops = {
> - .recalc_rate = jh71x0_clk_recalc_rate,
> - .determine_rate = jh71x0_clk_determine_rate,
> - .get_parent = jh71x0_clk_get_parent,
> - .set_parent = jh71x0_clk_set_parent,
> - .set_rate = jh71x0_clk_set_rate,
> - .debug_init = jh71x0_clk_debug_init,
> +static const struct clk_ops starfive_clk_mdiv_ops = {
> + .recalc_rate = starfive_clk_recalc_rate,
> + .determine_rate = starfive_clk_determine_rate,
> + .get_parent = starfive_clk_get_parent,
> + .set_parent = starfive_clk_set_parent,
> + .set_rate = starfive_clk_set_rate,
> + .debug_init = starfive_clk_debug_init,
> };
>
> -static const struct clk_ops jh71x0_clk_gmd_ops = {
> - .enable = jh71x0_clk_enable,
> - .disable = jh71x0_clk_disable,
> - .is_enabled = jh71x0_clk_is_enabled,
> - .recalc_rate = jh71x0_clk_recalc_rate,
> - .determine_rate = jh71x0_clk_determine_rate,
> - .get_parent = jh71x0_clk_get_parent,
> - .set_parent = jh71x0_clk_set_parent,
> - .set_rate = jh71x0_clk_set_rate,
> - .debug_init = jh71x0_clk_debug_init,
> +static const struct clk_ops starfive_clk_gmd_ops = {
> + .enable = starfive_clk_enable,
> + .disable = starfive_clk_disable,
> + .is_enabled = starfive_clk_is_enabled,
> + .recalc_rate = starfive_clk_recalc_rate,
> + .determine_rate = starfive_clk_determine_rate,
> + .get_parent = starfive_clk_get_parent,
> + .set_parent = starfive_clk_set_parent,
> + .set_rate = starfive_clk_set_rate,
> + .debug_init = starfive_clk_debug_init,
> };
>
> -static const struct clk_ops jh71x0_clk_inv_ops = {
> - .get_phase = jh71x0_clk_get_phase,
> - .set_phase = jh71x0_clk_set_phase,
> - .debug_init = jh71x0_clk_debug_init,
> +static const struct clk_ops starfive_clk_inv_ops = {
> + .get_phase = starfive_clk_get_phase,
> + .set_phase = starfive_clk_set_phase,
> + .debug_init = starfive_clk_debug_init,
> };
>
> -const struct clk_ops *starfive_jh71x0_clk_ops(u32 max)
> +const struct clk_ops *starfive_clk_ops(u32 max)
> {
> - if (max & JH71X0_CLK_DIV_MASK) {
> - if (max & JH71X0_CLK_MUX_MASK) {
> - if (max & JH71X0_CLK_ENABLE)
> - return &jh71x0_clk_gmd_ops;
> - return &jh71x0_clk_mdiv_ops;
> + if (max & STARFIVE_CLK_DIV_MASK) {
> + if (max & STARFIVE_CLK_MUX_MASK) {
> + if (max & STARFIVE_CLK_ENABLE)
> + return &starfive_clk_gmd_ops;
> + return &starfive_clk_mdiv_ops;
> }
> - if (max & JH71X0_CLK_ENABLE)
> - return &jh71x0_clk_gdiv_ops;
> - if (max == JH71X0_CLK_FRAC_MAX)
> - return &jh71x0_clk_fdiv_ops;
> - return &jh71x0_clk_div_ops;
> + if (max & STARFIVE_CLK_ENABLE)
> + return &starfive_clk_gdiv_ops;
> + if (max == STARFIVE_CLK_FRAC_MAX)
> + return &starfive_clk_fdiv_ops;
> + return &starfive_clk_div_ops;
> }
>
> - if (max & JH71X0_CLK_MUX_MASK) {
> - if (max & JH71X0_CLK_ENABLE)
> - return &jh71x0_clk_gmux_ops;
> - return &jh71x0_clk_mux_ops;
> + if (max & STARFIVE_CLK_MUX_MASK) {
> + if (max & STARFIVE_CLK_ENABLE)
> + return &starfive_clk_gmux_ops;
> + return &starfive_clk_mux_ops;
> }
>
> - if (max & JH71X0_CLK_ENABLE)
> - return &jh71x0_clk_gate_ops;
> + if (max & STARFIVE_CLK_ENABLE)
> + return &starfive_clk_gate_ops;
>
> - return &jh71x0_clk_inv_ops;
> + return &starfive_clk_inv_ops;
> }
> -EXPORT_SYMBOL_GPL(starfive_jh71x0_clk_ops);
> +EXPORT_SYMBOL_GPL(starfive_clk_ops);
> diff --git a/drivers/clk/starfive/clk-starfive-common.h b/drivers/clk/starfive/clk-starfive-common.h
> index 1f32f7024e9f..fed45311360c 100644
> --- a/drivers/clk/starfive/clk-starfive-common.h
> +++ b/drivers/clk/starfive/clk-starfive-common.h
> @@ -8,36 +8,36 @@
> #include <linux/spinlock.h>
>
> /* register fields */
> -#define JH71X0_CLK_ENABLE BIT(31)
> -#define JH71X0_CLK_INVERT BIT(30)
> -#define JH71X0_CLK_MUX_MASK GENMASK(27, 24)
> -#define JH71X0_CLK_MUX_SHIFT 24
> -#define JH71X0_CLK_DIV_MASK GENMASK(23, 0)
> -#define JH71X0_CLK_FRAC_MASK GENMASK(15, 8)
> -#define JH71X0_CLK_FRAC_SHIFT 8
> -#define JH71X0_CLK_INT_MASK GENMASK(7, 0)
> +#define STARFIVE_CLK_ENABLE BIT(31)
> +#define STARFIVE_CLK_INVERT BIT(30)
> +#define STARFIVE_CLK_MUX_MASK GENMASK(27, 24)
> +#define STARFIVE_CLK_MUX_SHIFT 24
> +#define STARFIVE_CLK_DIV_MASK GENMASK(23, 0)
> +#define STARFIVE_CLK_FRAC_MASK GENMASK(15, 8)
> +#define STARFIVE_CLK_FRAC_SHIFT 8
> +#define STARFIVE_CLK_INT_MASK GENMASK(7, 0)
>
> /* fractional divider min/max */
> -#define JH71X0_CLK_FRAC_MIN 100UL
> -#define JH71X0_CLK_FRAC_MAX 25599UL
> +#define STARFIVE_CLK_FRAC_MIN 100UL
> +#define STARFIVE_CLK_FRAC_MAX 25599UL
>
> /* clock data */
> -struct jh71x0_clk_data {
> +struct starfive_clk_data {
> const char *name;
> unsigned long flags;
> u32 max;
> u8 parents[4];
> };
>
> -#define JH71X0_GATE(_idx, _name, _flags, _parent) \
> +#define STARFIVE_GATE(_idx, _name, _flags, _parent) \
> [_idx] = { \
> .name = _name, \
> .flags = CLK_SET_RATE_PARENT | (_flags), \
> - .max = JH71X0_CLK_ENABLE, \
> + .max = STARFIVE_CLK_ENABLE, \
> .parents = { [0] = _parent }, \
> }
>
> -#define JH71X0__DIV(_idx, _name, _max, _parent) \
> +#define STARFIVE__DIV(_idx, _name, _max, _parent) \
> [_idx] = { \
> .name = _name, \
> .flags = 0, \
> @@ -45,79 +45,79 @@ struct jh71x0_clk_data {
> .parents = { [0] = _parent }, \
> }
>
> -#define JH71X0_GDIV(_idx, _name, _flags, _max, _parent) \
> +#define STARFIVE_GDIV(_idx, _name, _flags, _max, _parent) \
> [_idx] = { \
> .name = _name, \
> .flags = _flags, \
> - .max = JH71X0_CLK_ENABLE | (_max), \
> + .max = STARFIVE_CLK_ENABLE | (_max), \
> .parents = { [0] = _parent }, \
> }
>
> -#define JH71X0_FDIV(_idx, _name, _parent) \
> +#define STARFIVE_FDIV(_idx, _name, _parent) \
> [_idx] = { \
> .name = _name, \
> .flags = 0, \
> - .max = JH71X0_CLK_FRAC_MAX, \
> + .max = STARFIVE_CLK_FRAC_MAX, \
> .parents = { [0] = _parent }, \
> }
>
> -#define JH71X0__MUX(_idx, _name, _nparents, ...) \
> +#define STARFIVE__MUX(_idx, _name, _nparents, ...) \
> [_idx] = { \
> .name = _name, \
> .flags = 0, \
> - .max = ((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT, \
> + .max = ((_nparents) - 1) << STARFIVE_CLK_MUX_SHIFT, \
> .parents = { __VA_ARGS__ }, \
> }
>
> -#define JH71X0_GMUX(_idx, _name, _flags, _nparents, ...) \
> +#define STARFIVE_GMUX(_idx, _name, _flags, _nparents, ...) \
> [_idx] = { \
> .name = _name, \
> .flags = _flags, \
> - .max = JH71X0_CLK_ENABLE | \
> - (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT), \
> + .max = STARFIVE_CLK_ENABLE | \
> + (((_nparents) - 1) << STARFIVE_CLK_MUX_SHIFT), \
> .parents = { __VA_ARGS__ }, \
> }
>
> -#define JH71X0_MDIV(_idx, _name, _max, _nparents, ...) \
> +#define STARFIVE_MDIV(_idx, _name, _max, _nparents, ...) \
> [_idx] = { \
> .name = _name, \
> .flags = 0, \
> - .max = (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT) | (_max), \
> + .max = (((_nparents) - 1) << STARFIVE_CLK_MUX_SHIFT) | (_max), \
> .parents = { __VA_ARGS__ }, \
> }
>
> -#define JH71X0__GMD(_idx, _name, _flags, _max, _nparents, ...) \
> +#define STARFIVE__GMD(_idx, _name, _flags, _max, _nparents, ...) \
> [_idx] = { \
> .name = _name, \
> .flags = _flags, \
> - .max = JH71X0_CLK_ENABLE | \
> - (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT) | (_max), \
> + .max = STARFIVE_CLK_ENABLE | \
> + (((_nparents) - 1) << STARFIVE_CLK_MUX_SHIFT) | (_max), \
> .parents = { __VA_ARGS__ }, \
> }
>
> -#define JH71X0__INV(_idx, _name, _parent) \
> +#define STARFIVE__INV(_idx, _name, _parent) \
> [_idx] = { \
> .name = _name, \
> .flags = CLK_SET_RATE_PARENT, \
> - .max = JH71X0_CLK_INVERT, \
> + .max = STARFIVE_CLK_INVERT, \
> .parents = { [0] = _parent }, \
> }
>
> -struct jh71x0_clk {
> +struct starfive_clk {
> struct clk_hw hw;
> unsigned int idx;
> unsigned int max_div;
> };
>
> -struct jh71x0_clk_priv {
> +struct starfive_clk_priv {
> /* protect clk enable and set rate/parent from happening at the same time */
> spinlock_t rmw_lock;
> struct device *dev;
> void __iomem *base;
> struct clk_hw *pll[3];
> - struct jh71x0_clk reg[];
> + struct starfive_clk reg[];
> };
>
> -const struct clk_ops *starfive_jh71x0_clk_ops(u32 max);
> +const struct clk_ops *starfive_clk_ops(u32 max);
>
> #endif
> diff --git a/drivers/clk/starfive/clk-starfive-jh7100-audio.c b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
> index dc4c278606d7..dfe2befddce5 100644
> --- a/drivers/clk/starfive/clk-starfive-jh7100-audio.c
> +++ b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
> @@ -27,66 +27,68 @@
> #define JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD (JH7100_AUDCLK_END + 6)
> #define JH7100_AUDCLK_VAD_INTMEM (JH7100_AUDCLK_END + 7)
>
> -static const struct jh71x0_clk_data jh7100_audclk_data[] = {
> - JH71X0__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,
> - JH7100_AUDCLK_AUDIO_SRC,
> - JH7100_AUDCLK_AUDIO_12288),
> - JH71X0__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,
> - JH7100_AUDCLK_AUDIO_SRC,
> - JH7100_AUDCLK_AUDIO_12288),
> - JH71X0_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),
> - JH71X0_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,
> - JH7100_AUDCLK_ADC_MCLK,
> - JH7100_AUDCLK_I2SADC_BCLK_IOPAD),
> - JH71X0__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),
> - JH71X0_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,
> - JH7100_AUDCLK_I2SADC_BCLK_N,
> - JH7100_AUDCLK_I2SADC_LRCLK_IOPAD,
> - JH7100_AUDCLK_I2SADC_BCLK),
> - JH71X0_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),
> - JH71X0__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,
> - JH7100_AUDCLK_AUDIO_SRC,
> - JH7100_AUDCLK_AUDIO_12288),
> - JH71X0_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),
> - JH71X0__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,
> - JH7100_AUDCLK_AUDIO_SRC,
> - JH7100_AUDCLK_AUDIO_12288),
> - JH71X0_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),
> - JH71X0_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
> - JH71X0__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,
> - JH7100_AUDCLK_AUDIO_SRC,
> - JH7100_AUDCLK_AUDIO_12288),
> - JH71X0_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
> - JH71X0_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,
> - JH7100_AUDCLK_DAC_MCLK,
> - JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
> - JH71X0__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),
> - JH71X0_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,
> - JH7100_AUDCLK_I2S1_MCLK,
> - JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
> - JH71X0_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),
> - JH71X0_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,
> - JH7100_AUDCLK_I2S1_MCLK,
> - JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
> - JH71X0__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),
> - JH71X0_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,
> - JH7100_AUDCLK_I2S1_BCLK_N,
> - JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD),
> - JH71X0_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),
> - JH71X0__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),
> - JH71X0_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),
> - JH71X0_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),
> - JH71X0_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),
> - JH71X0_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),
> - JH71X0__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
> - JH71X0__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
> - JH7100_AUDCLK_VAD_INTMEM,
> - JH7100_AUDCLK_AUDIO_12288),
> +static const struct starfive_clk_data jh7100_audclk_data[] = {
> + STARFIVE__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,
> + JH7100_AUDCLK_AUDIO_SRC,
> + JH7100_AUDCLK_AUDIO_12288),
> + STARFIVE__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,
> + JH7100_AUDCLK_AUDIO_SRC,
> + JH7100_AUDCLK_AUDIO_12288),
> + STARFIVE_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),
> + STARFIVE_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,
> + JH7100_AUDCLK_ADC_MCLK,
> + JH7100_AUDCLK_I2SADC_BCLK_IOPAD),
> + STARFIVE__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),
> + STARFIVE_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,
> + JH7100_AUDCLK_I2SADC_BCLK_N,
> + JH7100_AUDCLK_I2SADC_LRCLK_IOPAD,
> + JH7100_AUDCLK_I2SADC_BCLK),
> + STARFIVE_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),
> + STARFIVE__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,
> + JH7100_AUDCLK_AUDIO_SRC,
> + JH7100_AUDCLK_AUDIO_12288),
> + STARFIVE_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),
> + STARFIVE__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,
> + JH7100_AUDCLK_AUDIO_SRC,
> + JH7100_AUDCLK_AUDIO_12288),
> + STARFIVE_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),
> + STARFIVE_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
> + STARFIVE__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,
> + JH7100_AUDCLK_AUDIO_SRC,
> + JH7100_AUDCLK_AUDIO_12288),
> + STARFIVE_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
> + STARFIVE_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,
> + JH7100_AUDCLK_DAC_MCLK,
> + JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
> + STARFIVE__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),
> + STARFIVE_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,
> + JH7100_AUDCLK_I2S1_MCLK,
> + JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
> + STARFIVE_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),
> + STARFIVE_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,
> + JH7100_AUDCLK_I2S1_MCLK,
> + JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
> + STARFIVE__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),
> + STARFIVE_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,
> + JH7100_AUDCLK_I2S1_BCLK_N,
> + JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD),
> + STARFIVE_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),
> + STARFIVE__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),
> + STARFIVE_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),
> + STARFIVE_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),
> + STARFIVE_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4,
> + JH7100_AUDCLK_USB_APB),
> + STARFIVE_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3,
> + JH7100_AUDCLK_USB_APB),
> + STARFIVE__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
> + STARFIVE__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
> + JH7100_AUDCLK_VAD_INTMEM,
> + JH7100_AUDCLK_AUDIO_12288),
> };
>
> static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *data)
> {
> - struct jh71x0_clk_priv *priv = data;
> + struct starfive_clk_priv *priv = data;
> unsigned int idx = clkspec->args[0];
>
> if (idx < JH7100_AUDCLK_END)
> @@ -97,7 +99,7 @@ static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *d
>
> static int jh7100_audclk_probe(struct platform_device *pdev)
> {
> - struct jh71x0_clk_priv *priv;
> + struct starfive_clk_priv *priv;
> unsigned int idx;
> int ret;
>
> @@ -116,12 +118,13 @@ static int jh7100_audclk_probe(struct platform_device *pdev)
> struct clk_parent_data parents[4] = {};
> struct clk_init_data init = {
> .name = jh7100_audclk_data[idx].name,
> - .ops = starfive_jh71x0_clk_ops(max),
> + .ops = starfive_clk_ops(max),
> .parent_data = parents,
> - .num_parents = ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
> + .num_parents = ((max & STARFIVE_CLK_MUX_MASK)
> + >> STARFIVE_CLK_MUX_SHIFT) + 1,
> .flags = jh7100_audclk_data[idx].flags,
> };
> - struct jh71x0_clk *clk = &priv->reg[idx];
> + struct starfive_clk *clk = &priv->reg[idx];
> unsigned int i;
>
> for (i = 0; i < init.num_parents; i++) {
> @@ -139,7 +142,7 @@ static int jh7100_audclk_probe(struct platform_device *pdev)
>
> clk->hw.init = &init;
> clk->idx = idx;
> - clk->max_div = max & JH71X0_CLK_DIV_MASK;
> + clk->max_div = max & STARFIVE_CLK_DIV_MASK;
>
> ret = devm_clk_hw_register(priv->dev, &clk->hw);
> if (ret)
> diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c
> index 6bb6a6af9f28..946a437f534b 100644
> --- a/drivers/clk/starfive/clk-starfive-jh7100.c
> +++ b/drivers/clk/starfive/clk-starfive-jh7100.c
> @@ -23,253 +23,257 @@
> #define JH7100_CLK_GMAC_RMII_REF (JH7100_CLK_END + 2)
> #define JH7100_CLK_GMAC_GR_MII_RX (JH7100_CLK_END + 3)
>
> -static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {
> - JH71X0__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
> - JH7100_CLK_OSC_SYS,
> - JH7100_CLK_PLL0_OUT,
> - JH7100_CLK_PLL1_OUT,
> - JH7100_CLK_PLL2_OUT),
> - JH71X0__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3,
> - JH7100_CLK_OSC_SYS,
> - JH7100_CLK_PLL1_OUT,
> - JH7100_CLK_PLL2_OUT),
> - JH71X0__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4,
> - JH7100_CLK_OSC_SYS,
> - JH7100_CLK_PLL0_OUT,
> - JH7100_CLK_PLL1_OUT,
> - JH7100_CLK_PLL2_OUT),
> - JH71X0__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3,
> - JH7100_CLK_OSC_SYS,
> - JH7100_CLK_PLL0_OUT,
> - JH7100_CLK_PLL2_OUT),
> - JH71X0__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2,
> - JH7100_CLK_OSC_SYS,
> - JH7100_CLK_PLL0_OUT),
> - JH71X0__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2,
> - JH7100_CLK_OSC_SYS,
> - JH7100_CLK_PLL2_OUT),
> - JH71X0__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3,
> - JH7100_CLK_OSC_SYS,
> - JH7100_CLK_PLL1_OUT,
> - JH7100_CLK_PLL2_OUT),
> - JH71X0__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3,
> - JH7100_CLK_OSC_AUD,
> - JH7100_CLK_PLL0_OUT,
> - JH7100_CLK_PLL2_OUT),
> - JH71X0_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),
> - JH71X0__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3,
> - JH7100_CLK_OSC_SYS,
> - JH7100_CLK_PLL1_OUT,
> - JH7100_CLK_PLL2_OUT),
> - JH71X0__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3,
> - JH7100_CLK_OSC_SYS,
> - JH7100_CLK_PLL0_OUT,
> - JH7100_CLK_PLL1_OUT),
> - JH71X0__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3,
> - JH7100_CLK_OSC_AUD,
> - JH7100_CLK_PLL0_OUT,
> - JH7100_CLK_PLL2_OUT),
> - JH71X0__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT),
> - JH71X0__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT),
> - JH71X0__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT),
> - JH71X0__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT),
> - JH71X0_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),
> - JH71X0_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),
> - JH71X0_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),
> - JH71X0__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2,
> - JH7100_CLK_OSC_SYS,
> - JH7100_CLK_OSC_AUD),
> - JH71X0__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
> - JH71X0__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE),
> - JH71X0__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
> - JH71X0__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS),
> - JH71X0__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS),
> - JH71X0_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
> - JH71X0_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
> - JH71X0_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE),
> - JH71X0_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE),
> - JH71X0_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI),
> - JH71X0_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL, JH7100_CLK_OSC_SYS),
> - JH71X0_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI),
> - JH71X0_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI),
> - JH71X0_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS),
> - JH71X0__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT),
> - JH71X0_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS),
> - JH71X0_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS),
> - JH71X0_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS),
> - JH71X0_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV),
> - JH71X0__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT),
> - JH71X0_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC),
> - JH71X0__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
> - JH71X0__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus", 8, JH7100_CLK_VCDECBUS_SRC),
> - JH71X0_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi", 0, JH7100_CLK_VDEC_BUS),
> - JH71X0_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk", 0, JH7100_CLK_VDEC_BUS),
> - JH71X0_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
> - JH71X0_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
> - JH71X0_GATE(JH7100_CLK_VDEC_APB, "vdec_apb", 0, JH7100_CLK_APB1_BUS),
> - JH71X0_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
> - JH71X0_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
> - JH71X0_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", 0, JH7100_CLK_APB1_BUS),
> - JH71X0_GDIV(JH7100_CLK_GC300_2X, "gc300_2x", 0, 8, JH7100_CLK_CDECHIFI4_ROOT),
> - JH71X0_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb", 0, JH7100_CLK_AHB_BUS),
> - JH71X0__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus", 8, JH7100_CLK_VCDECBUS_SRC),
> - JH71X0_GATE(JH7100_CLK_GC300_AXI, "gc300_axi", 0, JH7100_CLK_JPCGC300_AXIBUS),
> - JH71X0_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk", 0, JH7100_CLK_JPCGC300_AXIBUS),
> - JH71X0__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC),
> - JH71X0_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS),
> - JH71X0_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS),
> - JH71X0_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
> - JH71X0_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
> - JH71X0_GATE(JH7100_CLK_VENC_APB, "venc_apb", 0, JH7100_CLK_APB1_BUS),
> - JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_PLL1_OUT),
> - JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2,
> - JH7100_CLK_DDRPLL_DIV2),
> - JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2,
> - JH7100_CLK_DDRPLL_DIV4),
> - JH71X0_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_OSC_SYS),
> - JH71X0_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4,
> - JH7100_CLK_DDROSC_DIV2,
> - JH7100_CLK_DDRPLL_DIV2,
> - JH7100_CLK_DDRPLL_DIV4,
> - JH7100_CLK_DDRPLL_DIV8),
> - JH71X0_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4,
> - JH7100_CLK_DDROSC_DIV2,
> - JH7100_CLK_DDRPLL_DIV2,
> - JH7100_CLK_DDRPLL_DIV4,
> - JH7100_CLK_DDRPLL_DIV8),
> - JH71X0_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb", 0, JH7100_CLK_APB1_BUS),
> - JH71X0__DIV(JH7100_CLK_NOC_ROB, "noc_rob", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
> - JH71X0__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT),
> - JH71X0_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS),
> - JH71X0__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT),
> - JH71X0__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2,
> - JH7100_CLK_CPU_AXI,
> - JH7100_CLK_NNEBUS_SRC1),
> - JH71X0_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS),
> - JH71X0_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi", 0, JH7100_CLK_NNE_BUS),
> - JH71X0_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi", 0, JH7100_CLK_NNE_BUS),
> - JH71X0_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi", CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS),
> - JH71X0__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
> - JH71X0__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree", 8, JH7100_CLK_HIFI4_SRC),
> - JH71X0_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core", 0, JH7100_CLK_HIFI4_COREFREE),
> - JH71X0__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus", 8, JH7100_CLK_HIFI4_COREFREE),
> - JH71X0_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi", 0, JH7100_CLK_HIFI4_BUS),
> - JH71X0_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi", 0, JH7100_CLK_HIFI4_BUS),
> - JH71X0__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
> - JH71X0_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
> - JH71X0_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
> - JH71X0_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
> - JH71X0__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
> - JH71X0_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS),
> - JH71X0_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS),
> - JH71X0__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT),
> - JH71X0_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),
> - JH71X0_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32,
> - JH7100_CLK_USBPHY_ROOTDIV),
> - JH71X0__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
> - JH7100_CLK_OSC_SYS,
> - JH7100_CLK_USBPHY_PLLDIV25M),
> - JH71X0_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT),
> - JH71X0_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV),
> - JH71X0_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD),
> - JH71X0_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT),
> - JH71X0__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus", 8, JH7100_CLK_VIN_SRC),
> - JH71X0_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi", 0, JH7100_CLK_ISP0_BUS),
> - JH71X0_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi", 0, JH7100_CLK_ISP0_BUS),
> - JH71X0_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi", 0, JH7100_CLK_ISP0_BUS),
> - JH71X0__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus", 8, JH7100_CLK_VIN_SRC),
> - JH71X0_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi", 0, JH7100_CLK_ISP1_BUS),
> - JH71X0_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi", 0, JH7100_CLK_ISP1_BUS),
> - JH71X0__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC),
> - JH71X0_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS),
> - JH71X0_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS),
> - JH71X0_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT),
> - JH71X0__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT),
> - JH71X0__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC),
> - JH71X0_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS),
> - JH71X0_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS),
> - JH71X0_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS),
> - JH71X0_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC),
> - JH71X0__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT),
> - JH71X0_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS),
> - JH71X0_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC),
> - JH71X0__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT),
> - JH71X0_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS),
> - JH71X0__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT),
> - JH71X0_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV),
> - JH71X0_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),
> - JH71X0_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
> - JH71X0_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
> - JH71X0__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3,
> - JH7100_CLK_GMAC_GTX,
> - JH7100_CLK_GMAC_TX_INV,
> - JH7100_CLK_GMAC_RMII_TX),
> - JH71X0__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX),
> - JH71X0__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2,
> - JH7100_CLK_GMAC_GR_MII_RX,
> - JH7100_CLK_GMAC_RMII_RX),
> - JH71X0__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE),
> - JH71X0_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF),
> - JH71X0_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV),
> - JH71X0_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS),
> - JH71X0_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC),
> - JH71X0_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS),
> - JH71X0_GATE(JH7100_CLK_E24_AHB, "e24_ahb", 0, JH7100_CLK_AHB_BUS),
> - JH71X0_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle", 0, JH7100_CLK_OSC_SYS),
> - JH71X0_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", 0, JH7100_CLK_AHB_BUS),
> - JH71X0_GATE(JH7100_CLK_QSPI_APB, "qspi_apb", 0, JH7100_CLK_APB1_BUS),
> - JH71X0_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk", 0, 31, JH7100_CLK_PERH0_SRC),
> - JH71X0_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", 0, JH7100_CLK_AHB_BUS),
> - JH71X0_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB),
> - JH71X0_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB),
> - JH71X0_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB),
> - JH71X0_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS),
> - JH71X0_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS),
> - JH71X0_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS),
> - JH71X0_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC),
> - JH71X0_GATE(JH7100_CLK_UART1_APB, "uart1_apb", 0, JH7100_CLK_APB1_BUS),
> - JH71X0_GDIV(JH7100_CLK_UART1_CORE, "uart1_core", 0, 63, JH7100_CLK_PERH1_SRC),
> - JH71X0_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", 0, JH7100_CLK_APB1_BUS),
> - JH71X0_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 0, 63, JH7100_CLK_PERH1_SRC),
> - JH71X0_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", 0, JH7100_CLK_APB1_BUS),
> - JH71X0_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 0, 63, JH7100_CLK_PERH1_SRC),
> - JH71X0_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", 0, JH7100_CLK_APB1_BUS),
> - JH71X0_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 0, 63, JH7100_CLK_PERH1_SRC),
> - JH71X0_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", 0, JH7100_CLK_APB1_BUS),
> - JH71X0_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 0, 63, JH7100_CLK_PERH1_SRC),
> - JH71X0_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", 0, JH7100_CLK_APB1_BUS),
> - JH71X0_GATE(JH7100_CLK_UART2_APB, "uart2_apb", 0, JH7100_CLK_APB2_BUS),
> - JH71X0_GDIV(JH7100_CLK_UART2_CORE, "uart2_core", 0, 63, JH7100_CLK_PERH0_SRC),
> - JH71X0_GATE(JH7100_CLK_UART3_APB, "uart3_apb", 0, JH7100_CLK_APB2_BUS),
> - JH71X0_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC),
> - JH71X0_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", 0, JH7100_CLK_APB2_BUS),
> - JH71X0_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 0, 63, JH7100_CLK_PERH0_SRC),
> - JH71X0_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", 0, JH7100_CLK_APB2_BUS),
> - JH71X0_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 0, 63, JH7100_CLK_PERH0_SRC),
> - JH71X0_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", 0, JH7100_CLK_APB2_BUS),
> - JH71X0_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 0, 63, JH7100_CLK_PERH0_SRC),
> - JH71X0_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", 0, JH7100_CLK_APB2_BUS),
> - JH71X0_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC),
> - JH71X0_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS),
> - JH71X0_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
> - JH71X0_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
> - JH71X0_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
> - JH71X0_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
> - JH71X0_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
> - JH71X0_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
> - JH71X0_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
> - JH71X0_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
> - JH71X0_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS),
> - JH71X0_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS),
> - JH71X0_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS),
> - JH71X0_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS),
> - JH71X0_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS),
> - JH71X0_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS),
> +static const struct starfive_clk_data jh7100_clk_data[] __initconst = {
> + STARFIVE__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
> + JH7100_CLK_OSC_SYS,
> + JH7100_CLK_PLL0_OUT,
> + JH7100_CLK_PLL1_OUT,
> + JH7100_CLK_PLL2_OUT),
> + STARFIVE__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3,
> + JH7100_CLK_OSC_SYS,
> + JH7100_CLK_PLL1_OUT,
> + JH7100_CLK_PLL2_OUT),
> + STARFIVE__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4,
> + JH7100_CLK_OSC_SYS,
> + JH7100_CLK_PLL0_OUT,
> + JH7100_CLK_PLL1_OUT,
> + JH7100_CLK_PLL2_OUT),
> + STARFIVE__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3,
> + JH7100_CLK_OSC_SYS,
> + JH7100_CLK_PLL0_OUT,
> + JH7100_CLK_PLL2_OUT),
> + STARFIVE__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2,
> + JH7100_CLK_OSC_SYS,
> + JH7100_CLK_PLL0_OUT),
> + STARFIVE__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2,
> + JH7100_CLK_OSC_SYS,
> + JH7100_CLK_PLL2_OUT),
> + STARFIVE__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3,
> + JH7100_CLK_OSC_SYS,
> + JH7100_CLK_PLL1_OUT,
> + JH7100_CLK_PLL2_OUT),
> + STARFIVE__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3,
> + JH7100_CLK_OSC_AUD,
> + JH7100_CLK_PLL0_OUT,
> + JH7100_CLK_PLL2_OUT),
> + STARFIVE_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),
> + STARFIVE__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3,
> + JH7100_CLK_OSC_SYS,
> + JH7100_CLK_PLL1_OUT,
> + JH7100_CLK_PLL2_OUT),
> + STARFIVE__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3,
> + JH7100_CLK_OSC_SYS,
> + JH7100_CLK_PLL0_OUT,
> + JH7100_CLK_PLL1_OUT),
> + STARFIVE__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3,
> + JH7100_CLK_OSC_AUD,
> + JH7100_CLK_PLL0_OUT,
> + JH7100_CLK_PLL2_OUT),
> + STARFIVE__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT),
> + STARFIVE__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT),
> + STARFIVE__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT),
> + STARFIVE__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT),
> + STARFIVE_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),
> + STARFIVE_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),
> + STARFIVE_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),
> + STARFIVE__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2,
> + JH7100_CLK_OSC_SYS,
> + JH7100_CLK_OSC_AUD),
> + STARFIVE__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
> + STARFIVE__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE),
> + STARFIVE__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
> + STARFIVE__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS),
> + STARFIVE__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS),
> + STARFIVE_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
> + STARFIVE_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
> + STARFIVE_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE),
> + STARFIVE_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE),
> + STARFIVE_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI),
> + STARFIVE_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL,
> + JH7100_CLK_OSC_SYS),
> + STARFIVE_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI),
> + STARFIVE_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI),
> + STARFIVE_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS),
> + STARFIVE__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT),
> + STARFIVE_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS),
> + STARFIVE_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS),
> + STARFIVE_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS),
> + STARFIVE_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV),
> + STARFIVE__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT),
> + STARFIVE_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC),
> + STARFIVE__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
> + STARFIVE__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus", 8, JH7100_CLK_VCDECBUS_SRC),
> + STARFIVE_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi", 0, JH7100_CLK_VDEC_BUS),
> + STARFIVE_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk", 0, JH7100_CLK_VDEC_BUS),
> + STARFIVE_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
> + STARFIVE_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
> + STARFIVE_GATE(JH7100_CLK_VDEC_APB, "vdec_apb", 0, JH7100_CLK_APB1_BUS),
> + STARFIVE_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
> + STARFIVE_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
> + STARFIVE_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", 0, JH7100_CLK_APB1_BUS),
> + STARFIVE_GDIV(JH7100_CLK_GC300_2X, "gc300_2x", 0, 8, JH7100_CLK_CDECHIFI4_ROOT),
> + STARFIVE_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb", 0, JH7100_CLK_AHB_BUS),
> + STARFIVE__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus", 8, JH7100_CLK_VCDECBUS_SRC),
> + STARFIVE_GATE(JH7100_CLK_GC300_AXI, "gc300_axi", 0, JH7100_CLK_JPCGC300_AXIBUS),
> + STARFIVE_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk", 0, JH7100_CLK_JPCGC300_AXIBUS),
> + STARFIVE__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC),
> + STARFIVE_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS),
> + STARFIVE_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS),
> + STARFIVE_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
> + STARFIVE_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
> + STARFIVE_GATE(JH7100_CLK_VENC_APB, "venc_apb", 0, JH7100_CLK_APB1_BUS),
> + STARFIVE_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2,
> + JH7100_CLK_PLL1_OUT),
> + STARFIVE_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2,
> + JH7100_CLK_DDRPLL_DIV2),
> + STARFIVE_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2,
> + JH7100_CLK_DDRPLL_DIV4),
> + STARFIVE_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2,
> + JH7100_CLK_OSC_SYS),
> + STARFIVE_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4,
> + JH7100_CLK_DDROSC_DIV2,
> + JH7100_CLK_DDRPLL_DIV2,
> + JH7100_CLK_DDRPLL_DIV4,
> + JH7100_CLK_DDRPLL_DIV8),
> + STARFIVE_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4,
> + JH7100_CLK_DDROSC_DIV2,
> + JH7100_CLK_DDRPLL_DIV2,
> + JH7100_CLK_DDRPLL_DIV4,
> + JH7100_CLK_DDRPLL_DIV8),
> + STARFIVE_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb", 0, JH7100_CLK_APB1_BUS),
> + STARFIVE__DIV(JH7100_CLK_NOC_ROB, "noc_rob", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
> + STARFIVE__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT),
> + STARFIVE_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS),
> + STARFIVE__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT),
> + STARFIVE__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2,
> + JH7100_CLK_CPU_AXI,
> + JH7100_CLK_NNEBUS_SRC1),
> + STARFIVE_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS),
> + STARFIVE_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi", 0, JH7100_CLK_NNE_BUS),
> + STARFIVE_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi", 0, JH7100_CLK_NNE_BUS),
> + STARFIVE_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi", CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS),
> + STARFIVE__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
> + STARFIVE__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree", 8, JH7100_CLK_HIFI4_SRC),
> + STARFIVE_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core", 0, JH7100_CLK_HIFI4_COREFREE),
> + STARFIVE__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus", 8, JH7100_CLK_HIFI4_COREFREE),
> + STARFIVE_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi", 0, JH7100_CLK_HIFI4_BUS),
> + STARFIVE_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi", 0, JH7100_CLK_HIFI4_BUS),
> + STARFIVE__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
> + STARFIVE_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
> + STARFIVE_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
> + STARFIVE_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8,
> + JH7100_CLK_CPUNBUS_ROOT_DIV),
> + STARFIVE__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
> + STARFIVE_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS),
> + STARFIVE_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS),
> + STARFIVE__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT),
> + STARFIVE_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),
> + STARFIVE_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32,
> + JH7100_CLK_USBPHY_ROOTDIV),
> + STARFIVE__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
> + JH7100_CLK_OSC_SYS,
> + JH7100_CLK_USBPHY_PLLDIV25M),
> + STARFIVE_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT),
> + STARFIVE_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV),
> + STARFIVE_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD),
> + STARFIVE_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT),
> + STARFIVE__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus", 8, JH7100_CLK_VIN_SRC),
> + STARFIVE_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi", 0, JH7100_CLK_ISP0_BUS),
> + STARFIVE_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi", 0, JH7100_CLK_ISP0_BUS),
> + STARFIVE_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi", 0, JH7100_CLK_ISP0_BUS),
> + STARFIVE__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus", 8, JH7100_CLK_VIN_SRC),
> + STARFIVE_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi", 0, JH7100_CLK_ISP1_BUS),
> + STARFIVE_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi", 0, JH7100_CLK_ISP1_BUS),
> + STARFIVE__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC),
> + STARFIVE_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS),
> + STARFIVE_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS),
> + STARFIVE_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT),
> + STARFIVE__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT),
> + STARFIVE__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC),
> + STARFIVE_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS),
> + STARFIVE_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS),
> + STARFIVE_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS),
> + STARFIVE_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC),
> + STARFIVE__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT),
> + STARFIVE_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS),
> + STARFIVE_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC),
> + STARFIVE__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT),
> + STARFIVE_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS),
> + STARFIVE__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT),
> + STARFIVE_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV),
> + STARFIVE_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),
> + STARFIVE_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
> + STARFIVE_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
> + STARFIVE__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3,
> + JH7100_CLK_GMAC_GTX,
> + JH7100_CLK_GMAC_TX_INV,
> + JH7100_CLK_GMAC_RMII_TX),
> + STARFIVE__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX),
> + STARFIVE__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2,
> + JH7100_CLK_GMAC_GR_MII_RX,
> + JH7100_CLK_GMAC_RMII_RX),
> + STARFIVE__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE),
> + STARFIVE_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF),
> + STARFIVE_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV),
> + STARFIVE_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS),
> + STARFIVE_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC),
> + STARFIVE_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS),
> + STARFIVE_GATE(JH7100_CLK_E24_AHB, "e24_ahb", 0, JH7100_CLK_AHB_BUS),
> + STARFIVE_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle", 0, JH7100_CLK_OSC_SYS),
> + STARFIVE_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", 0, JH7100_CLK_AHB_BUS),
> + STARFIVE_GATE(JH7100_CLK_QSPI_APB, "qspi_apb", 0, JH7100_CLK_APB1_BUS),
> + STARFIVE_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk", 0, 31, JH7100_CLK_PERH0_SRC),
> + STARFIVE_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", 0, JH7100_CLK_AHB_BUS),
> + STARFIVE_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB),
> + STARFIVE_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB),
> + STARFIVE_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB),
> + STARFIVE_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS),
> + STARFIVE_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS),
> + STARFIVE_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS),
> + STARFIVE_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC),
> + STARFIVE_GATE(JH7100_CLK_UART1_APB, "uart1_apb", 0, JH7100_CLK_APB1_BUS),
> + STARFIVE_GDIV(JH7100_CLK_UART1_CORE, "uart1_core", 0, 63, JH7100_CLK_PERH1_SRC),
> + STARFIVE_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", 0, JH7100_CLK_APB1_BUS),
> + STARFIVE_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 0, 63, JH7100_CLK_PERH1_SRC),
> + STARFIVE_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", 0, JH7100_CLK_APB1_BUS),
> + STARFIVE_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 0, 63, JH7100_CLK_PERH1_SRC),
> + STARFIVE_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", 0, JH7100_CLK_APB1_BUS),
> + STARFIVE_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 0, 63, JH7100_CLK_PERH1_SRC),
> + STARFIVE_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", 0, JH7100_CLK_APB1_BUS),
> + STARFIVE_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 0, 63, JH7100_CLK_PERH1_SRC),
> + STARFIVE_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", 0, JH7100_CLK_APB1_BUS),
> + STARFIVE_GATE(JH7100_CLK_UART2_APB, "uart2_apb", 0, JH7100_CLK_APB2_BUS),
> + STARFIVE_GDIV(JH7100_CLK_UART2_CORE, "uart2_core", 0, 63, JH7100_CLK_PERH0_SRC),
> + STARFIVE_GATE(JH7100_CLK_UART3_APB, "uart3_apb", 0, JH7100_CLK_APB2_BUS),
> + STARFIVE_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC),
> + STARFIVE_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", 0, JH7100_CLK_APB2_BUS),
> + STARFIVE_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 0, 63, JH7100_CLK_PERH0_SRC),
> + STARFIVE_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", 0, JH7100_CLK_APB2_BUS),
> + STARFIVE_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 0, 63, JH7100_CLK_PERH0_SRC),
> + STARFIVE_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", 0, JH7100_CLK_APB2_BUS),
> + STARFIVE_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 0, 63, JH7100_CLK_PERH0_SRC),
> + STARFIVE_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", 0, JH7100_CLK_APB2_BUS),
> + STARFIVE_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC),
> + STARFIVE_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS),
> + STARFIVE_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
> + STARFIVE_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
> + STARFIVE_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
> + STARFIVE_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
> + STARFIVE_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
> + STARFIVE_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
> + STARFIVE_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
> + STARFIVE_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
> + STARFIVE_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS),
> + STARFIVE_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS),
> + STARFIVE_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS),
> + STARFIVE_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS),
> + STARFIVE_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS),
> + STARFIVE_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS),
> };
>
> static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data)
> {
> - struct jh71x0_clk_priv *priv = data;
> + struct starfive_clk_priv *priv = data;
> unsigned int idx = clkspec->args[0];
>
> if (idx < JH7100_CLK_PLL0_OUT)
> @@ -283,7 +287,7 @@ static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data
>
> static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
> {
> - struct jh71x0_clk_priv *priv;
> + struct starfive_clk_priv *priv;
> unsigned int idx;
> int ret;
>
> @@ -317,12 +321,13 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
> struct clk_parent_data parents[4] = {};
> struct clk_init_data init = {
> .name = jh7100_clk_data[idx].name,
> - .ops = starfive_jh71x0_clk_ops(max),
> + .ops = starfive_clk_ops(max),
> .parent_data = parents,
> - .num_parents = ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
> + .num_parents = ((max & STARFIVE_CLK_MUX_MASK)
> + >> STARFIVE_CLK_MUX_SHIFT) + 1,
> .flags = jh7100_clk_data[idx].flags,
> };
> - struct jh71x0_clk *clk = &priv->reg[idx];
> + struct starfive_clk *clk = &priv->reg[idx];
> unsigned int i;
>
> for (i = 0; i < init.num_parents; i++) {
> @@ -344,7 +349,7 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
>
> clk->hw.init = &init;
> clk->idx = idx;
> - clk->max_div = max & JH71X0_CLK_DIV_MASK;
> + clk->max_div = max & STARFIVE_CLK_DIV_MASK;
>
> ret = devm_clk_hw_register(priv->dev, &clk->hw);
> if (ret)
> diff --git a/drivers/clk/starfive/clk-starfive-jh7110-aon.c b/drivers/clk/starfive/clk-starfive-jh7110-aon.c
> index 62954eb7b50a..a7ce89b566eb 100644
> --- a/drivers/clk/starfive/clk-starfive-jh7110-aon.c
> +++ b/drivers/clk/starfive/clk-starfive-jh7110-aon.c
> @@ -23,40 +23,40 @@
> #define JH7110_AONCLK_GMAC0_GTXCLK (JH7110_AONCLK_END + 5)
> #define JH7110_AONCLK_RTC_OSC (JH7110_AONCLK_END + 6)
>
> -static const struct jh71x0_clk_data jh7110_aonclk_data[] = {
> +static const struct starfive_clk_data jh7110_aonclk_data[] = {
> /* source */
> - JH71X0__DIV(JH7110_AONCLK_OSC_DIV4, "osc_div4", 4, JH7110_AONCLK_OSC),
> - JH71X0__MUX(JH7110_AONCLK_APB_FUNC, "apb_func", 2,
> - JH7110_AONCLK_OSC_DIV4,
> - JH7110_AONCLK_OSC),
> + STARFIVE__DIV(JH7110_AONCLK_OSC_DIV4, "osc_div4", 4, JH7110_AONCLK_OSC),
> + STARFIVE__MUX(JH7110_AONCLK_APB_FUNC, "apb_func", 2,
> + JH7110_AONCLK_OSC_DIV4,
> + JH7110_AONCLK_OSC),
> /* gmac0 */
> - JH71X0_GATE(JH7110_AONCLK_GMAC0_AHB, "gmac0_ahb", 0, JH7110_AONCLK_STG_AXIAHB),
> - JH71X0_GATE(JH7110_AONCLK_GMAC0_AXI, "gmac0_axi", 0, JH7110_AONCLK_STG_AXIAHB),
> - JH71X0__DIV(JH7110_AONCLK_GMAC0_RMII_RTX, "gmac0_rmii_rtx", 30,
> - JH7110_AONCLK_GMAC0_RMII_REFIN),
> - JH71X0_GMUX(JH7110_AONCLK_GMAC0_TX, "gmac0_tx",
> - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2,
> - JH7110_AONCLK_GMAC0_GTXCLK,
> - JH7110_AONCLK_GMAC0_RMII_RTX),
> - JH71X0__INV(JH7110_AONCLK_GMAC0_TX_INV, "gmac0_tx_inv", JH7110_AONCLK_GMAC0_TX),
> - JH71X0__MUX(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", 2,
> - JH7110_AONCLK_GMAC0_RGMII_RXIN,
> - JH7110_AONCLK_GMAC0_RMII_RTX),
> - JH71X0__INV(JH7110_AONCLK_GMAC0_RX_INV, "gmac0_rx_inv", JH7110_AONCLK_GMAC0_RX),
> + STARFIVE_GATE(JH7110_AONCLK_GMAC0_AHB, "gmac0_ahb", 0, JH7110_AONCLK_STG_AXIAHB),
> + STARFIVE_GATE(JH7110_AONCLK_GMAC0_AXI, "gmac0_axi", 0, JH7110_AONCLK_STG_AXIAHB),
> + STARFIVE__DIV(JH7110_AONCLK_GMAC0_RMII_RTX, "gmac0_rmii_rtx", 30,
> + JH7110_AONCLK_GMAC0_RMII_REFIN),
> + STARFIVE_GMUX(JH7110_AONCLK_GMAC0_TX, "gmac0_tx",
> + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2,
> + JH7110_AONCLK_GMAC0_GTXCLK,
> + JH7110_AONCLK_GMAC0_RMII_RTX),
> + STARFIVE__INV(JH7110_AONCLK_GMAC0_TX_INV, "gmac0_tx_inv", JH7110_AONCLK_GMAC0_TX),
> + STARFIVE__MUX(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", 2,
> + JH7110_AONCLK_GMAC0_RGMII_RXIN,
> + JH7110_AONCLK_GMAC0_RMII_RTX),
> + STARFIVE__INV(JH7110_AONCLK_GMAC0_RX_INV, "gmac0_rx_inv", JH7110_AONCLK_GMAC0_RX),
> /* otpc */
> - JH71X0_GATE(JH7110_AONCLK_OTPC_APB, "otpc_apb", 0, JH7110_AONCLK_APB_BUS),
> + STARFIVE_GATE(JH7110_AONCLK_OTPC_APB, "otpc_apb", 0, JH7110_AONCLK_APB_BUS),
> /* rtc */
> - JH71X0_GATE(JH7110_AONCLK_RTC_APB, "rtc_apb", 0, JH7110_AONCLK_APB_BUS),
> - JH71X0__DIV(JH7110_AONCLK_RTC_INTERNAL, "rtc_internal", 1022, JH7110_AONCLK_OSC),
> - JH71X0__MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", 2,
> - JH7110_AONCLK_RTC_OSC,
> - JH7110_AONCLK_RTC_INTERNAL),
> - JH71X0_GATE(JH7110_AONCLK_RTC_CAL, "rtc_cal", 0, JH7110_AONCLK_OSC),
> + STARFIVE_GATE(JH7110_AONCLK_RTC_APB, "rtc_apb", 0, JH7110_AONCLK_APB_BUS),
> + STARFIVE__DIV(JH7110_AONCLK_RTC_INTERNAL, "rtc_internal", 1022, JH7110_AONCLK_OSC),
> + STARFIVE__MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", 2,
> + JH7110_AONCLK_RTC_OSC,
> + JH7110_AONCLK_RTC_INTERNAL),
> + STARFIVE_GATE(JH7110_AONCLK_RTC_CAL, "rtc_cal", 0, JH7110_AONCLK_OSC),
> };
>
> static struct clk_hw *jh7110_aonclk_get(struct of_phandle_args *clkspec, void *data)
> {
> - struct jh71x0_clk_priv *priv = data;
> + struct starfive_clk_priv *priv = data;
> unsigned int idx = clkspec->args[0];
>
> if (idx < JH7110_AONCLK_END)
> @@ -67,7 +67,7 @@ static struct clk_hw *jh7110_aonclk_get(struct of_phandle_args *clkspec, void *d
>
> static int jh7110_aoncrg_probe(struct platform_device *pdev)
> {
> - struct jh71x0_clk_priv *priv;
> + struct starfive_clk_priv *priv;
> unsigned int idx;
> int ret;
>
> @@ -88,13 +88,13 @@ static int jh7110_aoncrg_probe(struct platform_device *pdev)
> struct clk_parent_data parents[4] = {};
> struct clk_init_data init = {
> .name = jh7110_aonclk_data[idx].name,
> - .ops = starfive_jh71x0_clk_ops(max),
> + .ops = starfive_clk_ops(max),
> .parent_data = parents,
> .num_parents =
> - ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
> + ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
> .flags = jh7110_aonclk_data[idx].flags,
> };
> - struct jh71x0_clk *clk = &priv->reg[idx];
> + struct starfive_clk *clk = &priv->reg[idx];
> unsigned int i;
>
> for (i = 0; i < init.num_parents; i++) {
> @@ -120,7 +120,7 @@ static int jh7110_aoncrg_probe(struct platform_device *pdev)
>
> clk->hw.init = &init;
> clk->idx = idx;
> - clk->max_div = max & JH71X0_CLK_DIV_MASK;
> + clk->max_div = max & STARFIVE_CLK_DIV_MASK;
>
> ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
> if (ret)
> diff --git a/drivers/clk/starfive/clk-starfive-jh7110-isp.c b/drivers/clk/starfive/clk-starfive-jh7110-isp.c
> index ce034ed28532..be6040f718c0 100644
> --- a/drivers/clk/starfive/clk-starfive-jh7110-isp.c
> +++ b/drivers/clk/starfive/clk-starfive-jh7110-isp.c
> @@ -28,41 +28,41 @@ static struct clk_bulk_data jh7110_isp_top_clks[] = {
> { .id = "isp_top_axi" }
> };
>
> -static const struct jh71x0_clk_data jh7110_ispclk_data[] = {
> +static const struct starfive_clk_data jh7110_ispclk_data[] = {
> /* syscon */
> - JH71X0__DIV(JH7110_ISPCLK_DOM4_APB_FUNC, "dom4_apb_func", 15,
> - JH7110_ISPCLK_ISP_TOP_AXI),
> - JH71X0__DIV(JH7110_ISPCLK_MIPI_RX0_PXL, "mipi_rx0_pxl", 8,
> - JH7110_ISPCLK_ISP_TOP_CORE),
> - JH71X0__INV(JH7110_ISPCLK_DVP_INV, "dvp_inv", JH7110_ISPCLK_DVP_CLK),
> + STARFIVE__DIV(JH7110_ISPCLK_DOM4_APB_FUNC, "dom4_apb_func", 15,
> + JH7110_ISPCLK_ISP_TOP_AXI),
> + STARFIVE__DIV(JH7110_ISPCLK_MIPI_RX0_PXL, "mipi_rx0_pxl", 8,
> + JH7110_ISPCLK_ISP_TOP_CORE),
> + STARFIVE__INV(JH7110_ISPCLK_DVP_INV, "dvp_inv", JH7110_ISPCLK_DVP_CLK),
> /* vin */
> - JH71X0__DIV(JH7110_ISPCLK_M31DPHY_CFG_IN, "m31dphy_cfg_in", 16,
> - JH7110_ISPCLK_ISP_TOP_CORE),
> - JH71X0__DIV(JH7110_ISPCLK_M31DPHY_REF_IN, "m31dphy_ref_in", 16,
> - JH7110_ISPCLK_ISP_TOP_CORE),
> - JH71X0__DIV(JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0, "m31dphy_tx_esc_lan0", 60,
> - JH7110_ISPCLK_ISP_TOP_CORE),
> - JH71X0_GATE(JH7110_ISPCLK_VIN_APB, "vin_apb", 0,
> - JH7110_ISPCLK_DOM4_APB_FUNC),
> - JH71X0__DIV(JH7110_ISPCLK_VIN_SYS, "vin_sys", 8, JH7110_ISPCLK_ISP_TOP_CORE),
> - JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF0, "vin_pixel_if0", 0,
> - JH7110_ISPCLK_MIPI_RX0_PXL),
> - JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF1, "vin_pixel_if1", 0,
> - JH7110_ISPCLK_MIPI_RX0_PXL),
> - JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF2, "vin_pixel_if2", 0,
> - JH7110_ISPCLK_MIPI_RX0_PXL),
> - JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF3, "vin_pixel_if3", 0,
> - JH7110_ISPCLK_MIPI_RX0_PXL),
> - JH71X0__MUX(JH7110_ISPCLK_VIN_P_AXI_WR, "vin_p_axi_wr", 2,
> - JH7110_ISPCLK_MIPI_RX0_PXL,
> - JH7110_ISPCLK_DVP_INV),
> + STARFIVE__DIV(JH7110_ISPCLK_M31DPHY_CFG_IN, "m31dphy_cfg_in", 16,
> + JH7110_ISPCLK_ISP_TOP_CORE),
> + STARFIVE__DIV(JH7110_ISPCLK_M31DPHY_REF_IN, "m31dphy_ref_in", 16,
> + JH7110_ISPCLK_ISP_TOP_CORE),
> + STARFIVE__DIV(JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0, "m31dphy_tx_esc_lan0", 60,
> + JH7110_ISPCLK_ISP_TOP_CORE),
> + STARFIVE_GATE(JH7110_ISPCLK_VIN_APB, "vin_apb", 0,
> + JH7110_ISPCLK_DOM4_APB_FUNC),
> + STARFIVE__DIV(JH7110_ISPCLK_VIN_SYS, "vin_sys", 8, JH7110_ISPCLK_ISP_TOP_CORE),
> + STARFIVE_GATE(JH7110_ISPCLK_VIN_PIXEL_IF0, "vin_pixel_if0", 0,
> + JH7110_ISPCLK_MIPI_RX0_PXL),
> + STARFIVE_GATE(JH7110_ISPCLK_VIN_PIXEL_IF1, "vin_pixel_if1", 0,
> + JH7110_ISPCLK_MIPI_RX0_PXL),
> + STARFIVE_GATE(JH7110_ISPCLK_VIN_PIXEL_IF2, "vin_pixel_if2", 0,
> + JH7110_ISPCLK_MIPI_RX0_PXL),
> + STARFIVE_GATE(JH7110_ISPCLK_VIN_PIXEL_IF3, "vin_pixel_if3", 0,
> + JH7110_ISPCLK_MIPI_RX0_PXL),
> + STARFIVE__MUX(JH7110_ISPCLK_VIN_P_AXI_WR, "vin_p_axi_wr", 2,
> + JH7110_ISPCLK_MIPI_RX0_PXL,
> + JH7110_ISPCLK_DVP_INV),
> /* ispv2_top_wrapper */
> - JH71X0_GMUX(JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C, "ispv2_top_wrapper_c", 0, 2,
> - JH7110_ISPCLK_MIPI_RX0_PXL,
> - JH7110_ISPCLK_DVP_INV),
> + STARFIVE_GMUX(JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C, "ispv2_top_wrapper_c", 0, 2,
> + JH7110_ISPCLK_MIPI_RX0_PXL,
> + JH7110_ISPCLK_DVP_INV),
> };
>
> -static inline int jh7110_isp_top_rst_init(struct jh71x0_clk_priv *priv)
> +static inline int jh7110_isp_top_rst_init(struct starfive_clk_priv *priv)
> {
> struct reset_control *top_rsts;
>
> @@ -77,7 +77,7 @@ static inline int jh7110_isp_top_rst_init(struct jh71x0_clk_priv *priv)
>
> static struct clk_hw *jh7110_ispclk_get(struct of_phandle_args *clkspec, void *data)
> {
> - struct jh71x0_clk_priv *priv = data;
> + struct starfive_clk_priv *priv = data;
> unsigned int idx = clkspec->args[0];
>
> if (idx < JH7110_ISPCLK_END)
> @@ -110,7 +110,7 @@ static const struct dev_pm_ops jh7110_ispcrg_pm_ops = {
>
> static int jh7110_ispcrg_probe(struct platform_device *pdev)
> {
> - struct jh71x0_clk_priv *priv;
> + struct starfive_clk_priv *priv;
> struct jh7110_top_sysclk *top;
> unsigned int idx;
> int ret;
> @@ -153,13 +153,13 @@ static int jh7110_ispcrg_probe(struct platform_device *pdev)
> struct clk_parent_data parents[4] = {};
> struct clk_init_data init = {
> .name = jh7110_ispclk_data[idx].name,
> - .ops = starfive_jh71x0_clk_ops(max),
> + .ops = starfive_clk_ops(max),
> .parent_data = parents,
> .num_parents =
> - ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
> + ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
> .flags = jh7110_ispclk_data[idx].flags,
> };
> - struct jh71x0_clk *clk = &priv->reg[idx];
> + struct starfive_clk *clk = &priv->reg[idx];
> unsigned int i;
> const char *fw_name[JH7110_ISPCLK_EXT_END - JH7110_ISPCLK_END] = {
> "isp_top_core",
> @@ -179,7 +179,7 @@ static int jh7110_ispcrg_probe(struct platform_device *pdev)
>
> clk->hw.init = &init;
> clk->idx = idx;
> - clk->max_div = max & JH71X0_CLK_DIV_MASK;
> + clk->max_div = max & STARFIVE_CLK_DIV_MASK;
>
> ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
> if (ret)
> diff --git a/drivers/clk/starfive/clk-starfive-jh7110-stg.c b/drivers/clk/starfive/clk-starfive-jh7110-stg.c
> index dafcb7190592..2d6ee0ad343a 100644
> --- a/drivers/clk/starfive/clk-starfive-jh7110-stg.c
> +++ b/drivers/clk/starfive/clk-starfive-jh7110-stg.c
> @@ -25,59 +25,59 @@
> #define JH7110_STGCLK_APB_BUS (JH7110_STGCLK_END + 7)
> #define JH7110_STGCLK_EXT_END (JH7110_STGCLK_END + 8)
>
> -static const struct jh71x0_clk_data jh7110_stgclk_data[] = {
> +static const struct starfive_clk_data jh7110_stgclk_data[] = {
> /* hifi4 */
> - JH71X0_GATE(JH7110_STGCLK_HIFI4_CLK_CORE, "hifi4_clk_core", 0,
> - JH7110_STGCLK_HIFI4_CORE),
> + STARFIVE_GATE(JH7110_STGCLK_HIFI4_CLK_CORE, "hifi4_clk_core", 0,
> + JH7110_STGCLK_HIFI4_CORE),
> /* usb */
> - JH71X0_GATE(JH7110_STGCLK_USB0_APB, "usb0_apb", 0, JH7110_STGCLK_APB_BUS),
> - JH71X0_GATE(JH7110_STGCLK_USB0_UTMI_APB, "usb0_utmi_apb", 0, JH7110_STGCLK_APB_BUS),
> - JH71X0_GATE(JH7110_STGCLK_USB0_AXI, "usb0_axi", 0, JH7110_STGCLK_STG_AXIAHB),
> - JH71X0_GDIV(JH7110_STGCLK_USB0_LPM, "usb0_lpm", 0, 2, JH7110_STGCLK_OSC),
> - JH71X0_GDIV(JH7110_STGCLK_USB0_STB, "usb0_stb", 0, 4, JH7110_STGCLK_OSC),
> - JH71X0_GATE(JH7110_STGCLK_USB0_APP_125, "usb0_app_125", 0, JH7110_STGCLK_USB_125M),
> - JH71X0__DIV(JH7110_STGCLK_USB0_REFCLK, "usb0_refclk", 2, JH7110_STGCLK_OSC),
> + STARFIVE_GATE(JH7110_STGCLK_USB0_APB, "usb0_apb", 0, JH7110_STGCLK_APB_BUS),
> + STARFIVE_GATE(JH7110_STGCLK_USB0_UTMI_APB, "usb0_utmi_apb", 0, JH7110_STGCLK_APB_BUS),
> + STARFIVE_GATE(JH7110_STGCLK_USB0_AXI, "usb0_axi", 0, JH7110_STGCLK_STG_AXIAHB),
> + STARFIVE_GDIV(JH7110_STGCLK_USB0_LPM, "usb0_lpm", 0, 2, JH7110_STGCLK_OSC),
> + STARFIVE_GDIV(JH7110_STGCLK_USB0_STB, "usb0_stb", 0, 4, JH7110_STGCLK_OSC),
> + STARFIVE_GATE(JH7110_STGCLK_USB0_APP_125, "usb0_app_125", 0, JH7110_STGCLK_USB_125M),
> + STARFIVE__DIV(JH7110_STGCLK_USB0_REFCLK, "usb0_refclk", 2, JH7110_STGCLK_OSC),
> /* pci-e */
> - JH71X0_GATE(JH7110_STGCLK_PCIE0_AXI_MST0, "pcie0_axi_mst0", 0,
> - JH7110_STGCLK_STG_AXIAHB),
> - JH71X0_GATE(JH7110_STGCLK_PCIE0_APB, "pcie0_apb", 0, JH7110_STGCLK_APB_BUS),
> - JH71X0_GATE(JH7110_STGCLK_PCIE0_TL, "pcie0_tl", 0, JH7110_STGCLK_STG_AXIAHB),
> - JH71X0_GATE(JH7110_STGCLK_PCIE1_AXI_MST0, "pcie1_axi_mst0", 0,
> - JH7110_STGCLK_STG_AXIAHB),
> - JH71X0_GATE(JH7110_STGCLK_PCIE1_APB, "pcie1_apb", 0, JH7110_STGCLK_APB_BUS),
> - JH71X0_GATE(JH7110_STGCLK_PCIE1_TL, "pcie1_tl", 0, JH7110_STGCLK_STG_AXIAHB),
> - JH71X0_GATE(JH7110_STGCLK_PCIE_SLV_MAIN, "pcie_slv_main", CLK_IS_CRITICAL,
> - JH7110_STGCLK_STG_AXIAHB),
> + STARFIVE_GATE(JH7110_STGCLK_PCIE0_AXI_MST0, "pcie0_axi_mst0", 0,
> + JH7110_STGCLK_STG_AXIAHB),
> + STARFIVE_GATE(JH7110_STGCLK_PCIE0_APB, "pcie0_apb", 0, JH7110_STGCLK_APB_BUS),
> + STARFIVE_GATE(JH7110_STGCLK_PCIE0_TL, "pcie0_tl", 0, JH7110_STGCLK_STG_AXIAHB),
> + STARFIVE_GATE(JH7110_STGCLK_PCIE1_AXI_MST0, "pcie1_axi_mst0", 0,
> + JH7110_STGCLK_STG_AXIAHB),
> + STARFIVE_GATE(JH7110_STGCLK_PCIE1_APB, "pcie1_apb", 0, JH7110_STGCLK_APB_BUS),
> + STARFIVE_GATE(JH7110_STGCLK_PCIE1_TL, "pcie1_tl", 0, JH7110_STGCLK_STG_AXIAHB),
> + STARFIVE_GATE(JH7110_STGCLK_PCIE_SLV_MAIN, "pcie_slv_main", CLK_IS_CRITICAL,
> + JH7110_STGCLK_STG_AXIAHB),
> /* security */
> - JH71X0_GATE(JH7110_STGCLK_SEC_AHB, "sec_ahb", 0, JH7110_STGCLK_STG_AXIAHB),
> - JH71X0_GATE(JH7110_STGCLK_SEC_MISC_AHB, "sec_misc_ahb", 0, JH7110_STGCLK_STG_AXIAHB),
> + STARFIVE_GATE(JH7110_STGCLK_SEC_AHB, "sec_ahb", 0, JH7110_STGCLK_STG_AXIAHB),
> + STARFIVE_GATE(JH7110_STGCLK_SEC_MISC_AHB, "sec_misc_ahb", 0, JH7110_STGCLK_STG_AXIAHB),
> /* stg mtrx */
> - JH71X0_GATE(JH7110_STGCLK_GRP0_MAIN, "mtrx_grp0_main", CLK_IS_CRITICAL,
> - JH7110_STGCLK_CPU_BUS),
> - JH71X0_GATE(JH7110_STGCLK_GRP0_BUS, "mtrx_grp0_bus", CLK_IS_CRITICAL,
> - JH7110_STGCLK_NOCSTG_BUS),
> - JH71X0_GATE(JH7110_STGCLK_GRP0_STG, "mtrx_grp0_stg", CLK_IS_CRITICAL,
> - JH7110_STGCLK_STG_AXIAHB),
> - JH71X0_GATE(JH7110_STGCLK_GRP1_MAIN, "mtrx_grp1_main", CLK_IS_CRITICAL,
> - JH7110_STGCLK_CPU_BUS),
> - JH71X0_GATE(JH7110_STGCLK_GRP1_BUS, "mtrx_grp1_bus", CLK_IS_CRITICAL,
> - JH7110_STGCLK_NOCSTG_BUS),
> - JH71X0_GATE(JH7110_STGCLK_GRP1_STG, "mtrx_grp1_stg", CLK_IS_CRITICAL,
> - JH7110_STGCLK_STG_AXIAHB),
> - JH71X0_GATE(JH7110_STGCLK_GRP1_HIFI, "mtrx_grp1_hifi", CLK_IS_CRITICAL,
> - JH7110_STGCLK_HIFI4_AXI),
> + STARFIVE_GATE(JH7110_STGCLK_GRP0_MAIN, "mtrx_grp0_main", CLK_IS_CRITICAL,
> + JH7110_STGCLK_CPU_BUS),
> + STARFIVE_GATE(JH7110_STGCLK_GRP0_BUS, "mtrx_grp0_bus", CLK_IS_CRITICAL,
> + JH7110_STGCLK_NOCSTG_BUS),
> + STARFIVE_GATE(JH7110_STGCLK_GRP0_STG, "mtrx_grp0_stg", CLK_IS_CRITICAL,
> + JH7110_STGCLK_STG_AXIAHB),
> + STARFIVE_GATE(JH7110_STGCLK_GRP1_MAIN, "mtrx_grp1_main", CLK_IS_CRITICAL,
> + JH7110_STGCLK_CPU_BUS),
> + STARFIVE_GATE(JH7110_STGCLK_GRP1_BUS, "mtrx_grp1_bus", CLK_IS_CRITICAL,
> + JH7110_STGCLK_NOCSTG_BUS),
> + STARFIVE_GATE(JH7110_STGCLK_GRP1_STG, "mtrx_grp1_stg", CLK_IS_CRITICAL,
> + JH7110_STGCLK_STG_AXIAHB),
> + STARFIVE_GATE(JH7110_STGCLK_GRP1_HIFI, "mtrx_grp1_hifi", CLK_IS_CRITICAL,
> + JH7110_STGCLK_HIFI4_AXI),
> /* e24_rvpi */
> - JH71X0_GDIV(JH7110_STGCLK_E2_RTC, "e2_rtc", 0, 24, JH7110_STGCLK_OSC),
> - JH71X0_GATE(JH7110_STGCLK_E2_CORE, "e2_core", 0, JH7110_STGCLK_STG_AXIAHB),
> - JH71X0_GATE(JH7110_STGCLK_E2_DBG, "e2_dbg", 0, JH7110_STGCLK_STG_AXIAHB),
> + STARFIVE_GDIV(JH7110_STGCLK_E2_RTC, "e2_rtc", 0, 24, JH7110_STGCLK_OSC),
> + STARFIVE_GATE(JH7110_STGCLK_E2_CORE, "e2_core", 0, JH7110_STGCLK_STG_AXIAHB),
> + STARFIVE_GATE(JH7110_STGCLK_E2_DBG, "e2_dbg", 0, JH7110_STGCLK_STG_AXIAHB),
> /* dw_sgdma1p */
> - JH71X0_GATE(JH7110_STGCLK_DMA1P_AXI, "dma1p_axi", 0, JH7110_STGCLK_STG_AXIAHB),
> - JH71X0_GATE(JH7110_STGCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7110_STGCLK_STG_AXIAHB),
> + STARFIVE_GATE(JH7110_STGCLK_DMA1P_AXI, "dma1p_axi", 0, JH7110_STGCLK_STG_AXIAHB),
> + STARFIVE_GATE(JH7110_STGCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7110_STGCLK_STG_AXIAHB),
> };
>
> static struct clk_hw *jh7110_stgclk_get(struct of_phandle_args *clkspec, void *data)
> {
> - struct jh71x0_clk_priv *priv = data;
> + struct starfive_clk_priv *priv = data;
> unsigned int idx = clkspec->args[0];
>
> if (idx < JH7110_STGCLK_END)
> @@ -88,7 +88,7 @@ static struct clk_hw *jh7110_stgclk_get(struct of_phandle_args *clkspec, void *d
>
> static int jh7110_stgcrg_probe(struct platform_device *pdev)
> {
> - struct jh71x0_clk_priv *priv;
> + struct starfive_clk_priv *priv;
> unsigned int idx;
> int ret;
>
> @@ -108,13 +108,13 @@ static int jh7110_stgcrg_probe(struct platform_device *pdev)
> struct clk_parent_data parents[4] = {};
> struct clk_init_data init = {
> .name = jh7110_stgclk_data[idx].name,
> - .ops = starfive_jh71x0_clk_ops(max),
> + .ops = starfive_clk_ops(max),
> .parent_data = parents,
> .num_parents =
> - ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
> + ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
> .flags = jh7110_stgclk_data[idx].flags,
> };
> - struct jh71x0_clk *clk = &priv->reg[idx];
> + struct starfive_clk *clk = &priv->reg[idx];
> const char *fw_name[JH7110_STGCLK_EXT_END - JH7110_STGCLK_END] = {
> "osc",
> "hifi4_core",
> @@ -138,7 +138,7 @@ static int jh7110_stgcrg_probe(struct platform_device *pdev)
>
> clk->hw.init = &init;
> clk->idx = idx;
> - clk->max_div = max & JH71X0_CLK_DIV_MASK;
> + clk->max_div = max & STARFIVE_CLK_DIV_MASK;
>
> ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
> if (ret)
> diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> index e63353c70209..00ef88d9c2fd 100644
> --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> @@ -34,298 +34,301 @@
> #define JH7110_SYSCLK_PLL1_OUT (JH7110_SYSCLK_END + 10)
> #define JH7110_SYSCLK_PLL2_OUT (JH7110_SYSCLK_END + 11)
>
> -static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
> +static const struct starfive_clk_data jh7110_sysclk_data[] __initconst = {
> /* root */
> - JH71X0__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 2,
> - JH7110_SYSCLK_OSC,
> - JH7110_SYSCLK_PLL0_OUT),
> - JH71X0__DIV(JH7110_SYSCLK_CPU_CORE, "cpu_core", 7, JH7110_SYSCLK_CPU_ROOT),
> - JH71X0__DIV(JH7110_SYSCLK_CPU_BUS, "cpu_bus", 2, JH7110_SYSCLK_CPU_CORE),
> - JH71X0__MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", 2,
> - JH7110_SYSCLK_PLL2_OUT,
> - JH7110_SYSCLK_PLL1_OUT),
> - JH71X0_MDIV(JH7110_SYSCLK_PERH_ROOT, "perh_root", 2, 2,
> - JH7110_SYSCLK_PLL0_OUT,
> - JH7110_SYSCLK_PLL2_OUT),
> - JH71X0__MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", 2,
> - JH7110_SYSCLK_OSC,
> - JH7110_SYSCLK_PLL2_OUT),
> - JH71X0__DIV(JH7110_SYSCLK_NOCSTG_BUS, "nocstg_bus", 3, JH7110_SYSCLK_BUS_ROOT),
> - JH71X0__DIV(JH7110_SYSCLK_AXI_CFG0, "axi_cfg0", 3, JH7110_SYSCLK_BUS_ROOT),
> - JH71X0__DIV(JH7110_SYSCLK_STG_AXIAHB, "stg_axiahb", 2, JH7110_SYSCLK_AXI_CFG0),
> - JH71X0_GATE(JH7110_SYSCLK_AHB0, "ahb0", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB),
> - JH71X0_GATE(JH7110_SYSCLK_AHB1, "ahb1", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB),
> - JH71X0__DIV(JH7110_SYSCLK_APB_BUS, "apb_bus", 8, JH7110_SYSCLK_STG_AXIAHB),
> - JH71X0_GATE(JH7110_SYSCLK_APB0, "apb0", CLK_IS_CRITICAL, JH7110_SYSCLK_APB_BUS),
> - JH71X0__DIV(JH7110_SYSCLK_PLL0_DIV2, "pll0_div2", 2, JH7110_SYSCLK_PLL0_OUT),
> - JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV2, "pll1_div2", 2, JH7110_SYSCLK_PLL1_OUT),
> - JH71X0__DIV(JH7110_SYSCLK_PLL2_DIV2, "pll2_div2", 2, JH7110_SYSCLK_PLL2_OUT),
> - JH71X0__DIV(JH7110_SYSCLK_AUDIO_ROOT, "audio_root", 8, JH7110_SYSCLK_PLL2_OUT),
> - JH71X0__DIV(JH7110_SYSCLK_MCLK_INNER, "mclk_inner", 64, JH7110_SYSCLK_AUDIO_ROOT),
> - JH71X0__MUX(JH7110_SYSCLK_MCLK, "mclk", 2,
> - JH7110_SYSCLK_MCLK_INNER,
> - JH7110_SYSCLK_MCLK_EXT),
> - JH71X0_GATE(JH7110_SYSCLK_MCLK_OUT, "mclk_out", 0, JH7110_SYSCLK_MCLK_INNER),
> - JH71X0_MDIV(JH7110_SYSCLK_ISP_2X, "isp_2x", 8, 2,
> - JH7110_SYSCLK_PLL2_OUT,
> - JH7110_SYSCLK_PLL1_OUT),
> - JH71X0__DIV(JH7110_SYSCLK_ISP_AXI, "isp_axi", 4, JH7110_SYSCLK_ISP_2X),
> - JH71X0_GDIV(JH7110_SYSCLK_GCLK0, "gclk0", 0, 62, JH7110_SYSCLK_PLL0_DIV2),
> - JH71X0_GDIV(JH7110_SYSCLK_GCLK1, "gclk1", 0, 62, JH7110_SYSCLK_PLL1_DIV2),
> - JH71X0_GDIV(JH7110_SYSCLK_GCLK2, "gclk2", 0, 62, JH7110_SYSCLK_PLL2_DIV2),
> + STARFIVE__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 2,
> + JH7110_SYSCLK_OSC,
> + JH7110_SYSCLK_PLL0_OUT),
> + STARFIVE__DIV(JH7110_SYSCLK_CPU_CORE, "cpu_core", 7, JH7110_SYSCLK_CPU_ROOT),
> + STARFIVE__DIV(JH7110_SYSCLK_CPU_BUS, "cpu_bus", 2, JH7110_SYSCLK_CPU_CORE),
> + STARFIVE__MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", 2,
> + JH7110_SYSCLK_PLL2_OUT,
> + JH7110_SYSCLK_PLL1_OUT),
> + STARFIVE_MDIV(JH7110_SYSCLK_PERH_ROOT, "perh_root", 2, 2,
> + JH7110_SYSCLK_PLL0_OUT,
> + JH7110_SYSCLK_PLL2_OUT),
> + STARFIVE__MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", 2,
> + JH7110_SYSCLK_OSC,
> + JH7110_SYSCLK_PLL2_OUT),
> + STARFIVE__DIV(JH7110_SYSCLK_NOCSTG_BUS, "nocstg_bus", 3, JH7110_SYSCLK_BUS_ROOT),
> + STARFIVE__DIV(JH7110_SYSCLK_AXI_CFG0, "axi_cfg0", 3, JH7110_SYSCLK_BUS_ROOT),
> + STARFIVE__DIV(JH7110_SYSCLK_STG_AXIAHB, "stg_axiahb", 2, JH7110_SYSCLK_AXI_CFG0),
> + STARFIVE_GATE(JH7110_SYSCLK_AHB0, "ahb0", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB),
> + STARFIVE_GATE(JH7110_SYSCLK_AHB1, "ahb1", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB),
> + STARFIVE__DIV(JH7110_SYSCLK_APB_BUS, "apb_bus", 8, JH7110_SYSCLK_STG_AXIAHB),
> + STARFIVE_GATE(JH7110_SYSCLK_APB0, "apb0", CLK_IS_CRITICAL, JH7110_SYSCLK_APB_BUS),
> + STARFIVE__DIV(JH7110_SYSCLK_PLL0_DIV2, "pll0_div2", 2, JH7110_SYSCLK_PLL0_OUT),
> + STARFIVE__DIV(JH7110_SYSCLK_PLL1_DIV2, "pll1_div2", 2, JH7110_SYSCLK_PLL1_OUT),
> + STARFIVE__DIV(JH7110_SYSCLK_PLL2_DIV2, "pll2_div2", 2, JH7110_SYSCLK_PLL2_OUT),
> + STARFIVE__DIV(JH7110_SYSCLK_AUDIO_ROOT, "audio_root", 8, JH7110_SYSCLK_PLL2_OUT),
> + STARFIVE__DIV(JH7110_SYSCLK_MCLK_INNER, "mclk_inner", 64, JH7110_SYSCLK_AUDIO_ROOT),
> + STARFIVE__MUX(JH7110_SYSCLK_MCLK, "mclk", 2,
> + JH7110_SYSCLK_MCLK_INNER,
> + JH7110_SYSCLK_MCLK_EXT),
> + STARFIVE_GATE(JH7110_SYSCLK_MCLK_OUT, "mclk_out", 0, JH7110_SYSCLK_MCLK_INNER),
> + STARFIVE_MDIV(JH7110_SYSCLK_ISP_2X, "isp_2x", 8, 2,
> + JH7110_SYSCLK_PLL2_OUT,
> + JH7110_SYSCLK_PLL1_OUT),
> + STARFIVE__DIV(JH7110_SYSCLK_ISP_AXI, "isp_axi", 4, JH7110_SYSCLK_ISP_2X),
> + STARFIVE_GDIV(JH7110_SYSCLK_GCLK0, "gclk0", 0, 62, JH7110_SYSCLK_PLL0_DIV2),
> + STARFIVE_GDIV(JH7110_SYSCLK_GCLK1, "gclk1", 0, 62, JH7110_SYSCLK_PLL1_DIV2),
> + STARFIVE_GDIV(JH7110_SYSCLK_GCLK2, "gclk2", 0, 62, JH7110_SYSCLK_PLL2_DIV2),
> /* cores */
> - JH71X0_GATE(JH7110_SYSCLK_CORE, "core", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
> - JH71X0_GATE(JH7110_SYSCLK_CORE1, "core1", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
> - JH71X0_GATE(JH7110_SYSCLK_CORE2, "core2", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
> - JH71X0_GATE(JH7110_SYSCLK_CORE3, "core3", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
> - JH71X0_GATE(JH7110_SYSCLK_CORE4, "core4", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
> - JH71X0_GATE(JH7110_SYSCLK_DEBUG, "debug", 0, JH7110_SYSCLK_CPU_BUS),
> - JH71X0__DIV(JH7110_SYSCLK_RTC_TOGGLE, "rtc_toggle", 6, JH7110_SYSCLK_OSC),
> - JH71X0_GATE(JH7110_SYSCLK_TRACE0, "trace0", 0, JH7110_SYSCLK_CPU_CORE),
> - JH71X0_GATE(JH7110_SYSCLK_TRACE1, "trace1", 0, JH7110_SYSCLK_CPU_CORE),
> - JH71X0_GATE(JH7110_SYSCLK_TRACE2, "trace2", 0, JH7110_SYSCLK_CPU_CORE),
> - JH71X0_GATE(JH7110_SYSCLK_TRACE3, "trace3", 0, JH7110_SYSCLK_CPU_CORE),
> - JH71X0_GATE(JH7110_SYSCLK_TRACE4, "trace4", 0, JH7110_SYSCLK_CPU_CORE),
> - JH71X0_GATE(JH7110_SYSCLK_TRACE_COM, "trace_com", 0, JH7110_SYSCLK_CPU_BUS),
> + STARFIVE_GATE(JH7110_SYSCLK_CORE, "core", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
> + STARFIVE_GATE(JH7110_SYSCLK_CORE1, "core1", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
> + STARFIVE_GATE(JH7110_SYSCLK_CORE2, "core2", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
> + STARFIVE_GATE(JH7110_SYSCLK_CORE3, "core3", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
> + STARFIVE_GATE(JH7110_SYSCLK_CORE4, "core4", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
> + STARFIVE_GATE(JH7110_SYSCLK_DEBUG, "debug", 0, JH7110_SYSCLK_CPU_BUS),
> + STARFIVE__DIV(JH7110_SYSCLK_RTC_TOGGLE, "rtc_toggle", 6, JH7110_SYSCLK_OSC),
> + STARFIVE_GATE(JH7110_SYSCLK_TRACE0, "trace0", 0, JH7110_SYSCLK_CPU_CORE),
> + STARFIVE_GATE(JH7110_SYSCLK_TRACE1, "trace1", 0, JH7110_SYSCLK_CPU_CORE),
> + STARFIVE_GATE(JH7110_SYSCLK_TRACE2, "trace2", 0, JH7110_SYSCLK_CPU_CORE),
> + STARFIVE_GATE(JH7110_SYSCLK_TRACE3, "trace3", 0, JH7110_SYSCLK_CPU_CORE),
> + STARFIVE_GATE(JH7110_SYSCLK_TRACE4, "trace4", 0, JH7110_SYSCLK_CPU_CORE),
> + STARFIVE_GATE(JH7110_SYSCLK_TRACE_COM, "trace_com", 0, JH7110_SYSCLK_CPU_BUS),
> /* noc */
> - JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_CPU_AXI, "noc_bus_cpu_axi", CLK_IS_CRITICAL,
> - JH7110_SYSCLK_CPU_BUS),
> - JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI, "noc_bus_axicfg0_axi", CLK_IS_CRITICAL,
> - JH7110_SYSCLK_AXI_CFG0),
> + STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_CPU_AXI, "noc_bus_cpu_axi", CLK_IS_CRITICAL,
> + JH7110_SYSCLK_CPU_BUS),
> + STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI, "noc_bus_axicfg0_axi", CLK_IS_CRITICAL,
> + JH7110_SYSCLK_AXI_CFG0),
> /* ddr */
> - JH71X0__DIV(JH7110_SYSCLK_OSC_DIV2, "osc_div2", 2, JH7110_SYSCLK_OSC),
> - JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV4, "pll1_div4", 2, JH7110_SYSCLK_PLL1_DIV2),
> - JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV8, "pll1_div8", 2, JH7110_SYSCLK_PLL1_DIV4),
> - JH71X0__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 4,
> - JH7110_SYSCLK_OSC_DIV2,
> - JH7110_SYSCLK_PLL1_DIV2,
> - JH7110_SYSCLK_PLL1_DIV4,
> - JH7110_SYSCLK_PLL1_DIV8),
> - JH71X0_GATE(JH7110_SYSCLK_DDR_AXI, "ddr_axi", CLK_IS_CRITICAL, JH7110_SYSCLK_DDR_BUS),
> + STARFIVE__DIV(JH7110_SYSCLK_OSC_DIV2, "osc_div2", 2, JH7110_SYSCLK_OSC),
> + STARFIVE__DIV(JH7110_SYSCLK_PLL1_DIV4, "pll1_div4", 2, JH7110_SYSCLK_PLL1_DIV2),
> + STARFIVE__DIV(JH7110_SYSCLK_PLL1_DIV8, "pll1_div8", 2, JH7110_SYSCLK_PLL1_DIV4),
> + STARFIVE__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 4,
> + JH7110_SYSCLK_OSC_DIV2,
> + JH7110_SYSCLK_PLL1_DIV2,
> + JH7110_SYSCLK_PLL1_DIV4,
> + JH7110_SYSCLK_PLL1_DIV8),
> + STARFIVE_GATE(JH7110_SYSCLK_DDR_AXI, "ddr_axi", CLK_IS_CRITICAL, JH7110_SYSCLK_DDR_BUS),
> /* gpu */
> - JH71X0__DIV(JH7110_SYSCLK_GPU_CORE, "gpu_core", 7, JH7110_SYSCLK_GPU_ROOT),
> - JH71X0_GATE(JH7110_SYSCLK_GPU_CORE_CLK, "gpu_core_clk", 0, JH7110_SYSCLK_GPU_CORE),
> - JH71X0_GATE(JH7110_SYSCLK_GPU_SYS_CLK, "gpu_sys_clk", 0, JH7110_SYSCLK_ISP_AXI),
> - JH71X0_GATE(JH7110_SYSCLK_GPU_APB, "gpu_apb", 0, JH7110_SYSCLK_APB_BUS),
> - JH71X0_GDIV(JH7110_SYSCLK_GPU_RTC_TOGGLE, "gpu_rtc_toggle", 0, 12, JH7110_SYSCLK_OSC),
> - JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_GPU_AXI, "noc_bus_gpu_axi", 0, JH7110_SYSCLK_GPU_CORE),
> + STARFIVE__DIV(JH7110_SYSCLK_GPU_CORE, "gpu_core", 7, JH7110_SYSCLK_GPU_ROOT),
> + STARFIVE_GATE(JH7110_SYSCLK_GPU_CORE_CLK, "gpu_core_clk", 0, JH7110_SYSCLK_GPU_CORE),
> + STARFIVE_GATE(JH7110_SYSCLK_GPU_SYS_CLK, "gpu_sys_clk", 0, JH7110_SYSCLK_ISP_AXI),
> + STARFIVE_GATE(JH7110_SYSCLK_GPU_APB, "gpu_apb", 0, JH7110_SYSCLK_APB_BUS),
> + STARFIVE_GDIV(JH7110_SYSCLK_GPU_RTC_TOGGLE, "gpu_rtc_toggle", 0, 12, JH7110_SYSCLK_OSC),
> + STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_GPU_AXI, "noc_bus_gpu_axi", 0, JH7110_SYSCLK_GPU_CORE),
> /* isp */
> - JH71X0_GATE(JH7110_SYSCLK_ISP_TOP_CORE, "isp_top_core", 0, JH7110_SYSCLK_ISP_2X),
> - JH71X0_GATE(JH7110_SYSCLK_ISP_TOP_AXI, "isp_top_axi", 0, JH7110_SYSCLK_ISP_AXI),
> - JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_ISP_AXI, "noc_bus_isp_axi", CLK_IS_CRITICAL,
> - JH7110_SYSCLK_ISP_AXI),
> + STARFIVE_GATE(JH7110_SYSCLK_ISP_TOP_CORE, "isp_top_core", 0, JH7110_SYSCLK_ISP_2X),
> + STARFIVE_GATE(JH7110_SYSCLK_ISP_TOP_AXI, "isp_top_axi", 0, JH7110_SYSCLK_ISP_AXI),
> + STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_ISP_AXI, "noc_bus_isp_axi", CLK_IS_CRITICAL,
> + JH7110_SYSCLK_ISP_AXI),
> /* hifi4 */
> - JH71X0__DIV(JH7110_SYSCLK_HIFI4_CORE, "hifi4_core", 15, JH7110_SYSCLK_BUS_ROOT),
> - JH71X0__DIV(JH7110_SYSCLK_HIFI4_AXI, "hifi4_axi", 2, JH7110_SYSCLK_HIFI4_CORE),
> + STARFIVE__DIV(JH7110_SYSCLK_HIFI4_CORE, "hifi4_core", 15, JH7110_SYSCLK_BUS_ROOT),
> + STARFIVE__DIV(JH7110_SYSCLK_HIFI4_AXI, "hifi4_axi", 2, JH7110_SYSCLK_HIFI4_CORE),
> /* axi_cfg1 */
> - JH71X0_GATE(JH7110_SYSCLK_AXI_CFG1_MAIN, "axi_cfg1_main", CLK_IS_CRITICAL,
> - JH7110_SYSCLK_ISP_AXI),
> - JH71X0_GATE(JH7110_SYSCLK_AXI_CFG1_AHB, "axi_cfg1_ahb", CLK_IS_CRITICAL,
> - JH7110_SYSCLK_AHB0),
> + STARFIVE_GATE(JH7110_SYSCLK_AXI_CFG1_MAIN, "axi_cfg1_main", CLK_IS_CRITICAL,
> + JH7110_SYSCLK_ISP_AXI),
> + STARFIVE_GATE(JH7110_SYSCLK_AXI_CFG1_AHB, "axi_cfg1_ahb", CLK_IS_CRITICAL,
> + JH7110_SYSCLK_AHB0),
> /* vout */
> - JH71X0_GATE(JH7110_SYSCLK_VOUT_SRC, "vout_src", 0, JH7110_SYSCLK_PLL2_OUT),
> - JH71X0__DIV(JH7110_SYSCLK_VOUT_AXI, "vout_axi", 7, JH7110_SYSCLK_PLL2_OUT),
> - JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_DISP_AXI, "noc_bus_disp_axi", 0, JH7110_SYSCLK_VOUT_AXI),
> - JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_AHB, "vout_top_ahb", 0, JH7110_SYSCLK_AHB1),
> - JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_AXI, "vout_top_axi", 0, JH7110_SYSCLK_VOUT_AXI),
> - JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK, "vout_top_hdmitx0_mclk", 0,
> - JH7110_SYSCLK_MCLK),
> - JH71X0__DIV(JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF, "vout_top_mipiphy_ref", 2,
> - JH7110_SYSCLK_OSC),
> + STARFIVE_GATE(JH7110_SYSCLK_VOUT_SRC, "vout_src", 0, JH7110_SYSCLK_PLL2_OUT),
> + STARFIVE__DIV(JH7110_SYSCLK_VOUT_AXI, "vout_axi", 7, JH7110_SYSCLK_PLL2_OUT),
> + STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_DISP_AXI, "noc_bus_disp_axi", 0,
> + JH7110_SYSCLK_VOUT_AXI),
> + STARFIVE_GATE(JH7110_SYSCLK_VOUT_TOP_AHB, "vout_top_ahb", 0, JH7110_SYSCLK_AHB1),
> + STARFIVE_GATE(JH7110_SYSCLK_VOUT_TOP_AXI, "vout_top_axi", 0, JH7110_SYSCLK_VOUT_AXI),
> + STARFIVE_GATE(JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK, "vout_top_hdmitx0_mclk", 0,
> + JH7110_SYSCLK_MCLK),
> + STARFIVE__DIV(JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF, "vout_top_mipiphy_ref", 2,
> + JH7110_SYSCLK_OSC),
> /* jpegc */
> - JH71X0__DIV(JH7110_SYSCLK_JPEGC_AXI, "jpegc_axi", 16, JH7110_SYSCLK_PLL2_OUT),
> - JH71X0_GATE(JH7110_SYSCLK_CODAJ12_AXI, "codaj12_axi", 0, JH7110_SYSCLK_JPEGC_AXI),
> - JH71X0_GDIV(JH7110_SYSCLK_CODAJ12_CORE, "codaj12_core", 0, 16, JH7110_SYSCLK_PLL2_OUT),
> - JH71X0_GATE(JH7110_SYSCLK_CODAJ12_APB, "codaj12_apb", 0, JH7110_SYSCLK_APB_BUS),
> + STARFIVE__DIV(JH7110_SYSCLK_JPEGC_AXI, "jpegc_axi", 16, JH7110_SYSCLK_PLL2_OUT),
> + STARFIVE_GATE(JH7110_SYSCLK_CODAJ12_AXI, "codaj12_axi", 0, JH7110_SYSCLK_JPEGC_AXI),
> + STARFIVE_GDIV(JH7110_SYSCLK_CODAJ12_CORE, "codaj12_core", 0, 16, JH7110_SYSCLK_PLL2_OUT),
> + STARFIVE_GATE(JH7110_SYSCLK_CODAJ12_APB, "codaj12_apb", 0, JH7110_SYSCLK_APB_BUS),
> /* vdec */
> - JH71X0__DIV(JH7110_SYSCLK_VDEC_AXI, "vdec_axi", 7, JH7110_SYSCLK_BUS_ROOT),
> - JH71X0_GATE(JH7110_SYSCLK_WAVE511_AXI, "wave511_axi", 0, JH7110_SYSCLK_VDEC_AXI),
> - JH71X0_GDIV(JH7110_SYSCLK_WAVE511_BPU, "wave511_bpu", 0, 7, JH7110_SYSCLK_BUS_ROOT),
> - JH71X0_GDIV(JH7110_SYSCLK_WAVE511_VCE, "wave511_vce", 0, 7, JH7110_SYSCLK_PLL0_OUT),
> - JH71X0_GATE(JH7110_SYSCLK_WAVE511_APB, "wave511_apb", 0, JH7110_SYSCLK_APB_BUS),
> - JH71X0_GATE(JH7110_SYSCLK_VDEC_JPG, "vdec_jpg", 0, JH7110_SYSCLK_JPEGC_AXI),
> - JH71X0_GATE(JH7110_SYSCLK_VDEC_MAIN, "vdec_main", 0, JH7110_SYSCLK_VDEC_AXI),
> - JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_VDEC_AXI, "noc_bus_vdec_axi", 0, JH7110_SYSCLK_VDEC_AXI),
> + STARFIVE__DIV(JH7110_SYSCLK_VDEC_AXI, "vdec_axi", 7, JH7110_SYSCLK_BUS_ROOT),
> + STARFIVE_GATE(JH7110_SYSCLK_WAVE511_AXI, "wave511_axi", 0, JH7110_SYSCLK_VDEC_AXI),
> + STARFIVE_GDIV(JH7110_SYSCLK_WAVE511_BPU, "wave511_bpu", 0, 7, JH7110_SYSCLK_BUS_ROOT),
> + STARFIVE_GDIV(JH7110_SYSCLK_WAVE511_VCE, "wave511_vce", 0, 7, JH7110_SYSCLK_PLL0_OUT),
> + STARFIVE_GATE(JH7110_SYSCLK_WAVE511_APB, "wave511_apb", 0, JH7110_SYSCLK_APB_BUS),
> + STARFIVE_GATE(JH7110_SYSCLK_VDEC_JPG, "vdec_jpg", 0, JH7110_SYSCLK_JPEGC_AXI),
> + STARFIVE_GATE(JH7110_SYSCLK_VDEC_MAIN, "vdec_main", 0, JH7110_SYSCLK_VDEC_AXI),
> + STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_VDEC_AXI, "noc_bus_vdec_axi", 0,
> + JH7110_SYSCLK_VDEC_AXI),
> /* venc */
> - JH71X0__DIV(JH7110_SYSCLK_VENC_AXI, "venc_axi", 15, JH7110_SYSCLK_PLL2_OUT),
> - JH71X0_GATE(JH7110_SYSCLK_WAVE420L_AXI, "wave420l_axi", 0, JH7110_SYSCLK_VENC_AXI),
> - JH71X0_GDIV(JH7110_SYSCLK_WAVE420L_BPU, "wave420l_bpu", 0, 15, JH7110_SYSCLK_PLL2_OUT),
> - JH71X0_GDIV(JH7110_SYSCLK_WAVE420L_VCE, "wave420l_vce", 0, 15, JH7110_SYSCLK_PLL2_OUT),
> - JH71X0_GATE(JH7110_SYSCLK_WAVE420L_APB, "wave420l_apb", 0, JH7110_SYSCLK_APB_BUS),
> - JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_VENC_AXI, "noc_bus_venc_axi", 0, JH7110_SYSCLK_VENC_AXI),
> + STARFIVE__DIV(JH7110_SYSCLK_VENC_AXI, "venc_axi", 15, JH7110_SYSCLK_PLL2_OUT),
> + STARFIVE_GATE(JH7110_SYSCLK_WAVE420L_AXI, "wave420l_axi", 0, JH7110_SYSCLK_VENC_AXI),
> + STARFIVE_GDIV(JH7110_SYSCLK_WAVE420L_BPU, "wave420l_bpu", 0, 15, JH7110_SYSCLK_PLL2_OUT),
> + STARFIVE_GDIV(JH7110_SYSCLK_WAVE420L_VCE, "wave420l_vce", 0, 15, JH7110_SYSCLK_PLL2_OUT),
> + STARFIVE_GATE(JH7110_SYSCLK_WAVE420L_APB, "wave420l_apb", 0, JH7110_SYSCLK_APB_BUS),
> + STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_VENC_AXI, "noc_bus_venc_axi", 0,
> + JH7110_SYSCLK_VENC_AXI),
> /* axi_cfg0 */
> - JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN_DIV, "axi_cfg0_main_div", CLK_IS_CRITICAL,
> - JH7110_SYSCLK_AHB1),
> - JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN, "axi_cfg0_main", CLK_IS_CRITICAL,
> - JH7110_SYSCLK_AXI_CFG0),
> - JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_HIFI4, "axi_cfg0_hifi4", CLK_IS_CRITICAL,
> - JH7110_SYSCLK_HIFI4_AXI),
> + STARFIVE_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN_DIV, "axi_cfg0_main_div", CLK_IS_CRITICAL,
> + JH7110_SYSCLK_AHB1),
> + STARFIVE_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN, "axi_cfg0_main", CLK_IS_CRITICAL,
> + JH7110_SYSCLK_AXI_CFG0),
> + STARFIVE_GATE(JH7110_SYSCLK_AXI_CFG0_HIFI4, "axi_cfg0_hifi4", CLK_IS_CRITICAL,
> + JH7110_SYSCLK_HIFI4_AXI),
> /* intmem */
> - JH71X0_GATE(JH7110_SYSCLK_AXIMEM2_AXI, "aximem2_axi", 0, JH7110_SYSCLK_AXI_CFG0),
> + STARFIVE_GATE(JH7110_SYSCLK_AXIMEM2_AXI, "aximem2_axi", 0, JH7110_SYSCLK_AXI_CFG0),
> /* qspi */
> - JH71X0_GATE(JH7110_SYSCLK_QSPI_AHB, "qspi_ahb", 0, JH7110_SYSCLK_AHB1),
> - JH71X0_GATE(JH7110_SYSCLK_QSPI_APB, "qspi_apb", 0, JH7110_SYSCLK_APB_BUS),
> - JH71X0__DIV(JH7110_SYSCLK_QSPI_REF_SRC, "qspi_ref_src", 16, JH7110_SYSCLK_PLL0_OUT),
> - JH71X0_GMUX(JH7110_SYSCLK_QSPI_REF, "qspi_ref", 0, 2,
> - JH7110_SYSCLK_OSC,
> - JH7110_SYSCLK_QSPI_REF_SRC),
> + STARFIVE_GATE(JH7110_SYSCLK_QSPI_AHB, "qspi_ahb", 0, JH7110_SYSCLK_AHB1),
> + STARFIVE_GATE(JH7110_SYSCLK_QSPI_APB, "qspi_apb", 0, JH7110_SYSCLK_APB_BUS),
> + STARFIVE__DIV(JH7110_SYSCLK_QSPI_REF_SRC, "qspi_ref_src", 16, JH7110_SYSCLK_PLL0_OUT),
> + STARFIVE_GMUX(JH7110_SYSCLK_QSPI_REF, "qspi_ref", 0, 2,
> + JH7110_SYSCLK_OSC,
> + JH7110_SYSCLK_QSPI_REF_SRC),
> /* sdio */
> - JH71X0_GATE(JH7110_SYSCLK_SDIO0_AHB, "sdio0_ahb", 0, JH7110_SYSCLK_AHB0),
> - JH71X0_GATE(JH7110_SYSCLK_SDIO1_AHB, "sdio1_ahb", 0, JH7110_SYSCLK_AHB0),
> - JH71X0_GDIV(JH7110_SYSCLK_SDIO0_SDCARD, "sdio0_sdcard", 0, 15, JH7110_SYSCLK_AXI_CFG0),
> - JH71X0_GDIV(JH7110_SYSCLK_SDIO1_SDCARD, "sdio1_sdcard", 0, 15, JH7110_SYSCLK_AXI_CFG0),
> + STARFIVE_GATE(JH7110_SYSCLK_SDIO0_AHB, "sdio0_ahb", 0, JH7110_SYSCLK_AHB0),
> + STARFIVE_GATE(JH7110_SYSCLK_SDIO1_AHB, "sdio1_ahb", 0, JH7110_SYSCLK_AHB0),
> + STARFIVE_GDIV(JH7110_SYSCLK_SDIO0_SDCARD, "sdio0_sdcard", 0, 15, JH7110_SYSCLK_AXI_CFG0),
> + STARFIVE_GDIV(JH7110_SYSCLK_SDIO1_SDCARD, "sdio1_sdcard", 0, 15, JH7110_SYSCLK_AXI_CFG0),
> /* stg */
> - JH71X0__DIV(JH7110_SYSCLK_USB_125M, "usb_125m", 15, JH7110_SYSCLK_PLL0_OUT),
> - JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_STG_AXI, "noc_bus_stg_axi", CLK_IS_CRITICAL,
> - JH7110_SYSCLK_NOCSTG_BUS),
> + STARFIVE__DIV(JH7110_SYSCLK_USB_125M, "usb_125m", 15, JH7110_SYSCLK_PLL0_OUT),
> + STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_STG_AXI, "noc_bus_stg_axi", CLK_IS_CRITICAL,
> + JH7110_SYSCLK_NOCSTG_BUS),
> /* gmac1 */
> - JH71X0_GATE(JH7110_SYSCLK_GMAC1_AHB, "gmac1_ahb", 0, JH7110_SYSCLK_AHB0),
> - JH71X0_GATE(JH7110_SYSCLK_GMAC1_AXI, "gmac1_axi", 0, JH7110_SYSCLK_STG_AXIAHB),
> - JH71X0__DIV(JH7110_SYSCLK_GMAC_SRC, "gmac_src", 7, JH7110_SYSCLK_PLL0_OUT),
> - JH71X0__DIV(JH7110_SYSCLK_GMAC1_GTXCLK, "gmac1_gtxclk", 15, JH7110_SYSCLK_PLL0_OUT),
> - JH71X0__DIV(JH7110_SYSCLK_GMAC1_RMII_RTX, "gmac1_rmii_rtx", 30,
> - JH7110_SYSCLK_GMAC1_RMII_REFIN),
> - JH71X0_GDIV(JH7110_SYSCLK_GMAC1_PTP, "gmac1_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC),
> - JH71X0__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 2,
> - JH7110_SYSCLK_GMAC1_RGMII_RXIN,
> - JH7110_SYSCLK_GMAC1_RMII_RTX),
> - JH71X0__INV(JH7110_SYSCLK_GMAC1_RX_INV, "gmac1_rx_inv", JH7110_SYSCLK_GMAC1_RX),
> - JH71X0_GMUX(JH7110_SYSCLK_GMAC1_TX, "gmac1_tx",
> - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2,
> - JH7110_SYSCLK_GMAC1_GTXCLK,
> - JH7110_SYSCLK_GMAC1_RMII_RTX),
> - JH71X0__INV(JH7110_SYSCLK_GMAC1_TX_INV, "gmac1_tx_inv", JH7110_SYSCLK_GMAC1_TX),
> - JH71X0_GATE(JH7110_SYSCLK_GMAC1_GTXC, "gmac1_gtxc", 0, JH7110_SYSCLK_GMAC1_GTXCLK),
> + STARFIVE_GATE(JH7110_SYSCLK_GMAC1_AHB, "gmac1_ahb", 0, JH7110_SYSCLK_AHB0),
> + STARFIVE_GATE(JH7110_SYSCLK_GMAC1_AXI, "gmac1_axi", 0, JH7110_SYSCLK_STG_AXIAHB),
> + STARFIVE__DIV(JH7110_SYSCLK_GMAC_SRC, "gmac_src", 7, JH7110_SYSCLK_PLL0_OUT),
> + STARFIVE__DIV(JH7110_SYSCLK_GMAC1_GTXCLK, "gmac1_gtxclk", 15, JH7110_SYSCLK_PLL0_OUT),
> + STARFIVE__DIV(JH7110_SYSCLK_GMAC1_RMII_RTX, "gmac1_rmii_rtx", 30,
> + JH7110_SYSCLK_GMAC1_RMII_REFIN),
> + STARFIVE_GDIV(JH7110_SYSCLK_GMAC1_PTP, "gmac1_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC),
> + STARFIVE__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 2,
> + JH7110_SYSCLK_GMAC1_RGMII_RXIN,
> + JH7110_SYSCLK_GMAC1_RMII_RTX),
> + STARFIVE__INV(JH7110_SYSCLK_GMAC1_RX_INV, "gmac1_rx_inv", JH7110_SYSCLK_GMAC1_RX),
> + STARFIVE_GMUX(JH7110_SYSCLK_GMAC1_TX, "gmac1_tx",
> + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2,
> + JH7110_SYSCLK_GMAC1_GTXCLK,
> + JH7110_SYSCLK_GMAC1_RMII_RTX),
> + STARFIVE__INV(JH7110_SYSCLK_GMAC1_TX_INV, "gmac1_tx_inv", JH7110_SYSCLK_GMAC1_TX),
> + STARFIVE_GATE(JH7110_SYSCLK_GMAC1_GTXC, "gmac1_gtxc", 0, JH7110_SYSCLK_GMAC1_GTXCLK),
> /* gmac0 */
> - JH71X0_GDIV(JH7110_SYSCLK_GMAC0_GTXCLK, "gmac0_gtxclk", 0, 15, JH7110_SYSCLK_PLL0_OUT),
> - JH71X0_GDIV(JH7110_SYSCLK_GMAC0_PTP, "gmac0_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC),
> - JH71X0_GDIV(JH7110_SYSCLK_GMAC_PHY, "gmac_phy", 0, 31, JH7110_SYSCLK_GMAC_SRC),
> - JH71X0_GATE(JH7110_SYSCLK_GMAC0_GTXC, "gmac0_gtxc", 0, JH7110_SYSCLK_GMAC0_GTXCLK),
> + STARFIVE_GDIV(JH7110_SYSCLK_GMAC0_GTXCLK, "gmac0_gtxclk", 0, 15, JH7110_SYSCLK_PLL0_OUT),
> + STARFIVE_GDIV(JH7110_SYSCLK_GMAC0_PTP, "gmac0_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC),
> + STARFIVE_GDIV(JH7110_SYSCLK_GMAC_PHY, "gmac_phy", 0, 31, JH7110_SYSCLK_GMAC_SRC),
> + STARFIVE_GATE(JH7110_SYSCLK_GMAC0_GTXC, "gmac0_gtxc", 0, JH7110_SYSCLK_GMAC0_GTXCLK),
> /* apb misc */
> - JH71X0_GATE(JH7110_SYSCLK_IOMUX_APB, "iomux_apb", 0, JH7110_SYSCLK_APB_BUS),
> - JH71X0_GATE(JH7110_SYSCLK_MAILBOX_APB, "mailbox_apb", 0, JH7110_SYSCLK_APB_BUS),
> - JH71X0_GATE(JH7110_SYSCLK_INT_CTRL_APB, "int_ctrl_apb", 0, JH7110_SYSCLK_APB_BUS),
> + STARFIVE_GATE(JH7110_SYSCLK_IOMUX_APB, "iomux_apb", 0, JH7110_SYSCLK_APB_BUS),
> + STARFIVE_GATE(JH7110_SYSCLK_MAILBOX_APB, "mailbox_apb", 0, JH7110_SYSCLK_APB_BUS),
> + STARFIVE_GATE(JH7110_SYSCLK_INT_CTRL_APB, "int_ctrl_apb", 0, JH7110_SYSCLK_APB_BUS),
> /* can0 */
> - JH71X0_GATE(JH7110_SYSCLK_CAN0_APB, "can0_apb", 0, JH7110_SYSCLK_APB_BUS),
> - JH71X0_GDIV(JH7110_SYSCLK_CAN0_TIMER, "can0_timer", 0, 24, JH7110_SYSCLK_OSC),
> - JH71X0_GDIV(JH7110_SYSCLK_CAN0_CAN, "can0_can", 0, 63, JH7110_SYSCLK_PERH_ROOT),
> + STARFIVE_GATE(JH7110_SYSCLK_CAN0_APB, "can0_apb", 0, JH7110_SYSCLK_APB_BUS),
> + STARFIVE_GDIV(JH7110_SYSCLK_CAN0_TIMER, "can0_timer", 0, 24, JH7110_SYSCLK_OSC),
> + STARFIVE_GDIV(JH7110_SYSCLK_CAN0_CAN, "can0_can", 0, 63, JH7110_SYSCLK_PERH_ROOT),
> /* can1 */
> - JH71X0_GATE(JH7110_SYSCLK_CAN1_APB, "can1_apb", 0, JH7110_SYSCLK_APB_BUS),
> - JH71X0_GDIV(JH7110_SYSCLK_CAN1_TIMER, "can1_timer", 0, 24, JH7110_SYSCLK_OSC),
> - JH71X0_GDIV(JH7110_SYSCLK_CAN1_CAN, "can1_can", 0, 63, JH7110_SYSCLK_PERH_ROOT),
> + STARFIVE_GATE(JH7110_SYSCLK_CAN1_APB, "can1_apb", 0, JH7110_SYSCLK_APB_BUS),
> + STARFIVE_GDIV(JH7110_SYSCLK_CAN1_TIMER, "can1_timer", 0, 24, JH7110_SYSCLK_OSC),
> + STARFIVE_GDIV(JH7110_SYSCLK_CAN1_CAN, "can1_can", 0, 63, JH7110_SYSCLK_PERH_ROOT),
> /* pwm */
> - JH71X0_GATE(JH7110_SYSCLK_PWM_APB, "pwm_apb", 0, JH7110_SYSCLK_APB_BUS),
> + STARFIVE_GATE(JH7110_SYSCLK_PWM_APB, "pwm_apb", 0, JH7110_SYSCLK_APB_BUS),
> /* wdt */
> - JH71X0_GATE(JH7110_SYSCLK_WDT_APB, "wdt_apb", 0, JH7110_SYSCLK_APB_BUS),
> - JH71X0_GATE(JH7110_SYSCLK_WDT_CORE, "wdt_core", 0, JH7110_SYSCLK_OSC),
> + STARFIVE_GATE(JH7110_SYSCLK_WDT_APB, "wdt_apb", 0, JH7110_SYSCLK_APB_BUS),
> + STARFIVE_GATE(JH7110_SYSCLK_WDT_CORE, "wdt_core", 0, JH7110_SYSCLK_OSC),
> /* timer */
> - JH71X0_GATE(JH7110_SYSCLK_TIMER_APB, "timer_apb", 0, JH7110_SYSCLK_APB_BUS),
> - JH71X0_GATE(JH7110_SYSCLK_TIMER0, "timer0", 0, JH7110_SYSCLK_OSC),
> - JH71X0_GATE(JH7110_SYSCLK_TIMER1, "timer1", 0, JH7110_SYSCLK_OSC),
> - JH71X0_GATE(JH7110_SYSCLK_TIMER2, "timer2", 0, JH7110_SYSCLK_OSC),
> - JH71X0_GATE(JH7110_SYSCLK_TIMER3, "timer3", 0, JH7110_SYSCLK_OSC),
> + STARFIVE_GATE(JH7110_SYSCLK_TIMER_APB, "timer_apb", 0, JH7110_SYSCLK_APB_BUS),
> + STARFIVE_GATE(JH7110_SYSCLK_TIMER0, "timer0", 0, JH7110_SYSCLK_OSC),
> + STARFIVE_GATE(JH7110_SYSCLK_TIMER1, "timer1", 0, JH7110_SYSCLK_OSC),
> + STARFIVE_GATE(JH7110_SYSCLK_TIMER2, "timer2", 0, JH7110_SYSCLK_OSC),
> + STARFIVE_GATE(JH7110_SYSCLK_TIMER3, "timer3", 0, JH7110_SYSCLK_OSC),
> /* temp sensor */
> - JH71X0_GATE(JH7110_SYSCLK_TEMP_APB, "temp_apb", 0, JH7110_SYSCLK_APB_BUS),
> - JH71X0_GDIV(JH7110_SYSCLK_TEMP_CORE, "temp_core", 0, 24, JH7110_SYSCLK_OSC),
> + STARFIVE_GATE(JH7110_SYSCLK_TEMP_APB, "temp_apb", 0, JH7110_SYSCLK_APB_BUS),
> + STARFIVE_GDIV(JH7110_SYSCLK_TEMP_CORE, "temp_core", 0, 24, JH7110_SYSCLK_OSC),
> /* spi */
> - JH71X0_GATE(JH7110_SYSCLK_SPI0_APB, "spi0_apb", 0, JH7110_SYSCLK_APB0),
> - JH71X0_GATE(JH7110_SYSCLK_SPI1_APB, "spi1_apb", 0, JH7110_SYSCLK_APB0),
> - JH71X0_GATE(JH7110_SYSCLK_SPI2_APB, "spi2_apb", 0, JH7110_SYSCLK_APB0),
> - JH71X0_GATE(JH7110_SYSCLK_SPI3_APB, "spi3_apb", 0, JH7110_SYSCLK_APB_BUS),
> - JH71X0_GATE(JH7110_SYSCLK_SPI4_APB, "spi4_apb", 0, JH7110_SYSCLK_APB_BUS),
> - JH71X0_GATE(JH7110_SYSCLK_SPI5_APB, "spi5_apb", 0, JH7110_SYSCLK_APB_BUS),
> - JH71X0_GATE(JH7110_SYSCLK_SPI6_APB, "spi6_apb", 0, JH7110_SYSCLK_APB_BUS),
> + STARFIVE_GATE(JH7110_SYSCLK_SPI0_APB, "spi0_apb", 0, JH7110_SYSCLK_APB0),
> + STARFIVE_GATE(JH7110_SYSCLK_SPI1_APB, "spi1_apb", 0, JH7110_SYSCLK_APB0),
> + STARFIVE_GATE(JH7110_SYSCLK_SPI2_APB, "spi2_apb", 0, JH7110_SYSCLK_APB0),
> + STARFIVE_GATE(JH7110_SYSCLK_SPI3_APB, "spi3_apb", 0, JH7110_SYSCLK_APB_BUS),
> + STARFIVE_GATE(JH7110_SYSCLK_SPI4_APB, "spi4_apb", 0, JH7110_SYSCLK_APB_BUS),
> + STARFIVE_GATE(JH7110_SYSCLK_SPI5_APB, "spi5_apb", 0, JH7110_SYSCLK_APB_BUS),
> + STARFIVE_GATE(JH7110_SYSCLK_SPI6_APB, "spi6_apb", 0, JH7110_SYSCLK_APB_BUS),
> /* i2c */
> - JH71X0_GATE(JH7110_SYSCLK_I2C0_APB, "i2c0_apb", 0, JH7110_SYSCLK_APB0),
> - JH71X0_GATE(JH7110_SYSCLK_I2C1_APB, "i2c1_apb", 0, JH7110_SYSCLK_APB0),
> - JH71X0_GATE(JH7110_SYSCLK_I2C2_APB, "i2c2_apb", 0, JH7110_SYSCLK_APB0),
> - JH71X0_GATE(JH7110_SYSCLK_I2C3_APB, "i2c3_apb", 0, JH7110_SYSCLK_APB_BUS),
> - JH71X0_GATE(JH7110_SYSCLK_I2C4_APB, "i2c4_apb", 0, JH7110_SYSCLK_APB_BUS),
> - JH71X0_GATE(JH7110_SYSCLK_I2C5_APB, "i2c5_apb", 0, JH7110_SYSCLK_APB_BUS),
> - JH71X0_GATE(JH7110_SYSCLK_I2C6_APB, "i2c6_apb", 0, JH7110_SYSCLK_APB_BUS),
> + STARFIVE_GATE(JH7110_SYSCLK_I2C0_APB, "i2c0_apb", 0, JH7110_SYSCLK_APB0),
> + STARFIVE_GATE(JH7110_SYSCLK_I2C1_APB, "i2c1_apb", 0, JH7110_SYSCLK_APB0),
> + STARFIVE_GATE(JH7110_SYSCLK_I2C2_APB, "i2c2_apb", 0, JH7110_SYSCLK_APB0),
> + STARFIVE_GATE(JH7110_SYSCLK_I2C3_APB, "i2c3_apb", 0, JH7110_SYSCLK_APB_BUS),
> + STARFIVE_GATE(JH7110_SYSCLK_I2C4_APB, "i2c4_apb", 0, JH7110_SYSCLK_APB_BUS),
> + STARFIVE_GATE(JH7110_SYSCLK_I2C5_APB, "i2c5_apb", 0, JH7110_SYSCLK_APB_BUS),
> + STARFIVE_GATE(JH7110_SYSCLK_I2C6_APB, "i2c6_apb", 0, JH7110_SYSCLK_APB_BUS),
> /* uart */
> - JH71X0_GATE(JH7110_SYSCLK_UART0_APB, "uart0_apb", 0, JH7110_SYSCLK_APB0),
> - JH71X0_GATE(JH7110_SYSCLK_UART0_CORE, "uart0_core", 0, JH7110_SYSCLK_OSC),
> - JH71X0_GATE(JH7110_SYSCLK_UART1_APB, "uart1_apb", 0, JH7110_SYSCLK_APB0),
> - JH71X0_GATE(JH7110_SYSCLK_UART1_CORE, "uart1_core", 0, JH7110_SYSCLK_OSC),
> - JH71X0_GATE(JH7110_SYSCLK_UART2_APB, "uart2_apb", 0, JH7110_SYSCLK_APB0),
> - JH71X0_GATE(JH7110_SYSCLK_UART2_CORE, "uart2_core", 0, JH7110_SYSCLK_OSC),
> - JH71X0_GATE(JH7110_SYSCLK_UART3_APB, "uart3_apb", 0, JH7110_SYSCLK_APB0),
> - JH71X0_GDIV(JH7110_SYSCLK_UART3_CORE, "uart3_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
> - JH71X0_GATE(JH7110_SYSCLK_UART4_APB, "uart4_apb", 0, JH7110_SYSCLK_APB0),
> - JH71X0_GDIV(JH7110_SYSCLK_UART4_CORE, "uart4_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
> - JH71X0_GATE(JH7110_SYSCLK_UART5_APB, "uart5_apb", 0, JH7110_SYSCLK_APB0),
> - JH71X0_GDIV(JH7110_SYSCLK_UART5_CORE, "uart5_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
> + STARFIVE_GATE(JH7110_SYSCLK_UART0_APB, "uart0_apb", 0, JH7110_SYSCLK_APB0),
> + STARFIVE_GATE(JH7110_SYSCLK_UART0_CORE, "uart0_core", 0, JH7110_SYSCLK_OSC),
> + STARFIVE_GATE(JH7110_SYSCLK_UART1_APB, "uart1_apb", 0, JH7110_SYSCLK_APB0),
> + STARFIVE_GATE(JH7110_SYSCLK_UART1_CORE, "uart1_core", 0, JH7110_SYSCLK_OSC),
> + STARFIVE_GATE(JH7110_SYSCLK_UART2_APB, "uart2_apb", 0, JH7110_SYSCLK_APB0),
> + STARFIVE_GATE(JH7110_SYSCLK_UART2_CORE, "uart2_core", 0, JH7110_SYSCLK_OSC),
> + STARFIVE_GATE(JH7110_SYSCLK_UART3_APB, "uart3_apb", 0, JH7110_SYSCLK_APB0),
> + STARFIVE_GDIV(JH7110_SYSCLK_UART3_CORE, "uart3_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
> + STARFIVE_GATE(JH7110_SYSCLK_UART4_APB, "uart4_apb", 0, JH7110_SYSCLK_APB0),
> + STARFIVE_GDIV(JH7110_SYSCLK_UART4_CORE, "uart4_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
> + STARFIVE_GATE(JH7110_SYSCLK_UART5_APB, "uart5_apb", 0, JH7110_SYSCLK_APB0),
> + STARFIVE_GDIV(JH7110_SYSCLK_UART5_CORE, "uart5_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
> /* pwmdac */
> - JH71X0_GATE(JH7110_SYSCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7110_SYSCLK_APB0),
> - JH71X0_GDIV(JH7110_SYSCLK_PWMDAC_CORE, "pwmdac_core", 0, 256, JH7110_SYSCLK_AUDIO_ROOT),
> + STARFIVE_GATE(JH7110_SYSCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7110_SYSCLK_APB0),
> + STARFIVE_GDIV(JH7110_SYSCLK_PWMDAC_CORE, "pwmdac_core", 0, 256, JH7110_SYSCLK_AUDIO_ROOT),
> /* spdif */
> - JH71X0_GATE(JH7110_SYSCLK_SPDIF_APB, "spdif_apb", 0, JH7110_SYSCLK_APB0),
> - JH71X0_GATE(JH7110_SYSCLK_SPDIF_CORE, "spdif_core", 0, JH7110_SYSCLK_MCLK),
> + STARFIVE_GATE(JH7110_SYSCLK_SPDIF_APB, "spdif_apb", 0, JH7110_SYSCLK_APB0),
> + STARFIVE_GATE(JH7110_SYSCLK_SPDIF_CORE, "spdif_core", 0, JH7110_SYSCLK_MCLK),
> /* i2stx0 */
> - JH71X0_GATE(JH7110_SYSCLK_I2STX0_APB, "i2stx0_apb", 0, JH7110_SYSCLK_APB0),
> - JH71X0_GDIV(JH7110_SYSCLK_I2STX0_BCLK_MST, "i2stx0_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
> - JH71X0__INV(JH7110_SYSCLK_I2STX0_BCLK_MST_INV, "i2stx0_bclk_mst_inv",
> - JH7110_SYSCLK_I2STX0_BCLK_MST),
> - JH71X0_MDIV(JH7110_SYSCLK_I2STX0_LRCK_MST, "i2stx0_lrck_mst", 64, 2,
> - JH7110_SYSCLK_I2STX0_BCLK_MST_INV,
> - JH7110_SYSCLK_I2STX0_BCLK_MST),
> - JH71X0__MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk", 2,
> - JH7110_SYSCLK_I2STX0_BCLK_MST,
> - JH7110_SYSCLK_I2STX_BCLK_EXT),
> - JH71X0__INV(JH7110_SYSCLK_I2STX0_BCLK_INV, "i2stx0_bclk_inv", JH7110_SYSCLK_I2STX0_BCLK),
> - JH71X0__MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", 2,
> - JH7110_SYSCLK_I2STX0_LRCK_MST,
> - JH7110_SYSCLK_I2STX_LRCK_EXT),
> + STARFIVE_GATE(JH7110_SYSCLK_I2STX0_APB, "i2stx0_apb", 0, JH7110_SYSCLK_APB0),
> + STARFIVE_GDIV(JH7110_SYSCLK_I2STX0_BCLK_MST, "i2stx0_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
> + STARFIVE__INV(JH7110_SYSCLK_I2STX0_BCLK_MST_INV, "i2stx0_bclk_mst_inv",
> + JH7110_SYSCLK_I2STX0_BCLK_MST),
> + STARFIVE_MDIV(JH7110_SYSCLK_I2STX0_LRCK_MST, "i2stx0_lrck_mst", 64, 2,
> + JH7110_SYSCLK_I2STX0_BCLK_MST_INV,
> + JH7110_SYSCLK_I2STX0_BCLK_MST),
> + STARFIVE__MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk", 2,
> + JH7110_SYSCLK_I2STX0_BCLK_MST,
> + JH7110_SYSCLK_I2STX_BCLK_EXT),
> + STARFIVE__INV(JH7110_SYSCLK_I2STX0_BCLK_INV, "i2stx0_bclk_inv", JH7110_SYSCLK_I2STX0_BCLK),
> + STARFIVE__MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", 2,
> + JH7110_SYSCLK_I2STX0_LRCK_MST,
> + JH7110_SYSCLK_I2STX_LRCK_EXT),
> /* i2stx1 */
> - JH71X0_GATE(JH7110_SYSCLK_I2STX1_APB, "i2stx1_apb", 0, JH7110_SYSCLK_APB0),
> - JH71X0_GDIV(JH7110_SYSCLK_I2STX1_BCLK_MST, "i2stx1_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
> - JH71X0__INV(JH7110_SYSCLK_I2STX1_BCLK_MST_INV, "i2stx1_bclk_mst_inv",
> - JH7110_SYSCLK_I2STX1_BCLK_MST),
> - JH71X0_MDIV(JH7110_SYSCLK_I2STX1_LRCK_MST, "i2stx1_lrck_mst", 64, 2,
> - JH7110_SYSCLK_I2STX1_BCLK_MST_INV,
> - JH7110_SYSCLK_I2STX1_BCLK_MST),
> - JH71X0__MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", 2,
> - JH7110_SYSCLK_I2STX1_BCLK_MST,
> - JH7110_SYSCLK_I2STX_BCLK_EXT),
> - JH71X0__INV(JH7110_SYSCLK_I2STX1_BCLK_INV, "i2stx1_bclk_inv", JH7110_SYSCLK_I2STX1_BCLK),
> - JH71X0__MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", 2,
> - JH7110_SYSCLK_I2STX1_LRCK_MST,
> - JH7110_SYSCLK_I2STX_LRCK_EXT),
> + STARFIVE_GATE(JH7110_SYSCLK_I2STX1_APB, "i2stx1_apb", 0, JH7110_SYSCLK_APB0),
> + STARFIVE_GDIV(JH7110_SYSCLK_I2STX1_BCLK_MST, "i2stx1_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
> + STARFIVE__INV(JH7110_SYSCLK_I2STX1_BCLK_MST_INV, "i2stx1_bclk_mst_inv",
> + JH7110_SYSCLK_I2STX1_BCLK_MST),
> + STARFIVE_MDIV(JH7110_SYSCLK_I2STX1_LRCK_MST, "i2stx1_lrck_mst", 64, 2,
> + JH7110_SYSCLK_I2STX1_BCLK_MST_INV,
> + JH7110_SYSCLK_I2STX1_BCLK_MST),
> + STARFIVE__MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", 2,
> + JH7110_SYSCLK_I2STX1_BCLK_MST,
> + JH7110_SYSCLK_I2STX_BCLK_EXT),
> + STARFIVE__INV(JH7110_SYSCLK_I2STX1_BCLK_INV, "i2stx1_bclk_inv", JH7110_SYSCLK_I2STX1_BCLK),
> + STARFIVE__MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", 2,
> + JH7110_SYSCLK_I2STX1_LRCK_MST,
> + JH7110_SYSCLK_I2STX_LRCK_EXT),
> /* i2srx */
> - JH71X0_GATE(JH7110_SYSCLK_I2SRX_APB, "i2srx_apb", 0, JH7110_SYSCLK_APB0),
> - JH71X0_GDIV(JH7110_SYSCLK_I2SRX_BCLK_MST, "i2srx_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
> - JH71X0__INV(JH7110_SYSCLK_I2SRX_BCLK_MST_INV, "i2srx_bclk_mst_inv",
> - JH7110_SYSCLK_I2SRX_BCLK_MST),
> - JH71X0_MDIV(JH7110_SYSCLK_I2SRX_LRCK_MST, "i2srx_lrck_mst", 64, 2,
> - JH7110_SYSCLK_I2SRX_BCLK_MST_INV,
> - JH7110_SYSCLK_I2SRX_BCLK_MST),
> - JH71X0__MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", 2,
> - JH7110_SYSCLK_I2SRX_BCLK_MST,
> - JH7110_SYSCLK_I2SRX_BCLK_EXT),
> - JH71X0__INV(JH7110_SYSCLK_I2SRX_BCLK_INV, "i2srx_bclk_inv", JH7110_SYSCLK_I2SRX_BCLK),
> - JH71X0__MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", 2,
> - JH7110_SYSCLK_I2SRX_LRCK_MST,
> - JH7110_SYSCLK_I2SRX_LRCK_EXT),
> + STARFIVE_GATE(JH7110_SYSCLK_I2SRX_APB, "i2srx_apb", 0, JH7110_SYSCLK_APB0),
> + STARFIVE_GDIV(JH7110_SYSCLK_I2SRX_BCLK_MST, "i2srx_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
> + STARFIVE__INV(JH7110_SYSCLK_I2SRX_BCLK_MST_INV, "i2srx_bclk_mst_inv",
> + JH7110_SYSCLK_I2SRX_BCLK_MST),
> + STARFIVE_MDIV(JH7110_SYSCLK_I2SRX_LRCK_MST, "i2srx_lrck_mst", 64, 2,
> + JH7110_SYSCLK_I2SRX_BCLK_MST_INV,
> + JH7110_SYSCLK_I2SRX_BCLK_MST),
> + STARFIVE__MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", 2,
> + JH7110_SYSCLK_I2SRX_BCLK_MST,
> + JH7110_SYSCLK_I2SRX_BCLK_EXT),
> + STARFIVE__INV(JH7110_SYSCLK_I2SRX_BCLK_INV, "i2srx_bclk_inv", JH7110_SYSCLK_I2SRX_BCLK),
> + STARFIVE__MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", 2,
> + JH7110_SYSCLK_I2SRX_LRCK_MST,
> + JH7110_SYSCLK_I2SRX_LRCK_EXT),
> /* pdm */
> - JH71X0_GDIV(JH7110_SYSCLK_PDM_DMIC, "pdm_dmic", 0, 64, JH7110_SYSCLK_MCLK),
> - JH71X0_GATE(JH7110_SYSCLK_PDM_APB, "pdm_apb", 0, JH7110_SYSCLK_APB0),
> + STARFIVE_GDIV(JH7110_SYSCLK_PDM_DMIC, "pdm_dmic", 0, 64, JH7110_SYSCLK_MCLK),
> + STARFIVE_GATE(JH7110_SYSCLK_PDM_APB, "pdm_apb", 0, JH7110_SYSCLK_APB0),
> /* tdm */
> - JH71X0_GATE(JH7110_SYSCLK_TDM_AHB, "tdm_ahb", 0, JH7110_SYSCLK_AHB0),
> - JH71X0_GATE(JH7110_SYSCLK_TDM_APB, "tdm_apb", 0, JH7110_SYSCLK_APB0),
> - JH71X0_GDIV(JH7110_SYSCLK_TDM_INTERNAL, "tdm_internal", 0, 64, JH7110_SYSCLK_MCLK),
> - JH71X0__MUX(JH7110_SYSCLK_TDM_TDM, "tdm_tdm", 2,
> - JH7110_SYSCLK_TDM_INTERNAL,
> - JH7110_SYSCLK_TDM_EXT),
> - JH71X0__INV(JH7110_SYSCLK_TDM_TDM_INV, "tdm_tdm_inv", JH7110_SYSCLK_TDM_TDM),
> + STARFIVE_GATE(JH7110_SYSCLK_TDM_AHB, "tdm_ahb", 0, JH7110_SYSCLK_AHB0),
> + STARFIVE_GATE(JH7110_SYSCLK_TDM_APB, "tdm_apb", 0, JH7110_SYSCLK_APB0),
> + STARFIVE_GDIV(JH7110_SYSCLK_TDM_INTERNAL, "tdm_internal", 0, 64, JH7110_SYSCLK_MCLK),
> + STARFIVE__MUX(JH7110_SYSCLK_TDM_TDM, "tdm_tdm", 2,
> + JH7110_SYSCLK_TDM_INTERNAL,
> + JH7110_SYSCLK_TDM_EXT),
> + STARFIVE__INV(JH7110_SYSCLK_TDM_TDM_INV, "tdm_tdm_inv", JH7110_SYSCLK_TDM_TDM),
> /* jtag */
> - JH71X0__DIV(JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG, "jtag_certification_trng", 4,
> - JH7110_SYSCLK_OSC),
> + STARFIVE__DIV(JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG, "jtag_certification_trng", 4,
> + JH7110_SYSCLK_OSC),
> };
>
> static struct clk_hw *jh7110_sysclk_get(struct of_phandle_args *clkspec, void *data)
> {
> - struct jh71x0_clk_priv *priv = data;
> + struct starfive_clk_priv *priv = data;
> unsigned int idx = clkspec->args[0];
>
> if (idx < JH7110_SYSCLK_END)
> @@ -350,7 +353,7 @@ static void jh7110_reset_adev_release(struct device *dev)
> kfree(rdev);
> }
>
> -int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
> +int jh7110_reset_controller_register(struct starfive_clk_priv *priv,
> const char *adev_name,
> u32 adev_id)
> {
> @@ -387,7 +390,7 @@ EXPORT_SYMBOL_GPL(jh7110_reset_controller_register);
>
> static int __init jh7110_syscrg_probe(struct platform_device *pdev)
> {
> - struct jh71x0_clk_priv *priv;
> + struct starfive_clk_priv *priv;
> unsigned int idx;
> int ret;
> struct clk *pllclk;
> @@ -446,13 +449,13 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev)
> struct clk_parent_data parents[4] = {};
> struct clk_init_data init = {
> .name = jh7110_sysclk_data[idx].name,
> - .ops = starfive_jh71x0_clk_ops(max),
> + .ops = starfive_clk_ops(max),
> .parent_data = parents,
> .num_parents =
> - ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
> + ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
> .flags = jh7110_sysclk_data[idx].flags,
> };
> - struct jh71x0_clk *clk = &priv->reg[idx];
> + struct starfive_clk *clk = &priv->reg[idx];
> unsigned int i;
>
> for (i = 0; i < init.num_parents; i++) {
> @@ -490,7 +493,7 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev)
>
> clk->hw.init = &init;
> clk->idx = idx;
> - clk->max_div = max & JH71X0_CLK_DIV_MASK;
> + clk->max_div = max & STARFIVE_CLK_DIV_MASK;
>
> ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
> if (ret)
> diff --git a/drivers/clk/starfive/clk-starfive-jh7110-vout.c b/drivers/clk/starfive/clk-starfive-jh7110-vout.c
> index 10cc1ec43925..aca93c370bce 100644
> --- a/drivers/clk/starfive/clk-starfive-jh7110-vout.c
> +++ b/drivers/clk/starfive/clk-starfive-jh7110-vout.c
> @@ -30,45 +30,45 @@ static struct clk_bulk_data jh7110_vout_top_clks[] = {
> { .id = "vout_top_ahb" }
> };
>
> -static const struct jh71x0_clk_data jh7110_voutclk_data[] = {
> +static const struct starfive_clk_data jh7110_voutclk_data[] = {
> /* divider */
> - JH71X0__DIV(JH7110_VOUTCLK_APB, "apb", 8, JH7110_VOUTCLK_VOUT_TOP_AHB),
> - JH71X0__DIV(JH7110_VOUTCLK_DC8200_PIX, "dc8200_pix", 63, JH7110_VOUTCLK_VOUT_SRC),
> - JH71X0__DIV(JH7110_VOUTCLK_DSI_SYS, "dsi_sys", 31, JH7110_VOUTCLK_VOUT_SRC),
> - JH71X0__DIV(JH7110_VOUTCLK_TX_ESC, "tx_esc", 31, JH7110_VOUTCLK_VOUT_TOP_AHB),
> + STARFIVE__DIV(JH7110_VOUTCLK_APB, "apb", 8, JH7110_VOUTCLK_VOUT_TOP_AHB),
> + STARFIVE__DIV(JH7110_VOUTCLK_DC8200_PIX, "dc8200_pix", 63, JH7110_VOUTCLK_VOUT_SRC),
> + STARFIVE__DIV(JH7110_VOUTCLK_DSI_SYS, "dsi_sys", 31, JH7110_VOUTCLK_VOUT_SRC),
> + STARFIVE__DIV(JH7110_VOUTCLK_TX_ESC, "tx_esc", 31, JH7110_VOUTCLK_VOUT_TOP_AHB),
> /* dc8200 */
> - JH71X0_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
> - JH71X0_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
> - JH71X0_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0, JH7110_VOUTCLK_VOUT_TOP_AHB),
> - JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0, 2,
> - JH7110_VOUTCLK_DC8200_PIX,
> - JH7110_VOUTCLK_HDMITX0_PIXELCLK),
> - JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0, 2,
> - JH7110_VOUTCLK_DC8200_PIX,
> - JH7110_VOUTCLK_HDMITX0_PIXELCLK),
> + STARFIVE_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
> + STARFIVE_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
> + STARFIVE_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0, JH7110_VOUTCLK_VOUT_TOP_AHB),
> + STARFIVE_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0, 2,
> + JH7110_VOUTCLK_DC8200_PIX,
> + JH7110_VOUTCLK_HDMITX0_PIXELCLK),
> + STARFIVE_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0, 2,
> + JH7110_VOUTCLK_DC8200_PIX,
> + JH7110_VOUTCLK_HDMITX0_PIXELCLK),
> /* LCD */
> - JH71X0_GMUX(JH7110_VOUTCLK_DOM_VOUT_TOP_LCD, "dom_vout_top_lcd", 0, 2,
> - JH7110_VOUTCLK_DC8200_PIX0,
> - JH7110_VOUTCLK_DC8200_PIX1),
> + STARFIVE_GMUX(JH7110_VOUTCLK_DOM_VOUT_TOP_LCD, "dom_vout_top_lcd", 0, 2,
> + JH7110_VOUTCLK_DC8200_PIX0,
> + JH7110_VOUTCLK_DC8200_PIX1),
> /* dsiTx */
> - JH71X0_GATE(JH7110_VOUTCLK_DSITX_APB, "dsiTx_apb", 0, JH7110_VOUTCLK_DSI_SYS),
> - JH71X0_GATE(JH7110_VOUTCLK_DSITX_SYS, "dsiTx_sys", 0, JH7110_VOUTCLK_DSI_SYS),
> - JH71X0_GMUX(JH7110_VOUTCLK_DSITX_DPI, "dsiTx_dpi", 0, 2,
> - JH7110_VOUTCLK_DC8200_PIX,
> - JH7110_VOUTCLK_HDMITX0_PIXELCLK),
> - JH71X0_GATE(JH7110_VOUTCLK_DSITX_TXESC, "dsiTx_txesc", 0, JH7110_VOUTCLK_TX_ESC),
> + STARFIVE_GATE(JH7110_VOUTCLK_DSITX_APB, "dsiTx_apb", 0, JH7110_VOUTCLK_DSI_SYS),
> + STARFIVE_GATE(JH7110_VOUTCLK_DSITX_SYS, "dsiTx_sys", 0, JH7110_VOUTCLK_DSI_SYS),
> + STARFIVE_GMUX(JH7110_VOUTCLK_DSITX_DPI, "dsiTx_dpi", 0, 2,
> + JH7110_VOUTCLK_DC8200_PIX,
> + JH7110_VOUTCLK_HDMITX0_PIXELCLK),
> + STARFIVE_GATE(JH7110_VOUTCLK_DSITX_TXESC, "dsiTx_txesc", 0, JH7110_VOUTCLK_TX_ESC),
> /* mipitx DPHY */
> - JH71X0_GATE(JH7110_VOUTCLK_MIPITX_DPHY_TXESC, "mipitx_dphy_txesc", 0,
> - JH7110_VOUTCLK_TX_ESC),
> + STARFIVE_GATE(JH7110_VOUTCLK_MIPITX_DPHY_TXESC, "mipitx_dphy_txesc", 0,
> + JH7110_VOUTCLK_TX_ESC),
> /* hdmi */
> - JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_MCLK, "hdmi_tx_mclk", 0,
> - JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK),
> - JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_BCLK, "hdmi_tx_bclk", 0,
> - JH7110_VOUTCLK_I2STX0_BCLK),
> - JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_SYS, "hdmi_tx_sys", 0, JH7110_VOUTCLK_APB),
> + STARFIVE_GATE(JH7110_VOUTCLK_HDMI_TX_MCLK, "hdmi_tx_mclk", 0,
> + JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK),
> + STARFIVE_GATE(JH7110_VOUTCLK_HDMI_TX_BCLK, "hdmi_tx_bclk", 0,
> + JH7110_VOUTCLK_I2STX0_BCLK),
> + STARFIVE_GATE(JH7110_VOUTCLK_HDMI_TX_SYS, "hdmi_tx_sys", 0, JH7110_VOUTCLK_APB),
> };
>
> -static int jh7110_vout_top_rst_init(struct jh71x0_clk_priv *priv)
> +static int jh7110_vout_top_rst_init(struct starfive_clk_priv *priv)
> {
> struct reset_control *top_rst;
>
> @@ -82,7 +82,7 @@ static int jh7110_vout_top_rst_init(struct jh71x0_clk_priv *priv)
>
> static struct clk_hw *jh7110_voutclk_get(struct of_phandle_args *clkspec, void *data)
> {
> - struct jh71x0_clk_priv *priv = data;
> + struct starfive_clk_priv *priv = data;
> unsigned int idx = clkspec->args[0];
>
> if (idx < JH7110_VOUTCLK_END)
> @@ -115,7 +115,7 @@ static const struct dev_pm_ops jh7110_voutcrg_pm_ops = {
>
> static int jh7110_voutcrg_probe(struct platform_device *pdev)
> {
> - struct jh71x0_clk_priv *priv;
> + struct starfive_clk_priv *priv;
> struct jh7110_top_sysclk *top;
> unsigned int idx;
> int ret;
> @@ -158,13 +158,13 @@ static int jh7110_voutcrg_probe(struct platform_device *pdev)
> struct clk_parent_data parents[4] = {};
> struct clk_init_data init = {
> .name = jh7110_voutclk_data[idx].name,
> - .ops = starfive_jh71x0_clk_ops(max),
> + .ops = starfive_clk_ops(max),
> .parent_data = parents,
> .num_parents =
> - ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
> + ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1,
> .flags = jh7110_voutclk_data[idx].flags,
> };
> - struct jh71x0_clk *clk = &priv->reg[idx];
> + struct starfive_clk *clk = &priv->reg[idx];
> unsigned int i;
> const char *fw_name[JH7110_VOUTCLK_EXT_END - JH7110_VOUTCLK_END] = {
> "vout_src",
> @@ -186,7 +186,7 @@ static int jh7110_voutcrg_probe(struct platform_device *pdev)
>
> clk->hw.init = &init;
> clk->idx = idx;
> - clk->max_div = max & JH71X0_CLK_DIV_MASK;
> + clk->max_div = max & STARFIVE_CLK_DIV_MASK;
>
> ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
> if (ret)
> diff --git a/drivers/clk/starfive/clk-starfive-jh7110.h b/drivers/clk/starfive/clk-starfive-jh7110.h
> index 6b1bdf860f00..4a6dfd8d8636 100644
> --- a/drivers/clk/starfive/clk-starfive-jh7110.h
> +++ b/drivers/clk/starfive/clk-starfive-jh7110.h
> @@ -10,7 +10,7 @@ struct jh7110_top_sysclk {
> int top_clks_num;
> };
>
> -int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
> +int jh7110_reset_controller_register(struct starfive_clk_priv *priv,
> const char *adev_name,
> u32 adev_id);
>
> --
> 2.34.1
>
Sia Jee Heng wrote:
> Add support for JH8100 System clock generator.
>
> Signed-off-by: Sia Jee Heng <[email protected]>
> Reviewed-by: Ley Foon Tan <[email protected]>
> ---
> MAINTAINERS | 8 +
> drivers/clk/starfive/Kconfig | 9 +
> drivers/clk/starfive/Makefile | 1 +
> drivers/clk/starfive/clk-starfive-common.h | 9 +-
> drivers/clk/starfive/jh8100/Makefile | 3 +
> .../clk/starfive/jh8100/clk-starfive-jh8100.h | 11 +
> drivers/clk/starfive/jh8100/clk-sys.c | 455 ++++++++++++++++++
> 7 files changed, 495 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/starfive/jh8100/Makefile
> create mode 100644 drivers/clk/starfive/jh8100/clk-starfive-jh8100.h
> create mode 100644 drivers/clk/starfive/jh8100/clk-sys.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 788be9ab5b73..87bcb25becc1 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -20763,6 +20763,14 @@ F: Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
> F: drivers/phy/starfive/phy-jh7110-pcie.c
> F: drivers/phy/starfive/phy-jh7110-usb.c
>
> +STARFIVE JH8100 CLOCK DRIVERS
> +M: Sia Jee Heng <[email protected]>
> +M: Ley Foon Tan <[email protected]>
> +S: Maintained
> +F: Documentation/devicetree/bindings/clock/starfive,jh81*.yaml
> +F: drivers/clk/starfive/jh8100
> +F: include/dt-bindings/clock/starfive?jh81*.h
> +
> STATIC BRANCH/CALL
> M: Peter Zijlstra <[email protected]>
> M: Josh Poimboeuf <[email protected]>
> diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
> index ff8eace36e64..d8c7b9bb3895 100644
> --- a/drivers/clk/starfive/Kconfig
> +++ b/drivers/clk/starfive/Kconfig
> @@ -72,3 +72,12 @@ config CLK_STARFIVE_JH7110_VOUT
> help
> Say yes here to support the Video-Output clock controller
> on the StarFive JH7110 SoC.
> +
> +config CLK_STARFIVE_JH8100_SYS
> + bool "StarFive JH8100 System clock support"
> + depends on SOC_STARFIVE || COMPILE_TEST
> + select AUXILIARY_BUS
> + select CLK_STARFIVE_COMMON
> + default ARCH_STARFIVE
> + help
> + Say yes here to support the System clock controller on the StarFive JH8100 SoC.
> diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
> index 012f7ee83f8e..6cb3ce823330 100644
> --- a/drivers/clk/starfive/Makefile
> +++ b/drivers/clk/starfive/Makefile
> @@ -10,3 +10,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
> obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o
> obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o
> obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
> +obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS) += jh8100/
I don't really see why do you need a special subdirectory for the JH8100? The
JH7110 drivers do fine without it.
> diff --git a/drivers/clk/starfive/clk-starfive-common.h b/drivers/clk/starfive/clk-starfive-common.h
> index fed45311360c..ec30af0658cf 100644
> --- a/drivers/clk/starfive/clk-starfive-common.h
> +++ b/drivers/clk/starfive/clk-starfive-common.h
> @@ -103,6 +103,13 @@ struct starfive_clk_data {
> .parents = { [0] = _parent }, \
> }
>
> +#define STARFIVE_GINV(_idx, _name, _flags, _parent)[_idx] = { \
> + .name = _name, \
> + .flags = _flags, \
> + .max = STARFIVE_CLK_ENABLE | STARFIVE_CLK_INVERT, \
> + .parents = { [0] = _parent }, \
> +}
> +
> struct starfive_clk {
> struct clk_hw hw;
> unsigned int idx;
> @@ -114,7 +121,7 @@ struct starfive_clk_priv {
> spinlock_t rmw_lock;
> struct device *dev;
> void __iomem *base;
> - struct clk_hw *pll[3];
> + struct clk_hw *pll[8];
These extra slots are just used for fixed factor dummy PLLs right now, similar
to how the JH7110 first used them and later had to rework drivers and device
trees for the proper PLL driver.
This time around I'd much rather you work on getting the PLL driver in first,
so we don't need all that churn.
> struct starfive_clk reg[];
> };
>
> diff --git a/drivers/clk/starfive/jh8100/Makefile b/drivers/clk/starfive/jh8100/Makefile
> new file mode 100644
> index 000000000000..af6a09e220d3
> --- /dev/null
> +++ b/drivers/clk/starfive/jh8100/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0
> +# StarFive JH8100 Clock
> +obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS) += clk-sys.o
This will name the module clk-sys, which is way too generic. Please name this
clk-starfive-jh8100-sys similar to the JH7110 drivers.
> diff --git a/drivers/clk/starfive/jh8100/clk-starfive-jh8100.h b/drivers/clk/starfive/jh8100/clk-starfive-jh8100.h
> new file mode 100644
> index 000000000000..7c8249c11464
> --- /dev/null
> +++ b/drivers/clk/starfive/jh8100/clk-starfive-jh8100.h
> @@ -0,0 +1,11 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef __CLK_STARFIVE_JH8100_H
> +#define __CLK_STARFIVE_JH8100_H
> +
> +#include "../clk-starfive-common.h"
> +
> +int jh8100_reset_controller_register(struct starfive_clk_priv *priv,
> + const char *adev_name,
> + u32 adev_id);
> +
> +#endif
> diff --git a/drivers/clk/starfive/jh8100/clk-sys.c b/drivers/clk/starfive/jh8100/clk-sys.c
> new file mode 100644
> index 000000000000..e2c802523c7d
> --- /dev/null
> +++ b/drivers/clk/starfive/jh8100/clk-sys.c
> @@ -0,0 +1,455 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * StarFive JH8100 System Clock Driver
> + *
> + * Copyright (C) 2023 StarFive Technology Co., Ltd.
> + *
> + * Author: Jee Heng Sia <[email protected]>
> + *
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/auxiliary_bus.h>
> +#include <linux/clk-provider.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +
> +#include <soc/starfive/reset-starfive-common.h>
> +
> +#include <dt-bindings/clock/starfive,jh8100-crg.h>
> +
> +#include "clk-starfive-jh8100.h"
> +
> +/* external clocks */
> +#define SYSCRG_CLK_OSC (SYSCRG_CLK_END + 0)
> +#define SYSCRG_CLK_MCLK_EXT (SYSCRG_CLK_END + 1)
> +#define SYSCRG_CLK_PLL0_OUT (SYSCRG_CLK_END + 2)
> +#define SYSCRG_CLK_PLL1_OUT (SYSCRG_CLK_END + 3)
> +#define SYSCRG_CLK_PLL2_OUT (SYSCRG_CLK_END + 4)
> +#define SYSCRG_CLK_PLL3_OUT (SYSCRG_CLK_END + 5)
> +#define SYSCRG_CLK_PLL4_OUT (SYSCRG_CLK_END + 6)
> +#define SYSCRG_CLK_PLL6_OUT (SYSCRG_CLK_END + 7)
> +#define SYSCRG_CLK_PLL7_OUT (SYSCRG_CLK_END + 8)
> +
> +static const struct starfive_clk_data jh8100_syscrg_clk_data[] __initconst = {
> + /* root */
> + STARFIVE__DIV(SYSCRG_CLK_VDEC_ROOT_PREOSC, "sys_clk_vdec_root_preosc", 10,
> + SYSCRG_CLK_PLL7_OUT),
> + STARFIVE__MUX(SYSCRG_CLK_VDEC_ROOT, "sys_clk_vdec_root", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_VDEC_ROOT_PREOSC),
> + STARFIVE__DIV(SYSCRG_CLK_VENC_ROOT_PREOSC, "sys_clk_venc_root_preosc", 10,
> + SYSCRG_CLK_PLL7_OUT),
> + STARFIVE__MUX(SYSCRG_CLK_VENC_ROOT, "sys_clk_venc_root", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_VENC_ROOT_PREOSC),
> + STARFIVE__DIV(SYSCRG_CLK_GPU_ROOT, "sys_clk_gpu_root", 7,
> + SYSCRG_CLK_PLL0_OUT),
> + STARFIVE__MUX(SYSCRG_CLK_GPU_CORE, "sys_clk_gpu_core", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_GPU_ROOT),
> + STARFIVE__DIV(SYSCRG_CLK_VOUT_ROOT0_PREOSC, "sys_clk_vout_root0_preosc", 127,
> + SYSCRG_CLK_PLL1_OUT),
> + STARFIVE__MUX(SYSCRG_CLK_VOUT_ROOT0, "sys_clk_vout_root0", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_VOUT_ROOT0_PREOSC),
> + STARFIVE__DIV(SYSCRG_CLK_VOUT_ROOT1_PREOSC, "sys_clk_vout_root1_preosc", 127,
> + SYSCRG_CLK_PLL6_OUT),
> + STARFIVE__MUX(SYSCRG_CLK_VOUT_ROOT1, "sys_clk_vout_root1", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_VOUT_ROOT1_PREOSC),
> + STARFIVE__DIV(SYSCRG_CLK_VOUT_SCAN_ATS, "sys_clk_vout_scan_ats", 6,
> + SYSCRG_CLK_PLL3_OUT),
> + STARFIVE__DIV(SYSCRG_CLK_PERH_ROOT_PREOSC, "sys_clk_perh_root_preosc", 4,
> + SYSCRG_CLK_PLL0_OUT),
> + STARFIVE__MUX(SYSCRG_CLK_PERH_ROOT, "sys_clk_perh_root", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_PERH_ROOT_PREOSC),
> + STARFIVE__DIV(SYSCRG_CLK_AXI_200_PREOSC, "sys_clk_axi_200_preosc", 4,
> + SYSCRG_CLK_PLL0_OUT),
> + STARFIVE__MUX(SYSCRG_CLK_AXI_200, "sys_clk_axi_200", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_200_PREOSC),
> + STARFIVE__MUX(SYSCRG_CLK_AXI_200_GMAC, "sys_clk_axi_200_gmac", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_200_PREOSC),
> + STARFIVE__DIV(SYSCRG_CLK_AXI_500_PREOSC, "sys_clk_axi_500_preosc", 10,
> + SYSCRG_CLK_PLL0_OUT),
> + STARFIVE__MUX(SYSCRG_CLK_AXI_500, "sys_clk_axi_500", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_500_PREOSC),
> + STARFIVE__MUX(SYSCRG_CLK_AXI_500_PCIEX1A, "sys_clk_axi_500_pciex1a", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_500_PREOSC),
> + STARFIVE__MUX(SYSCRG_CLK_AXI_500_PCIEX1B, "sys_clk_axi_500_pciex1b", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_500_PREOSC),
> + STARFIVE__MUX(SYSCRG_CLK_AXI_500_PCIEX2, "sys_clk_axi_500_pciex2", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_500_PREOSC),
> + STARFIVE__MUX(SYSCRG_CLK_AXI_500_PCIEX8, "sys_clk_axi_500_pciex8", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_500_PREOSC),
> + STARFIVE__DIV(SYSCRG_CLK_AXI_400_PREOSC, "sys_clk_axi_400_preosc", 10,
> + SYSCRG_CLK_PLL0_OUT),
> + STARFIVE__MUX(SYSCRG_CLK_AXI_400, "sys_clk_axi_400", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_400_PREOSC),
> + STARFIVE__MUX(SYSCRG_CLK_AXI_400_APBOOTRAM, "sys_clk_axi_400_apbootram", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_400_PREOSC),
> + STARFIVE__DIV(SYSCRG_CLK_AXI_125_PREOSC, "sys_clk_axi_125_preosc", 32,
> + SYSCRG_CLK_PLL0_OUT),
> + STARFIVE__MUX(SYSCRG_CLK_AXI_125, "sys_clk_axi_125", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_125_PREOSC),
> + STARFIVE__DIV(SYSCRG_CLK_AHB0_PREOSC, "sys_clk_ahb0_preosc", 15,
> + SYSCRG_CLK_PLL0_OUT),
> + STARFIVE__MUX(SYSCRG_CLK_AHB0, "sys_clk_ahb0", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_AHB0_PREOSC),
> + STARFIVE__DIV(SYSCRG_CLK_APB_BUS_FUNC, "sys_clk_apb_bus_func", 30,
> + SYSCRG_CLK_PLL0_OUT),
> + STARFIVE__MUX(SYSCRG_CLK_APB_BUS, "sys_clk_apb_bus", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
> + STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER0, "sys_clk_apb_bus_per0", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
> + STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER1, "sys_clk_apb_bus_per1", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
> + STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER2, "sys_clk_apb_bus_per2", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
> + STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER3, "sys_clk_apb_bus_per3", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
> + STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER4, "sys_clk_apb_bus_per4", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
> + STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER5, "sys_clk_apb_bus_per5", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
> + STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER6, "sys_clk_apb_bus_per6", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
> + STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER7, "sys_clk_apb_bus_per7", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
> + STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER8, "sys_clk_apb_bus_per8", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
> + STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER9, "sys_clk_apb_bus_per9", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
> + STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER10, "sys_clk_apb_bus_per10", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
> + STARFIVE__MUX(SYSCRG_CLK_SPI_CORE_100, "sys_clk_spi_core_100", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
> + STARFIVE__DIV(SYSCRG_CLK_PLL1_DIV2, "sys_clk_pll1_div2", 2,
> + SYSCRG_CLK_PLL1_OUT),
> + STARFIVE__DIV(SYSCRG_CLK_PLL2_DIV2, "sys_clk_pll2_div2", 2,
> + SYSCRG_CLK_PLL2_OUT),
> + STARFIVE__DIV(SYSCRG_CLK_PLL3_DIV2, "sys_clk_pll3_div2", 2,
> + SYSCRG_CLK_PLL3_OUT),
> + STARFIVE__DIV(SYSCRG_CLK_PLL4_DIV2, "sys_clk_pll4_div2", 2,
> + SYSCRG_CLK_PLL4_OUT),
> + STARFIVE__DIV(SYSCRG_CLK_PLL6_DIV2, "sys_clk_pll6_div2", 2,
> + SYSCRG_CLK_PLL6_OUT),
> + STARFIVE__DIV(SYSCRG_CLK_PLL7_DIV2, "sys_clk_pll7_div2", 2,
> + SYSCRG_CLK_PLL7_OUT),
> + STARFIVE__DIV(SYSCRG_CLK_AUDIO_ROOT, "sys_clk_audio_root", 8,
> + SYSCRG_CLK_PLL2_OUT),
> + STARFIVE__DIV(SYSCRG_CLK_MCLK_INNER, "sys_clk_mclk_inner", 64,
> + SYSCRG_CLK_AUDIO_ROOT),
> + STARFIVE__MUX(SYSCRG_CLK_MCLK, "sys_clk_mclk", 2,
> + SYSCRG_CLK_MCLK_INNER, SYSCRG_CLK_MCLK_EXT),
> + STARFIVE_GATE(SYSCRG_CLK_MCLK_OUT, "sys_clk_mclk_out", 0,
> + SYSCRG_CLK_MCLK_INNER),
> + STARFIVE_MDIV(SYSCRG_CLK_ISP_2X_PREOSC, "sys_clk_isp_2x_preosc", 8, 2,
> + SYSCRG_CLK_PLL7_OUT, SYSCRG_CLK_PLL0_OUT),
> + STARFIVE__MUX(SYSCRG_CLK_ISP_2X, "sys_clk_isp_2x", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_ISP_2X_PREOSC),
> + STARFIVE__DIV(SYSCRG_CLK_ISP_AXI, "sys_clk_isp_axi", 4,
> + SYSCRG_CLK_ISP_2X),
> + STARFIVE_GDIV(SYSCRG_CLK_GCLK1, "sys_clk_gclk1", CLK_IS_CRITICAL, 120,
> + SYSCRG_CLK_PLL1_DIV2),
> + STARFIVE_GDIV(SYSCRG_CLK_GCLK2, "sys_clk_gclk2", CLK_IS_CRITICAL, 120,
> + SYSCRG_CLK_PLL2_DIV2),
> + STARFIVE_GDIV(SYSCRG_CLK_GCLK3, "sys_clk_gclk3", CLK_IS_CRITICAL, 120,
> + SYSCRG_CLK_PLL3_DIV2),
> + STARFIVE_GDIV(SYSCRG_CLK_GCLK4, "sys_clk_gclk4", CLK_IS_CRITICAL, 120,
> + SYSCRG_CLK_PLL4_DIV2),
> + STARFIVE_GDIV(SYSCRG_CLK_GCLK6, "sys_clk_gclk6", CLK_IS_CRITICAL, 120,
> + SYSCRG_CLK_PLL6_DIV2),
> + STARFIVE_GDIV(SYSCRG_CLK_GCLK7, "sys_clk_gclk7", CLK_IS_CRITICAL, 120,
> + SYSCRG_CLK_PLL7_DIV2),
> + /* flexnoc (se) */
> + STARFIVE__DIV(SYSCRG_CLK_FLEXNOC0_PREOSC, "sys_clk_flexnoc0_preosc", 8,
> + SYSCRG_CLK_PLL0_OUT),
> + STARFIVE__MUX(SYSCRG_CLK_FLEXNOC0, "sys_clk_flexnoc0", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_FLEXNOC0_PREOSC),
> + STARFIVE__DIV(SYSCRG_CLK_FLEXNOC1_PREOSC, "sys_clk_flexnoc1_preosc", 8,
> + SYSCRG_CLK_PLL0_OUT),
> + STARFIVE__MUX(SYSCRG_CLK_FLEXNOC1, "sys_clk_flexnoc1", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_FLEXNOC1_PREOSC),
> + STARFIVE__DIV(SYSCRG_CLK_FLEXNOC2_PREOSC, "sys_clk_flexnoc2_preosc", 12,
> + SYSCRG_CLK_PLL0_OUT),
> + STARFIVE__MUX(SYSCRG_CLK_FLEXNOC2, "sys_clk_flexnoc2", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_FLEXNOC2_PREOSC),
> + STARFIVE__MUX(SYSCRG_CLK_VDEC_CORE, "sys_clk_vdec_core", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_FLEXNOC1_PREOSC),
> + /* img_gpu (se) */
> + STARFIVE_GATE(SYSCRG_CLK_GPU_CORE_ICG, "sys_clk_gpu_core_icg", 0,
> + SYSCRG_CLK_GPU_CORE),
> + STARFIVE_GATE(SYSCRG_CLK_IMG_GPU_CLK_APB, "sys_clk_img_gpu_clk_apb", 0,
> + SYSCRG_CLK_APB_BUS_PER7),
> + STARFIVE_GATE(SYSCRG_CLK_IMG_GPU_RTC_TOGGLE, "sys_clk_img_gpu_rtc_toggle", 0,
> + SYSCRG_CLK_OSC),
> + STARFIVE_GATE(SYSCRG_CLK_IMG_GPU_TIMER_USC, "sys_clk_img_gpu_timer_usc", 0,
> + SYSCRG_CLK_OSC),
> + /* hifi4 (se) */
> + STARFIVE__DIV(SYSCRG_CLK_HIFI4_CORE_PREOSC, "sys_clk_hifi4_core_preosc", 15,
> + SYSCRG_CLK_PLL0_OUT),
> + STARFIVE__MUX(SYSCRG_CLK_HIFI4_CORE, "sys_clk_hifi4_core", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_HIFI4_CORE_PREOSC),
> + /* espi */
> + STARFIVE__DIV(SYSCRG_CLK_ESPI_200_PREOSC, "sys_clk_espi_200_preosc", 2,
> + SYSCRG_CLK_PLL0_OUT),
> + STARFIVE__MUX(SYSCRG_CLK_ESPI_200, "sys_clk_espi_200", 2,
> + SYSCRG_CLK_OSC, SYSCRG_CLK_ESPI_200_PREOSC),
> + /* hd audio */
> + STARFIVE__DIV(SYSCRG_CLK_HD_AUDIO_48M, "sys_clk_hd_audio_48m", 80,
> + SYSCRG_CLK_PLL7_OUT),
> + /* dom vout */
> + STARFIVE__DIV(SYSCRG_CLK_VOUT_DC_CORE, "sys_clk_vout_dc_core", 10,
> + SYSCRG_CLK_PLL7_OUT),
> + STARFIVE__DIV(SYSCRG_CLK_VOUT_AXI, "sys_clk_vout_axi", 10,
> + SYSCRG_CLK_PLL7_OUT),
> + /* stg2_usb_wrap (se) */
> + STARFIVE__DIV(SYSCRG_CLK_USB_WRAP_625, "sys_clk_usb_wrap_625", 6,
> + SYSCRG_CLK_PLL0_OUT),
> + STARFIVE__DIV(SYSCRG_CLK_USB_WRAP_480, "sys_clk_usb_wrap_480", 8,
> + SYSCRG_CLK_PLL0_OUT),
> + STARFIVE__DIV(SYSCRG_CLK_USB_WRAP_240, "sys_clk_usb_wrap_240", 2,
> + SYSCRG_CLK_USB_WRAP_480),
> + STARFIVE__DIV(SYSCRG_CLK_USB_WRAP_60, "sys_clk_usb_wrap_60", 10,
> + SYSCRG_CLK_USB_WRAP_480),
> + STARFIVE__DIV(SYSCRG_CLK_USB_WRAP_156P25, "sys_clk_usb_wrap_156p25", 4,
> + SYSCRG_CLK_USB_WRAP_625),
> + STARFIVE__DIV(SYSCRG_CLK_USB_WRAP_312P5, "sys_clk_usb_wrap_312p5", 2,
> + SYSCRG_CLK_USB_WRAP_625),
> + /* stg */
> + STARFIVE__DIV(SYSCRG_CLK_USB_125M, "sys_clk_usb_125m", 32,
> + SYSCRG_CLK_PLL0_OUT),
> + /* Flexnoc (se) */
> + STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_APBOOTRAM, "sys_clk_flexnoc_apbootram",
> + CLK_IS_CRITICAL, SYSCRG_CLK_AXI_400_APBOOTRAM),
> + STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_PCIEX1AMST, "sys_clk_flexnoc_pciex1amst",
> + CLK_IS_CRITICAL, SYSCRG_CLK_AXI_500_PCIEX1A),
> + STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_PCIEX1ASLV, "sys_clk_flexnoc_pciex1aslv",
> + CLK_IS_CRITICAL, SYSCRG_CLK_AXI_500_PCIEX1A),
> + STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_PCIEX1BMST, "sys_clk_flexnoc_pciex1bmst",
> + CLK_IS_CRITICAL, SYSCRG_CLK_AXI_500_PCIEX1B),
> + STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_PCIEX1BSLV, "sys_clk_flexnoc_pciex1bslv",
> + CLK_IS_CRITICAL, SYSCRG_CLK_AXI_500_PCIEX1B),
> + STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_PCIEX2MST, "sys_clk_flexnoc_pciex2mst",
> + CLK_IS_CRITICAL, SYSCRG_CLK_AXI_500_PCIEX2),
> + STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_PCIEX2SLV, "sys_clk_flexnoc_pciex2slv",
> + CLK_IS_CRITICAL, SYSCRG_CLK_AXI_500_PCIEX2),
> + STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_PCIEX8MST, "sys_clk_flexnoc_pciex8mst",
> + CLK_IS_CRITICAL, SYSCRG_CLK_AXI_500_PCIEX8),
> + STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_PCIEX8SLV, "sys_clk_flexnoc_pciex8slv",
> + CLK_IS_CRITICAL, SYSCRG_CLK_AXI_500_PCIEX8),
> + STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_GMACSYSSLV, "sys_clk_flexnoc_gmacsysslv",
> + CLK_IS_CRITICAL, SYSCRG_CLK_AXI_200_GMAC),
> + /* gmac1 (se) */
> + STARFIVE__DIV(SYSCRG_CLK_GMAC_SRC, "sys_clk_gmac_src", 7,
> + SYSCRG_CLK_PLL0_OUT),
> + STARFIVE__DIV(SYSCRG_CLK_GMAC1_GTXCLK_TOP, "sys_clk_gmac1_gtxclk_top", 400,
> + SYSCRG_CLK_PLL0_OUT),
> + STARFIVE__DIV(SYSCRG_CLK_GMAC1_PTP, "sys_clk_gmac1_ptp", 31,
> + SYSCRG_CLK_GMAC_SRC),
> + /* hd audio */
> + STARFIVE_GATE(SYSCRG_CLK_HD_AUDIO_SYSTEM_CLOCK, "sys_clk_hd_audio_system_clock",
> + 0, SYSCRG_CLK_APB_BUS_PER7),
> + STARFIVE_GATE(SYSCRG_CLK_HD_AUDIO_CLOCK_48, "sys_clk_hd_audio_clock_48",
> + 0, SYSCRG_CLK_HD_AUDIO_48M),
> + STARFIVE_GATE(SYSCRG_CLK_HD_AUDIO_BCLK_POST_OCC_IN, "sys_clk_hd_audio_bclk_post_occ_in",
> + 0, SYSCRG_CLK_HD_AUDIO_48M),
> + /* nne_vip (se) */
> + STARFIVE_GATE(SYSCRG_CLK_NNE_VIP_ACLK, "sys_clk_nne_vip_aclk",
> + 0, SYSCRG_CLK_AXI_500),
> + STARFIVE_GATE(SYSCRG_CLK_NNE_VIP_HCLK, "sys_clk_nne_vip_hclk",
> + 0, SYSCRG_CLK_AXI_200),
> + STARFIVE_GMUX(SYSCRG_CLK_NNE_VIP_CLKCORE, "sys_clk_nne_vip_clkcore", 0, 2,
> + SYSCRG_CLK_PLL2_OUT,
> + SYSCRG_CLK_PLL0_OUT),
> + /* icg_en */
> + STARFIVE_GATE(SYSCRG_CLK_GPU_ICG_EN, "sys_clk_gpu_en",
> + 0, SYSCRG_CLK_GPU_CORE),
> + STARFIVE_GATE(SYSCRG_CLK_HD_AUDIO_ICG_EN, "sys_clk_hd_audio_en",
> + 0, SYSCRG_CLK_APB_BUS),
> + STARFIVE_GATE(SYSCRG_CLK_NNE_ICG_EN, "sys_clk_nne_en",
> + CLK_IGNORE_UNUSED, SYSCRG_CLK_PLL2_OUT),
> +};
Please drop the redundant sys_clk_ prefix from all the clock names similar to
how it was done for the JH71X0s.
/Emil
Sia Jee Heng wrote:
> Add bindings for the System-North-West clock and reset generator
> (SYSCRG-NW) on JH8100 SoC.
>
> Signed-off-by: Sia Jee Heng <[email protected]>
> Reviewed-by: Ley Foon Tan <[email protected]>
> ---
> .../clock/starfive,jh8100-syscrg-nw.yaml | 119 ++++++++++++++++++
The JH7110 clocks, the JH8100 system and always-on all follow the Xcrg pattern:
syscrg
aoncrg
stgcrg
ispcrg
voutcrg
etc.
Is there a reason the north-west, north-east and south-west breaks this pattern?
I'd have expected them to be called something like
nwcrg, JH8100_NWCLK_*, JH8100_NWRST_*,
necrg, JH8100_NECLK_*, JH8100_NERST_* and
swcrg, JH8100_SWCLK_*, JH8100_SWRST_*
Just like all the other Starfive drivers.
> .../dt-bindings/clock/starfive,jh8100-crg.h | 45 +++++++
> .../dt-bindings/reset/starfive,jh8100-crg.h | 15 +++
> 3 files changed, 179 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-nw.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-nw.yaml b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-nw.yaml
> new file mode 100644
> index 000000000000..b16a874828dd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-nw.yaml
> @@ -0,0 +1,119 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/starfive,jh8100-syscrg-nw.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH8100 System-North-West Clock and Reset Generator
> +
> +maintainers:
> + - Sia Jee Heng <[email protected]>
> +
> +properties:
> + compatible:
> + const: starfive,jh8100-syscrg-nw
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Main Oscillator (24 MHz)
> + - description: APB_BUS clock from SYSCRG
> + - description: ISP_2X clock from SYSCRG
> + - description: ISP_AXI clock from SYSCRG
> + - description: VOUT_ROOT0 clock from SYSCRG
> + - description: VOUT_ROOT1 clock from SYSCRG
> + - description: VOUT_SCAN_ATS clock from SYSCRG
> + - description: VOUT_DC_CORE clock from SYSCRG
> + - description: VOUT_AXI clock from SYSCRG
> + - description: AXI_400 clock from SYSCRG
> + - description: AXI_200 clock from SYSCRG
> + - description: Peripheral clock from SYSCRG
> + - description: External DVP clock
> + - description: External ISP DPHY TAP TCK clock
> + - description: External golbal clock
> + - description: External i2s_tscko clock
> + - description: External VOUT MIPI DPHY TAP TCK
> + - description: External VOUT eDP TAP TCK
> + - description: External SPI In2 clock
> +
> + clock-names:
> + items:
> + - const: clk_osc
> + - const: sys_clk_apb_bus
> + - const: sys_clk_isp_2x
> + - const: sys_clk_isp_axi
> + - const: sys_clk_vout_root0
> + - const: sys_clk_vout_root1
> + - const: sys_clk_vout_scan_ats
> + - const: sys_clk_vout_dc_core
> + - const: sys_clk_vout_axi
> + - const: sys_clk_axi_400
> + - const: sys_clk_axi_200
> + - const: sys_clk_perh_root_preosc
> + - const: clk_dvp_ext
> + - const: clk_isp_dphy_tap_tck_ext
> + - const: clk_glb_ext_clk
> + - const: clk_i2s_tscko
> + - const: clk_vout_mipi_dphy_tap_tck_ext
> + - const: clk_vout_edp_tap_tck_ext
> + - const: clk_spi_in2_ext
> +
> + '#clock-cells':
> + const: 1
> + description:
> + See <dt-bindings/clock/starfive,jh8100-crg.h> for valid indices.
> +
> + '#reset-cells':
> + const: 1
> + description:
> + See <dt-bindings/reset/starfive,jh8100-crg.h> for valid indices.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - '#clock-cells'
> + - '#reset-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/starfive,jh8100-crg.h>
> +
> + clock-controller@123c0000 {
> + compatible = "starfive,jh8100-syscrg-nw";
> + reg = <0x123c0000 0x10000>;
> + clocks = <&clk_osc>, <&syscrg SYSCRG_CLK_APB_BUS>,
> + <&syscrg SYSCRG_CLK_ISP_2X>,
> + <&syscrg SYSCRG_CLK_ISP_AXI>,
> + <&syscrg SYSCRG_CLK_VOUT_ROOT0>,
> + <&syscrg SYSCRG_CLK_VOUT_ROOT1>,
> + <&syscrg SYSCRG_CLK_VOUT_SCAN_ATS>,
> + <&syscrg SYSCRG_CLK_VOUT_DC_CORE>,
> + <&syscrg SYSCRG_CLK_VOUT_AXI>,
> + <&syscrg SYSCRG_CLK_AXI_400>,
> + <&syscrg SYSCRG_CLK_AXI_200>,
> + <&syscrg SYSCRG_CLK_PERH_ROOT_PREOSC>,
> + <&clk_dvp_ext>,
> + <&clk_isp_dphy_tap_tck_ext>,
> + <&clk_glb_ext_clk>,
> + <&clk_i2s_tscko>,
> + <&clk_vout_mipi_dphy_tap_tck_ext>,
> + <&clk_vout_edp_tap_tck_ext>,
> + <&clk_spi_in2_ext>;
> + clock-names = "clk_osc", "sys_clk_apb_bus", "sys_clk_isp_2x",
> + "sys_clk_isp_axi", "sys_clk_vout_root0",
> + "sys_clk_vout_root1", "sys_clk_vout_scan_ats",
> + "sys_clk_vout_dc_core", "sys_clk_vout_axi",
> + "sys_clk_axi_400", "sys_clk_axi_200",
> + "sys_clk_perh_root_preosc", "clk_dvp_ext",
> + "clk_isp_dphy_tap_tck_ext", "clk_glb_ext_clk",
> + "clk_i2s_tscko", "clk_vout_mipi_dphy_tap_tck_ext",
> + "clk_vout_edp_tap_tck_ext", "clk_spi_in2_ext";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h
> index e5bb588ce798..8417455c2409 100644
> --- a/include/dt-bindings/clock/starfive,jh8100-crg.h
> +++ b/include/dt-bindings/clock/starfive,jh8100-crg.h
> @@ -120,4 +120,49 @@
> #define SYSCRG_CLK_NNE_ICG_EN 108
>
> #define SYSCRG_CLK_END 109
> +
> +/* SYSCRG_NW_CLK */
> +#define SYSCRG_NW_CLK_PLL5_DIV2 0
> +#define SYSCRG_NW_CLK_GCLK5 1
> +#define SYSCRG_NW_CLK_GPIO_100 2
> +#define SYSCRG_NW_CLK_GPIO_50 3
> +#define SYSCRG_NW_CLK_GPIO_150 4
> +#define SYSCRG_NW_CLK_GPIO_60 5
> +#define SYSCRG_NW_CLK_IOMUX_WEST_PCLK 6
> +#define SYSCRG_NW_CLK_I2C6_APB 7
> +#define SYSCRG_NW_CLK_I2C7_APB 8
> +#define SYSCRG_NW_CLK_SPI2_APB 9
> +#define SYSCRG_NW_CLK_SPI2_CORE 10
> +#define SYSCRG_NW_CLK_SPI2_SCLK_IN 11
> +#define SYSCRG_NW_CLK_SMBUS1_APB 12
> +#define SYSCRG_NW_CLK_SMBUS1_CORE 13
> +#define SYSCRG_NW_CLK_ISP_DVP 14
> +#define SYSCRG_NW_CLK_ISP_CORE_2X 15
> +#define SYSCRG_NW_CLK_ISP_AXI 16
> +#define SYSCRG_NW_CLK_ISP_DPHY_TAP_TCK 17
> +#define SYSCRG_NW_CLK_FLEXNOC_ISPSLV 18
> +#define SYSCRG_NW_CLK_VOUT_PIX0 19
> +#define SYSCRG_NW_CLK_VOUT_PIX1 20
> +#define SYSCRG_NW_CLK_VOUT_SCAN_ATS 21
> +#define SYSCRG_NW_CLK_VOUT_DC_CORE 22
> +#define SYSCRG_NW_CLK_VOUT_APB 23
> +#define SYSCRG_NW_CLK_VOUT_DSI 24
> +#define SYSCRG_NW_CLK_VOUT_AHB 25
> +#define SYSCRG_NW_CLK_VOUT_AXI 26
> +#define SYSCRG_NW_CLK_VOUT_MIPI_DPHY_TAP_TCK 27
> +#define SYSCRG_NW_CLK_VOUT_EDP_PHY_TAP_TCK 28
> +#define SYSCRG_NW_CLK_UART5_CORE_PREOSC 29
> +#define SYSCRG_NW_CLK_UART5_APB 30
> +#define SYSCRG_NW_CLK_UART5_CORE 31
> +#define SYSCRG_NW_CLK_UART6_CORE_PREOSC 32
> +#define SYSCRG_NW_CLK_UART6_APB 33
> +#define SYSCRG_NW_CLK_UART6_CORE 34
> +#define SYSCRG_NW_CLK_SPI2_ICG_EN 35
> +#define SYSCRG_NW_CLK_SMBUS1_ICG_EN 36
> +#define SYSCRG_NW_CLK_ISP_ICG_EN 37
> +#define SYSCRG_NW_CLK_VOUT_ICG_EN 38
> +#define SYSCRG_NW_CLK_UART5_ICG_EN 39
> +#define SYSCRG_NW_CLK_UART6_ICG_EN 40
> +
> +#define SYSCRG_NW_CLK_END 41
> #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */
> diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h
> index 3b7b92488e76..8c3a858bdf6a 100644
> --- a/include/dt-bindings/reset/starfive,jh8100-crg.h
> +++ b/include/dt-bindings/reset/starfive,jh8100-crg.h
> @@ -20,4 +20,19 @@
>
> #define SYSCRG_RESET_NR_RESETS 8
>
> +/*
> + * syscrg_nw: assert0
> + */
> +#define SYSCRG_NW_RSTN_PRESETN 0
> +#define SYSCRG_NW_RSTN_SYS_IOMUX_W 1
> +#define SYSCRG_NW_RSTN_I2C6 2
> +#define SYSCRG_NW_RSTN_I2C7 3
> +#define SYSCRG_NW_RSTN_SPI2 4
> +#define SYSCRG_NW_RSTN_SMBUS1 5
> +#define SYSCRG_NW_RSTN_UART5 6
> +#define SYSCRG_NW_RSTN_UART6 7
> +#define SYSCRG_NW_RSTN_MERAK0_TVSENSOR 8
> +#define SYSCRG_NW_RSTN_MERAK1_TVSENSOR 9
> +
> +#define SYSCRG_NW_RESET_NR_RESETS 10
> #endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */
> --
> 2.34.1
>
Sia Jee Heng wrote:
> Add SYSCRG/SYSCRG-NE/SYSCRG-NW/SYSCRG-SW/AONCRG clock and reset
> nodes for JH8100 RISC-V SoC.
>
> Signed-off-by: Sia Jee Heng <[email protected]>
> Reviewed-by: Ley Foon Tan <[email protected]>
> ---
> arch/riscv/boot/dts/starfive/jh8100-clk.dtsi | 180 +++++++++++++++++++
> arch/riscv/boot/dts/starfive/jh8100.dtsi | 115 ++++++++++++
Why the split here? I mean why can't the clocks just be in the jh8100.dtsi?
> 2 files changed, 295 insertions(+)
> create mode 100644 arch/riscv/boot/dts/starfive/jh8100-clk.dtsi
>
> diff --git a/arch/riscv/boot/dts/starfive/jh8100-clk.dtsi b/arch/riscv/boot/dts/starfive/jh8100-clk.dtsi
> new file mode 100644
> index 000000000000..27ba249f523e
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh8100-clk.dtsi
> @@ -0,0 +1,180 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2023 StarFive Technology Co., Ltd.
> + */
> +
> +/ {
> + clk_osc: clk_osc {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24000000>;
> + };
> +
> + clk_i2srx_bclk_ext: clk_i2srx_bclk_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <12288000>;
> + };
> +
> + clk_i2srx_lrck_ext: clk_i2srx_lrck_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <192000>;
> + };
> +
> + clk_mclk_ext: clk_mclk_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <49152000>;
> + };
> + /* sys-ne */
> + clk_usb3_tap_tck_ext: clk_usb3_tap_tck_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + };
> +
> + clk_glb_ext_clk: clk_glb_ext_clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <30000000>;
> + };
> +
> + clk_usb1_tap_tck_ext: clk_usb1_tap_tck_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + };
> +
> + clk_usb2_tap_tck_ext: clk_usb2_tap_tck_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + };
> +
> + clk_i2s_tscko: clk_i2s_tscko {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <12800000>;
> + };
> +
> + clk_typec_tap_tck_ext: clk_typec_tap_tck_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + };
> +
> + clk_spi_in0_ext: clk_spi_in0_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + };
> +
> + clk_spi_in1_ext: clk_spi_in1_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + };
> +
> + clk_spi_in2_ext: clk_spi_in2_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + };
> +
> + clk_i2stx_bclk_ext: clk_i2stx_bclk_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <12288000>;
> + };
> +
> + clk_i2stx_lrck_ext: clk_i2stx_lrck_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <192000>;
> + };
> + /* sys-nw */
> + clk_dvp_ext: clk_dvp_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <150000000>;
> + };
> +
> + clk_isp_dphy_tap_tck_ext: clk_isp_dphy_tap_tck_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + };
> +
> + clk_vout_mipi_dphy_tap_tck_ext: clk_vout_mipi_dphy_tap_tck_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + };
> +
> + clk_vout_edp_tap_tck_ext: clk_vout_edp_tap_tck_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + };
> +
> + clk_rtc: clk_rtc {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + };
> + /* aon */
> + clk_gmac0_rmii_func: clk_gmac0_rmii_func {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <50000000>;
> + };
> +
> + clk_gmac0_rgmii_func: clk_gmac0_rgmii_func {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <125000000>;
> + };
> +
> + clk_aon50: clk_aon50 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <50000000>;
> + };
> +
> + clk_aon125: clk_aon125 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <125000000>;
> + };
> +
> + clk_aon2000: clk_aon2000 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <2000000000>;
> + };
> +
> + clk_aon200: clk_aon200 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <200000000>;
> + };
> +
> + clk_aon667: clk_isp_aon667 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <667000000>;
> + };
> +
> + clk_i3c_ext: clk_i3c_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <12500000>;
> + };
> +
> + clk_espi_ext: clk_espi_ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <60000000>;
> + };
> +};
> diff --git a/arch/riscv/boot/dts/starfive/jh8100.dtsi b/arch/riscv/boot/dts/starfive/jh8100.dtsi
> index f26aff5c1ddf..9863c61324a0 100644
> --- a/arch/riscv/boot/dts/starfive/jh8100.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh8100.dtsi
> @@ -4,6 +4,9 @@
> */
>
> /dts-v1/;
> +#include <dt-bindings/clock/starfive,jh8100-crg.h>
> +#include <dt-bindings/reset/starfive,jh8100-crg.h>
> +#include "jh8100-clk.dtsi"
>
> / {
> compatible = "starfive,jh8100";
> @@ -357,6 +360,104 @@ uart4: serial@121a0000 {
> status = "disabled";
> };
>
> + syscrg_ne: syscrg_ne@12320000 {
> + compatible = "starfive,jh8100-syscrg-ne";
> + reg = <0x0 0x12320000 0x0 0x10000>;
> + clocks = <&clk_osc>, <&syscrg SYSCRG_CLK_AXI_400>,
> + <&syscrg SYSCRG_CLK_VOUT_ROOT0>,
> + <&syscrg SYSCRG_CLK_VOUT_ROOT1>,
> + <&syscrg SYSCRG_CLK_USB_WRAP_480>,
> + <&syscrg SYSCRG_CLK_USB_WRAP_625>,
> + <&syscrg SYSCRG_CLK_USB_WRAP_240>,
> + <&syscrg SYSCRG_CLK_USB_WRAP_60>,
> + <&syscrg SYSCRG_CLK_USB_WRAP_156P25>,
> + <&syscrg SYSCRG_CLK_USB_WRAP_312P5>,
> + <&syscrg SYSCRG_CLK_USB_125M>,
> + <&syscrg_nw SYSCRG_NW_CLK_GPIO_100>,
> + <&syscrg SYSCRG_CLK_PERH_ROOT>, <&syscrg SYSCRG_CLK_MCLK>,
> + <&syscrg SYSCRG_CLK_PERH_ROOT_PREOSC>,
> + <&syscrg SYSCRG_CLK_AHB0>,
> + <&syscrg SYSCRG_CLK_APB_BUS_PER1>,
> + <&syscrg SYSCRG_CLK_APB_BUS_PER2>,
> + <&syscrg SYSCRG_CLK_APB_BUS_PER3>,
> + <&syscrg SYSCRG_CLK_APB_BUS_PER5>,
> + <&syscrg SYSCRG_CLK_VENC_ROOT>,
> + <&syscrg SYSCRG_CLK_SPI_CORE_100>,
> + <&clk_glb_ext_clk>, <&clk_usb3_tap_tck_ext>,
> + <&clk_usb1_tap_tck_ext>, <&clk_usb2_tap_tck_ext>,
> + <&clk_typec_tap_tck_ext>, <&clk_spi_in0_ext>,
> + <&clk_spi_in1_ext>, <&clk_i2stx_bclk_ext>, <&clk_i2stx_lrck_ext>;
> + clock-names = "clk_osc", "sys_clk_axi_400",
> + "sys_clk_vout_root0", "sys_clk_vout_root1",
> + "sys_clk_usb_wrap_480", "sys_clk_usb_wrap_625",
> + "sys_clk_usb_wrap_240", "sys_clk_usb_wrap_60",
> + "sys_clk_usb_wrap_156p25", "sys_clk_usb_wrap_312p5",
> + "sys_clk_usb_125m", "sys_nw_clk_gpio_100",
> + "sys_clk_perh_root", "sys_clk_mclk",
> + "sys_clk_perh_root_preosc", "sys_clk_ahb0",
> + "sys_clk_apb_bus_per1", "sys_clk_apb_bus_per2",
> + "sys_clk_apb_bus_per3", "sys_clk_apb_bus_per5",
> + "sys_clk_venc_root", "sys_clk_spi_core_100",
> + "clk_glb_ext_clk", "clk_usb3_tap_tck_ext",
> + "clk_usb1_tap_tck_ext", "clk_usb2_tap_tck_ext",
> + "clk_typec_tap_tck_ext", "clk_spi_in0_ext",
> + "clk_spi_in1_ext", "clk_i2stx_bclk_ext",
> + "clk_i2stx_lrck_ext";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + syscrg_nw: syscrg_nw@123c0000 {
> + compatible = "starfive,jh8100-syscrg-nw";
> + reg = <0x0 0x123c0000 0x0 0x10000>;
> + clocks = <&clk_osc>, <&syscrg SYSCRG_CLK_APB_BUS>,
> + <&syscrg SYSCRG_CLK_ISP_2X>, <&syscrg SYSCRG_CLK_ISP_AXI>,
> + <&syscrg SYSCRG_CLK_VOUT_ROOT0>, <&syscrg SYSCRG_CLK_VOUT_ROOT1>,
> + <&syscrg SYSCRG_CLK_VOUT_SCAN_ATS>,
> + <&syscrg SYSCRG_CLK_VOUT_DC_CORE>, <&syscrg SYSCRG_CLK_VOUT_AXI>,
> + <&syscrg SYSCRG_CLK_AXI_400>, <&syscrg SYSCRG_CLK_AXI_200>,
> + <&syscrg SYSCRG_CLK_PERH_ROOT_PREOSC>,
> + <&clk_dvp_ext>, <&clk_isp_dphy_tap_tck_ext>,
> + <&clk_glb_ext_clk>, <&clk_i2s_tscko>,
> + <&clk_vout_mipi_dphy_tap_tck_ext>, <&clk_vout_edp_tap_tck_ext>,
> + <&clk_spi_in2_ext>;
> + clock-names = "clk_osc", "sys_clk_apb_bus",
> + "sys_clk_isp_2x", "sys_clk_isp_axi",
> + "sys_clk_vout_root0", "sys_clk_vout_root1",
> + "sys_clk_vout_scan_ats", "sys_clk_vout_dc_core",
> + "sys_clk_vout_axi", "sys_clk_axi_400",
> + "sys_clk_axi_200", "sys_clk_perh_root_preosc", "clk_dvp_ext",
> + "clk_isp_dphy_tap_tck_ext", "clk_glb_ext_clk",
> + "clk_i2s_tscko", "clk_vout_mipi_dphy_tap_tck_ext",
> + "clk_vout_edp_tap_tck_ext", "clk_spi_in2_ext";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + syscrg: syscrg@126d0000 {
> + compatible = "starfive,jh8100-syscrg";
> + reg = <0x0 0x126d0000 0x0 0x10000>;
> + clocks = <&clk_osc>, <&clk_i2srx_bclk_ext>,
> + <&clk_i2srx_lrck_ext>, <&clk_mclk_ext>;
> + clock-names = "clk_osc", "clk_i2srx_bclk_ext",
> + "clk_i2srx_lrck_ext", "clk_mclk_ext";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + syscrg_sw: syscrg_sw@12720000 {
> + compatible = "starfive,jh8100-syscrg-sw";
> + reg = <0x0 0x12720000 0x0 0x10000>;
> + clocks = <&syscrg SYSCRG_CLK_APB_BUS>,
> + <&syscrg SYSCRG_CLK_VDEC_ROOT>,
> + <&syscrg SYSCRG_CLK_FLEXNOC1>;
> + clock-names = "sys_clk_apb_bus",
> + "sys_clk_vdec_root",
> + "sys_clk_flexnoc1";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> uart5: serial@127d0000 {
> compatible = "starfive,jh8100-uart", "cdns,uart-r1p8";
> reg = <0x0 0x127d0000 0x0 0x10000>;
> @@ -374,5 +475,19 @@ uart6: serial@127e0000 {
> interrupts = <73>;
> status = "disabled";
> };
> +
> + aoncrg: aoncrg@1f310000 {
> + compatible = "starfive,jh8100-aoncrg";
> + reg = <0x0 0x1f310000 0x0 0x10000>;
> + clocks = <&clk_osc>, <&clk_gmac0_rmii_func>,
> + <&clk_gmac0_rgmii_func>, <&clk_aon125>,
> + <&clk_aon2000>, <&clk_aon200>,
> + <&clk_aon667>, <&clk_rtc>;
> + clock-names = "clk_osc", "clk_gmac0_rmii_func", "clk_gmac0_rgmii_func",
> + "clk_aon125", "clk_aon2000", "clk_aon200",
> + "clk_aon667", "clk_rtc";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> };
> };
> --
> 2.34.1
>
Sia Jee Heng wrote:
> This patch series enabled basic clock & reset support for StarFive
> JH8100 SoC.
>
> This patch series depends on the Initial device tree support for
> StarFive JH8100 SoC patch series which can be found at below link:
> https://lore.kernel.org/lkml/[email protected]/
>
> StarFive JH8100 shares a similar clock and reset design with JH7110.
> To facilitate the reuse of the file and its functionalities, files
> containing the 'jh71x0' naming convention are renamed to use the
> 'common' wording. Internal functions that contain the 'jh71x0'
> naming convention are renamed to use 'starfive.' This is accomplished
> through patches 1, 2, 3, and 4.
I'm a little sceptical all this renaming is worth it, but if think it's likely
that future starfive SoCs can use the same clock drivers I'm ok with it. Just
know that you'll look a bit silly if your "JH9100" can't use these drivers and
you'll already need different starfive and starfive-gen2 drivers.
/Emil
>
>
> Patch 5 adds documentation to describe System (SYSCRG) Clock & Reset
> binding.
> Patch 6 adds SYSCRG clock driver.
>
> patch 7 adds documentation to describe System-North-West (SYSCRG-NW)
> Clock & Reset binding.
> Patch 8 adds SYSCRG-NW clock driver.
>
> patch 9 adds documentation to describe System-North-East (SYSCRG-NE)
> Clock & Reset binding.
> Patch 10 adds SYSCRG-NE clock driver.
>
> patch 11 adds documentation to describe System-South-West (SYSCRG-SW)
> Clock & Reset binding.
> Patch 12 adds SYSCRG-SW clock driver.
>
> patch 13 adds documentation to describe Always-On (AON)
> Clock & Reset binding.
> Patch 14 adds AON clock driver.
>
> Patch 15 adds support for the auxiliary reset driver.
>
> Patch 16 adds clocks and reset nodes to the JH8100 device tree.
>
> Sia Jee Heng (16):
> reset: starfive: Rename file name "jh71x0" to "common"
> reset: starfive: Convert the word "jh71x0" to "starfive"
> clk: starfive: Rename file name "jh71x0" to "common"
> clk: starfive: Convert the word "jh71x0" to "starfive"
> dt-bindings: clock: Add StarFive JH8100 System clock and reset
> generator
> clk: starfive: Add JH8100 System clock generator driver
> dt-bindings: clock: Add StarFive JH8100 System-North-West clock and
> reset generator
> clk: starfive: Add JH8100 System-North-West clock generator driver
> dt-bindings: clock: Add StarFive JH8100 System-North-East clock and
> reset generator
> clk: starfive: Add JH8100 System-North-East clock generator driver
> dt-bindings: clock: Add StarFive JH8100 System-South-West clock and
> reset generator
> clk: starfive: Add JH8100 System-South-West clock generator driver
> dt-bindings: clock: Add StarFive JH8100 Always-On clock and reset
> generator
> clk: starfive: Add JH8100 Always-On clock generator driver
> reset: starfive: Add StarFive JH8100 reset driver
> riscv: dts: starfive: jh8100: Add clocks and resets nodes
>
> .../clock/starfive,jh8100-aoncrg.yaml | 77 +++
> .../clock/starfive,jh8100-syscrg-ne.yaml | 158 +++++
> .../clock/starfive,jh8100-syscrg-nw.yaml | 119 ++++
> .../clock/starfive,jh8100-syscrg-sw.yaml | 66 ++
> .../clock/starfive,jh8100-syscrg.yaml | 66 ++
> MAINTAINERS | 15 +
> arch/riscv/boot/dts/starfive/jh8100-clk.dtsi | 180 ++++++
> arch/riscv/boot/dts/starfive/jh8100.dtsi | 115 ++++
> drivers/clk/starfive/Kconfig | 49 +-
> drivers/clk/starfive/Makefile | 3 +-
> drivers/clk/starfive/clk-starfive-common.c | 327 ++++++++++
> drivers/clk/starfive/clk-starfive-common.h | 130 ++++
> .../clk/starfive/clk-starfive-jh7100-audio.c | 127 ++--
> drivers/clk/starfive/clk-starfive-jh7100.c | 503 ++++++++--------
> .../clk/starfive/clk-starfive-jh7110-aon.c | 62 +-
> .../clk/starfive/clk-starfive-jh7110-isp.c | 72 +--
> .../clk/starfive/clk-starfive-jh7110-stg.c | 94 +--
> .../clk/starfive/clk-starfive-jh7110-sys.c | 523 ++++++++--------
> .../clk/starfive/clk-starfive-jh7110-vout.c | 74 +--
> drivers/clk/starfive/clk-starfive-jh7110.h | 4 +-
> drivers/clk/starfive/clk-starfive-jh71x0.c | 327 ----------
> drivers/clk/starfive/clk-starfive-jh71x0.h | 123 ----
> drivers/clk/starfive/jh8100/Makefile | 7 +
> drivers/clk/starfive/jh8100/clk-aon.c | 275 +++++++++
> .../clk/starfive/jh8100/clk-starfive-jh8100.h | 11 +
> drivers/clk/starfive/jh8100/clk-sys-ne.c | 566 ++++++++++++++++++
> drivers/clk/starfive/jh8100/clk-sys-nw.c | 268 +++++++++
> drivers/clk/starfive/jh8100/clk-sys-sw.c | 136 +++++
> drivers/clk/starfive/jh8100/clk-sys.c | 455 ++++++++++++++
> drivers/reset/starfive/Kconfig | 14 +-
> drivers/reset/starfive/Makefile | 4 +-
> ...rfive-jh71x0.c => reset-starfive-common.c} | 68 +--
> .../reset/starfive/reset-starfive-common.h | 14 +
> .../reset/starfive/reset-starfive-jh7100.c | 4 +-
> .../reset/starfive/reset-starfive-jh7110.c | 8 +-
> .../reset/starfive/reset-starfive-jh71x0.h | 14 -
> .../reset/starfive/reset-starfive-jh8100.c | 102 ++++
> .../dt-bindings/clock/starfive,jh8100-crg.h | 430 +++++++++++++
> .../dt-bindings/reset/starfive,jh8100-crg.h | 127 ++++
> ...rfive-jh71x0.h => reset-starfive-common.h} | 10 +-
> 40 files changed, 4485 insertions(+), 1242 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-aoncrg.yaml
> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-ne.yaml
> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-nw.yaml
> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-sw.yaml
> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg.yaml
> create mode 100644 arch/riscv/boot/dts/starfive/jh8100-clk.dtsi
> create mode 100644 drivers/clk/starfive/clk-starfive-common.c
> create mode 100644 drivers/clk/starfive/clk-starfive-common.h
> delete mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.c
> delete mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.h
> create mode 100644 drivers/clk/starfive/jh8100/Makefile
> create mode 100644 drivers/clk/starfive/jh8100/clk-aon.c
> create mode 100644 drivers/clk/starfive/jh8100/clk-starfive-jh8100.h
> create mode 100644 drivers/clk/starfive/jh8100/clk-sys-ne.c
> create mode 100644 drivers/clk/starfive/jh8100/clk-sys-nw.c
> create mode 100644 drivers/clk/starfive/jh8100/clk-sys-sw.c
> create mode 100644 drivers/clk/starfive/jh8100/clk-sys.c
> rename drivers/reset/starfive/{reset-starfive-jh71x0.c => reset-starfive-common.c} (55%)
> create mode 100644 drivers/reset/starfive/reset-starfive-common.h
> delete mode 100644 drivers/reset/starfive/reset-starfive-jh71x0.h
> create mode 100644 drivers/reset/starfive/reset-starfive-jh8100.c
> create mode 100644 include/dt-bindings/clock/starfive,jh8100-crg.h
> create mode 100644 include/dt-bindings/reset/starfive,jh8100-crg.h
> rename include/soc/starfive/{reset-starfive-jh71x0.h => reset-starfive-common.h} (50%)
>
> --
> 2.34.1
>
On 06/12/2023 12:49, Sia Jee Heng wrote:
> Add bindings for the System clocks and reset generator
> (SYSCRG) on JH8100 SoC.
>
> Signed-off-by: Sia Jee Heng <[email protected]>
> Reviewed-by: Ley Foon Tan <[email protected]>
> ---
...
> + clocks:
> + items:
> + - description: Main Oscillator (24 MHz)
> + - description: External I2S Rx BCLK clock
> + - description: External I2S Rx LRCK clock
> + - description: External MCLK clock
> +
> + clock-names:
> + items:
> + - const: clk_osc
> + - const: clk_i2srx_bclk_ext
> + - const: clk_i2srx_lrck_ext
> + - const: clk_mclk_ext
Drop clk_ prefixes everywhere.
> +
> + '#clock-cells':
> + const: 1
> + description:
> + See <dt-bindings/clock/starfive,jh8100-crg.h> for valid indices.
> +
> + '#reset-cells':
> + const: 1
> + description:
> + See <dt-bindings/reset/starfive-jh8100-crg.h> for valid indices.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - '#clock-cells'
> + - '#reset-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/starfive,jh8100-crg.h>
> +
> + clock-controller@126d0000 {
> + compatible = "starfive,jh8100-syscrg";
Use 4 spaces for example indentation.
> + reg = <0x126d0000 0x10000>;
> + clocks = <&clk_osc>, <&clk_i2srx_bclk_ext>,
> + <&clk_i2srx_lrck_ext>, <&clk_mclk_ext>;
> + clock-names = "clk_osc", "clk_i2srx_bclk_ext",
> + "clk_i2srx_lrck_ext", "clk_mclk_ext";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h
> new file mode 100644
> index 000000000000..e5bb588ce798
> --- /dev/null
> +++ b/include/dt-bindings/clock/starfive,jh8100-crg.h
> @@ -0,0 +1,123 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR MIT */
How about keeping the same license as binding?
> +/*
> + * Copyright (C) 2023 StarFive Technology Co., Ltd.
> + * Sia Jee Heng <[email protected]>
> + *
> + */
> +
...
> +#define SYSCRG_CLK_NNE_ICG_EN 108
> +
> +#define SYSCRG_CLK_END 109
Drop from binding header.
> +#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */
...
> + */
> +#define SYSCRG_RSTN_SYS_SYSCON 0
> +#define SYSCRG_RSTN_CLK_MOD 1
> +#define SYSCRG_RSTN_GPU 2
> +#define SYSCRG_RSTN_GPU_SPU 3
> +#define SYSCRG_RSTN_GPU_TVSENSOR 4
> +#define SYSCRG_RSTN_PPU_OP_NORET_GPU_RESET 5
> +#define SYSCRG_RSTN_NNE 6
> +#define SYSCRG_RSTN_HD_AUDIO 7
> +
> +#define SYSCRG_RESET_NR_RESETS 8
Drop from binding header.
> +
> +#endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */
Best regards,
Krzysztof
On 06/12/2023 12:49, Sia Jee Heng wrote:
> Add bindings for the System-North-West clock and reset generator
> (SYSCRG-NW) on JH8100 SoC.
>
> Signed-off-by: Sia Jee Heng <[email protected]>
> Reviewed-by: Ley Foon Tan <[email protected]>
> ---
> .../clock/starfive,jh8100-syscrg-nw.yaml | 119 ++++++++++++++++++
> .../dt-bindings/clock/starfive,jh8100-crg.h | 45 +++++++
> .../dt-bindings/reset/starfive,jh8100-crg.h | 15 +++
> 3 files changed, 179 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-nw.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-nw.yaml b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-nw.yaml
> new file mode 100644
> index 000000000000..b16a874828dd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-nw.yaml
> @@ -0,0 +1,119 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/starfive,jh8100-syscrg-nw.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH8100 System-North-West Clock and Reset Generator
> +
> +maintainers:
> + - Sia Jee Heng <[email protected]>
> +
> +properties:
> + compatible:
> + const: starfive,jh8100-syscrg-nw
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Main Oscillator (24 MHz)
> + - description: APB_BUS clock from SYSCRG
> + - description: ISP_2X clock from SYSCRG
> + - description: ISP_AXI clock from SYSCRG
> + - description: VOUT_ROOT0 clock from SYSCRG
> + - description: VOUT_ROOT1 clock from SYSCRG
> + - description: VOUT_SCAN_ATS clock from SYSCRG
> + - description: VOUT_DC_CORE clock from SYSCRG
> + - description: VOUT_AXI clock from SYSCRG
> + - description: AXI_400 clock from SYSCRG
> + - description: AXI_200 clock from SYSCRG
> + - description: Peripheral clock from SYSCRG
> + - description: External DVP clock
> + - description: External ISP DPHY TAP TCK clock
> + - description: External golbal clock
> + - description: External i2s_tscko clock
> + - description: External VOUT MIPI DPHY TAP TCK
> + - description: External VOUT eDP TAP TCK
> + - description: External SPI In2 clock
> +
> + clock-names:
> + items:
> + - const: clk_osc
> + - const: sys_clk_apb_bus
> + - const: sys_clk_isp_2x
> + - const: sys_clk_isp_axi
> + - const: sys_clk_vout_root0
> + - const: sys_clk_vout_root1
> + - const: sys_clk_vout_scan_ats
> + - const: sys_clk_vout_dc_core
> + - const: sys_clk_vout_axi
> + - const: sys_clk_axi_400
> + - const: sys_clk_axi_200
> + - const: sys_clk_perh_root_preosc
> + - const: clk_dvp_ext
> + - const: clk_isp_dphy_tap_tck_ext
> + - const: clk_glb_ext_clk
> + - const: clk_i2s_tscko
> + - const: clk_vout_mipi_dphy_tap_tck_ext
> + - const: clk_vout_edp_tap_tck_ext
> + - const: clk_spi_in2_ext
Same comments as for other patch.
> +
> + '#clock-cells':
> + const: 1
> + description:
> + See <dt-bindings/clock/starfive,jh8100-crg.h> for valid indices.
> +
> + '#reset-cells':
> + const: 1
> + description:
> + See <dt-bindings/reset/starfive,jh8100-crg.h> for valid indices.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - '#clock-cells'
> + - '#reset-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/starfive,jh8100-crg.h>
> +
> + clock-controller@123c0000 {
> + compatible = "starfive,jh8100-syscrg-nw";
Same comments as for other patch.
> + reg = <0x123c0000 0x10000>;
> + clocks = <&clk_osc>, <&syscrg SYSCRG_CLK_APB_BUS>,
> + <&syscrg SYSCRG_CLK_ISP_2X>,
> + <&syscrg SYSCRG_CLK_ISP_AXI>,
> + <&syscrg SYSCRG_CLK_VOUT_ROOT0>,
> + <&syscrg SYSCRG_CLK_VOUT_ROOT1>,
> + <&syscrg SYSCRG_CLK_VOUT_SCAN_ATS>,
> + <&syscrg SYSCRG_CLK_VOUT_DC_CORE>,
> + <&syscrg SYSCRG_CLK_VOUT_AXI>,
> + <&syscrg SYSCRG_CLK_AXI_400>,
> + <&syscrg SYSCRG_CLK_AXI_200>,
> + <&syscrg SYSCRG_CLK_PERH_ROOT_PREOSC>,
> + <&clk_dvp_ext>,
> + <&clk_isp_dphy_tap_tck_ext>,
> + <&clk_glb_ext_clk>,
> + <&clk_i2s_tscko>,
> + <&clk_vout_mipi_dphy_tap_tck_ext>,
> + <&clk_vout_edp_tap_tck_ext>,
> + <&clk_spi_in2_ext>;
> + clock-names = "clk_osc", "sys_clk_apb_bus", "sys_clk_isp_2x",
> + "sys_clk_isp_axi", "sys_clk_vout_root0",
> + "sys_clk_vout_root1", "sys_clk_vout_scan_ats",
> + "sys_clk_vout_dc_core", "sys_clk_vout_axi",
> + "sys_clk_axi_400", "sys_clk_axi_200",
> + "sys_clk_perh_root_preosc", "clk_dvp_ext",
> + "clk_isp_dphy_tap_tck_ext", "clk_glb_ext_clk",
> + "clk_i2s_tscko", "clk_vout_mipi_dphy_tap_tck_ext",
> + "clk_vout_edp_tap_tck_ext", "clk_spi_in2_ext";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h
> index e5bb588ce798..8417455c2409 100644
> --- a/include/dt-bindings/clock/starfive,jh8100-crg.h
> +++ b/include/dt-bindings/clock/starfive,jh8100-crg.h
> @@ -120,4 +120,49 @@
> #define SYSCRG_CLK_NNE_ICG_EN 108
>
> #define SYSCRG_CLK_END 109
> +
> +/* SYSCRG_NW_CLK */
> +#define SYSCRG_NW_CLK_PLL5_DIV2 0
> +#define SYSCRG_NW_CLK_GCLK5 1
> +#define SYSCRG_NW_CLK_GPIO_100 2
> +#define SYSCRG_NW_CLK_GPIO_50 3
> +#define SYSCRG_NW_CLK_GPIO_150 4
> +#define SYSCRG_NW_CLK_GPIO_60 5
> +#define SYSCRG_NW_CLK_IOMUX_WEST_PCLK 6
> +#define SYSCRG_NW_CLK_I2C6_APB 7
> +#define SYSCRG_NW_CLK_I2C7_APB 8
> +#define SYSCRG_NW_CLK_SPI2_APB 9
> +#define SYSCRG_NW_CLK_SPI2_CORE 10
> +#define SYSCRG_NW_CLK_SPI2_SCLK_IN 11
> +#define SYSCRG_NW_CLK_SMBUS1_APB 12
> +#define SYSCRG_NW_CLK_SMBUS1_CORE 13
> +#define SYSCRG_NW_CLK_ISP_DVP 14
> +#define SYSCRG_NW_CLK_ISP_CORE_2X 15
> +#define SYSCRG_NW_CLK_ISP_AXI 16
> +#define SYSCRG_NW_CLK_ISP_DPHY_TAP_TCK 17
> +#define SYSCRG_NW_CLK_FLEXNOC_ISPSLV 18
> +#define SYSCRG_NW_CLK_VOUT_PIX0 19
> +#define SYSCRG_NW_CLK_VOUT_PIX1 20
> +#define SYSCRG_NW_CLK_VOUT_SCAN_ATS 21
> +#define SYSCRG_NW_CLK_VOUT_DC_CORE 22
> +#define SYSCRG_NW_CLK_VOUT_APB 23
> +#define SYSCRG_NW_CLK_VOUT_DSI 24
> +#define SYSCRG_NW_CLK_VOUT_AHB 25
> +#define SYSCRG_NW_CLK_VOUT_AXI 26
> +#define SYSCRG_NW_CLK_VOUT_MIPI_DPHY_TAP_TCK 27
> +#define SYSCRG_NW_CLK_VOUT_EDP_PHY_TAP_TCK 28
> +#define SYSCRG_NW_CLK_UART5_CORE_PREOSC 29
> +#define SYSCRG_NW_CLK_UART5_APB 30
> +#define SYSCRG_NW_CLK_UART5_CORE 31
> +#define SYSCRG_NW_CLK_UART6_CORE_PREOSC 32
> +#define SYSCRG_NW_CLK_UART6_APB 33
> +#define SYSCRG_NW_CLK_UART6_CORE 34
> +#define SYSCRG_NW_CLK_SPI2_ICG_EN 35
> +#define SYSCRG_NW_CLK_SMBUS1_ICG_EN 36
> +#define SYSCRG_NW_CLK_ISP_ICG_EN 37
> +#define SYSCRG_NW_CLK_VOUT_ICG_EN 38
> +#define SYSCRG_NW_CLK_UART5_ICG_EN 39
> +#define SYSCRG_NW_CLK_UART6_ICG_EN 40
> +
> +#define SYSCRG_NW_CLK_END 41
Same comments as for other patch.
> #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */
> diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h
> index 3b7b92488e76..8c3a858bdf6a 100644
> --- a/include/dt-bindings/reset/starfive,jh8100-crg.h
> +++ b/include/dt-bindings/reset/starfive,jh8100-crg.h
> @@ -20,4 +20,19 @@
>
> #define SYSCRG_RESET_NR_RESETS 8
>
> +/*
> + * syscrg_nw: assert0
> + */
> +#define SYSCRG_NW_RSTN_PRESETN 0
> +#define SYSCRG_NW_RSTN_SYS_IOMUX_W 1
> +#define SYSCRG_NW_RSTN_I2C6 2
> +#define SYSCRG_NW_RSTN_I2C7 3
> +#define SYSCRG_NW_RSTN_SPI2 4
> +#define SYSCRG_NW_RSTN_SMBUS1 5
> +#define SYSCRG_NW_RSTN_UART5 6
> +#define SYSCRG_NW_RSTN_UART6 7
> +#define SYSCRG_NW_RSTN_MERAK0_TVSENSOR 8
> +#define SYSCRG_NW_RSTN_MERAK1_TVSENSOR 9
> +
> +#define SYSCRG_NW_RESET_NR_RESETS 10
Same comments as for other patch.
Best regards,
Krzysztof
On 06/12/2023 12:49, Sia Jee Heng wrote:
> Add bindings for the System-North-East clock and reset generator
> (SYSCRG-NE) on JH8100 SoC.
>
> Signed-off-by: Sia Jee Heng <[email protected]>
> Reviewed-by: Ley Foon Tan <[email protected]>
> ---
> .../clock/starfive,jh8100-syscrg-ne.yaml | 158 ++++++++++++++++
> .../dt-bindings/clock/starfive,jh8100-crg.h | 179 ++++++++++++++++++
> .../dt-bindings/reset/starfive,jh8100-crg.h | 61 ++++++
All my previous comments are applicable.
Best regards,
Krzysztof
On 06/12/2023 12:49, Sia Jee Heng wrote:
> Add bindings for the System-South-West clock and reset generator
> (SYSCRG-SW) on JH8100 SoC.
>
> Signed-off-by: Sia Jee Heng <[email protected]>
> Reviewed-by: Ley Foon Tan <[email protected]>
> ---
All my previous comments are applicable.
Best regards,
Krzysztof
On 06/12/2023 12:49, Sia Jee Heng wrote:
> Add bindings for the Always-On clock and reset generator
> (AONCRG) on JH8100 SoC.
>
> Signed-off-by: Sia Jee Heng <[email protected]>
> Reviewed-by: Ley Foon Tan <[email protected]>
All my previous comments are applicable.
Best regards,
Krzysztof
On 06/12/2023 12:50, Sia Jee Heng wrote:
> Add SYSCRG/SYSCRG-NE/SYSCRG-NW/SYSCRG-SW/AONCRG clock and reset
> nodes for JH8100 RISC-V SoC.
>
> Signed-off-by: Sia Jee Heng <[email protected]>
> Reviewed-by: Ley Foon Tan <[email protected]>
Really? Looks automated... Care to provide any links to effects of
internal review?
> ---
> arch/riscv/boot/dts/starfive/jh8100-clk.dtsi | 180 +++++++++++++++++++
> arch/riscv/boot/dts/starfive/jh8100.dtsi | 115 ++++++++++++
> 2 files changed, 295 insertions(+)
> create mode 100644 arch/riscv/boot/dts/starfive/jh8100-clk.dtsi
>
> diff --git a/arch/riscv/boot/dts/starfive/jh8100-clk.dtsi b/arch/riscv/boot/dts/starfive/jh8100-clk.dtsi
> new file mode 100644
> index 000000000000..27ba249f523e
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh8100-clk.dtsi
> @@ -0,0 +1,180 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2023 StarFive Technology Co., Ltd.
> + */
> +
> +/ {
> + clk_osc: clk_osc {
No underscores in node names.
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24000000>;
> + };
> +
...
> diff --git a/arch/riscv/boot/dts/starfive/jh8100.dtsi b/arch/riscv/boot/dts/starfive/jh8100.dtsi
> index f26aff5c1ddf..9863c61324a0 100644
> --- a/arch/riscv/boot/dts/starfive/jh8100.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh8100.dtsi
> @@ -4,6 +4,9 @@
> */
>
> /dts-v1/;
> +#include <dt-bindings/clock/starfive,jh8100-crg.h>
> +#include <dt-bindings/reset/starfive,jh8100-crg.h>
> +#include "jh8100-clk.dtsi"
>
> / {
> compatible = "starfive,jh8100";
> @@ -357,6 +360,104 @@ uart4: serial@121a0000 {
> status = "disabled";
> };
>
> + syscrg_ne: syscrg_ne@12320000 {
clock-controller@
Just open your bindings and take a look how it is done there...
This applies everywhere
Best regards,
Krzysztof
On 08/12/2023 17:39, Emil Renner Berthing wrote:
> Sia Jee Heng wrote:
>> Add SYSCRG/SYSCRG-NE/SYSCRG-NW/SYSCRG-SW/AONCRG clock and reset
>> nodes for JH8100 RISC-V SoC.
>>
>> Signed-off-by: Sia Jee Heng <[email protected]>
>> Reviewed-by: Ley Foon Tan <[email protected]>
>> ---
>> arch/riscv/boot/dts/starfive/jh8100-clk.dtsi | 180 +++++++++++++++++++
>> arch/riscv/boot/dts/starfive/jh8100.dtsi | 115 ++++++++++++
>
> Why the split here? I mean why can't the clocks just be in the jh8100.dtsi?
There should be. What's the point? Clocks are internal part of SoC and
not really re-usable piece of hardware.
Best regards,
Krzysztof
> -----Original Message-----
> From: Emil Renner Berthing <[email protected]>
> Sent: Saturday, December 9, 2023 12:25 AM
> To: JeeHeng Sia <[email protected]>; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> <[email protected]>; Xingyu Wu <[email protected]>
> Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon Tan
> <[email protected]>
> Subject: Re: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver
>
> Sia Jee Heng wrote:
> > Add support for JH8100 System clock generator.
> >
> > Signed-off-by: Sia Jee Heng <[email protected]>
> > Reviewed-by: Ley Foon Tan <[email protected]>
> > ---
> > MAINTAINERS | 8 +
> > drivers/clk/starfive/Kconfig | 9 +
> > drivers/clk/starfive/Makefile | 1 +
> > drivers/clk/starfive/clk-starfive-common.h | 9 +-
> > drivers/clk/starfive/jh8100/Makefile | 3 +
> > .../clk/starfive/jh8100/clk-starfive-jh8100.h | 11 +
> > drivers/clk/starfive/jh8100/clk-sys.c | 455 ++++++++++++++++++
> > 7 files changed, 495 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/clk/starfive/jh8100/Makefile
> > create mode 100644 drivers/clk/starfive/jh8100/clk-starfive-jh8100.h
> > create mode 100644 drivers/clk/starfive/jh8100/clk-sys.c
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 788be9ab5b73..87bcb25becc1 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -20763,6 +20763,14 @@ F: Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
> > F: drivers/phy/starfive/phy-jh7110-pcie.c
> > F: drivers/phy/starfive/phy-jh7110-usb.c
> >
> > +STARFIVE JH8100 CLOCK DRIVERS
> > +M: Sia Jee Heng <[email protected]>
> > +M: Ley Foon Tan <[email protected]>
> > +S: Maintained
> > +F: Documentation/devicetree/bindings/clock/starfive,jh81*.yaml
> > +F: drivers/clk/starfive/jh8100
> > +F: include/dt-bindings/clock/starfive?jh81*.h
> > +
> > STATIC BRANCH/CALL
> > M: Peter Zijlstra <[email protected]>
> > M: Josh Poimboeuf <[email protected]>
> > diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
> > index ff8eace36e64..d8c7b9bb3895 100644
> > --- a/drivers/clk/starfive/Kconfig
> > +++ b/drivers/clk/starfive/Kconfig
> > @@ -72,3 +72,12 @@ config CLK_STARFIVE_JH7110_VOUT
> > help
> > Say yes here to support the Video-Output clock controller
> > on the StarFive JH7110 SoC.
> > +
> > +config CLK_STARFIVE_JH8100_SYS
> > + bool "StarFive JH8100 System clock support"
> > + depends on SOC_STARFIVE || COMPILE_TEST
> > + select AUXILIARY_BUS
> > + select CLK_STARFIVE_COMMON
> > + default ARCH_STARFIVE
> > + help
> > + Say yes here to support the System clock controller on the StarFive JH8100 SoC.
> > diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
> > index 012f7ee83f8e..6cb3ce823330 100644
> > --- a/drivers/clk/starfive/Makefile
> > +++ b/drivers/clk/starfive/Makefile
> > @@ -10,3 +10,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
> > obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o
> > obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o
> > obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
> > +obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS) += jh8100/
>
> I don't really see why do you need a special subdirectory for the JH8100? The
> JH7110 drivers do fine without it.
Each subfolder can represent a different platform, making it easier to
locate and maintain platform-specific code. Since the code is expected
to grow in the future, let's start organizing it in a folder-based structure
for easier maintenance at a later stage.
>
> > diff --git a/drivers/clk/starfive/clk-starfive-common.h b/drivers/clk/starfive/clk-starfive-common.h
> > index fed45311360c..ec30af0658cf 100644
> > --- a/drivers/clk/starfive/clk-starfive-common.h
> > +++ b/drivers/clk/starfive/clk-starfive-common.h
> > @@ -103,6 +103,13 @@ struct starfive_clk_data {
> > .parents = { [0] = _parent }, \
> > }
> >
> > +#define STARFIVE_GINV(_idx, _name, _flags, _parent)[_idx] = { \
> > + .name = _name, \
> > + .flags = _flags, \
> > + .max = STARFIVE_CLK_ENABLE | STARFIVE_CLK_INVERT, \
> > + .parents = { [0] = _parent }, \
> > +}
> > +
> > struct starfive_clk {
> > struct clk_hw hw;
> > unsigned int idx;
> > @@ -114,7 +121,7 @@ struct starfive_clk_priv {
> > spinlock_t rmw_lock;
> > struct device *dev;
> > void __iomem *base;
> > - struct clk_hw *pll[3];
> > + struct clk_hw *pll[8];
>
> These extra slots are just used for fixed factor dummy PLLs right now, similar
> to how the JH7110 first used them and later had to rework drivers and device
> trees for the proper PLL driver.
Yes, its intention is similar to JH8100. We will submit other clock
domains and PLL at later stage but not so soon.
>
> This time around I'd much rather you work on getting the PLL driver in first,
> so we don't need all that churn.
I am sorry but we started development on FPGA. Unfortunately, the PLL driver
and other domains are planned to be finished at a later stage. I have tried
to minimize the churn as much as possible.
>
> > struct starfive_clk reg[];
> > };
> >
> > diff --git a/drivers/clk/starfive/jh8100/Makefile b/drivers/clk/starfive/jh8100/Makefile
> > new file mode 100644
> > index 000000000000..af6a09e220d3
> > --- /dev/null
> > +++ b/drivers/clk/starfive/jh8100/Makefile
> > @@ -0,0 +1,3 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +# StarFive JH8100 Clock
> > +obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS) += clk-sys.o
>
> This will name the module clk-sys, which is way too generic. Please name this
> clk-starfive-jh8100-sys similar to the JH7110 drivers.
>
> > diff --git a/drivers/clk/starfive/jh8100/clk-starfive-jh8100.h b/drivers/clk/starfive/jh8100/clk-starfive-jh8100.h
> > new file mode 100644
> > index 000000000000..7c8249c11464
> > --- /dev/null
> > +++ b/drivers/clk/starfive/jh8100/clk-starfive-jh8100.h
> > @@ -0,0 +1,11 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +#ifndef __CLK_STARFIVE_JH8100_H
> > +#define __CLK_STARFIVE_JH8100_H
> > +
> > +#include "../clk-starfive-common.h"
> > +
> > +int jh8100_reset_controller_register(struct starfive_clk_priv *priv,
> > + const char *adev_name,
> > + u32 adev_id);
> > +
> > +#endif
> > diff --git a/drivers/clk/starfive/jh8100/clk-sys.c b/drivers/clk/starfive/jh8100/clk-sys.c
> > new file mode 100644
> > index 000000000000..e2c802523c7d
> > --- /dev/null
> > +++ b/drivers/clk/starfive/jh8100/clk-sys.c
> > @@ -0,0 +1,455 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * StarFive JH8100 System Clock Driver
> > + *
> > + * Copyright (C) 2023 StarFive Technology Co., Ltd.
> > + *
> > + * Author: Jee Heng Sia <[email protected]>
> > + *
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/auxiliary_bus.h>
> > +#include <linux/clk-provider.h>
> > +#include <linux/init.h>
> > +#include <linux/io.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/slab.h>
> > +
> > +#include <soc/starfive/reset-starfive-common.h>
> > +
> > +#include <dt-bindings/clock/starfive,jh8100-crg.h>
> > +
> > +#include "clk-starfive-jh8100.h"
> > +
> > +/* external clocks */
> > +#define SYSCRG_CLK_OSC (SYSCRG_CLK_END + 0)
> > +#define SYSCRG_CLK_MCLK_EXT (SYSCRG_CLK_END + 1)
> > +#define SYSCRG_CLK_PLL0_OUT (SYSCRG_CLK_END + 2)
> > +#define SYSCRG_CLK_PLL1_OUT (SYSCRG_CLK_END + 3)
> > +#define SYSCRG_CLK_PLL2_OUT (SYSCRG_CLK_END + 4)
> > +#define SYSCRG_CLK_PLL3_OUT (SYSCRG_CLK_END + 5)
> > +#define SYSCRG_CLK_PLL4_OUT (SYSCRG_CLK_END + 6)
> > +#define SYSCRG_CLK_PLL6_OUT (SYSCRG_CLK_END + 7)
> > +#define SYSCRG_CLK_PLL7_OUT (SYSCRG_CLK_END + 8)
> > +
> > +static const struct starfive_clk_data jh8100_syscrg_clk_data[] __initconst = {
> > + /* root */
> > + STARFIVE__DIV(SYSCRG_CLK_VDEC_ROOT_PREOSC, "sys_clk_vdec_root_preosc", 10,
> > + SYSCRG_CLK_PLL7_OUT),
> > + STARFIVE__MUX(SYSCRG_CLK_VDEC_ROOT, "sys_clk_vdec_root", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_VDEC_ROOT_PREOSC),
> > + STARFIVE__DIV(SYSCRG_CLK_VENC_ROOT_PREOSC, "sys_clk_venc_root_preosc", 10,
> > + SYSCRG_CLK_PLL7_OUT),
> > + STARFIVE__MUX(SYSCRG_CLK_VENC_ROOT, "sys_clk_venc_root", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_VENC_ROOT_PREOSC),
> > + STARFIVE__DIV(SYSCRG_CLK_GPU_ROOT, "sys_clk_gpu_root", 7,
> > + SYSCRG_CLK_PLL0_OUT),
> > + STARFIVE__MUX(SYSCRG_CLK_GPU_CORE, "sys_clk_gpu_core", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_GPU_ROOT),
> > + STARFIVE__DIV(SYSCRG_CLK_VOUT_ROOT0_PREOSC, "sys_clk_vout_root0_preosc", 127,
> > + SYSCRG_CLK_PLL1_OUT),
> > + STARFIVE__MUX(SYSCRG_CLK_VOUT_ROOT0, "sys_clk_vout_root0", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_VOUT_ROOT0_PREOSC),
> > + STARFIVE__DIV(SYSCRG_CLK_VOUT_ROOT1_PREOSC, "sys_clk_vout_root1_preosc", 127,
> > + SYSCRG_CLK_PLL6_OUT),
> > + STARFIVE__MUX(SYSCRG_CLK_VOUT_ROOT1, "sys_clk_vout_root1", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_VOUT_ROOT1_PREOSC),
> > + STARFIVE__DIV(SYSCRG_CLK_VOUT_SCAN_ATS, "sys_clk_vout_scan_ats", 6,
> > + SYSCRG_CLK_PLL3_OUT),
> > + STARFIVE__DIV(SYSCRG_CLK_PERH_ROOT_PREOSC, "sys_clk_perh_root_preosc", 4,
> > + SYSCRG_CLK_PLL0_OUT),
> > + STARFIVE__MUX(SYSCRG_CLK_PERH_ROOT, "sys_clk_perh_root", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_PERH_ROOT_PREOSC),
> > + STARFIVE__DIV(SYSCRG_CLK_AXI_200_PREOSC, "sys_clk_axi_200_preosc", 4,
> > + SYSCRG_CLK_PLL0_OUT),
> > + STARFIVE__MUX(SYSCRG_CLK_AXI_200, "sys_clk_axi_200", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_200_PREOSC),
> > + STARFIVE__MUX(SYSCRG_CLK_AXI_200_GMAC, "sys_clk_axi_200_gmac", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_200_PREOSC),
> > + STARFIVE__DIV(SYSCRG_CLK_AXI_500_PREOSC, "sys_clk_axi_500_preosc", 10,
> > + SYSCRG_CLK_PLL0_OUT),
> > + STARFIVE__MUX(SYSCRG_CLK_AXI_500, "sys_clk_axi_500", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_500_PREOSC),
> > + STARFIVE__MUX(SYSCRG_CLK_AXI_500_PCIEX1A, "sys_clk_axi_500_pciex1a", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_500_PREOSC),
> > + STARFIVE__MUX(SYSCRG_CLK_AXI_500_PCIEX1B, "sys_clk_axi_500_pciex1b", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_500_PREOSC),
> > + STARFIVE__MUX(SYSCRG_CLK_AXI_500_PCIEX2, "sys_clk_axi_500_pciex2", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_500_PREOSC),
> > + STARFIVE__MUX(SYSCRG_CLK_AXI_500_PCIEX8, "sys_clk_axi_500_pciex8", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_500_PREOSC),
> > + STARFIVE__DIV(SYSCRG_CLK_AXI_400_PREOSC, "sys_clk_axi_400_preosc", 10,
> > + SYSCRG_CLK_PLL0_OUT),
> > + STARFIVE__MUX(SYSCRG_CLK_AXI_400, "sys_clk_axi_400", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_400_PREOSC),
> > + STARFIVE__MUX(SYSCRG_CLK_AXI_400_APBOOTRAM, "sys_clk_axi_400_apbootram", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_400_PREOSC),
> > + STARFIVE__DIV(SYSCRG_CLK_AXI_125_PREOSC, "sys_clk_axi_125_preosc", 32,
> > + SYSCRG_CLK_PLL0_OUT),
> > + STARFIVE__MUX(SYSCRG_CLK_AXI_125, "sys_clk_axi_125", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_AXI_125_PREOSC),
> > + STARFIVE__DIV(SYSCRG_CLK_AHB0_PREOSC, "sys_clk_ahb0_preosc", 15,
> > + SYSCRG_CLK_PLL0_OUT),
> > + STARFIVE__MUX(SYSCRG_CLK_AHB0, "sys_clk_ahb0", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_AHB0_PREOSC),
> > + STARFIVE__DIV(SYSCRG_CLK_APB_BUS_FUNC, "sys_clk_apb_bus_func", 30,
> > + SYSCRG_CLK_PLL0_OUT),
> > + STARFIVE__MUX(SYSCRG_CLK_APB_BUS, "sys_clk_apb_bus", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
> > + STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER0, "sys_clk_apb_bus_per0", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
> > + STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER1, "sys_clk_apb_bus_per1", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
> > + STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER2, "sys_clk_apb_bus_per2", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
> > + STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER3, "sys_clk_apb_bus_per3", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
> > + STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER4, "sys_clk_apb_bus_per4", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
> > + STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER5, "sys_clk_apb_bus_per5", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
> > + STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER6, "sys_clk_apb_bus_per6", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
> > + STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER7, "sys_clk_apb_bus_per7", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
> > + STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER8, "sys_clk_apb_bus_per8", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
> > + STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER9, "sys_clk_apb_bus_per9", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
> > + STARFIVE__MUX(SYSCRG_CLK_APB_BUS_PER10, "sys_clk_apb_bus_per10", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
> > + STARFIVE__MUX(SYSCRG_CLK_SPI_CORE_100, "sys_clk_spi_core_100", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_APB_BUS_FUNC),
> > + STARFIVE__DIV(SYSCRG_CLK_PLL1_DIV2, "sys_clk_pll1_div2", 2,
> > + SYSCRG_CLK_PLL1_OUT),
> > + STARFIVE__DIV(SYSCRG_CLK_PLL2_DIV2, "sys_clk_pll2_div2", 2,
> > + SYSCRG_CLK_PLL2_OUT),
> > + STARFIVE__DIV(SYSCRG_CLK_PLL3_DIV2, "sys_clk_pll3_div2", 2,
> > + SYSCRG_CLK_PLL3_OUT),
> > + STARFIVE__DIV(SYSCRG_CLK_PLL4_DIV2, "sys_clk_pll4_div2", 2,
> > + SYSCRG_CLK_PLL4_OUT),
> > + STARFIVE__DIV(SYSCRG_CLK_PLL6_DIV2, "sys_clk_pll6_div2", 2,
> > + SYSCRG_CLK_PLL6_OUT),
> > + STARFIVE__DIV(SYSCRG_CLK_PLL7_DIV2, "sys_clk_pll7_div2", 2,
> > + SYSCRG_CLK_PLL7_OUT),
> > + STARFIVE__DIV(SYSCRG_CLK_AUDIO_ROOT, "sys_clk_audio_root", 8,
> > + SYSCRG_CLK_PLL2_OUT),
> > + STARFIVE__DIV(SYSCRG_CLK_MCLK_INNER, "sys_clk_mclk_inner", 64,
> > + SYSCRG_CLK_AUDIO_ROOT),
> > + STARFIVE__MUX(SYSCRG_CLK_MCLK, "sys_clk_mclk", 2,
> > + SYSCRG_CLK_MCLK_INNER, SYSCRG_CLK_MCLK_EXT),
> > + STARFIVE_GATE(SYSCRG_CLK_MCLK_OUT, "sys_clk_mclk_out", 0,
> > + SYSCRG_CLK_MCLK_INNER),
> > + STARFIVE_MDIV(SYSCRG_CLK_ISP_2X_PREOSC, "sys_clk_isp_2x_preosc", 8, 2,
> > + SYSCRG_CLK_PLL7_OUT, SYSCRG_CLK_PLL0_OUT),
> > + STARFIVE__MUX(SYSCRG_CLK_ISP_2X, "sys_clk_isp_2x", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_ISP_2X_PREOSC),
> > + STARFIVE__DIV(SYSCRG_CLK_ISP_AXI, "sys_clk_isp_axi", 4,
> > + SYSCRG_CLK_ISP_2X),
> > + STARFIVE_GDIV(SYSCRG_CLK_GCLK1, "sys_clk_gclk1", CLK_IS_CRITICAL, 120,
> > + SYSCRG_CLK_PLL1_DIV2),
> > + STARFIVE_GDIV(SYSCRG_CLK_GCLK2, "sys_clk_gclk2", CLK_IS_CRITICAL, 120,
> > + SYSCRG_CLK_PLL2_DIV2),
> > + STARFIVE_GDIV(SYSCRG_CLK_GCLK3, "sys_clk_gclk3", CLK_IS_CRITICAL, 120,
> > + SYSCRG_CLK_PLL3_DIV2),
> > + STARFIVE_GDIV(SYSCRG_CLK_GCLK4, "sys_clk_gclk4", CLK_IS_CRITICAL, 120,
> > + SYSCRG_CLK_PLL4_DIV2),
> > + STARFIVE_GDIV(SYSCRG_CLK_GCLK6, "sys_clk_gclk6", CLK_IS_CRITICAL, 120,
> > + SYSCRG_CLK_PLL6_DIV2),
> > + STARFIVE_GDIV(SYSCRG_CLK_GCLK7, "sys_clk_gclk7", CLK_IS_CRITICAL, 120,
> > + SYSCRG_CLK_PLL7_DIV2),
> > + /* flexnoc (se) */
> > + STARFIVE__DIV(SYSCRG_CLK_FLEXNOC0_PREOSC, "sys_clk_flexnoc0_preosc", 8,
> > + SYSCRG_CLK_PLL0_OUT),
> > + STARFIVE__MUX(SYSCRG_CLK_FLEXNOC0, "sys_clk_flexnoc0", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_FLEXNOC0_PREOSC),
> > + STARFIVE__DIV(SYSCRG_CLK_FLEXNOC1_PREOSC, "sys_clk_flexnoc1_preosc", 8,
> > + SYSCRG_CLK_PLL0_OUT),
> > + STARFIVE__MUX(SYSCRG_CLK_FLEXNOC1, "sys_clk_flexnoc1", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_FLEXNOC1_PREOSC),
> > + STARFIVE__DIV(SYSCRG_CLK_FLEXNOC2_PREOSC, "sys_clk_flexnoc2_preosc", 12,
> > + SYSCRG_CLK_PLL0_OUT),
> > + STARFIVE__MUX(SYSCRG_CLK_FLEXNOC2, "sys_clk_flexnoc2", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_FLEXNOC2_PREOSC),
> > + STARFIVE__MUX(SYSCRG_CLK_VDEC_CORE, "sys_clk_vdec_core", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_FLEXNOC1_PREOSC),
> > + /* img_gpu (se) */
> > + STARFIVE_GATE(SYSCRG_CLK_GPU_CORE_ICG, "sys_clk_gpu_core_icg", 0,
> > + SYSCRG_CLK_GPU_CORE),
> > + STARFIVE_GATE(SYSCRG_CLK_IMG_GPU_CLK_APB, "sys_clk_img_gpu_clk_apb", 0,
> > + SYSCRG_CLK_APB_BUS_PER7),
> > + STARFIVE_GATE(SYSCRG_CLK_IMG_GPU_RTC_TOGGLE, "sys_clk_img_gpu_rtc_toggle", 0,
> > + SYSCRG_CLK_OSC),
> > + STARFIVE_GATE(SYSCRG_CLK_IMG_GPU_TIMER_USC, "sys_clk_img_gpu_timer_usc", 0,
> > + SYSCRG_CLK_OSC),
> > + /* hifi4 (se) */
> > + STARFIVE__DIV(SYSCRG_CLK_HIFI4_CORE_PREOSC, "sys_clk_hifi4_core_preosc", 15,
> > + SYSCRG_CLK_PLL0_OUT),
> > + STARFIVE__MUX(SYSCRG_CLK_HIFI4_CORE, "sys_clk_hifi4_core", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_HIFI4_CORE_PREOSC),
> > + /* espi */
> > + STARFIVE__DIV(SYSCRG_CLK_ESPI_200_PREOSC, "sys_clk_espi_200_preosc", 2,
> > + SYSCRG_CLK_PLL0_OUT),
> > + STARFIVE__MUX(SYSCRG_CLK_ESPI_200, "sys_clk_espi_200", 2,
> > + SYSCRG_CLK_OSC, SYSCRG_CLK_ESPI_200_PREOSC),
> > + /* hd audio */
> > + STARFIVE__DIV(SYSCRG_CLK_HD_AUDIO_48M, "sys_clk_hd_audio_48m", 80,
> > + SYSCRG_CLK_PLL7_OUT),
> > + /* dom vout */
> > + STARFIVE__DIV(SYSCRG_CLK_VOUT_DC_CORE, "sys_clk_vout_dc_core", 10,
> > + SYSCRG_CLK_PLL7_OUT),
> > + STARFIVE__DIV(SYSCRG_CLK_VOUT_AXI, "sys_clk_vout_axi", 10,
> > + SYSCRG_CLK_PLL7_OUT),
> > + /* stg2_usb_wrap (se) */
> > + STARFIVE__DIV(SYSCRG_CLK_USB_WRAP_625, "sys_clk_usb_wrap_625", 6,
> > + SYSCRG_CLK_PLL0_OUT),
> > + STARFIVE__DIV(SYSCRG_CLK_USB_WRAP_480, "sys_clk_usb_wrap_480", 8,
> > + SYSCRG_CLK_PLL0_OUT),
> > + STARFIVE__DIV(SYSCRG_CLK_USB_WRAP_240, "sys_clk_usb_wrap_240", 2,
> > + SYSCRG_CLK_USB_WRAP_480),
> > + STARFIVE__DIV(SYSCRG_CLK_USB_WRAP_60, "sys_clk_usb_wrap_60", 10,
> > + SYSCRG_CLK_USB_WRAP_480),
> > + STARFIVE__DIV(SYSCRG_CLK_USB_WRAP_156P25, "sys_clk_usb_wrap_156p25", 4,
> > + SYSCRG_CLK_USB_WRAP_625),
> > + STARFIVE__DIV(SYSCRG_CLK_USB_WRAP_312P5, "sys_clk_usb_wrap_312p5", 2,
> > + SYSCRG_CLK_USB_WRAP_625),
> > + /* stg */
> > + STARFIVE__DIV(SYSCRG_CLK_USB_125M, "sys_clk_usb_125m", 32,
> > + SYSCRG_CLK_PLL0_OUT),
> > + /* Flexnoc (se) */
> > + STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_APBOOTRAM, "sys_clk_flexnoc_apbootram",
> > + CLK_IS_CRITICAL, SYSCRG_CLK_AXI_400_APBOOTRAM),
> > + STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_PCIEX1AMST, "sys_clk_flexnoc_pciex1amst",
> > + CLK_IS_CRITICAL, SYSCRG_CLK_AXI_500_PCIEX1A),
> > + STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_PCIEX1ASLV, "sys_clk_flexnoc_pciex1aslv",
> > + CLK_IS_CRITICAL, SYSCRG_CLK_AXI_500_PCIEX1A),
> > + STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_PCIEX1BMST, "sys_clk_flexnoc_pciex1bmst",
> > + CLK_IS_CRITICAL, SYSCRG_CLK_AXI_500_PCIEX1B),
> > + STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_PCIEX1BSLV, "sys_clk_flexnoc_pciex1bslv",
> > + CLK_IS_CRITICAL, SYSCRG_CLK_AXI_500_PCIEX1B),
> > + STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_PCIEX2MST, "sys_clk_flexnoc_pciex2mst",
> > + CLK_IS_CRITICAL, SYSCRG_CLK_AXI_500_PCIEX2),
> > + STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_PCIEX2SLV, "sys_clk_flexnoc_pciex2slv",
> > + CLK_IS_CRITICAL, SYSCRG_CLK_AXI_500_PCIEX2),
> > + STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_PCIEX8MST, "sys_clk_flexnoc_pciex8mst",
> > + CLK_IS_CRITICAL, SYSCRG_CLK_AXI_500_PCIEX8),
> > + STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_PCIEX8SLV, "sys_clk_flexnoc_pciex8slv",
> > + CLK_IS_CRITICAL, SYSCRG_CLK_AXI_500_PCIEX8),
> > + STARFIVE_GATE(SYSCRG_CLK_FLEXNOC_GMACSYSSLV, "sys_clk_flexnoc_gmacsysslv",
> > + CLK_IS_CRITICAL, SYSCRG_CLK_AXI_200_GMAC),
> > + /* gmac1 (se) */
> > + STARFIVE__DIV(SYSCRG_CLK_GMAC_SRC, "sys_clk_gmac_src", 7,
> > + SYSCRG_CLK_PLL0_OUT),
> > + STARFIVE__DIV(SYSCRG_CLK_GMAC1_GTXCLK_TOP, "sys_clk_gmac1_gtxclk_top", 400,
> > + SYSCRG_CLK_PLL0_OUT),
> > + STARFIVE__DIV(SYSCRG_CLK_GMAC1_PTP, "sys_clk_gmac1_ptp", 31,
> > + SYSCRG_CLK_GMAC_SRC),
> > + /* hd audio */
> > + STARFIVE_GATE(SYSCRG_CLK_HD_AUDIO_SYSTEM_CLOCK, "sys_clk_hd_audio_system_clock",
> > + 0, SYSCRG_CLK_APB_BUS_PER7),
> > + STARFIVE_GATE(SYSCRG_CLK_HD_AUDIO_CLOCK_48, "sys_clk_hd_audio_clock_48",
> > + 0, SYSCRG_CLK_HD_AUDIO_48M),
> > + STARFIVE_GATE(SYSCRG_CLK_HD_AUDIO_BCLK_POST_OCC_IN, "sys_clk_hd_audio_bclk_post_occ_in",
> > + 0, SYSCRG_CLK_HD_AUDIO_48M),
> > + /* nne_vip (se) */
> > + STARFIVE_GATE(SYSCRG_CLK_NNE_VIP_ACLK, "sys_clk_nne_vip_aclk",
> > + 0, SYSCRG_CLK_AXI_500),
> > + STARFIVE_GATE(SYSCRG_CLK_NNE_VIP_HCLK, "sys_clk_nne_vip_hclk",
> > + 0, SYSCRG_CLK_AXI_200),
> > + STARFIVE_GMUX(SYSCRG_CLK_NNE_VIP_CLKCORE, "sys_clk_nne_vip_clkcore", 0, 2,
> > + SYSCRG_CLK_PLL2_OUT,
> > + SYSCRG_CLK_PLL0_OUT),
> > + /* icg_en */
> > + STARFIVE_GATE(SYSCRG_CLK_GPU_ICG_EN, "sys_clk_gpu_en",
> > + 0, SYSCRG_CLK_GPU_CORE),
> > + STARFIVE_GATE(SYSCRG_CLK_HD_AUDIO_ICG_EN, "sys_clk_hd_audio_en",
> > + 0, SYSCRG_CLK_APB_BUS),
> > + STARFIVE_GATE(SYSCRG_CLK_NNE_ICG_EN, "sys_clk_nne_en",
> > + CLK_IGNORE_UNUSED, SYSCRG_CLK_PLL2_OUT),
> > +};
>
> Please drop the redundant sys_clk_ prefix from all the clock names similar to
> how it was done for the JH71X0s.
Ok.
>
> /Emil
> -----Original Message-----
> From: Emil Renner Berthing <[email protected]>
> Sent: Saturday, December 9, 2023 12:37 AM
> To: JeeHeng Sia <[email protected]>; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> <[email protected]>; Xingyu Wu <[email protected]>
> Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon Tan
> <[email protected]>
> Subject: Re: [PATCH v1 07/16] dt-bindings: clock: Add StarFive JH8100 System-North-West clock and reset generator
>
> Sia Jee Heng wrote:
> > Add bindings for the System-North-West clock and reset generator
> > (SYSCRG-NW) on JH8100 SoC.
> >
> > Signed-off-by: Sia Jee Heng <[email protected]>
> > Reviewed-by: Ley Foon Tan <[email protected]>
> > ---
> > .../clock/starfive,jh8100-syscrg-nw.yaml | 119 ++++++++++++++++++
>
> The JH7110 clocks, the JH8100 system and always-on all follow the Xcrg pattern:
> syscrg
> aoncrg
> stgcrg
> ispcrg
> voutcrg
> etc.
>
> Is there a reason the north-west, north-east and south-west breaks this pattern?
> I'd have expected them to be called something like
> nwcrg, JH8100_NWCLK_*, JH8100_NWRST_*,
> necrg, JH8100_NECLK_*, JH8100_NERST_* and
> swcrg, JH8100_SWCLK_*, JH8100_SWRST_*
>
> Just like all the other Starfive drivers.
Understood your concern. We don’t have the intention to break the pattern,
but the reason we skip the SoC_ prefix is that the SoC names were already
defined in the header file with the SoC name.
However, I can put it back, of course.
>
> > .../dt-bindings/clock/starfive,jh8100-crg.h | 45 +++++++
> > .../dt-bindings/reset/starfive,jh8100-crg.h | 15 +++
> > 3 files changed, 179 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-nw.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-nw.yaml
> b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-nw.yaml
> > new file mode 100644
> > index 000000000000..b16a874828dd
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-nw.yaml
> > @@ -0,0 +1,119 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/starfive,jh8100-syscrg-nw.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: StarFive JH8100 System-North-West Clock and Reset Generator
> > +
> > +maintainers:
> > + - Sia Jee Heng <[email protected]>
> > +
> > +properties:
> > + compatible:
> > + const: starfive,jh8100-syscrg-nw
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + items:
> > + - description: Main Oscillator (24 MHz)
> > + - description: APB_BUS clock from SYSCRG
> > + - description: ISP_2X clock from SYSCRG
> > + - description: ISP_AXI clock from SYSCRG
> > + - description: VOUT_ROOT0 clock from SYSCRG
> > + - description: VOUT_ROOT1 clock from SYSCRG
> > + - description: VOUT_SCAN_ATS clock from SYSCRG
> > + - description: VOUT_DC_CORE clock from SYSCRG
> > + - description: VOUT_AXI clock from SYSCRG
> > + - description: AXI_400 clock from SYSCRG
> > + - description: AXI_200 clock from SYSCRG
> > + - description: Peripheral clock from SYSCRG
> > + - description: External DVP clock
> > + - description: External ISP DPHY TAP TCK clock
> > + - description: External golbal clock
> > + - description: External i2s_tscko clock
> > + - description: External VOUT MIPI DPHY TAP TCK
> > + - description: External VOUT eDP TAP TCK
> > + - description: External SPI In2 clock
> > +
> > + clock-names:
> > + items:
> > + - const: clk_osc
> > + - const: sys_clk_apb_bus
> > + - const: sys_clk_isp_2x
> > + - const: sys_clk_isp_axi
> > + - const: sys_clk_vout_root0
> > + - const: sys_clk_vout_root1
> > + - const: sys_clk_vout_scan_ats
> > + - const: sys_clk_vout_dc_core
> > + - const: sys_clk_vout_axi
> > + - const: sys_clk_axi_400
> > + - const: sys_clk_axi_200
> > + - const: sys_clk_perh_root_preosc
> > + - const: clk_dvp_ext
> > + - const: clk_isp_dphy_tap_tck_ext
> > + - const: clk_glb_ext_clk
> > + - const: clk_i2s_tscko
> > + - const: clk_vout_mipi_dphy_tap_tck_ext
> > + - const: clk_vout_edp_tap_tck_ext
> > + - const: clk_spi_in2_ext
> > +
> > + '#clock-cells':
> > + const: 1
> > + description:
> > + See <dt-bindings/clock/starfive,jh8100-crg.h> for valid indices.
> > +
> > + '#reset-cells':
> > + const: 1
> > + description:
> > + See <dt-bindings/reset/starfive,jh8100-crg.h> for valid indices.
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > + - clock-names
> > + - '#clock-cells'
> > + - '#reset-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/starfive,jh8100-crg.h>
> > +
> > + clock-controller@123c0000 {
> > + compatible = "starfive,jh8100-syscrg-nw";
> > + reg = <0x123c0000 0x10000>;
> > + clocks = <&clk_osc>, <&syscrg SYSCRG_CLK_APB_BUS>,
> > + <&syscrg SYSCRG_CLK_ISP_2X>,
> > + <&syscrg SYSCRG_CLK_ISP_AXI>,
> > + <&syscrg SYSCRG_CLK_VOUT_ROOT0>,
> > + <&syscrg SYSCRG_CLK_VOUT_ROOT1>,
> > + <&syscrg SYSCRG_CLK_VOUT_SCAN_ATS>,
> > + <&syscrg SYSCRG_CLK_VOUT_DC_CORE>,
> > + <&syscrg SYSCRG_CLK_VOUT_AXI>,
> > + <&syscrg SYSCRG_CLK_AXI_400>,
> > + <&syscrg SYSCRG_CLK_AXI_200>,
> > + <&syscrg SYSCRG_CLK_PERH_ROOT_PREOSC>,
> > + <&clk_dvp_ext>,
> > + <&clk_isp_dphy_tap_tck_ext>,
> > + <&clk_glb_ext_clk>,
> > + <&clk_i2s_tscko>,
> > + <&clk_vout_mipi_dphy_tap_tck_ext>,
> > + <&clk_vout_edp_tap_tck_ext>,
> > + <&clk_spi_in2_ext>;
> > + clock-names = "clk_osc", "sys_clk_apb_bus", "sys_clk_isp_2x",
> > + "sys_clk_isp_axi", "sys_clk_vout_root0",
> > + "sys_clk_vout_root1", "sys_clk_vout_scan_ats",
> > + "sys_clk_vout_dc_core", "sys_clk_vout_axi",
> > + "sys_clk_axi_400", "sys_clk_axi_200",
> > + "sys_clk_perh_root_preosc", "clk_dvp_ext",
> > + "clk_isp_dphy_tap_tck_ext", "clk_glb_ext_clk",
> > + "clk_i2s_tscko", "clk_vout_mipi_dphy_tap_tck_ext",
> > + "clk_vout_edp_tap_tck_ext", "clk_spi_in2_ext";
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h
> > index e5bb588ce798..8417455c2409 100644
> > --- a/include/dt-bindings/clock/starfive,jh8100-crg.h
> > +++ b/include/dt-bindings/clock/starfive,jh8100-crg.h
> > @@ -120,4 +120,49 @@
> > #define SYSCRG_CLK_NNE_ICG_EN 108
> >
> > #define SYSCRG_CLK_END 109
> > +
> > +/* SYSCRG_NW_CLK */
> > +#define SYSCRG_NW_CLK_PLL5_DIV2 0
> > +#define SYSCRG_NW_CLK_GCLK5 1
> > +#define SYSCRG_NW_CLK_GPIO_100 2
> > +#define SYSCRG_NW_CLK_GPIO_50 3
> > +#define SYSCRG_NW_CLK_GPIO_150 4
> > +#define SYSCRG_NW_CLK_GPIO_60 5
> > +#define SYSCRG_NW_CLK_IOMUX_WEST_PCLK 6
> > +#define SYSCRG_NW_CLK_I2C6_APB 7
> > +#define SYSCRG_NW_CLK_I2C7_APB 8
> > +#define SYSCRG_NW_CLK_SPI2_APB 9
> > +#define SYSCRG_NW_CLK_SPI2_CORE 10
> > +#define SYSCRG_NW_CLK_SPI2_SCLK_IN 11
> > +#define SYSCRG_NW_CLK_SMBUS1_APB 12
> > +#define SYSCRG_NW_CLK_SMBUS1_CORE 13
> > +#define SYSCRG_NW_CLK_ISP_DVP 14
> > +#define SYSCRG_NW_CLK_ISP_CORE_2X 15
> > +#define SYSCRG_NW_CLK_ISP_AXI 16
> > +#define SYSCRG_NW_CLK_ISP_DPHY_TAP_TCK 17
> > +#define SYSCRG_NW_CLK_FLEXNOC_ISPSLV 18
> > +#define SYSCRG_NW_CLK_VOUT_PIX0 19
> > +#define SYSCRG_NW_CLK_VOUT_PIX1 20
> > +#define SYSCRG_NW_CLK_VOUT_SCAN_ATS 21
> > +#define SYSCRG_NW_CLK_VOUT_DC_CORE 22
> > +#define SYSCRG_NW_CLK_VOUT_APB 23
> > +#define SYSCRG_NW_CLK_VOUT_DSI 24
> > +#define SYSCRG_NW_CLK_VOUT_AHB 25
> > +#define SYSCRG_NW_CLK_VOUT_AXI 26
> > +#define SYSCRG_NW_CLK_VOUT_MIPI_DPHY_TAP_TCK 27
> > +#define SYSCRG_NW_CLK_VOUT_EDP_PHY_TAP_TCK 28
> > +#define SYSCRG_NW_CLK_UART5_CORE_PREOSC 29
> > +#define SYSCRG_NW_CLK_UART5_APB 30
> > +#define SYSCRG_NW_CLK_UART5_CORE 31
> > +#define SYSCRG_NW_CLK_UART6_CORE_PREOSC 32
> > +#define SYSCRG_NW_CLK_UART6_APB 33
> > +#define SYSCRG_NW_CLK_UART6_CORE 34
> > +#define SYSCRG_NW_CLK_SPI2_ICG_EN 35
> > +#define SYSCRG_NW_CLK_SMBUS1_ICG_EN 36
> > +#define SYSCRG_NW_CLK_ISP_ICG_EN 37
> > +#define SYSCRG_NW_CLK_VOUT_ICG_EN 38
> > +#define SYSCRG_NW_CLK_UART5_ICG_EN 39
> > +#define SYSCRG_NW_CLK_UART6_ICG_EN 40
> > +
> > +#define SYSCRG_NW_CLK_END 41
> > #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */
> > diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h
> > index 3b7b92488e76..8c3a858bdf6a 100644
> > --- a/include/dt-bindings/reset/starfive,jh8100-crg.h
> > +++ b/include/dt-bindings/reset/starfive,jh8100-crg.h
> > @@ -20,4 +20,19 @@
> >
> > #define SYSCRG_RESET_NR_RESETS 8
> >
> > +/*
> > + * syscrg_nw: assert0
> > + */
> > +#define SYSCRG_NW_RSTN_PRESETN 0
> > +#define SYSCRG_NW_RSTN_SYS_IOMUX_W 1
> > +#define SYSCRG_NW_RSTN_I2C6 2
> > +#define SYSCRG_NW_RSTN_I2C7 3
> > +#define SYSCRG_NW_RSTN_SPI2 4
> > +#define SYSCRG_NW_RSTN_SMBUS1 5
> > +#define SYSCRG_NW_RSTN_UART5 6
> > +#define SYSCRG_NW_RSTN_UART6 7
> > +#define SYSCRG_NW_RSTN_MERAK0_TVSENSOR 8
> > +#define SYSCRG_NW_RSTN_MERAK1_TVSENSOR 9
> > +
> > +#define SYSCRG_NW_RESET_NR_RESETS 10
> > #endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */
> > --
> > 2.34.1
> >
> -----Original Message-----
> From: Emil Renner Berthing <[email protected]>
> Sent: Saturday, December 9, 2023 12:40 AM
> To: JeeHeng Sia <[email protected]>; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> <[email protected]>; Xingyu Wu <[email protected]>
> Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon Tan
> <[email protected]>
> Subject: Re: [PATCH v1 16/16] riscv: dts: starfive: jh8100: Add clocks and resets nodes
>
> Sia Jee Heng wrote:
> > Add SYSCRG/SYSCRG-NE/SYSCRG-NW/SYSCRG-SW/AONCRG clock and reset
> > nodes for JH8100 RISC-V SoC.
> >
> > Signed-off-by: Sia Jee Heng <[email protected]>
> > Reviewed-by: Ley Foon Tan <[email protected]>
> > ---
> > arch/riscv/boot/dts/starfive/jh8100-clk.dtsi | 180 +++++++++++++++++++
> > arch/riscv/boot/dts/starfive/jh8100.dtsi | 115 ++++++++++++
>
> Why the split here? I mean why can't the clocks just be in the jh8100.dtsi?
The reason is that the number of fixed clocks increases when more and more
domain clocks are added. So, that is why we split out the clock file.
>
> > 2 files changed, 295 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/starfive/jh8100-clk.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/starfive/jh8100-clk.dtsi b/arch/riscv/boot/dts/starfive/jh8100-clk.dtsi
> > new file mode 100644
> > index 000000000000..27ba249f523e
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/starfive/jh8100-clk.dtsi
> > @@ -0,0 +1,180 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (C) 2023 StarFive Technology Co., Ltd.
> > + */
> > +
> > +/ {
> > + clk_osc: clk_osc {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <24000000>;
> > + };
> > +
> > + clk_i2srx_bclk_ext: clk_i2srx_bclk_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <12288000>;
> > + };
> > +
> > + clk_i2srx_lrck_ext: clk_i2srx_lrck_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <192000>;
> > + };
> > +
> > + clk_mclk_ext: clk_mclk_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <49152000>;
> > + };
> > + /* sys-ne */
> > + clk_usb3_tap_tck_ext: clk_usb3_tap_tck_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + };
> > +
> > + clk_glb_ext_clk: clk_glb_ext_clk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <30000000>;
> > + };
> > +
> > + clk_usb1_tap_tck_ext: clk_usb1_tap_tck_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + };
> > +
> > + clk_usb2_tap_tck_ext: clk_usb2_tap_tck_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + };
> > +
> > + clk_i2s_tscko: clk_i2s_tscko {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <12800000>;
> > + };
> > +
> > + clk_typec_tap_tck_ext: clk_typec_tap_tck_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + };
> > +
> > + clk_spi_in0_ext: clk_spi_in0_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + };
> > +
> > + clk_spi_in1_ext: clk_spi_in1_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + };
> > +
> > + clk_spi_in2_ext: clk_spi_in2_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + };
> > +
> > + clk_i2stx_bclk_ext: clk_i2stx_bclk_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <12288000>;
> > + };
> > +
> > + clk_i2stx_lrck_ext: clk_i2stx_lrck_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <192000>;
> > + };
> > + /* sys-nw */
> > + clk_dvp_ext: clk_dvp_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <150000000>;
> > + };
> > +
> > + clk_isp_dphy_tap_tck_ext: clk_isp_dphy_tap_tck_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + };
> > +
> > + clk_vout_mipi_dphy_tap_tck_ext: clk_vout_mipi_dphy_tap_tck_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + };
> > +
> > + clk_vout_edp_tap_tck_ext: clk_vout_edp_tap_tck_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + };
> > +
> > + clk_rtc: clk_rtc {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <32768>;
> > + };
> > + /* aon */
> > + clk_gmac0_rmii_func: clk_gmac0_rmii_func {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <50000000>;
> > + };
> > +
> > + clk_gmac0_rgmii_func: clk_gmac0_rgmii_func {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <125000000>;
> > + };
> > +
> > + clk_aon50: clk_aon50 {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <50000000>;
> > + };
> > +
> > + clk_aon125: clk_aon125 {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <125000000>;
> > + };
> > +
> > + clk_aon2000: clk_aon2000 {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <2000000000>;
> > + };
> > +
> > + clk_aon200: clk_aon200 {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <200000000>;
> > + };
> > +
> > + clk_aon667: clk_isp_aon667 {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <667000000>;
> > + };
> > +
> > + clk_i3c_ext: clk_i3c_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <12500000>;
> > + };
> > +
> > + clk_espi_ext: clk_espi_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <60000000>;
> > + };
> > +};
> > diff --git a/arch/riscv/boot/dts/starfive/jh8100.dtsi b/arch/riscv/boot/dts/starfive/jh8100.dtsi
> > index f26aff5c1ddf..9863c61324a0 100644
> > --- a/arch/riscv/boot/dts/starfive/jh8100.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh8100.dtsi
> > @@ -4,6 +4,9 @@
> > */
> >
> > /dts-v1/;
> > +#include <dt-bindings/clock/starfive,jh8100-crg.h>
> > +#include <dt-bindings/reset/starfive,jh8100-crg.h>
> > +#include "jh8100-clk.dtsi"
> >
> > / {
> > compatible = "starfive,jh8100";
> > @@ -357,6 +360,104 @@ uart4: serial@121a0000 {
> > status = "disabled";
> > };
> >
> > + syscrg_ne: syscrg_ne@12320000 {
> > + compatible = "starfive,jh8100-syscrg-ne";
> > + reg = <0x0 0x12320000 0x0 0x10000>;
> > + clocks = <&clk_osc>, <&syscrg SYSCRG_CLK_AXI_400>,
> > + <&syscrg SYSCRG_CLK_VOUT_ROOT0>,
> > + <&syscrg SYSCRG_CLK_VOUT_ROOT1>,
> > + <&syscrg SYSCRG_CLK_USB_WRAP_480>,
> > + <&syscrg SYSCRG_CLK_USB_WRAP_625>,
> > + <&syscrg SYSCRG_CLK_USB_WRAP_240>,
> > + <&syscrg SYSCRG_CLK_USB_WRAP_60>,
> > + <&syscrg SYSCRG_CLK_USB_WRAP_156P25>,
> > + <&syscrg SYSCRG_CLK_USB_WRAP_312P5>,
> > + <&syscrg SYSCRG_CLK_USB_125M>,
> > + <&syscrg_nw SYSCRG_NW_CLK_GPIO_100>,
> > + <&syscrg SYSCRG_CLK_PERH_ROOT>, <&syscrg SYSCRG_CLK_MCLK>,
> > + <&syscrg SYSCRG_CLK_PERH_ROOT_PREOSC>,
> > + <&syscrg SYSCRG_CLK_AHB0>,
> > + <&syscrg SYSCRG_CLK_APB_BUS_PER1>,
> > + <&syscrg SYSCRG_CLK_APB_BUS_PER2>,
> > + <&syscrg SYSCRG_CLK_APB_BUS_PER3>,
> > + <&syscrg SYSCRG_CLK_APB_BUS_PER5>,
> > + <&syscrg SYSCRG_CLK_VENC_ROOT>,
> > + <&syscrg SYSCRG_CLK_SPI_CORE_100>,
> > + <&clk_glb_ext_clk>, <&clk_usb3_tap_tck_ext>,
> > + <&clk_usb1_tap_tck_ext>, <&clk_usb2_tap_tck_ext>,
> > + <&clk_typec_tap_tck_ext>, <&clk_spi_in0_ext>,
> > + <&clk_spi_in1_ext>, <&clk_i2stx_bclk_ext>, <&clk_i2stx_lrck_ext>;
> > + clock-names = "clk_osc", "sys_clk_axi_400",
> > + "sys_clk_vout_root0", "sys_clk_vout_root1",
> > + "sys_clk_usb_wrap_480", "sys_clk_usb_wrap_625",
> > + "sys_clk_usb_wrap_240", "sys_clk_usb_wrap_60",
> > + "sys_clk_usb_wrap_156p25", "sys_clk_usb_wrap_312p5",
> > + "sys_clk_usb_125m", "sys_nw_clk_gpio_100",
> > + "sys_clk_perh_root", "sys_clk_mclk",
> > + "sys_clk_perh_root_preosc", "sys_clk_ahb0",
> > + "sys_clk_apb_bus_per1", "sys_clk_apb_bus_per2",
> > + "sys_clk_apb_bus_per3", "sys_clk_apb_bus_per5",
> > + "sys_clk_venc_root", "sys_clk_spi_core_100",
> > + "clk_glb_ext_clk", "clk_usb3_tap_tck_ext",
> > + "clk_usb1_tap_tck_ext", "clk_usb2_tap_tck_ext",
> > + "clk_typec_tap_tck_ext", "clk_spi_in0_ext",
> > + "clk_spi_in1_ext", "clk_i2stx_bclk_ext",
> > + "clk_i2stx_lrck_ext";
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > +
> > + syscrg_nw: syscrg_nw@123c0000 {
> > + compatible = "starfive,jh8100-syscrg-nw";
> > + reg = <0x0 0x123c0000 0x0 0x10000>;
> > + clocks = <&clk_osc>, <&syscrg SYSCRG_CLK_APB_BUS>,
> > + <&syscrg SYSCRG_CLK_ISP_2X>, <&syscrg SYSCRG_CLK_ISP_AXI>,
> > + <&syscrg SYSCRG_CLK_VOUT_ROOT0>, <&syscrg SYSCRG_CLK_VOUT_ROOT1>,
> > + <&syscrg SYSCRG_CLK_VOUT_SCAN_ATS>,
> > + <&syscrg SYSCRG_CLK_VOUT_DC_CORE>, <&syscrg SYSCRG_CLK_VOUT_AXI>,
> > + <&syscrg SYSCRG_CLK_AXI_400>, <&syscrg SYSCRG_CLK_AXI_200>,
> > + <&syscrg SYSCRG_CLK_PERH_ROOT_PREOSC>,
> > + <&clk_dvp_ext>, <&clk_isp_dphy_tap_tck_ext>,
> > + <&clk_glb_ext_clk>, <&clk_i2s_tscko>,
> > + <&clk_vout_mipi_dphy_tap_tck_ext>, <&clk_vout_edp_tap_tck_ext>,
> > + <&clk_spi_in2_ext>;
> > + clock-names = "clk_osc", "sys_clk_apb_bus",
> > + "sys_clk_isp_2x", "sys_clk_isp_axi",
> > + "sys_clk_vout_root0", "sys_clk_vout_root1",
> > + "sys_clk_vout_scan_ats", "sys_clk_vout_dc_core",
> > + "sys_clk_vout_axi", "sys_clk_axi_400",
> > + "sys_clk_axi_200", "sys_clk_perh_root_preosc", "clk_dvp_ext",
> > + "clk_isp_dphy_tap_tck_ext", "clk_glb_ext_clk",
> > + "clk_i2s_tscko", "clk_vout_mipi_dphy_tap_tck_ext",
> > + "clk_vout_edp_tap_tck_ext", "clk_spi_in2_ext";
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > +
> > + syscrg: syscrg@126d0000 {
> > + compatible = "starfive,jh8100-syscrg";
> > + reg = <0x0 0x126d0000 0x0 0x10000>;
> > + clocks = <&clk_osc>, <&clk_i2srx_bclk_ext>,
> > + <&clk_i2srx_lrck_ext>, <&clk_mclk_ext>;
> > + clock-names = "clk_osc", "clk_i2srx_bclk_ext",
> > + "clk_i2srx_lrck_ext", "clk_mclk_ext";
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > +
> > + syscrg_sw: syscrg_sw@12720000 {
> > + compatible = "starfive,jh8100-syscrg-sw";
> > + reg = <0x0 0x12720000 0x0 0x10000>;
> > + clocks = <&syscrg SYSCRG_CLK_APB_BUS>,
> > + <&syscrg SYSCRG_CLK_VDEC_ROOT>,
> > + <&syscrg SYSCRG_CLK_FLEXNOC1>;
> > + clock-names = "sys_clk_apb_bus",
> > + "sys_clk_vdec_root",
> > + "sys_clk_flexnoc1";
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > +
> > uart5: serial@127d0000 {
> > compatible = "starfive,jh8100-uart", "cdns,uart-r1p8";
> > reg = <0x0 0x127d0000 0x0 0x10000>;
> > @@ -374,5 +475,19 @@ uart6: serial@127e0000 {
> > interrupts = <73>;
> > status = "disabled";
> > };
> > +
> > + aoncrg: aoncrg@1f310000 {
> > + compatible = "starfive,jh8100-aoncrg";
> > + reg = <0x0 0x1f310000 0x0 0x10000>;
> > + clocks = <&clk_osc>, <&clk_gmac0_rmii_func>,
> > + <&clk_gmac0_rgmii_func>, <&clk_aon125>,
> > + <&clk_aon2000>, <&clk_aon200>,
> > + <&clk_aon667>, <&clk_rtc>;
> > + clock-names = "clk_osc", "clk_gmac0_rmii_func", "clk_gmac0_rgmii_func",
> > + "clk_aon125", "clk_aon2000", "clk_aon200",
> > + "clk_aon667", "clk_rtc";
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > };
> > };
> > --
> > 2.34.1
> >
> -----Original Message-----
> From: Emil Renner Berthing <[email protected]>
> Sent: Saturday, December 9, 2023 12:53 AM
> To: JeeHeng Sia <[email protected]>; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> <[email protected]>; Xingyu Wu <[email protected]>
> Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon Tan
> <[email protected]>
> Subject: Re: [PATCH v1 00/16] Basic clock and reset support for StarFive JH8100 RISC-V SoC
>
> Sia Jee Heng wrote:
> > This patch series enabled basic clock & reset support for StarFive
> > JH8100 SoC.
> >
> > This patch series depends on the Initial device tree support for
> > StarFive JH8100 SoC patch series which can be found at below link:
> > https://lore.kernel.org/lkml/[email protected]/
> >
> > StarFive JH8100 shares a similar clock and reset design with JH7110.
> > To facilitate the reuse of the file and its functionalities, files
> > containing the 'jh71x0' naming convention are renamed to use the
> > 'common' wording. Internal functions that contain the 'jh71x0'
> > naming convention are renamed to use 'starfive.' This is accomplished
> > through patches 1, 2, 3, and 4.
>
> I'm a little sceptical all this renaming is worth it, but if think it's likely
> that future starfive SoCs can use the same clock drivers I'm ok with it. Just
> know that you'll look a bit silly if your "JH9100" can't use these drivers and
> you'll already need different starfive and starfive-gen2 drivers.
Thank you for your understanding.
>
> /Emil
> >
> >
> > Patch 5 adds documentation to describe System (SYSCRG) Clock & Reset
> > binding.
> > Patch 6 adds SYSCRG clock driver.
> >
> > patch 7 adds documentation to describe System-North-West (SYSCRG-NW)
> > Clock & Reset binding.
> > Patch 8 adds SYSCRG-NW clock driver.
> >
> > patch 9 adds documentation to describe System-North-East (SYSCRG-NE)
> > Clock & Reset binding.
> > Patch 10 adds SYSCRG-NE clock driver.
> >
> > patch 11 adds documentation to describe System-South-West (SYSCRG-SW)
> > Clock & Reset binding.
> > Patch 12 adds SYSCRG-SW clock driver.
> >
> > patch 13 adds documentation to describe Always-On (AON)
> > Clock & Reset binding.
> > Patch 14 adds AON clock driver.
> >
> > Patch 15 adds support for the auxiliary reset driver.
> >
> > Patch 16 adds clocks and reset nodes to the JH8100 device tree.
> >
> > Sia Jee Heng (16):
> > reset: starfive: Rename file name "jh71x0" to "common"
> > reset: starfive: Convert the word "jh71x0" to "starfive"
> > clk: starfive: Rename file name "jh71x0" to "common"
> > clk: starfive: Convert the word "jh71x0" to "starfive"
> > dt-bindings: clock: Add StarFive JH8100 System clock and reset
> > generator
> > clk: starfive: Add JH8100 System clock generator driver
> > dt-bindings: clock: Add StarFive JH8100 System-North-West clock and
> > reset generator
> > clk: starfive: Add JH8100 System-North-West clock generator driver
> > dt-bindings: clock: Add StarFive JH8100 System-North-East clock and
> > reset generator
> > clk: starfive: Add JH8100 System-North-East clock generator driver
> > dt-bindings: clock: Add StarFive JH8100 System-South-West clock and
> > reset generator
> > clk: starfive: Add JH8100 System-South-West clock generator driver
> > dt-bindings: clock: Add StarFive JH8100 Always-On clock and reset
> > generator
> > clk: starfive: Add JH8100 Always-On clock generator driver
> > reset: starfive: Add StarFive JH8100 reset driver
> > riscv: dts: starfive: jh8100: Add clocks and resets nodes
> >
> > .../clock/starfive,jh8100-aoncrg.yaml | 77 +++
> > .../clock/starfive,jh8100-syscrg-ne.yaml | 158 +++++
> > .../clock/starfive,jh8100-syscrg-nw.yaml | 119 ++++
> > .../clock/starfive,jh8100-syscrg-sw.yaml | 66 ++
> > .../clock/starfive,jh8100-syscrg.yaml | 66 ++
> > MAINTAINERS | 15 +
> > arch/riscv/boot/dts/starfive/jh8100-clk.dtsi | 180 ++++++
> > arch/riscv/boot/dts/starfive/jh8100.dtsi | 115 ++++
> > drivers/clk/starfive/Kconfig | 49 +-
> > drivers/clk/starfive/Makefile | 3 +-
> > drivers/clk/starfive/clk-starfive-common.c | 327 ++++++++++
> > drivers/clk/starfive/clk-starfive-common.h | 130 ++++
> > .../clk/starfive/clk-starfive-jh7100-audio.c | 127 ++--
> > drivers/clk/starfive/clk-starfive-jh7100.c | 503 ++++++++--------
> > .../clk/starfive/clk-starfive-jh7110-aon.c | 62 +-
> > .../clk/starfive/clk-starfive-jh7110-isp.c | 72 +--
> > .../clk/starfive/clk-starfive-jh7110-stg.c | 94 +--
> > .../clk/starfive/clk-starfive-jh7110-sys.c | 523 ++++++++--------
> > .../clk/starfive/clk-starfive-jh7110-vout.c | 74 +--
> > drivers/clk/starfive/clk-starfive-jh7110.h | 4 +-
> > drivers/clk/starfive/clk-starfive-jh71x0.c | 327 ----------
> > drivers/clk/starfive/clk-starfive-jh71x0.h | 123 ----
> > drivers/clk/starfive/jh8100/Makefile | 7 +
> > drivers/clk/starfive/jh8100/clk-aon.c | 275 +++++++++
> > .../clk/starfive/jh8100/clk-starfive-jh8100.h | 11 +
> > drivers/clk/starfive/jh8100/clk-sys-ne.c | 566 ++++++++++++++++++
> > drivers/clk/starfive/jh8100/clk-sys-nw.c | 268 +++++++++
> > drivers/clk/starfive/jh8100/clk-sys-sw.c | 136 +++++
> > drivers/clk/starfive/jh8100/clk-sys.c | 455 ++++++++++++++
> > drivers/reset/starfive/Kconfig | 14 +-
> > drivers/reset/starfive/Makefile | 4 +-
> > ...rfive-jh71x0.c => reset-starfive-common.c} | 68 +--
> > .../reset/starfive/reset-starfive-common.h | 14 +
> > .../reset/starfive/reset-starfive-jh7100.c | 4 +-
> > .../reset/starfive/reset-starfive-jh7110.c | 8 +-
> > .../reset/starfive/reset-starfive-jh71x0.h | 14 -
> > .../reset/starfive/reset-starfive-jh8100.c | 102 ++++
> > .../dt-bindings/clock/starfive,jh8100-crg.h | 430 +++++++++++++
> > .../dt-bindings/reset/starfive,jh8100-crg.h | 127 ++++
> > ...rfive-jh71x0.h => reset-starfive-common.h} | 10 +-
> > 40 files changed, 4485 insertions(+), 1242 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-aoncrg.yaml
> > create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-ne.yaml
> > create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-nw.yaml
> > create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-sw.yaml
> > create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg.yaml
> > create mode 100644 arch/riscv/boot/dts/starfive/jh8100-clk.dtsi
> > create mode 100644 drivers/clk/starfive/clk-starfive-common.c
> > create mode 100644 drivers/clk/starfive/clk-starfive-common.h
> > delete mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.c
> > delete mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.h
> > create mode 100644 drivers/clk/starfive/jh8100/Makefile
> > create mode 100644 drivers/clk/starfive/jh8100/clk-aon.c
> > create mode 100644 drivers/clk/starfive/jh8100/clk-starfive-jh8100.h
> > create mode 100644 drivers/clk/starfive/jh8100/clk-sys-ne.c
> > create mode 100644 drivers/clk/starfive/jh8100/clk-sys-nw.c
> > create mode 100644 drivers/clk/starfive/jh8100/clk-sys-sw.c
> > create mode 100644 drivers/clk/starfive/jh8100/clk-sys.c
> > rename drivers/reset/starfive/{reset-starfive-jh71x0.c => reset-starfive-common.c} (55%)
> > create mode 100644 drivers/reset/starfive/reset-starfive-common.h
> > delete mode 100644 drivers/reset/starfive/reset-starfive-jh71x0.h
> > create mode 100644 drivers/reset/starfive/reset-starfive-jh8100.c
> > create mode 100644 include/dt-bindings/clock/starfive,jh8100-crg.h
> > create mode 100644 include/dt-bindings/reset/starfive,jh8100-crg.h
> > rename include/soc/starfive/{reset-starfive-jh71x0.h => reset-starfive-common.h} (50%)
> >
> > --
> > 2.34.1
> >
> -----Original Message-----
> From: Krzysztof Kozlowski <[email protected]>
> Sent: Saturday, December 9, 2023 1:53 AM
> To: JeeHeng Sia <[email protected]>; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> <[email protected]>; Xingyu Wu <[email protected]>
> Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon Tan
> <[email protected]>
> Subject: Re: [PATCH v1 05/16] dt-bindings: clock: Add StarFive JH8100 System clock and reset generator
>
> On 06/12/2023 12:49, Sia Jee Heng wrote:
> > Add bindings for the System clocks and reset generator
> > (SYSCRG) on JH8100 SoC.
> >
> > Signed-off-by: Sia Jee Heng <[email protected]>
> > Reviewed-by: Ley Foon Tan <[email protected]>
> > ---
>
> ...
>
> > + clocks:
> > + items:
> > + - description: Main Oscillator (24 MHz)
> > + - description: External I2S Rx BCLK clock
> > + - description: External I2S Rx LRCK clock
> > + - description: External MCLK clock
> > +
> > + clock-names:
> > + items:
> > + - const: clk_osc
> > + - const: clk_i2srx_bclk_ext
> > + - const: clk_i2srx_lrck_ext
> > + - const: clk_mclk_ext
>
> Drop clk_ prefixes everywhere.
Noted.
>
> > +
> > + '#clock-cells':
> > + const: 1
> > + description:
> > + See <dt-bindings/clock/starfive,jh8100-crg.h> for valid indices.
> > +
> > + '#reset-cells':
> > + const: 1
> > + description:
> > + See <dt-bindings/reset/starfive-jh8100-crg.h> for valid indices.
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > + - clock-names
> > + - '#clock-cells'
> > + - '#reset-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/starfive,jh8100-crg.h>
> > +
> > + clock-controller@126d0000 {
> > + compatible = "starfive,jh8100-syscrg";
>
> Use 4 spaces for example indentation.
Noted
>
> > + reg = <0x126d0000 0x10000>;
> > + clocks = <&clk_osc>, <&clk_i2srx_bclk_ext>,
> > + <&clk_i2srx_lrck_ext>, <&clk_mclk_ext>;
> > + clock-names = "clk_osc", "clk_i2srx_bclk_ext",
> > + "clk_i2srx_lrck_ext", "clk_mclk_ext";
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h
> > new file mode 100644
> > index 000000000000..e5bb588ce798
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/starfive,jh8100-crg.h
> > @@ -0,0 +1,123 @@
> > +/* SPDX-License-Identifier: GPL-2.0 OR MIT */
>
> How about keeping the same license as binding?
Shouldn't b a problem.
>
> > +/*
> > + * Copyright (C) 2023 StarFive Technology Co., Ltd.
> > + * Sia Jee Heng <[email protected]>
> > + *
> > + */
> > +
>
> ...
>
> > +#define SYSCRG_CLK_NNE_ICG_EN 108
> > +
> > +#define SYSCRG_CLK_END 109
>
> Drop from binding header.
Do you mean don’t define the number of clk in the header? I'll have to define
It in the driver then..
>
> > +#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */
>
> ...
>
> > + */
> > +#define SYSCRG_RSTN_SYS_SYSCON 0
> > +#define SYSCRG_RSTN_CLK_MOD 1
> > +#define SYSCRG_RSTN_GPU 2
> > +#define SYSCRG_RSTN_GPU_SPU 3
> > +#define SYSCRG_RSTN_GPU_TVSENSOR 4
> > +#define SYSCRG_RSTN_PPU_OP_NORET_GPU_RESET 5
> > +#define SYSCRG_RSTN_NNE 6
> > +#define SYSCRG_RSTN_HD_AUDIO 7
> > +
> > +#define SYSCRG_RESET_NR_RESETS 8
>
> Drop from binding header.
Do you mean don’t define the number of reset in the header? I'll have to define
It in the driver then..
>
> > +
> > +#endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */
>
> Best regards,
> Krzysztof
> -----Original Message-----
> From: Krzysztof Kozlowski <[email protected]>
> Sent: Saturday, December 9, 2023 1:54 AM
> To: JeeHeng Sia <[email protected]>; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> <[email protected]>; Xingyu Wu <[email protected]>
> Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon Tan
> <[email protected]>
> Subject: Re: [PATCH v1 07/16] dt-bindings: clock: Add StarFive JH8100 System-North-West clock and reset generator
>
> On 06/12/2023 12:49, Sia Jee Heng wrote:
> > Add bindings for the System-North-West clock and reset generator
> > (SYSCRG-NW) on JH8100 SoC.
> >
> > Signed-off-by: Sia Jee Heng <[email protected]>
> > Reviewed-by: Ley Foon Tan <[email protected]>
> > ---
> > .../clock/starfive,jh8100-syscrg-nw.yaml | 119 ++++++++++++++++++
> > .../dt-bindings/clock/starfive,jh8100-crg.h | 45 +++++++
> > .../dt-bindings/reset/starfive,jh8100-crg.h | 15 +++
> > 3 files changed, 179 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-nw.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-nw.yaml
> b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-nw.yaml
> > new file mode 100644
> > index 000000000000..b16a874828dd
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg-nw.yaml
> > @@ -0,0 +1,119 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/starfive,jh8100-syscrg-nw.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: StarFive JH8100 System-North-West Clock and Reset Generator
> > +
> > +maintainers:
> > + - Sia Jee Heng <[email protected]>
> > +
> > +properties:
> > + compatible:
> > + const: starfive,jh8100-syscrg-nw
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + items:
> > + - description: Main Oscillator (24 MHz)
> > + - description: APB_BUS clock from SYSCRG
> > + - description: ISP_2X clock from SYSCRG
> > + - description: ISP_AXI clock from SYSCRG
> > + - description: VOUT_ROOT0 clock from SYSCRG
> > + - description: VOUT_ROOT1 clock from SYSCRG
> > + - description: VOUT_SCAN_ATS clock from SYSCRG
> > + - description: VOUT_DC_CORE clock from SYSCRG
> > + - description: VOUT_AXI clock from SYSCRG
> > + - description: AXI_400 clock from SYSCRG
> > + - description: AXI_200 clock from SYSCRG
> > + - description: Peripheral clock from SYSCRG
> > + - description: External DVP clock
> > + - description: External ISP DPHY TAP TCK clock
> > + - description: External golbal clock
> > + - description: External i2s_tscko clock
> > + - description: External VOUT MIPI DPHY TAP TCK
> > + - description: External VOUT eDP TAP TCK
> > + - description: External SPI In2 clock
> > +
> > + clock-names:
> > + items:
> > + - const: clk_osc
> > + - const: sys_clk_apb_bus
> > + - const: sys_clk_isp_2x
> > + - const: sys_clk_isp_axi
> > + - const: sys_clk_vout_root0
> > + - const: sys_clk_vout_root1
> > + - const: sys_clk_vout_scan_ats
> > + - const: sys_clk_vout_dc_core
> > + - const: sys_clk_vout_axi
> > + - const: sys_clk_axi_400
> > + - const: sys_clk_axi_200
> > + - const: sys_clk_perh_root_preosc
> > + - const: clk_dvp_ext
> > + - const: clk_isp_dphy_tap_tck_ext
> > + - const: clk_glb_ext_clk
> > + - const: clk_i2s_tscko
> > + - const: clk_vout_mipi_dphy_tap_tck_ext
> > + - const: clk_vout_edp_tap_tck_ext
> > + - const: clk_spi_in2_ext
>
> Same comments as for other patch.
Noted.
>
> > +
> > + '#clock-cells':
> > + const: 1
> > + description:
> > + See <dt-bindings/clock/starfive,jh8100-crg.h> for valid indices.
> > +
> > + '#reset-cells':
> > + const: 1
> > + description:
> > + See <dt-bindings/reset/starfive,jh8100-crg.h> for valid indices.
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > + - clock-names
> > + - '#clock-cells'
> > + - '#reset-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/starfive,jh8100-crg.h>
> > +
> > + clock-controller@123c0000 {
> > + compatible = "starfive,jh8100-syscrg-nw";
>
> Same comments as for other patch.
Noted.
>
>
> > + reg = <0x123c0000 0x10000>;
> > + clocks = <&clk_osc>, <&syscrg SYSCRG_CLK_APB_BUS>,
> > + <&syscrg SYSCRG_CLK_ISP_2X>,
> > + <&syscrg SYSCRG_CLK_ISP_AXI>,
> > + <&syscrg SYSCRG_CLK_VOUT_ROOT0>,
> > + <&syscrg SYSCRG_CLK_VOUT_ROOT1>,
> > + <&syscrg SYSCRG_CLK_VOUT_SCAN_ATS>,
> > + <&syscrg SYSCRG_CLK_VOUT_DC_CORE>,
> > + <&syscrg SYSCRG_CLK_VOUT_AXI>,
> > + <&syscrg SYSCRG_CLK_AXI_400>,
> > + <&syscrg SYSCRG_CLK_AXI_200>,
> > + <&syscrg SYSCRG_CLK_PERH_ROOT_PREOSC>,
> > + <&clk_dvp_ext>,
> > + <&clk_isp_dphy_tap_tck_ext>,
> > + <&clk_glb_ext_clk>,
> > + <&clk_i2s_tscko>,
> > + <&clk_vout_mipi_dphy_tap_tck_ext>,
> > + <&clk_vout_edp_tap_tck_ext>,
> > + <&clk_spi_in2_ext>;
> > + clock-names = "clk_osc", "sys_clk_apb_bus", "sys_clk_isp_2x",
> > + "sys_clk_isp_axi", "sys_clk_vout_root0",
> > + "sys_clk_vout_root1", "sys_clk_vout_scan_ats",
> > + "sys_clk_vout_dc_core", "sys_clk_vout_axi",
> > + "sys_clk_axi_400", "sys_clk_axi_200",
> > + "sys_clk_perh_root_preosc", "clk_dvp_ext",
> > + "clk_isp_dphy_tap_tck_ext", "clk_glb_ext_clk",
> > + "clk_i2s_tscko", "clk_vout_mipi_dphy_tap_tck_ext",
> > + "clk_vout_edp_tap_tck_ext", "clk_spi_in2_ext";
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h
> > index e5bb588ce798..8417455c2409 100644
> > --- a/include/dt-bindings/clock/starfive,jh8100-crg.h
> > +++ b/include/dt-bindings/clock/starfive,jh8100-crg.h
> > @@ -120,4 +120,49 @@
> > #define SYSCRG_CLK_NNE_ICG_EN 108
> >
> > #define SYSCRG_CLK_END 109
> > +
> > +/* SYSCRG_NW_CLK */
> > +#define SYSCRG_NW_CLK_PLL5_DIV2 0
> > +#define SYSCRG_NW_CLK_GCLK5 1
> > +#define SYSCRG_NW_CLK_GPIO_100 2
> > +#define SYSCRG_NW_CLK_GPIO_50 3
> > +#define SYSCRG_NW_CLK_GPIO_150 4
> > +#define SYSCRG_NW_CLK_GPIO_60 5
> > +#define SYSCRG_NW_CLK_IOMUX_WEST_PCLK 6
> > +#define SYSCRG_NW_CLK_I2C6_APB 7
> > +#define SYSCRG_NW_CLK_I2C7_APB 8
> > +#define SYSCRG_NW_CLK_SPI2_APB 9
> > +#define SYSCRG_NW_CLK_SPI2_CORE 10
> > +#define SYSCRG_NW_CLK_SPI2_SCLK_IN 11
> > +#define SYSCRG_NW_CLK_SMBUS1_APB 12
> > +#define SYSCRG_NW_CLK_SMBUS1_CORE 13
> > +#define SYSCRG_NW_CLK_ISP_DVP 14
> > +#define SYSCRG_NW_CLK_ISP_CORE_2X 15
> > +#define SYSCRG_NW_CLK_ISP_AXI 16
> > +#define SYSCRG_NW_CLK_ISP_DPHY_TAP_TCK 17
> > +#define SYSCRG_NW_CLK_FLEXNOC_ISPSLV 18
> > +#define SYSCRG_NW_CLK_VOUT_PIX0 19
> > +#define SYSCRG_NW_CLK_VOUT_PIX1 20
> > +#define SYSCRG_NW_CLK_VOUT_SCAN_ATS 21
> > +#define SYSCRG_NW_CLK_VOUT_DC_CORE 22
> > +#define SYSCRG_NW_CLK_VOUT_APB 23
> > +#define SYSCRG_NW_CLK_VOUT_DSI 24
> > +#define SYSCRG_NW_CLK_VOUT_AHB 25
> > +#define SYSCRG_NW_CLK_VOUT_AXI 26
> > +#define SYSCRG_NW_CLK_VOUT_MIPI_DPHY_TAP_TCK 27
> > +#define SYSCRG_NW_CLK_VOUT_EDP_PHY_TAP_TCK 28
> > +#define SYSCRG_NW_CLK_UART5_CORE_PREOSC 29
> > +#define SYSCRG_NW_CLK_UART5_APB 30
> > +#define SYSCRG_NW_CLK_UART5_CORE 31
> > +#define SYSCRG_NW_CLK_UART6_CORE_PREOSC 32
> > +#define SYSCRG_NW_CLK_UART6_APB 33
> > +#define SYSCRG_NW_CLK_UART6_CORE 34
> > +#define SYSCRG_NW_CLK_SPI2_ICG_EN 35
> > +#define SYSCRG_NW_CLK_SMBUS1_ICG_EN 36
> > +#define SYSCRG_NW_CLK_ISP_ICG_EN 37
> > +#define SYSCRG_NW_CLK_VOUT_ICG_EN 38
> > +#define SYSCRG_NW_CLK_UART5_ICG_EN 39
> > +#define SYSCRG_NW_CLK_UART6_ICG_EN 40
> > +
> > +#define SYSCRG_NW_CLK_END 41
>
> Same comments as for other patch.
Noted.
>
>
> > #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */
> > diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h
> > index 3b7b92488e76..8c3a858bdf6a 100644
> > --- a/include/dt-bindings/reset/starfive,jh8100-crg.h
> > +++ b/include/dt-bindings/reset/starfive,jh8100-crg.h
> > @@ -20,4 +20,19 @@
> >
> > #define SYSCRG_RESET_NR_RESETS 8
> >
> > +/*
> > + * syscrg_nw: assert0
> > + */
> > +#define SYSCRG_NW_RSTN_PRESETN 0
> > +#define SYSCRG_NW_RSTN_SYS_IOMUX_W 1
> > +#define SYSCRG_NW_RSTN_I2C6 2
> > +#define SYSCRG_NW_RSTN_I2C7 3
> > +#define SYSCRG_NW_RSTN_SPI2 4
> > +#define SYSCRG_NW_RSTN_SMBUS1 5
> > +#define SYSCRG_NW_RSTN_UART5 6
> > +#define SYSCRG_NW_RSTN_UART6 7
> > +#define SYSCRG_NW_RSTN_MERAK0_TVSENSOR 8
> > +#define SYSCRG_NW_RSTN_MERAK1_TVSENSOR 9
> > +
> > +#define SYSCRG_NW_RESET_NR_RESETS 10
>
> Same comments as for other patch.
Noted.
>
>
>
> Best regards,
> Krzysztof
> -----Original Message-----
> From: Krzysztof Kozlowski <[email protected]>
> Sent: Saturday, December 9, 2023 1:54 AM
> To: JeeHeng Sia <[email protected]>; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> <[email protected]>; Xingyu Wu <[email protected]>
> Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon Tan
> <[email protected]>
> Subject: Re: [PATCH v1 11/16] dt-bindings: clock: Add StarFive JH8100 System-South-West clock and reset generator
>
> On 06/12/2023 12:49, Sia Jee Heng wrote:
> > Add bindings for the System-South-West clock and reset generator
> > (SYSCRG-SW) on JH8100 SoC.
> >
> > Signed-off-by: Sia Jee Heng <[email protected]>
> > Reviewed-by: Ley Foon Tan <[email protected]>
> > ---
>
> All my previous comments are applicable.
Noted.
>
> Best regards,
> Krzysztof
> -----Original Message-----
> From: Krzysztof Kozlowski <[email protected]>
> Sent: Saturday, December 9, 2023 1:54 AM
> To: JeeHeng Sia <[email protected]>; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> <[email protected]>; Xingyu Wu <[email protected]>
> Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon Tan
> <[email protected]>
> Subject: Re: [PATCH v1 09/16] dt-bindings: clock: Add StarFive JH8100 System-North-East clock and reset generator
>
> On 06/12/2023 12:49, Sia Jee Heng wrote:
> > Add bindings for the System-North-East clock and reset generator
> > (SYSCRG-NE) on JH8100 SoC.
> >
> > Signed-off-by: Sia Jee Heng <[email protected]>
> > Reviewed-by: Ley Foon Tan <[email protected]>
> > ---
> > .../clock/starfive,jh8100-syscrg-ne.yaml | 158 ++++++++++++++++
> > .../dt-bindings/clock/starfive,jh8100-crg.h | 179 ++++++++++++++++++
> > .../dt-bindings/reset/starfive,jh8100-crg.h | 61 ++++++
>
> All my previous comments are applicable.
Noted.
>
> Best regards,
> Krzysztof
> -----Original Message-----
> From: Krzysztof Kozlowski <[email protected]>
> Sent: Saturday, December 9, 2023 1:55 AM
> To: JeeHeng Sia <[email protected]>; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> <[email protected]>; Xingyu Wu <[email protected]>
> Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon Tan
> <[email protected]>
> Subject: Re: [PATCH v1 13/16] dt-bindings: clock: Add StarFive JH8100 Always-On clock and reset generator
>
> On 06/12/2023 12:49, Sia Jee Heng wrote:
> > Add bindings for the Always-On clock and reset generator
> > (AONCRG) on JH8100 SoC.
> >
> > Signed-off-by: Sia Jee Heng <[email protected]>
> > Reviewed-by: Ley Foon Tan <[email protected]>
>
> All my previous comments are applicable.
Noted.
>
> Best regards,
> Krzysztof
> -----Original Message-----
> From: Krzysztof Kozlowski <[email protected]>
> Sent: Saturday, December 9, 2023 1:58 AM
> To: Emil Renner Berthing <[email protected]>; JeeHeng Sia <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> <[email protected]>; Xingyu Wu <[email protected]>
> Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon Tan
> <[email protected]>
> Subject: Re: [PATCH v1 16/16] riscv: dts: starfive: jh8100: Add clocks and resets nodes
>
> On 08/12/2023 17:39, Emil Renner Berthing wrote:
> > Sia Jee Heng wrote:
> >> Add SYSCRG/SYSCRG-NE/SYSCRG-NW/SYSCRG-SW/AONCRG clock and reset
> >> nodes for JH8100 RISC-V SoC.
> >>
> >> Signed-off-by: Sia Jee Heng <[email protected]>
> >> Reviewed-by: Ley Foon Tan <[email protected]>
> >> ---
> >> arch/riscv/boot/dts/starfive/jh8100-clk.dtsi | 180 +++++++++++++++++++
> >> arch/riscv/boot/dts/starfive/jh8100.dtsi | 115 ++++++++++++
> >
> > Why the split here? I mean why can't the clocks just be in the jh8100.dtsi?
>
> There should be. What's the point? Clocks are internal part of SoC and
> not really re-usable piece of hardware.
Can move it back to the SoC.dtsi
>
> Best regards,
> Krzysztof
> -----Original Message-----
> From: Krzysztof Kozlowski <[email protected]>
> Sent: Saturday, December 9, 2023 1:57 AM
> To: JeeHeng Sia <[email protected]>; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> <[email protected]>; Xingyu Wu <[email protected]>
> Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon Tan
> <[email protected]>
> Subject: Re: [PATCH v1 16/16] riscv: dts: starfive: jh8100: Add clocks and resets nodes
>
> On 06/12/2023 12:50, Sia Jee Heng wrote:
> > Add SYSCRG/SYSCRG-NE/SYSCRG-NW/SYSCRG-SW/AONCRG clock and reset
> > nodes for JH8100 RISC-V SoC.
> >
> > Signed-off-by: Sia Jee Heng <[email protected]>
> > Reviewed-by: Ley Foon Tan <[email protected]>
>
> Really? Looks automated... Care to provide any links to effects of
> internal review?
https://gitlab.starfivetech.com/jeeheng.sia/linux/-/commits/JH8100_Upstream/
>
> > ---
> > arch/riscv/boot/dts/starfive/jh8100-clk.dtsi | 180 +++++++++++++++++++
> > arch/riscv/boot/dts/starfive/jh8100.dtsi | 115 ++++++++++++
> > 2 files changed, 295 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/starfive/jh8100-clk.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/starfive/jh8100-clk.dtsi b/arch/riscv/boot/dts/starfive/jh8100-clk.dtsi
> > new file mode 100644
> > index 000000000000..27ba249f523e
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/starfive/jh8100-clk.dtsi
> > @@ -0,0 +1,180 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (C) 2023 StarFive Technology Co., Ltd.
> > + */
> > +
> > +/ {
> > + clk_osc: clk_osc {
>
> No underscores in node names.
Noted.
>
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <24000000>;
> > + };
> > +
>
> ...
>
> > diff --git a/arch/riscv/boot/dts/starfive/jh8100.dtsi b/arch/riscv/boot/dts/starfive/jh8100.dtsi
> > index f26aff5c1ddf..9863c61324a0 100644
> > --- a/arch/riscv/boot/dts/starfive/jh8100.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh8100.dtsi
> > @@ -4,6 +4,9 @@
> > */
> >
> > /dts-v1/;
> > +#include <dt-bindings/clock/starfive,jh8100-crg.h>
> > +#include <dt-bindings/reset/starfive,jh8100-crg.h>
> > +#include "jh8100-clk.dtsi"
> >
> > / {
> > compatible = "starfive,jh8100";
> > @@ -357,6 +360,104 @@ uart4: serial@121a0000 {
> > status = "disabled";
> > };
> >
> > + syscrg_ne: syscrg_ne@12320000 {
>
> clock-controller@
>
> Just open your bindings and take a look how it is done there...
>
> This applies everywhere
>
> Best regards,
> Krzysztof
On 12/12/2023 03:47, JeeHeng Sia wrote:
>>> +#define SYSCRG_CLK_NNE_ICG_EN 108
>>> +
>>> +#define SYSCRG_CLK_END 109
>>
>> Drop from binding header.
> Do you mean don’t define the number of clk in the header?
Yes
> I'll have to define
> It in the driver then..
And this is a problem because?
Best regards,
Krzysztof
On 12/12/2023 03:58, JeeHeng Sia wrote:
>
>
>> -----Original Message-----
>> From: Krzysztof Kozlowski <[email protected]>
>> Sent: Saturday, December 9, 2023 1:57 AM
>> To: JeeHeng Sia <[email protected]>; [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
>> <[email protected]>; Xingyu Wu <[email protected]>
>> Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon Tan
>> <[email protected]>
>> Subject: Re: [PATCH v1 16/16] riscv: dts: starfive: jh8100: Add clocks and resets nodes
>>
>> On 06/12/2023 12:50, Sia Jee Heng wrote:
>>> Add SYSCRG/SYSCRG-NE/SYSCRG-NW/SYSCRG-SW/AONCRG clock and reset
>>> nodes for JH8100 RISC-V SoC.
>>>
>>> Signed-off-by: Sia Jee Heng <[email protected]>
>>> Reviewed-by: Ley Foon Tan <[email protected]>
>>
>> Really? Looks automated... Care to provide any links to effects of
>> internal review?
> https://gitlab.starfivetech.com/jeeheng.sia/linux/-/commits/JH8100_Upstream/
>>
>>> ---
>>> arch/riscv/boot/dts/starfive/jh8100-clk.dtsi | 180 +++++++++++++++++++
>>> arch/riscv/boot/dts/starfive/jh8100.dtsi | 115 ++++++++++++
>>> 2 files changed, 295 insertions(+)
>>> create mode 100644 arch/riscv/boot/dts/starfive/jh8100-clk.dtsi
>>>
>>> diff --git a/arch/riscv/boot/dts/starfive/jh8100-clk.dtsi b/arch/riscv/boot/dts/starfive/jh8100-clk.dtsi
>>> new file mode 100644
>>> index 000000000000..27ba249f523e
>>> --- /dev/null
>>> +++ b/arch/riscv/boot/dts/starfive/jh8100-clk.dtsi
>>> @@ -0,0 +1,180 @@
>>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>>> +/*
>>> + * Copyright (C) 2023 StarFive Technology Co., Ltd.
>>> + */
>>> +
>>> +/ {
>>> + clk_osc: clk_osc {
>>
>> No underscores in node names.
> Noted.
>>
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <24000000>;
>>> + };
>>> +
>>
>> ...
>>
>>> diff --git a/arch/riscv/boot/dts/starfive/jh8100.dtsi b/arch/riscv/boot/dts/starfive/jh8100.dtsi
>>> index f26aff5c1ddf..9863c61324a0 100644
>>> --- a/arch/riscv/boot/dts/starfive/jh8100.dtsi
>>> +++ b/arch/riscv/boot/dts/starfive/jh8100.dtsi
>>> @@ -4,6 +4,9 @@
>>> */
>>>
>>> /dts-v1/;
>>> +#include <dt-bindings/clock/starfive,jh8100-crg.h>
>>> +#include <dt-bindings/reset/starfive,jh8100-crg.h>
>>> +#include "jh8100-clk.dtsi"
>>>
>>> / {
>>> compatible = "starfive,jh8100";
>>> @@ -357,6 +360,104 @@ uart4: serial@121a0000 {
>>> status = "disabled";
>>> };
>>>
>>> + syscrg_ne: syscrg_ne@12320000 {
>>
>> clock-controller@
>>
>> Just open your bindings and take a look how it is done there...
>>
>> This applies everywhere
I assume you did not ignore all the other comments you did not respond to.
Best regards,
Krzysztof
> -----Original Message-----
> From: Krzysztof Kozlowski <[email protected]>
> Sent: Tuesday, December 12, 2023 4:44 PM
> To: JeeHeng Sia <[email protected]>; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> <[email protected]>; Xingyu Wu <[email protected]>
> Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon Tan
> <[email protected]>
> Subject: Re: [PATCH v1 16/16] riscv: dts: starfive: jh8100: Add clocks and resets nodes
>
> On 12/12/2023 03:58, JeeHeng Sia wrote:
> >
> >
> >> -----Original Message-----
> >> From: Krzysztof Kozlowski <[email protected]>
> >> Sent: Saturday, December 9, 2023 1:57 AM
> >> To: JeeHeng Sia <[email protected]>; [email protected]; [email protected]; [email protected];
> >> [email protected]; [email protected]; [email protected]; [email protected];
> >> [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> >> <[email protected]>; Xingyu Wu <[email protected]>
> >> Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon
> Tan
> >> <[email protected]>
> >> Subject: Re: [PATCH v1 16/16] riscv: dts: starfive: jh8100: Add clocks and resets nodes
> >>
> >> On 06/12/2023 12:50, Sia Jee Heng wrote:
> >>> Add SYSCRG/SYSCRG-NE/SYSCRG-NW/SYSCRG-SW/AONCRG clock and reset
> >>> nodes for JH8100 RISC-V SoC.
> >>>
> >>> Signed-off-by: Sia Jee Heng <[email protected]>
> >>> Reviewed-by: Ley Foon Tan <[email protected]>
> >>
> >> Really? Looks automated... Care to provide any links to effects of
> >> internal review?
> > https://gitlab.starfivetech.com/jeeheng.sia/linux/-/commits/JH8100_Upstream/
> >>
> >>> ---
> >>> arch/riscv/boot/dts/starfive/jh8100-clk.dtsi | 180 +++++++++++++++++++
> >>> arch/riscv/boot/dts/starfive/jh8100.dtsi | 115 ++++++++++++
> >>> 2 files changed, 295 insertions(+)
> >>> create mode 100644 arch/riscv/boot/dts/starfive/jh8100-clk.dtsi
> >>>
> >>> diff --git a/arch/riscv/boot/dts/starfive/jh8100-clk.dtsi b/arch/riscv/boot/dts/starfive/jh8100-clk.dtsi
> >>> new file mode 100644
> >>> index 000000000000..27ba249f523e
> >>> --- /dev/null
> >>> +++ b/arch/riscv/boot/dts/starfive/jh8100-clk.dtsi
> >>> @@ -0,0 +1,180 @@
> >>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> >>> +/*
> >>> + * Copyright (C) 2023 StarFive Technology Co., Ltd.
> >>> + */
> >>> +
> >>> +/ {
> >>> + clk_osc: clk_osc {
> >>
> >> No underscores in node names.
> > Noted.
> >>
> >>> + compatible = "fixed-clock";
> >>> + #clock-cells = <0>;
> >>> + clock-frequency = <24000000>;
> >>> + };
> >>> +
> >>
> >> ...
> >>
> >>> diff --git a/arch/riscv/boot/dts/starfive/jh8100.dtsi b/arch/riscv/boot/dts/starfive/jh8100.dtsi
> >>> index f26aff5c1ddf..9863c61324a0 100644
> >>> --- a/arch/riscv/boot/dts/starfive/jh8100.dtsi
> >>> +++ b/arch/riscv/boot/dts/starfive/jh8100.dtsi
> >>> @@ -4,6 +4,9 @@
> >>> */
> >>>
> >>> /dts-v1/;
> >>> +#include <dt-bindings/clock/starfive,jh8100-crg.h>
> >>> +#include <dt-bindings/reset/starfive,jh8100-crg.h>
> >>> +#include "jh8100-clk.dtsi"
> >>>
> >>> / {
> >>> compatible = "starfive,jh8100";
> >>> @@ -357,6 +360,104 @@ uart4: serial@121a0000 {
> >>> status = "disabled";
> >>> };
> >>>
> >>> + syscrg_ne: syscrg_ne@12320000 {
> >>
> >> clock-controller@
> >>
> >> Just open your bindings and take a look how it is done there...
> >>
> >> This applies everywhere
>
> I assume you did not ignore all the other comments you did not respond to.
Arr, my bad. Will fix it.
>
> Best regards,
> Krzysztof
> -----Original Message-----
> From: Krzysztof Kozlowski <[email protected]>
> Sent: Tuesday, December 12, 2023 4:43 PM
> To: JeeHeng Sia <[email protected]>; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> <[email protected]>; Xingyu Wu <[email protected]>
> Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon Tan
> <[email protected]>
> Subject: Re: [PATCH v1 05/16] dt-bindings: clock: Add StarFive JH8100 System clock and reset generator
>
> On 12/12/2023 03:47, JeeHeng Sia wrote:
> >>> +#define SYSCRG_CLK_NNE_ICG_EN 108
> >>> +
> >>> +#define SYSCRG_CLK_END 109
> >>
> >> Drop from binding header.
> > Do you mean don’t define the number of clk in the header?
>
> Yes
>
> > I'll have to define
> > It in the driver then..
>
> And this is a problem because?
Nope, not a problem.
>
>
> Best regards,
> Krzysztof
> -----Original Message-----
> From: Emil Renner Berthing <[email protected]>
> Sent: Saturday, December 9, 2023 12:25 AM
> To: JeeHeng Sia <[email protected]>; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> <[email protected]>; Xingyu Wu <[email protected]>
> Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon Tan
> <[email protected]>
> Subject: Re: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver
>
> Sia Jee Heng wrote:
> > Add support for JH8100 System clock generator.
> >
> > Signed-off-by: Sia Jee Heng <[email protected]>
> > Reviewed-by: Ley Foon Tan <[email protected]>
> > ---
> > MAINTAINERS | 8 +
> > drivers/clk/starfive/Kconfig | 9 +
> > drivers/clk/starfive/Makefile | 1 +
> > drivers/clk/starfive/clk-starfive-common.h | 9 +-
> > drivers/clk/starfive/jh8100/Makefile | 3 +
> > .../clk/starfive/jh8100/clk-starfive-jh8100.h | 11 +
> > drivers/clk/starfive/jh8100/clk-sys.c | 455 ++++++++++++++++++
> > 7 files changed, 495 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/clk/starfive/jh8100/Makefile
> > create mode 100644 drivers/clk/starfive/jh8100/clk-starfive-jh8100.h
> > create mode 100644 drivers/clk/starfive/jh8100/clk-sys.c
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 788be9ab5b73..87bcb25becc1 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -20763,6 +20763,14 @@ F: Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
> > F: drivers/phy/starfive/phy-jh7110-pcie.c
> > F: drivers/phy/starfive/phy-jh7110-usb.c
> >
> > +STARFIVE JH8100 CLOCK DRIVERS
> > +M: Sia Jee Heng <[email protected]>
> > +M: Ley Foon Tan <[email protected]>
> > +S: Maintained
> > +F: Documentation/devicetree/bindings/clock/starfive,jh81*.yaml
> > +F: drivers/clk/starfive/jh8100
> > +F: include/dt-bindings/clock/starfive?jh81*.h
> > +
> > STATIC BRANCH/CALL
> > M: Peter Zijlstra <[email protected]>
> > M: Josh Poimboeuf <[email protected]>
> > diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
> > index ff8eace36e64..d8c7b9bb3895 100644
> > --- a/drivers/clk/starfive/Kconfig
> > +++ b/drivers/clk/starfive/Kconfig
> > @@ -72,3 +72,12 @@ config CLK_STARFIVE_JH7110_VOUT
> > help
> > Say yes here to support the Video-Output clock controller
> > on the StarFive JH7110 SoC.
[...]
> > diff --git a/drivers/clk/starfive/jh8100/Makefile b/drivers/clk/starfive/jh8100/Makefile
> > new file mode 100644
> > index 000000000000..af6a09e220d3
> > --- /dev/null
> > +++ b/drivers/clk/starfive/jh8100/Makefile
> > @@ -0,0 +1,3 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +# StarFive JH8100 Clock
> > +obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS) += clk-sys.o
>
> This will name the module clk-sys, which is way too generic. Please name this
> clk-starfive-jh8100-sys similar to the JH7110 drivers.
Just realized that I haven't reply to this comment.
I can't give it a longer name otherwise compiler will throw warning.
That’s why ends up to use a shorter name and keep it under jh8100 folder.
>
[...]
JeeHeng Sia wrote:
> > -----Original Message-----
> > From: Emil Renner Berthing <[email protected]>
> > Sent: Saturday, December 9, 2023 12:25 AM
> > To: JeeHeng Sia <[email protected]>; [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> > <[email protected]>; Xingyu Wu <[email protected]>
> > Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon Tan
> > <[email protected]>
> > Subject: Re: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver
> >
> > Sia Jee Heng wrote:
> > > Add support for JH8100 System clock generator.
> > >
> > > Signed-off-by: Sia Jee Heng <[email protected]>
> > > Reviewed-by: Ley Foon Tan <[email protected]>
> > > ---
> > > MAINTAINERS | 8 +
> > > drivers/clk/starfive/Kconfig | 9 +
> > > drivers/clk/starfive/Makefile | 1 +
> > > drivers/clk/starfive/clk-starfive-common.h | 9 +-
> > > drivers/clk/starfive/jh8100/Makefile | 3 +
> > > .../clk/starfive/jh8100/clk-starfive-jh8100.h | 11 +
> > > drivers/clk/starfive/jh8100/clk-sys.c | 455 ++++++++++++++++++
> > > 7 files changed, 495 insertions(+), 1 deletion(-)
> > > create mode 100644 drivers/clk/starfive/jh8100/Makefile
> > > create mode 100644 drivers/clk/starfive/jh8100/clk-starfive-jh8100.h
> > > create mode 100644 drivers/clk/starfive/jh8100/clk-sys.c
...
> > > diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
> > > index 012f7ee83f8e..6cb3ce823330 100644
> > > --- a/drivers/clk/starfive/Makefile
> > > +++ b/drivers/clk/starfive/Makefile
> > > @@ -10,3 +10,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
> > > obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o
> > > obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o
> > > obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
> > > +obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS) += jh8100/
> >
> > I don't really see why do you need a special subdirectory for the JH8100? The
> > JH7110 drivers do fine without it.
> Each subfolder can represent a different platform, making it easier to
> locate and maintain platform-specific code. Since the code is expected
> to grow in the future, let's start organizing it in a folder-based structure
> for easier maintenance at a later stage.
Yes, but that's not what you're doing here. You're making just one of the 3
almost identical drivers be different for no good reason.
> > > diff --git a/drivers/clk/starfive/clk-starfive-common.h b/drivers/clk/starfive/clk-starfive-common.h
> > > index fed45311360c..ec30af0658cf 100644
> > > --- a/drivers/clk/starfive/clk-starfive-common.h
> > > +++ b/drivers/clk/starfive/clk-starfive-common.h
> > > @@ -103,6 +103,13 @@ struct starfive_clk_data {
> > > .parents = { [0] = _parent }, \
> > > }
> > >
> > > +#define STARFIVE_GINV(_idx, _name, _flags, _parent)[_idx] = { \
> > > + .name = _name, \
> > > + .flags = _flags, \
> > > + .max = STARFIVE_CLK_ENABLE | STARFIVE_CLK_INVERT, \
> > > + .parents = { [0] = _parent }, \
> > > +}
> > > +
> > > struct starfive_clk {
> > > struct clk_hw hw;
> > > unsigned int idx;
> > > @@ -114,7 +121,7 @@ struct starfive_clk_priv {
> > > spinlock_t rmw_lock;
> > > struct device *dev;
> > > void __iomem *base;
> > > - struct clk_hw *pll[3];
> > > + struct clk_hw *pll[8];
> >
> > These extra slots are just used for fixed factor dummy PLLs right now, similar
> > to how the JH7110 first used them and later had to rework drivers and device
> > trees for the proper PLL driver.
> Yes, its intention is similar to JH8100. We will submit other clock
> domains and PLL at later stage but not so soon.
> >
> > This time around I'd much rather you work on getting the PLL driver in first,
> > so we don't need all that churn.
> I am sorry but we started development on FPGA. Unfortunately, the PLL driver
> and other domains are planned to be finished at a later stage. I have tried
> to minimize the churn as much as possible.
It's awesome that you're beginning upstreaming early, but if you don't have
this in silicon yet, how do you even know that this driver works?
If you're just using this for testing on FPGAs you can create dummy fixed
clocks in the device tree for the PLLs that this driver can consume. Then
later when you have a PLL driver you can replace those fixed clocks with the
output of that driver.
/Emil
JeeHeng Sia wrote:
> > -----Original Message-----
> > From: Emil Renner Berthing <[email protected]>
> > Sent: Saturday, December 9, 2023 12:37 AM
> > To: JeeHeng Sia <[email protected]>; [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> > <[email protected]>; Xingyu Wu <[email protected]>
> > Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon Tan
> > <[email protected]>
> > Subject: Re: [PATCH v1 07/16] dt-bindings: clock: Add StarFive JH8100 System-North-West clock and reset generator
> >
> > Sia Jee Heng wrote:
> > > Add bindings for the System-North-West clock and reset generator
> > > (SYSCRG-NW) on JH8100 SoC.
> > >
> > > Signed-off-by: Sia Jee Heng <[email protected]>
> > > Reviewed-by: Ley Foon Tan <[email protected]>
> > > ---
> > > .../clock/starfive,jh8100-syscrg-nw.yaml | 119 ++++++++++++++++++
> >
> > The JH7110 clocks, the JH8100 system and always-on all follow the Xcrg pattern:
> > syscrg
> > aoncrg
> > stgcrg
> > ispcrg
> > voutcrg
> > etc.
> >
> > Is there a reason the north-west, north-east and south-west breaks this pattern?
> > I'd have expected them to be called something like
> > nwcrg, JH8100_NWCLK_*, JH8100_NWRST_*,
> > necrg, JH8100_NECLK_*, JH8100_NERST_* and
> > swcrg, JH8100_SWCLK_*, JH8100_SWRST_*
> >
> > Just like all the other Starfive drivers.
> Understood your concern. We don’t have the intention to break the pattern,
> but the reason we skip the SoC_ prefix is that the SoC names were already
> defined in the header file with the SoC name.
> However, I can put it back, of course.
Yes, all these 3 JHXX00 drivers are almost identical. There should be no reason
to name any one of them differently. Having them all be as similar as possible
will make it a lot easier to maintain in the future. If you don't like a
pattern then please change it for all the similar drivers and don't make just
one of them be different.
/Emil
JeeHeng Sia wrote:
>
>
> > -----Original Message-----
> > From: Emil Renner Berthing <[email protected]>
> > Sent: Saturday, December 9, 2023 12:25 AM
> > To: JeeHeng Sia <[email protected]>; [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> > <[email protected]>; Xingyu Wu <[email protected]>
> > Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon Tan
> > <[email protected]>
> > Subject: Re: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver
> >
> > Sia Jee Heng wrote:
> > > Add support for JH8100 System clock generator.
> > >
> > > Signed-off-by: Sia Jee Heng <[email protected]>
> > > Reviewed-by: Ley Foon Tan <[email protected]>
> > > ---
> > > MAINTAINERS | 8 +
> > > drivers/clk/starfive/Kconfig | 9 +
> > > drivers/clk/starfive/Makefile | 1 +
> > > drivers/clk/starfive/clk-starfive-common.h | 9 +-
> > > drivers/clk/starfive/jh8100/Makefile | 3 +
> > > .../clk/starfive/jh8100/clk-starfive-jh8100.h | 11 +
> > > drivers/clk/starfive/jh8100/clk-sys.c | 455 ++++++++++++++++++
> > > 7 files changed, 495 insertions(+), 1 deletion(-)
> > > create mode 100644 drivers/clk/starfive/jh8100/Makefile
> > > create mode 100644 drivers/clk/starfive/jh8100/clk-starfive-jh8100.h
> > > create mode 100644 drivers/clk/starfive/jh8100/clk-sys.c
> > >
[...]
> > > diff --git a/drivers/clk/starfive/jh8100/Makefile b/drivers/clk/starfive/jh8100/Makefile
> > > new file mode 100644
> > > index 000000000000..af6a09e220d3
> > > --- /dev/null
> > > +++ b/drivers/clk/starfive/jh8100/Makefile
> > > @@ -0,0 +1,3 @@
> > > +# SPDX-License-Identifier: GPL-2.0
> > > +# StarFive JH8100 Clock
> > > +obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS) += clk-sys.o
> >
> > This will name the module clk-sys, which is way too generic. Please name this
> > clk-starfive-jh8100-sys similar to the JH7110 drivers.
> Just realized that I haven't reply to this comment.
> I can't give it a longer name otherwise compiler will throw warning.
> That’s why ends up to use a shorter name and keep it under jh8100 folder.
I'm sorry, how does that make any sense? If the compiler can compile
drivers/clk/starfive/clk-starfive-jh7110-sys.c
just fine, then why would it have trouble with
drivers/clk/starfive/clk-starfive-jh8100-sys.c
/Emil
> -----Original Message-----
> From: Emil Renner Berthing <[email protected]>
> Sent: Wednesday, December 13, 2023 7:57 PM
> To: JeeHeng Sia <[email protected]>; Emil Renner Berthing <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> <[email protected]>; Xingyu Wu <[email protected]>
> Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon Tan
> <[email protected]>
> Subject: RE: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver
>
> JeeHeng Sia wrote:
> > > -----Original Message-----
> > > From: Emil Renner Berthing <[email protected]>
> > > Sent: Saturday, December 9, 2023 12:25 AM
> > > To: JeeHeng Sia <[email protected]>; [email protected]; [email protected]; [email protected];
> > > [email protected]; [email protected]; [email protected]; [email protected];
> > > [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> > > <[email protected]>; Xingyu Wu <[email protected]>
> > > Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon
> Tan
> > > <[email protected]>
> > > Subject: Re: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver
> > >
> > > Sia Jee Heng wrote:
> > > > Add support for JH8100 System clock generator.
> > > >
> > > > Signed-off-by: Sia Jee Heng <[email protected]>
> > > > Reviewed-by: Ley Foon Tan <[email protected]>
> > > > ---
> > > > MAINTAINERS | 8 +
> > > > drivers/clk/starfive/Kconfig | 9 +
> > > > drivers/clk/starfive/Makefile | 1 +
> > > > drivers/clk/starfive/clk-starfive-common.h | 9 +-
> > > > drivers/clk/starfive/jh8100/Makefile | 3 +
> > > > .../clk/starfive/jh8100/clk-starfive-jh8100.h | 11 +
> > > > drivers/clk/starfive/jh8100/clk-sys.c | 455 ++++++++++++++++++
> > > > 7 files changed, 495 insertions(+), 1 deletion(-)
> > > > create mode 100644 drivers/clk/starfive/jh8100/Makefile
> > > > create mode 100644 drivers/clk/starfive/jh8100/clk-starfive-jh8100.h
> > > > create mode 100644 drivers/clk/starfive/jh8100/clk-sys.c
> ...
> > > > diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
> > > > index 012f7ee83f8e..6cb3ce823330 100644
> > > > --- a/drivers/clk/starfive/Makefile
> > > > +++ b/drivers/clk/starfive/Makefile
> > > > @@ -10,3 +10,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
> > > > obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o
> > > > obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o
> > > > obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
> > > > +obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS) += jh8100/
> > >
> > > I don't really see why do you need a special subdirectory for the JH8100? The
> > > JH7110 drivers do fine without it.
> > Each subfolder can represent a different platform, making it easier to
> > locate and maintain platform-specific code. Since the code is expected
> > to grow in the future, let's start organizing it in a folder-based structure
> > for easier maintenance at a later stage.
>
> Yes, but that's not what you're doing here. You're making just one of the 3
> almost identical drivers be different for no good reason.
I will restructure it for the other 2 platforms.
>
[...]
JeeHeng Sia wrote:
>
>
> > -----Original Message-----
> > From: Emil Renner Berthing <[email protected]>
> > Sent: Wednesday, December 13, 2023 7:57 PM
> > To: JeeHeng Sia <[email protected]>; Emil Renner Berthing <[email protected]>; [email protected];
> > [email protected]; [email protected]; [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> > <[email protected]>; Xingyu Wu <[email protected]>
> > Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon Tan
> > <[email protected]>
> > Subject: RE: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver
> >
> > JeeHeng Sia wrote:
> > > > -----Original Message-----
> > > > From: Emil Renner Berthing <[email protected]>
> > > > Sent: Saturday, December 9, 2023 12:25 AM
> > > > To: JeeHeng Sia <[email protected]>; [email protected]; [email protected]; [email protected];
> > > > [email protected]; [email protected]; [email protected]; [email protected];
> > > > [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> > > > <[email protected]>; Xingyu Wu <[email protected]>
> > > > Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon
> > Tan
> > > > <[email protected]>
> > > > Subject: Re: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver
> > > >
> > > > Sia Jee Heng wrote:
> > > > > Add support for JH8100 System clock generator.
> > > > >
> > > > > Signed-off-by: Sia Jee Heng <[email protected]>
> > > > > Reviewed-by: Ley Foon Tan <[email protected]>
> > > > > ---
> > > > > MAINTAINERS | 8 +
> > > > > drivers/clk/starfive/Kconfig | 9 +
> > > > > drivers/clk/starfive/Makefile | 1 +
> > > > > drivers/clk/starfive/clk-starfive-common.h | 9 +-
> > > > > drivers/clk/starfive/jh8100/Makefile | 3 +
> > > > > .../clk/starfive/jh8100/clk-starfive-jh8100.h | 11 +
> > > > > drivers/clk/starfive/jh8100/clk-sys.c | 455 ++++++++++++++++++
> > > > > 7 files changed, 495 insertions(+), 1 deletion(-)
> > > > > create mode 100644 drivers/clk/starfive/jh8100/Makefile
> > > > > create mode 100644 drivers/clk/starfive/jh8100/clk-starfive-jh8100.h
> > > > > create mode 100644 drivers/clk/starfive/jh8100/clk-sys.c
> > ...
> > > > > diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
> > > > > index 012f7ee83f8e..6cb3ce823330 100644
> > > > > --- a/drivers/clk/starfive/Makefile
> > > > > +++ b/drivers/clk/starfive/Makefile
> > > > > @@ -10,3 +10,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
> > > > > obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o
> > > > > obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o
> > > > > obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
> > > > > +obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS) += jh8100/
> > > >
> > > > I don't really see why do you need a special subdirectory for the JH8100? The
> > > > JH7110 drivers do fine without it.
> > > Each subfolder can represent a different platform, making it easier to
> > > locate and maintain platform-specific code. Since the code is expected
> > > to grow in the future, let's start organizing it in a folder-based structure
> > > for easier maintenance at a later stage.
> >
> > Yes, but that's not what you're doing here. You're making just one of the 3
> > almost identical drivers be different for no good reason.
> I will restructure it for the other 2 platforms.
That would be less bad, but you still haven't explained why you need to move
everything around like that:
https://lore.kernel.org/linux-riscv/CAJM55Z_3Mty2LftPVkQC1wbwtGeznMMAk9mAjH_GoNuL7CKtaQ@mail.gmail.com/
I don't think just "too many files" is a very good argument here. Just look at
drivers/clk/sunxi
/Emil
> -----Original Message-----
> From: Emil Renner Berthing <[email protected]>
> Sent: Wednesday, December 13, 2023 8:05 PM
> To: JeeHeng Sia <[email protected]>; Emil Renner Berthing <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> <[email protected]>; Xingyu Wu <[email protected]>
> Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon Tan
> <[email protected]>
> Subject: RE: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver
>
> JeeHeng Sia wrote:
> >
> >
> > > -----Original Message-----
> > > From: Emil Renner Berthing <[email protected]>
> > > Sent: Saturday, December 9, 2023 12:25 AM
> > > To: JeeHeng Sia <[email protected]>; [email protected]; [email protected]; [email protected];
> > > [email protected]; [email protected]; [email protected]; [email protected];
> > > [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> > > <[email protected]>; Xingyu Wu <[email protected]>
> > > Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon
> Tan
> > > <[email protected]>
> > > Subject: Re: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver
> > >
> > > Sia Jee Heng wrote:
> > > > Add support for JH8100 System clock generator.
> > > >
> > > > Signed-off-by: Sia Jee Heng <[email protected]>
> > > > Reviewed-by: Ley Foon Tan <[email protected]>
> > > > ---
> > > > MAINTAINERS | 8 +
> > > > drivers/clk/starfive/Kconfig | 9 +
> > > > drivers/clk/starfive/Makefile | 1 +
> > > > drivers/clk/starfive/clk-starfive-common.h | 9 +-
> > > > drivers/clk/starfive/jh8100/Makefile | 3 +
> > > > .../clk/starfive/jh8100/clk-starfive-jh8100.h | 11 +
> > > > drivers/clk/starfive/jh8100/clk-sys.c | 455 ++++++++++++++++++
> > > > 7 files changed, 495 insertions(+), 1 deletion(-)
> > > > create mode 100644 drivers/clk/starfive/jh8100/Makefile
> > > > create mode 100644 drivers/clk/starfive/jh8100/clk-starfive-jh8100.h
> > > > create mode 100644 drivers/clk/starfive/jh8100/clk-sys.c
> > > >
> [...]
> > > > diff --git a/drivers/clk/starfive/jh8100/Makefile b/drivers/clk/starfive/jh8100/Makefile
> > > > new file mode 100644
> > > > index 000000000000..af6a09e220d3
> > > > --- /dev/null
> > > > +++ b/drivers/clk/starfive/jh8100/Makefile
> > > > @@ -0,0 +1,3 @@
> > > > +# SPDX-License-Identifier: GPL-2.0
> > > > +# StarFive JH8100 Clock
> > > > +obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS) += clk-sys.o
> > >
> > > This will name the module clk-sys, which is way too generic. Please name this
> > > clk-starfive-jh8100-sys similar to the JH7110 drivers.
> > Just realized that I haven't reply to this comment.
> > I can't give it a longer name otherwise compiler will throw warning.
> > That’s why ends up to use a shorter name and keep it under jh8100 folder.
>
> I'm sorry, how does that make any sense? If the compiler can compile
>
> drivers/clk/starfive/clk-starfive-jh7110-sys.c
>
> just fine, then why would it have trouble with
>
> drivers/clk/starfive/clk-starfive-jh8100-sys.c
Based on the experiment conducted at the early stage, the warning message is coming
from the name of the auxiliary device (reset in this case). We try to map the name of
the reset device with the file's name, and at that moment, the file name is longer than
32 characters in length. In your given example, 'clk-starfive-jh8100-sys' is within the
32-character limit, so it should be okay. Given that the trend is not to use subfolders to
differentiate the platform clock driver, I am okay with removing the subfolder and
following the naming convention from the JH71xx's file name.
>
> /Emil
> -----Original Message-----
> From: Emil Renner Berthing <[email protected]>
> Sent: Wednesday, December 20, 2023 1:40 AM
> To: JeeHeng Sia <[email protected]>; Emil Renner Berthing <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> <[email protected]>; Xingyu Wu <[email protected]>
> Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon Tan
> <[email protected]>
> Subject: RE: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver
>
> JeeHeng Sia wrote:
> >
> >
> > > -----Original Message-----
> > > From: Emil Renner Berthing <[email protected]>
> > > Sent: Wednesday, December 13, 2023 7:57 PM
> > > To: JeeHeng Sia <[email protected]>; Emil Renner Berthing <[email protected]>; [email protected];
> > > [email protected]; [email protected]; [email protected]; [email protected]; [email protected];
> > > [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> > > <[email protected]>; Xingyu Wu <[email protected]>
> > > Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon
> Tan
> > > <[email protected]>
> > > Subject: RE: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver
> > >
> > > JeeHeng Sia wrote:
> > > > > -----Original Message-----
> > > > > From: Emil Renner Berthing <[email protected]>
> > > > > Sent: Saturday, December 9, 2023 12:25 AM
> > > > > To: JeeHeng Sia <[email protected]>; [email protected]; [email protected]; [email protected];
> > > > > [email protected]; [email protected]; [email protected]; [email protected];
> > > > > [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> > > > > <[email protected]>; Xingyu Wu <[email protected]>
> > > > > Cc: [email protected]; [email protected]; [email protected]; [email protected];
> Leyfoon
> > > Tan
> > > > > <[email protected]>
> > > > > Subject: Re: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver
> > > > >
> > > > > Sia Jee Heng wrote:
> > > > > > Add support for JH8100 System clock generator.
> > > > > >
> > > > > > Signed-off-by: Sia Jee Heng <[email protected]>
> > > > > > Reviewed-by: Ley Foon Tan <[email protected]>
> > > > > > ---
> > > > > > MAINTAINERS | 8 +
> > > > > > drivers/clk/starfive/Kconfig | 9 +
> > > > > > drivers/clk/starfive/Makefile | 1 +
> > > > > > drivers/clk/starfive/clk-starfive-common.h | 9 +-
> > > > > > drivers/clk/starfive/jh8100/Makefile | 3 +
> > > > > > .../clk/starfive/jh8100/clk-starfive-jh8100.h | 11 +
> > > > > > drivers/clk/starfive/jh8100/clk-sys.c | 455 ++++++++++++++++++
> > > > > > 7 files changed, 495 insertions(+), 1 deletion(-)
> > > > > > create mode 100644 drivers/clk/starfive/jh8100/Makefile
> > > > > > create mode 100644 drivers/clk/starfive/jh8100/clk-starfive-jh8100.h
> > > > > > create mode 100644 drivers/clk/starfive/jh8100/clk-sys.c
> > > ...
> > > > > > diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
> > > > > > index 012f7ee83f8e..6cb3ce823330 100644
> > > > > > --- a/drivers/clk/starfive/Makefile
> > > > > > +++ b/drivers/clk/starfive/Makefile
> > > > > > @@ -10,3 +10,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
> > > > > > obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o
> > > > > > obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o
> > > > > > obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
> > > > > > +obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS) += jh8100/
> > > > >
> > > > > I don't really see why do you need a special subdirectory for the JH8100? The
> > > > > JH7110 drivers do fine without it.
> > > > Each subfolder can represent a different platform, making it easier to
> > > > locate and maintain platform-specific code. Since the code is expected
> > > > to grow in the future, let's start organizing it in a folder-based structure
> > > > for easier maintenance at a later stage.
> > >
> > > Yes, but that's not what you're doing here. You're making just one of the 3
> > > almost identical drivers be different for no good reason.
> > I will restructure it for the other 2 platforms.
>
> That would be less bad, but you still haven't explained why you need to move
> everything around like that:
> https://lore.kernel.org/linux-riscv/CAJM55Z_3Mty2LftPVkQC1wbwtGeznMMAk9mAjH_GoNuL7CKtaQ@mail.gmail.com/
>
> I don't think just "too many files" is a very good argument here. Just look at
> drivers/clk/sunxi
Thanks. Given that the trend is not to use subfolders to differentiate the platform
clock driver, I am okay with removing the subfolder and following the naming
convention from the JH71xx's file name.
>
> /Emil
> -----Original Message-----
> From: Emil Renner Berthing <[email protected]>
> Sent: Wednesday, December 13, 2023 7:57 PM
> To: JeeHeng Sia <[email protected]>; Emil Renner Berthing <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> <[email protected]>; Xingyu Wu <[email protected]>
> Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon Tan
> <[email protected]>
> Subject: RE: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver
>
> JeeHeng Sia wrote:
> > > -----Original Message-----
> > > From: Emil Renner Berthing <[email protected]>
> > > Sent: Saturday, December 9, 2023 12:25 AM
> > > To: JeeHeng Sia <[email protected]>; [email protected]; [email protected]; [email protected];
> > > [email protected]; [email protected]; [email protected]; [email protected];
> > > [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> > > <[email protected]>; Xingyu Wu <[email protected]>
> > > Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon
> Tan
> > > <[email protected]>
> > > Subject: Re: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver
> > >
> > > Sia Jee Heng wrote:
> > > > Add support for JH8100 System clock generator.
> > > >
> > > > Signed-off-by: Sia Jee Heng <[email protected]>
> > > > Reviewed-by: Ley Foon Tan <[email protected]>
> > > > ---
> > > > MAINTAINERS | 8 +
> > > > drivers/clk/starfive/Kconfig | 9 +
> > > > drivers/clk/starfive/Makefile | 1 +
> > > > drivers/clk/starfive/clk-starfive-common.h | 9 +-
> > > > drivers/clk/starfive/jh8100/Makefile | 3 +
> > > > .../clk/starfive/jh8100/clk-starfive-jh8100.h | 11 +
> > > > drivers/clk/starfive/jh8100/clk-sys.c | 455 ++++++++++++++++++
> > > > 7 files changed, 495 insertions(+), 1 deletion(-)
> > > > create mode 100644 drivers/clk/starfive/jh8100/Makefile
> > > > create mode 100644 drivers/clk/starfive/jh8100/clk-starfive-jh8100.h
> > > > create mode 100644 drivers/clk/starfive/jh8100/clk-sys.c
> ...
> > > > diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
> > > > index 012f7ee83f8e..6cb3ce823330 100644
> > > > --- a/drivers/clk/starfive/Makefile
> > > > +++ b/drivers/clk/starfive/Makefile
> > > > @@ -10,3 +10,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
> > > > obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o
> > > > obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o
> > > > obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
> > > > +obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS) += jh8100/
> > >
> > > I don't really see why do you need a special subdirectory for the JH8100? The
> > > JH7110 drivers do fine without it.
> > Each subfolder can represent a different platform, making it easier to
> > locate and maintain platform-specific code. Since the code is expected
> > to grow in the future, let's start organizing it in a folder-based structure
> > for easier maintenance at a later stage.
>
> Yes, but that's not what you're doing here. You're making just one of the 3
> almost identical drivers be different for no good reason.
>
> > > > diff --git a/drivers/clk/starfive/clk-starfive-common.h b/drivers/clk/starfive/clk-starfive-common.h
> > > > index fed45311360c..ec30af0658cf 100644
> > > > --- a/drivers/clk/starfive/clk-starfive-common.h
> > > > +++ b/drivers/clk/starfive/clk-starfive-common.h
> > > > @@ -103,6 +103,13 @@ struct starfive_clk_data {
> > > > .parents = { [0] = _parent }, \
> > > > }
> > > >
> > > > +#define STARFIVE_GINV(_idx, _name, _flags, _parent)[_idx] = { \
> > > > + .name = _name, \
> > > > + .flags = _flags, \
> > > > + .max = STARFIVE_CLK_ENABLE | STARFIVE_CLK_INVERT, \
> > > > + .parents = { [0] = _parent }, \
> > > > +}
> > > > +
> > > > struct starfive_clk {
> > > > struct clk_hw hw;
> > > > unsigned int idx;
> > > > @@ -114,7 +121,7 @@ struct starfive_clk_priv {
> > > > spinlock_t rmw_lock;
> > > > struct device *dev;
> > > > void __iomem *base;
> > > > - struct clk_hw *pll[3];
> > > > + struct clk_hw *pll[8];
> > >
> > > These extra slots are just used for fixed factor dummy PLLs right now, similar
> > > to how the JH7110 first used them and later had to rework drivers and device
> > > trees for the proper PLL driver.
> > Yes, its intention is similar to JH8100. We will submit other clock
> > domains and PLL at later stage but not so soon.
> > >
> > > This time around I'd much rather you work on getting the PLL driver in first,
> > > so we don't need all that churn.
> > I am sorry but we started development on FPGA. Unfortunately, the PLL driver
> > and other domains are planned to be finished at a later stage. I have tried
> > to minimize the churn as much as possible.
>
> It's awesome that you're beginning upstreaming early, but if you don't have
> this in silicon yet, how do you even know that this driver works?
>
> If you're just using this for testing on FPGAs you can create dummy fixed
> clocks in the device tree for the PLLs that this driver can consume. Then
> later when you have a PLL driver you can replace those fixed clocks with the
> output of that driver.
The PLL fixed clocks were created in the C code. I interpret this message
as a suggestion to create a PLL fixed clock in the DT?
>
> /Emil
JeeHeng Sia wrote:
>
>
> > -----Original Message-----
> > From: Emil Renner Berthing <[email protected]>
> > Sent: Wednesday, December 13, 2023 7:57 PM
> > To: JeeHeng Sia <[email protected]>; Emil Renner Berthing <[email protected]>; [email protected];
> > [email protected]; [email protected]; [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> > <[email protected]>; Xingyu Wu <[email protected]>
> > Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon Tan
> > <[email protected]>
> > Subject: RE: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver
> >
> > JeeHeng Sia wrote:
> > > > -----Original Message-----
> > > > From: Emil Renner Berthing <[email protected]>
> > > > Sent: Saturday, December 9, 2023 12:25 AM
> > > > To: JeeHeng Sia <[email protected]>; [email protected]; [email protected]; [email protected];
> > > > [email protected]; [email protected]; [email protected]; [email protected];
> > > > [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> > > > <[email protected]>; Xingyu Wu <[email protected]>
> > > > Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon
> > Tan
> > > > <[email protected]>
> > > > Subject: Re: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver
> > > >
> > > > Sia Jee Heng wrote:
> > > > > Add support for JH8100 System clock generator.
> > > > >
> > > > > Signed-off-by: Sia Jee Heng <[email protected]>
> > > > > Reviewed-by: Ley Foon Tan <[email protected]>
> > > > > ---
> > > > > MAINTAINERS | 8 +
> > > > > drivers/clk/starfive/Kconfig | 9 +
> > > > > drivers/clk/starfive/Makefile | 1 +
> > > > > drivers/clk/starfive/clk-starfive-common.h | 9 +-
> > > > > drivers/clk/starfive/jh8100/Makefile | 3 +
> > > > > .../clk/starfive/jh8100/clk-starfive-jh8100.h | 11 +
> > > > > drivers/clk/starfive/jh8100/clk-sys.c | 455 ++++++++++++++++++
> > > > > 7 files changed, 495 insertions(+), 1 deletion(-)
> > > > > create mode 100644 drivers/clk/starfive/jh8100/Makefile
> > > > > create mode 100644 drivers/clk/starfive/jh8100/clk-starfive-jh8100.h
> > > > > create mode 100644 drivers/clk/starfive/jh8100/clk-sys.c
> > ...
> > > > > diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
> > > > > index 012f7ee83f8e..6cb3ce823330 100644
> > > > > --- a/drivers/clk/starfive/Makefile
> > > > > +++ b/drivers/clk/starfive/Makefile
> > > > > @@ -10,3 +10,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
> > > > > obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o
> > > > > obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o
> > > > > obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
> > > > > +obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS) += jh8100/
> > > >
> > > > I don't really see why do you need a special subdirectory for the JH8100? The
> > > > JH7110 drivers do fine without it.
> > > Each subfolder can represent a different platform, making it easier to
> > > locate and maintain platform-specific code. Since the code is expected
> > > to grow in the future, let's start organizing it in a folder-based structure
> > > for easier maintenance at a later stage.
> >
> > Yes, but that's not what you're doing here. You're making just one of the 3
> > almost identical drivers be different for no good reason.
> >
> > > > > diff --git a/drivers/clk/starfive/clk-starfive-common.h b/drivers/clk/starfive/clk-starfive-common.h
> > > > > index fed45311360c..ec30af0658cf 100644
> > > > > --- a/drivers/clk/starfive/clk-starfive-common.h
> > > > > +++ b/drivers/clk/starfive/clk-starfive-common.h
> > > > > @@ -103,6 +103,13 @@ struct starfive_clk_data {
> > > > > .parents = { [0] = _parent }, \
> > > > > }
> > > > >
> > > > > +#define STARFIVE_GINV(_idx, _name, _flags, _parent)[_idx] = { \
> > > > > + .name = _name, \
> > > > > + .flags = _flags, \
> > > > > + .max = STARFIVE_CLK_ENABLE | STARFIVE_CLK_INVERT, \
> > > > > + .parents = { [0] = _parent }, \
> > > > > +}
> > > > > +
> > > > > struct starfive_clk {
> > > > > struct clk_hw hw;
> > > > > unsigned int idx;
> > > > > @@ -114,7 +121,7 @@ struct starfive_clk_priv {
> > > > > spinlock_t rmw_lock;
> > > > > struct device *dev;
> > > > > void __iomem *base;
> > > > > - struct clk_hw *pll[3];
> > > > > + struct clk_hw *pll[8];
> > > >
> > > > These extra slots are just used for fixed factor dummy PLLs right now, similar
> > > > to how the JH7110 first used them and later had to rework drivers and device
> > > > trees for the proper PLL driver.
> > > Yes, its intention is similar to JH8100. We will submit other clock
> > > domains and PLL at later stage but not so soon.
> > > >
> > > > This time around I'd much rather you work on getting the PLL driver in first,
> > > > so we don't need all that churn.
> > > I am sorry but we started development on FPGA. Unfortunately, the PLL driver
> > > and other domains are planned to be finished at a later stage. I have tried
> > > to minimize the churn as much as possible.
> >
> > It's awesome that you're beginning upstreaming early, but if you don't have
> > this in silicon yet, how do you even know that this driver works?
> >
> > If you're just using this for testing on FPGAs you can create dummy fixed
> > clocks in the device tree for the PLLs that this driver can consume. Then
> > later when you have a PLL driver you can replace those fixed clocks with the
> > output of that driver.
> The PLL fixed clocks were created in the C code. I interpret this message
> as a suggestion to create a PLL fixed clock in the DT?
Yes, then you don't need to change the clock driver and its bindings but just
need to update the clock references to the PLL driver once you have that.
/Emil
> -----Original Message-----
> From: Emil Renner Berthing <[email protected]>
> Sent: Wednesday, December 20, 2023 9:08 PM
> To: JeeHeng Sia <[email protected]>; Emil Renner Berthing <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected]; Hal Feng
> <[email protected]>; Xingyu Wu <[email protected]>
> Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leyfoon Tan
> <[email protected]>
> Subject: RE: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver
>
> JeeHeng Sia wrote:
[...]
> > >
> > > If you're just using this for testing on FPGAs you can create dummy fixed
> > > clocks in the device tree for the PLLs that this driver can consume. Then
> > > later when you have a PLL driver you can replace those fixed clocks with the
> > > output of that driver.
> > The PLL fixed clocks were created in the C code. I interpret this message
> > as a suggestion to create a PLL fixed clock in the DT?
>
> Yes, then you don't need to change the clock driver and its bindings but just
> need to update the clock references to the PLL driver once you have that.
Ok.
>
> /Emil