This series is based on matthias github, v6.1-next.
The previous discussion:
https://patchwork.kernel.org/project/linux-mediatek/patch/[email protected]/
Change from v1:
- move allOf before additionalProperties
- add buck isolation setting patches into series
Allen-KH Cheng (6):
soc: mediatek: pm-domains: Add buck isolation offset and mask to power
domain data
soc: mediatek: pm-domains: Add buck isolation setting in power domain
dt-bindings: power: Add MT8192 ADSP power domain
soc: mediatek: pm-domains: Add ADSP power domain data for MT8192
dt-bindings: arm: mediatek: Add missing power-domains property
arm64: dts: mediatek: Add the missing ADSP power domains controller
for MT8192
.../arm/mediatek/mediatek,mt8192-clock.yaml | 17 +++++++++++++++++
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 9 +++++++++
drivers/soc/mediatek/mt8192-pm-domains.h | 16 ++++++++++++++++
drivers/soc/mediatek/mtk-pm-domains.c | 8 ++++++++
drivers/soc/mediatek/mtk-pm-domains.h | 5 +++++
include/dt-bindings/power/mt8192-power.h | 1 +
6 files changed, 56 insertions(+)
--
2.18.0
Add the missing ADSP power domains controller for mt8192-scp_adsp clock
controllers.
Fixes: 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192 clock controllers")
Signed-off-by: Allen-KH Cheng <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 6b20376191a7..6ee60db3ac23 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -511,6 +511,14 @@
};
};
};
+
+ power-domain@MT8192_POWER_DOMAIN_ADSP {
+ reg = <MT8192_POWER_DOMAIN_ADSP>;
+ clocks = <&topckgen CLK_TOP_ADSP_SEL>;
+ clock-names = "adsp";
+ mediatek,infracfg = <&infracfg>;
+ #power-domain-cells = <0>;
+ };
};
};
@@ -574,6 +582,7 @@
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8192-scp_adsp";
reg = <0 0x10720000 0 0x1000>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_ADSP>;
#clock-cells = <1>;
};
--
2.18.0
Add ADSP pm-domains (mtcmos) data for MT8192 SoC.
Signed-off-by: Allen-KH Cheng <[email protected]>
---
drivers/soc/mediatek/mt8192-pm-domains.h | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/soc/mediatek/mt8192-pm-domains.h b/drivers/soc/mediatek/mt8192-pm-domains.h
index b97b2051920f..19e58f0ca1df 100644
--- a/drivers/soc/mediatek/mt8192-pm-domains.h
+++ b/drivers/soc/mediatek/mt8192-pm-domains.h
@@ -287,6 +287,22 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
},
+ [MT8192_POWER_DOMAIN_ADSP] = {
+ .name = "adsp",
+ .sta_mask = BIT(22),
+ .ctl_offs = 0x0358,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .ext_buck_iso_offs = 0x039C,
+ .ext_buck_iso_mask = BIT(2),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_ADSP,
+ MT8192_TOP_AXI_PROT_EN_2_SET,
+ MT8192_TOP_AXI_PROT_EN_2_CLR,
+ MT8192_TOP_AXI_PROT_EN_2_STA1),
+ },
+ .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_EXT_BUCK_ISO,
+ },
[MT8192_POWER_DOMAIN_CAM] = {
.name = "cam",
.sta_mask = BIT(23),
--
2.18.0
Add power domain ID for the ADSP power partition found on MT8192 SoC.
Signed-off-by: Allen-KH Cheng <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
---
include/dt-bindings/power/mt8192-power.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/power/mt8192-power.h b/include/dt-bindings/power/mt8192-power.h
index 4eaa53d7270a..63e81cd0d06d 100644
--- a/include/dt-bindings/power/mt8192-power.h
+++ b/include/dt-bindings/power/mt8192-power.h
@@ -28,5 +28,6 @@
#define MT8192_POWER_DOMAIN_CAM_RAWA 18
#define MT8192_POWER_DOMAIN_CAM_RAWB 19
#define MT8192_POWER_DOMAIN_CAM_RAWC 20
+#define MT8192_POWER_DOMAIN_ADSP 21
#endif /* _DT_BINDINGS_POWER_MT8192_POWER_H */
--
2.18.0
The "mediatek,mt8192-scp_adsp" binding requires a power domain to be
specified.
Fixes: 4a803990aeb1 ("dt-bindings: ARM: Mediatek: Add new document bindings of MT8192 clock")
Signed-off-by: Allen-KH Cheng <[email protected]>
---
.../arm/mediatek/mediatek,mt8192-clock.yaml | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
index b57cc2e69efb..ce8dd2bfb533 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
@@ -40,6 +40,9 @@ properties:
reg:
maxItems: 1
+ power-domains:
+ maxItems: 1
+
'#clock-cells':
const: 1
@@ -47,13 +50,27 @@ required:
- compatible
- reg
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mediatek,mt8192-scp_adsp
+ then:
+ required:
+ - power-domains
+
additionalProperties: false
examples:
- |
+ #include <dt-bindings/power/mt8192-power.h>
+
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8192-scp_adsp";
reg = <0x10720000 0x1000>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_ADSP>;
#clock-cells = <1>;
};
--
2.18.0
On 21/12/2022 04:44, Allen-KH Cheng wrote:
> The "mediatek,mt8192-scp_adsp" binding requires a power domain to be
> specified.
That's not true. Before this patch, how does the binding require a power
domain? Please show me the part of binding which requires it.
Best regards,
Krzysztof
Il 21/12/22 04:44, Allen-KH Cheng ha scritto:
> Add power domain ID for the ADSP power partition found on MT8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <[email protected]>
> Acked-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Il 21/12/22 04:44, Allen-KH Cheng ha scritto:
> Add the missing ADSP power domains controller for mt8192-scp_adsp clock
> controllers.
>
> Fixes: 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192 clock controllers")
> Signed-off-by: Allen-KH Cheng <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Il 21/12/22 11:33, Krzysztof Kozlowski ha scritto:
> On 21/12/2022 11:22, AngeloGioacchino Del Regno wrote:
>> Il 21/12/22 04:44, Allen-KH Cheng ha scritto:
>>> The "mediatek,mt8192-scp_adsp" binding requires a power domain to be
>>> specified.
>>>
>>> Fixes: 4a803990aeb1 ("dt-bindings: ARM: Mediatek: Add new document bindings of MT8192 clock")
>>> Signed-off-by: Allen-KH Cheng <[email protected]>
>>> ---
>>> .../arm/mediatek/mediatek,mt8192-clock.yaml | 17 +++++++++++++++++
>>> 1 file changed, 17 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
>>> index b57cc2e69efb..ce8dd2bfb533 100644
>>> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
>>> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
>>> @@ -40,6 +40,9 @@ properties:
>>> reg:
>>> maxItems: 1
>>>
>>> + power-domains:
>>> + maxItems: 1
>>> +
>>> '#clock-cells':
>>> const: 1
>>>
>>> @@ -47,13 +50,27 @@ required:
>>> - compatible
>>> - reg
>>>
>>> +allOf:
>>
>> allOf is unnecessary here.
>
> If you mean that "if:" can be without it, then it is better to have
> allOf. It grows often, so you avoid useless indentation change later.
>
>
Yes, that's what I mean. I've suggested so because I don't expect this list
to grow in the future.
Regards,
Angelo
On 21/12/2022 11:22, AngeloGioacchino Del Regno wrote:
> Il 21/12/22 04:44, Allen-KH Cheng ha scritto:
>> The "mediatek,mt8192-scp_adsp" binding requires a power domain to be
>> specified.
>>
>> Fixes: 4a803990aeb1 ("dt-bindings: ARM: Mediatek: Add new document bindings of MT8192 clock")
>> Signed-off-by: Allen-KH Cheng <[email protected]>
>> ---
>> .../arm/mediatek/mediatek,mt8192-clock.yaml | 17 +++++++++++++++++
>> 1 file changed, 17 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
>> index b57cc2e69efb..ce8dd2bfb533 100644
>> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
>> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
>> @@ -40,6 +40,9 @@ properties:
>> reg:
>> maxItems: 1
>>
>> + power-domains:
>> + maxItems: 1
>> +
>> '#clock-cells':
>> const: 1
>>
>> @@ -47,13 +50,27 @@ required:
>> - compatible
>> - reg
>>
>> +allOf:
>
> allOf is unnecessary here.
If you mean that "if:" can be without it, then it is better to have
allOf. It grows often, so you avoid useless indentation change later.
Best regards,
Krzysztof
Il 21/12/22 04:44, Allen-KH Cheng ha scritto:
> Add ADSP pm-domains (mtcmos) data for MT8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Il 21/12/22 04:44, Allen-KH Cheng ha scritto:
> The "mediatek,mt8192-scp_adsp" binding requires a power domain to be
> specified.
>
> Fixes: 4a803990aeb1 ("dt-bindings: ARM: Mediatek: Add new document bindings of MT8192 clock")
> Signed-off-by: Allen-KH Cheng <[email protected]>
> ---
> .../arm/mediatek/mediatek,mt8192-clock.yaml | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
> index b57cc2e69efb..ce8dd2bfb533 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
> @@ -40,6 +40,9 @@ properties:
> reg:
> maxItems: 1
>
> + power-domains:
> + maxItems: 1
> +
> '#clock-cells':
> const: 1
>
> @@ -47,13 +50,27 @@ required:
> - compatible
> - reg
>
> +allOf:
allOf is unnecessary here.
Regards,
Angelo
On Wed, Dec 21, 2022 at 4:18 PM Krzysztof Kozlowski
<[email protected]> wrote:
>
> On 21/12/2022 04:44, Allen-KH Cheng wrote:
> > The "mediatek,mt8192-scp_adsp" binding requires a power domain to be
> > specified.
>
> That's not true. Before this patch, how does the binding require a power
> domain? Please show me the part of binding which requires it.
Maybe this should be reworded to something like the following?
<--- cut
The SCP_ADSP clock controller has a power domain dependency that was not
described properly. Add it to the binding.
<--- cut
This was discovered when I was reworking the clock drivers. The clocks
in this controller were being turned off by the clock core, which would
result in the system locking up. MediaTek said this was due to the power
domain.
Regards
ChenYu
On 21/12/2022 04:44, Allen-KH Cheng wrote:
> Add ADSP pm-domains (mtcmos) data for MT8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <[email protected]>
> ---
> drivers/soc/mediatek/mt8192-pm-domains.h | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8192-pm-domains.h b/drivers/soc/mediatek/mt8192-pm-domains.h
> index b97b2051920f..19e58f0ca1df 100644
> --- a/drivers/soc/mediatek/mt8192-pm-domains.h
> +++ b/drivers/soc/mediatek/mt8192-pm-domains.h
> @@ -287,6 +287,22 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> },
> + [MT8192_POWER_DOMAIN_ADSP] = {
> + .name = "adsp",
> + .sta_mask = BIT(22),
> + .ctl_offs = 0x0358,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + .ext_buck_iso_offs = 0x039C,
Can we get a define for this magic number please?
Regards,
Matthias
> + .ext_buck_iso_mask = BIT(2),
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_ADSP,
> + MT8192_TOP_AXI_PROT_EN_2_SET,
> + MT8192_TOP_AXI_PROT_EN_2_CLR,
> + MT8192_TOP_AXI_PROT_EN_2_STA1),
> + },
> + .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_EXT_BUCK_ISO,
> + },
> [MT8192_POWER_DOMAIN_CAM] = {
> .name = "cam",
> .sta_mask = BIT(23),