From: Biwen Li <[email protected]>
The 'fsl,ippdexpcr1-alt-addr' property is used to handle an errata A-008646
on LS1021A
Signed-off-by: Biwen Li <[email protected]>
Signed-off-by: Ran Wang <[email protected]>
---
Documentation/devicetree/bindings/soc/fsl/rcpm.txt | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
index 5a33619..1be58a3 100644
--- a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
+++ b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
@@ -34,6 +34,11 @@ Chassis Version Example Chips
Optional properties:
- little-endian : RCPM register block is Little Endian. Without it RCPM
will be Big Endian (default case).
+ - fsl,ippdexpcr1-alt-addr : The property is related to a hardware issue
+ on SoC LS1021A and only needed on SoC LS1021A.
+ Must include 2 entries:
+ The first entry must be a link to the SCFG device node.
+ The 2nd entry must be offset of register IPPDEXPCR1 in SCFG.
Example:
The RCPM node for T4240:
@@ -43,6 +48,20 @@ The RCPM node for T4240:
#fsl,rcpm-wakeup-cells = <2>;
};
+The RCPM node for LS1021A:
+ rcpm: rcpm@1ee2140 {
+ compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+";
+ reg = <0x0 0x1ee2140 0x0 0x8>;
+ #fsl,rcpm-wakeup-cells = <2>;
+
+ /*
+ * The second and third entry compose an alt offset
+ * address for IPPDEXPCR1(SCFG_SPARECR8)
+ */
+ fsl,ippdexpcr1-alt-addr = <&scfg 0x51c>;
+ };
+
+
* Freescale RCPM Wakeup Source Device Tree Bindings
-------------------------------------------
Required fsl,rcpm-wakeup property should be added to a device node if the device
--
2.7.4
From: Biwen Li <[email protected]>
Description:
- Reading configuration register RCPM_IPPDEXPCR1
always return zero
Workaround:
- Save register RCPM_IPPDEXPCR1's value to
register SCFG_SPARECR8.(uboot's psci also
need reading value from the register SCFG_SPARECR8
to set register RCPM_IPPDEXPCR1)
Impact:
- FlexTimer module will cannot wakeup system in
deep sleep on SoC LS1021A
Signed-off-by: Biwen Li <[email protected]>
Signed-off-by: Ran Wang <[email protected]>
---
drivers/soc/fsl/rcpm.c | 42 +++++++++++++++++++++++++++++++++++++++++-
1 file changed, 41 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/fsl/rcpm.c b/drivers/soc/fsl/rcpm.c
index a093dbe..e6354f5 100644
--- a/drivers/soc/fsl/rcpm.c
+++ b/drivers/soc/fsl/rcpm.c
@@ -2,7 +2,7 @@
//
// rcpm.c - Freescale QorIQ RCPM driver
//
-// Copyright 2019 NXP
+// Copyright 2019-2020 NXP
//
// Author: Ran Wang <[email protected]>
@@ -13,6 +13,9 @@
#include <linux/slab.h>
#include <linux/suspend.h>
#include <linux/kernel.h>
+#include <linux/acpi.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
#define RCPM_WAKEUP_CELL_MAX_SIZE 7
@@ -37,6 +40,9 @@ static int rcpm_pm_prepare(struct device *dev)
struct device_node *np = dev->of_node;
u32 value[RCPM_WAKEUP_CELL_MAX_SIZE + 1];
u32 setting[RCPM_WAKEUP_CELL_MAX_SIZE] = {0};
+ struct regmap *scfg_addr_regmap = NULL;
+ u32 reg_offset[2];
+ u32 reg_value = 0;
rcpm = dev_get_drvdata(dev);
if (!rcpm)
@@ -90,6 +96,40 @@ static int rcpm_pm_prepare(struct device *dev)
tmp |= ioread32be(address);
iowrite32be(tmp, address);
}
+ /*
+ * Workaround of errata A-008646 on SoC LS1021A:
+ * There is a bug of register ippdexpcr1.
+ * Reading configuration register RCPM_IPPDEXPCR1
+ * always return zero. So save ippdexpcr1's value
+ * to register SCFG_SPARECR8.And the value of
+ * ippdexpcr1 will be read from SCFG_SPARECR8.
+ */
+ if (device_property_present(dev, "fsl,ippdexpcr1-alt-addr")) {
+ if (dev_of_node(dev)) {
+ scfg_addr_regmap = syscon_regmap_lookup_by_phandle(np,
+ "fsl,ippdexpcr1-alt-addr");
+ } else if (is_acpi_node(dev->fwnode)) {
+ continue;
+ }
+
+ if (scfg_addr_regmap && (i == 1)) {
+ if (device_property_read_u32_array(dev,
+ "fsl,ippdexpcr1-alt-addr",
+ reg_offset,
+ 2)) {
+ scfg_addr_regmap = NULL;
+ continue;
+ }
+ /* Read value from register SCFG_SPARECR8 */
+ regmap_read(scfg_addr_regmap,
+ reg_offset[1],
+ ®_value);
+ /* Write value to register SCFG_SPARECR8 */
+ regmap_write(scfg_addr_regmap,
+ reg_offset[1],
+ tmp | reg_value);
+ }
+ }
}
return 0;
--
2.7.4
> -----Original Message-----
> From: Ran Wang <[email protected]>
> Sent: Wednesday, September 16, 2020 3:18 AM
> To: Leo Li <[email protected]>; Rob Herring <[email protected]>;
> Shawn Guo <[email protected]>
> Cc: [email protected]; [email protected];
> [email protected]; [email protected]; Biwen Li
> <[email protected]>; Ran Wang <[email protected]>
> Subject: [PATCH 1/5] Documentation: dt: binding: fsl: Add 'fsl,ippdexpcr1-alt-
> addr' property
>
> From: Biwen Li <[email protected]>
>
> The 'fsl,ippdexpcr1-alt-addr' property is used to handle an errata A-008646 on
> LS1021A
It looks like the previous version of this patch has gotten the reviewed-by from Rob. It would be good to be added to the patch for new submission.
>
> Signed-off-by: Biwen Li <[email protected]>
> Signed-off-by: Ran Wang <[email protected]>
> ---
> Documentation/devicetree/bindings/soc/fsl/rcpm.txt | 19
> +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> index 5a33619..1be58a3 100644
> --- a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> +++ b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> @@ -34,6 +34,11 @@ Chassis Version Example Chips
> Optional properties:
> - little-endian : RCPM register block is Little Endian. Without it RCPM
> will be Big Endian (default case).
> + - fsl,ippdexpcr1-alt-addr : The property is related to a hardware issue
> + on SoC LS1021A and only needed on SoC LS1021A.
> + Must include 2 entries:
> + The first entry must be a link to the SCFG device node.
> + The 2nd entry must be offset of register IPPDEXPCR1 in SCFG.
>
> Example:
> The RCPM node for T4240:
> @@ -43,6 +48,20 @@ The RCPM node for T4240:
> #fsl,rcpm-wakeup-cells = <2>;
> };
>
> +The RCPM node for LS1021A:
> + rcpm: rcpm@1ee2140 {
> + compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+";
> + reg = <0x0 0x1ee2140 0x0 0x8>;
> + #fsl,rcpm-wakeup-cells = <2>;
> +
> + /*
> + * The second and third entry compose an alt offset
> + * address for IPPDEXPCR1(SCFG_SPARECR8)
> + */
> + fsl,ippdexpcr1-alt-addr = <&scfg 0x51c>;
> + };
> +
> +
> * Freescale RCPM Wakeup Source Device Tree Bindings
> -------------------------------------------
> Required fsl,rcpm-wakeup property should be added to a device node if the
> device
> --
> 2.7.4
> -----Original Message-----
> From: Ran Wang <[email protected]>
> Sent: Wednesday, September 16, 2020 3:18 AM
> To: Leo Li <[email protected]>; Rob Herring <[email protected]>;
> Shawn Guo <[email protected]>
> Cc: [email protected]; [email protected];
> [email protected]; [email protected]; Biwen Li
> <[email protected]>; Ran Wang <[email protected]>
> Subject: [PATCH 2/5] soc: fsl: handle RCPM errata A-008646 on SoC LS1021A
>
> From: Biwen Li <[email protected]>
>
> Description:
> - Reading configuration register RCPM_IPPDEXPCR1
> always return zero
>
> Workaround:
> - Save register RCPM_IPPDEXPCR1's value to
> register SCFG_SPARECR8.(uboot's psci also
> need reading value from the register SCFG_SPARECR8
> to set register RCPM_IPPDEXPCR1)
>
> Impact:
> - FlexTimer module will cannot wakeup system in
Will not..
Also it will be better to merge this with the issue description part above to prevent confusion.
> deep sleep on SoC LS1021A
>
> Signed-off-by: Biwen Li <[email protected]>
> Signed-off-by: Ran Wang <[email protected]>
> ---
> drivers/soc/fsl/rcpm.c | 42
> +++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 41 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/soc/fsl/rcpm.c b/drivers/soc/fsl/rcpm.c
> index a093dbe..e6354f5 100644
> --- a/drivers/soc/fsl/rcpm.c
> +++ b/drivers/soc/fsl/rcpm.c
> @@ -2,7 +2,7 @@
> //
> // rcpm.c - Freescale QorIQ RCPM driver
> //
> -// Copyright 2019 NXP
> +// Copyright 2019-2020 NXP
> //
> // Author: Ran Wang <[email protected]>
>
> @@ -13,6 +13,9 @@
> #include <linux/slab.h>
> #include <linux/suspend.h>
> #include <linux/kernel.h>
> +#include <linux/acpi.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/regmap.h>
>
> #define RCPM_WAKEUP_CELL_MAX_SIZE 7
>
> @@ -37,6 +40,9 @@ static int rcpm_pm_prepare(struct device *dev)
> struct device_node *np = dev->of_node;
> u32 value[RCPM_WAKEUP_CELL_MAX_SIZE + 1];
> u32 setting[RCPM_WAKEUP_CELL_MAX_SIZE] = {0};
> + struct regmap *scfg_addr_regmap = NULL;
> + u32 reg_offset[2];
> + u32 reg_value = 0;
>
> rcpm = dev_get_drvdata(dev);
> if (!rcpm)
> @@ -90,6 +96,40 @@ static int rcpm_pm_prepare(struct device *dev)
> tmp |= ioread32be(address);
> iowrite32be(tmp, address);
> }
> + /*
> + * Workaround of errata A-008646 on SoC LS1021A:
> + * There is a bug of register ippdexpcr1.
> + * Reading configuration register RCPM_IPPDEXPCR1
> + * always return zero. So save ippdexpcr1's value
> + * to register SCFG_SPARECR8.And the value of
> + * ippdexpcr1 will be read from SCFG_SPARECR8.
> + */
> + if (device_property_present(dev, "fsl,ippdexpcr1-alt-addr"))
> {
> + if (dev_of_node(dev)) {
> + scfg_addr_regmap =
> syscon_regmap_lookup_by_phandle(np,
> +
> "fsl,ippdexpcr1-alt-addr");
> + } else if (is_acpi_node(dev->fwnode)) {
> + continue;
> + }
> +
> + if (scfg_addr_regmap && (i == 1)) {
> + if (device_property_read_u32_array(dev,
> + "fsl,ippdexpcr1-alt-addr",
> + reg_offset,
> + 2)) {
It is not necessary to read out the whole fsl,ippdexpcr1-alt-addr property if we only need the offset. Also you can change to use the syscon_regmap_lookup_by_phandle_args() API above to simplify the code.
> + scfg_addr_regmap = NULL;
> + continue;
> + }
> + /* Read value from register SCFG_SPARECR8
> */
> + regmap_read(scfg_addr_regmap,
> + reg_offset[1],
> + ®_value);
> + /* Write value to register SCFG_SPARECR8 */
> + regmap_write(scfg_addr_regmap,
> + reg_offset[1],
> + tmp | reg_value);
> + }
> + }
> }
>
> return 0;
> --
> 2.7.4
Hi Leo
Tuesday, September 22, 2020 6:43 AM, Leo Li wrote:
>
>
> > -----Original Message-----
> > From: Ran Wang <[email protected]>
> > Sent: Wednesday, September 16, 2020 3:18 AM
> > To: Leo Li <[email protected]>; Rob Herring <[email protected]>;
> > Shawn Guo <[email protected]>
> > Cc: [email protected];
> > [email protected];
> > [email protected]; [email protected]; Biwen Li
> > <[email protected]>; Ran Wang <[email protected]>
> > Subject: [PATCH 2/5] soc: fsl: handle RCPM errata A-008646 on SoC
> > LS1021A
> >
> > From: Biwen Li <[email protected]>
> >
> > Description:
> > - Reading configuration register RCPM_IPPDEXPCR1
> > always return zero
> >
> > Workaround:
> > - Save register RCPM_IPPDEXPCR1's value to
> > register SCFG_SPARECR8.(uboot's psci also
> > need reading value from the register SCFG_SPARECR8
> > to set register RCPM_IPPDEXPCR1)
> >
> > Impact:
> > - FlexTimer module will cannot wakeup system in
> Will not..
> Also it will be better to merge this with the issue description part above to
> prevent confusion.
OK
> > deep sleep on SoC LS1021A
> >
> > Signed-off-by: Biwen Li <[email protected]>
> > Signed-off-by: Ran Wang <[email protected]>
> > ---
> > drivers/soc/fsl/rcpm.c | 42
> > +++++++++++++++++++++++++++++++++++++++++-
> > 1 file changed, 41 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/soc/fsl/rcpm.c b/drivers/soc/fsl/rcpm.c index
> > a093dbe..e6354f5 100644
> > --- a/drivers/soc/fsl/rcpm.c
> > +++ b/drivers/soc/fsl/rcpm.c
> > @@ -2,7 +2,7 @@
> > //
> > // rcpm.c - Freescale QorIQ RCPM driver // -// Copyright 2019 NXP
> > +// Copyright 2019-2020 NXP
> > //
> > // Author: Ran Wang <[email protected]>
> >
> > @@ -13,6 +13,9 @@
> > #include <linux/slab.h>
> > #include <linux/suspend.h>
> > #include <linux/kernel.h>
> > +#include <linux/acpi.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/regmap.h>
> >
> > #define RCPM_WAKEUP_CELL_MAX_SIZE 7
> >
> > @@ -37,6 +40,9 @@ static int rcpm_pm_prepare(struct device *dev)
> > struct device_node *np = dev->of_node;
> > u32 value[RCPM_WAKEUP_CELL_MAX_SIZE + 1];
> > u32 setting[RCPM_WAKEUP_CELL_MAX_SIZE] = {0};
> > + struct regmap *scfg_addr_regmap = NULL;
> > + u32 reg_offset[2];
> > + u32 reg_value = 0;
> >
> > rcpm = dev_get_drvdata(dev);
> > if (!rcpm)
> > @@ -90,6 +96,40 @@ static int rcpm_pm_prepare(struct device *dev)
> > tmp |= ioread32be(address);
> > iowrite32be(tmp, address);
> > }
> > + /*
> > + * Workaround of errata A-008646 on SoC LS1021A:
> > + * There is a bug of register ippdexpcr1.
> > + * Reading configuration register RCPM_IPPDEXPCR1
> > + * always return zero. So save ippdexpcr1's value
> > + * to register SCFG_SPARECR8.And the value of
> > + * ippdexpcr1 will be read from SCFG_SPARECR8.
> > + */
> > + if (device_property_present(dev, "fsl,ippdexpcr1-alt-addr"))
> > {
> > + if (dev_of_node(dev)) {
> > + scfg_addr_regmap =
> > syscon_regmap_lookup_by_phandle(np,
> > +
> > "fsl,ippdexpcr1-alt-addr");
> > + } else if (is_acpi_node(dev->fwnode)) {
> > + continue;
> > + }
> > +
> > + if (scfg_addr_regmap && (i == 1)) {
> > + if (device_property_read_u32_array(dev,
> > + "fsl,ippdexpcr1-alt-addr",
> > + reg_offset,
> > + 2)) {
>
> It is not necessary to read out the whole fsl,ippdexpcr1-alt-addr property if we
> only need the offset. Also you can change to use the
> syscon_regmap_lookup_by_phandle_args() API above to simplify the code.
Got it, will update it in next version, thanks.
Regards,
Ran
> > + scfg_addr_regmap = NULL;
> > + continue;
> > + }
> > + /* Read value from register SCFG_SPARECR8
> > */
> > + regmap_read(scfg_addr_regmap,
> > + reg_offset[1],
> > + ®_value);
> > + /* Write value to register SCFG_SPARECR8 */
> > + regmap_write(scfg_addr_regmap,
> > + reg_offset[1],
> > + tmp | reg_value);
> > + }
> > + }
> > }
> >
> > return 0;
> > --
> > 2.7.4
Hi Leo, Rob,
On Tuesday, September 22, 2020 6:20 AM, Leo Li wrote:
>
> > -----Original Message-----
> > From: Ran Wang <[email protected]>
> > Sent: Wednesday, September 16, 2020 3:18 AM
> > To: Leo Li <[email protected]>; Rob Herring <[email protected]>;
> > Shawn Guo <[email protected]>
> > Cc: [email protected];
> > [email protected];
> > [email protected]; [email protected]; Biwen Li
> > <[email protected]>; Ran Wang <[email protected]>
> > Subject: [PATCH 1/5] Documentation: dt: binding: fsl: Add
> > 'fsl,ippdexpcr1-alt- addr' property
> >
> > From: Biwen Li <[email protected]>
> >
> > The 'fsl,ippdexpcr1-alt-addr' property is used to handle an errata
> > A-008646 on LS1021A
>
> It looks like the previous version of this patch has gotten the reviewed-by from
> Rob. It would be good to be added to the patch for new submission.
Actually this patch has one update from previous version (https://lore.kernel.org/patchwork/patch/1161631/):
Reduce entry number from 3 to 2.
So I'd like to have a review for this one, sorry for not highlight this in advance.
Regards,
Ran
> >
> > Signed-off-by: Biwen Li <[email protected]>
> > Signed-off-by: Ran Wang <[email protected]>
> > ---
> > Documentation/devicetree/bindings/soc/fsl/rcpm.txt | 19
> > +++++++++++++++++++
> > 1 file changed, 19 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> > b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> > index 5a33619..1be58a3 100644
> > --- a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> > +++ b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> > @@ -34,6 +34,11 @@ Chassis Version Example Chips
> > Optional properties:
> > - little-endian : RCPM register block is Little Endian. Without it RCPM
> > will be Big Endian (default case).
> > + - fsl,ippdexpcr1-alt-addr : The property is related to a hardware issue
> > + on SoC LS1021A and only needed on SoC LS1021A.
> > + Must include 2 entries:
> > + The first entry must be a link to the SCFG device node.
> > + The 2nd entry must be offset of register IPPDEXPCR1 in SCFG.
> >
> > Example:
> > The RCPM node for T4240:
> > @@ -43,6 +48,20 @@ The RCPM node for T4240:
> > #fsl,rcpm-wakeup-cells = <2>;
> > };
> >
> > +The RCPM node for LS1021A:
> > + rcpm: rcpm@1ee2140 {
> > + compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+";
> > + reg = <0x0 0x1ee2140 0x0 0x8>;
> > + #fsl,rcpm-wakeup-cells = <2>;
> > +
> > + /*
> > + * The second and third entry compose an alt offset
> > + * address for IPPDEXPCR1(SCFG_SPARECR8)
> > + */
> > + fsl,ippdexpcr1-alt-addr = <&scfg 0x51c>;
> > + };
> > +
> > +
> > * Freescale RCPM Wakeup Source Device Tree Bindings
> > -------------------------------------------
> > Required fsl,rcpm-wakeup property should be added to a device node if
> > the device
> > --
> > 2.7.4
On Wed, Sep 16, 2020 at 04:18:27PM +0800, Ran Wang wrote:
> From: Biwen Li <[email protected]>
>
> The 'fsl,ippdexpcr1-alt-addr' property is used to handle an errata A-008646
> on LS1021A
>
> Signed-off-by: Biwen Li <[email protected]>
> Signed-off-by: Ran Wang <[email protected]>
> ---
> Documentation/devicetree/bindings/soc/fsl/rcpm.txt | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> index 5a33619..1be58a3 100644
> --- a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> +++ b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> @@ -34,6 +34,11 @@ Chassis Version Example Chips
> Optional properties:
> - little-endian : RCPM register block is Little Endian. Without it RCPM
> will be Big Endian (default case).
> + - fsl,ippdexpcr1-alt-addr : The property is related to a hardware issue
> + on SoC LS1021A and only needed on SoC LS1021A.
> + Must include 2 entries:
> + The first entry must be a link to the SCFG device node.
> + The 2nd entry must be offset of register IPPDEXPCR1 in SCFG.
You don't need a DT change for this. You can find SCFG node by its
compatible string and then the offset should be known given this issue
is only on 1 SoC.
Rob
Hi Rob,
On Wednesday, September 23, 2020 10:33 AM, Rob Herring wrote:
>
> On Wed, Sep 16, 2020 at 04:18:27PM +0800, Ran Wang wrote:
> > From: Biwen Li <[email protected]>
> >
> > The 'fsl,ippdexpcr1-alt-addr' property is used to handle an errata
> > A-008646 on LS1021A
> >
> > Signed-off-by: Biwen Li <[email protected]>
> > Signed-off-by: Ran Wang <[email protected]>
> > ---
> > Documentation/devicetree/bindings/soc/fsl/rcpm.txt | 19
> > +++++++++++++++++++
> > 1 file changed, 19 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> > b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> > index 5a33619..1be58a3 100644
> > --- a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> > +++ b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> > @@ -34,6 +34,11 @@ Chassis Version Example Chips
> > Optional properties:
> > - little-endian : RCPM register block is Little Endian. Without it RCPM
> > will be Big Endian (default case).
> > + - fsl,ippdexpcr1-alt-addr : The property is related to a hardware issue
> > + on SoC LS1021A and only needed on SoC LS1021A.
> > + Must include 2 entries:
> > + The first entry must be a link to the SCFG device node.
> > + The 2nd entry must be offset of register IPPDEXPCR1 in SCFG.
>
> You don't need a DT change for this. You can find SCFG node by its compatible
> string and then the offset should be known given this issue is only on 1 SoC.
Did you mean that RCPM driver just to access IPPDEXPCR1 shadowed register in SCFG
directly without fetching it's offset info. from DT?
Regards,
Ran
Hi Rob
Not sure whether you have missed this mail with my query.
Regards,
Ran
On Wednesday, September 23, 2020 2:44 PM Ran Wang wrote:
>
> Hi Rob,
>
> On Wednesday, September 23, 2020 10:33 AM, Rob Herring wrote:
> >
> > On Wed, Sep 16, 2020 at 04:18:27PM +0800, Ran Wang wrote:
> > > From: Biwen Li <[email protected]>
> > >
> > > The 'fsl,ippdexpcr1-alt-addr' property is used to handle an errata
> > > A-008646 on LS1021A
> > >
> > > Signed-off-by: Biwen Li <[email protected]>
> > > Signed-off-by: Ran Wang <[email protected]>
> > > ---
> > > Documentation/devicetree/bindings/soc/fsl/rcpm.txt | 19
> > > +++++++++++++++++++
> > > 1 file changed, 19 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> > > b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> > > index 5a33619..1be58a3 100644
> > > --- a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> > > +++ b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> > > @@ -34,6 +34,11 @@ Chassis Version Example Chips
> > > Optional properties:
> > > - little-endian : RCPM register block is Little Endian. Without it RCPM
> > > will be Big Endian (default case).
> > > + - fsl,ippdexpcr1-alt-addr : The property is related to a hardware issue
> > > + on SoC LS1021A and only needed on SoC LS1021A.
> > > + Must include 2 entries:
> > > + The first entry must be a link to the SCFG device node.
> > > + The 2nd entry must be offset of register IPPDEXPCR1 in SCFG.
> >
> > You don't need a DT change for this. You can find SCFG node by its
> > compatible string and then the offset should be known given this issue is
> only on 1 SoC.
>
> Did you mean that RCPM driver just to access IPPDEXPCR1 shadowed register
> in SCFG directly without fetching it's offset info. from DT?
>
> Regards,
> Ran
On Wed, Sep 23, 2020 at 1:44 AM Ran Wang <[email protected]> wrote:
>
> Hi Rob,
>
> On Wednesday, September 23, 2020 10:33 AM, Rob Herring wrote:
> >
> > On Wed, Sep 16, 2020 at 04:18:27PM +0800, Ran Wang wrote:
> > > From: Biwen Li <[email protected]>
> > >
> > > The 'fsl,ippdexpcr1-alt-addr' property is used to handle an errata
> > > A-008646 on LS1021A
> > >
> > > Signed-off-by: Biwen Li <[email protected]>
> > > Signed-off-by: Ran Wang <[email protected]>
> > > ---
> > > Documentation/devicetree/bindings/soc/fsl/rcpm.txt | 19
> > > +++++++++++++++++++
> > > 1 file changed, 19 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> > > b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> > > index 5a33619..1be58a3 100644
> > > --- a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> > > +++ b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> > > @@ -34,6 +34,11 @@ Chassis Version Example Chips
> > > Optional properties:
> > > - little-endian : RCPM register block is Little Endian. Without it RCPM
> > > will be Big Endian (default case).
> > > + - fsl,ippdexpcr1-alt-addr : The property is related to a hardware issue
> > > + on SoC LS1021A and only needed on SoC LS1021A.
> > > + Must include 2 entries:
> > > + The first entry must be a link to the SCFG device node.
> > > + The 2nd entry must be offset of register IPPDEXPCR1 in SCFG.
> >
> > You don't need a DT change for this. You can find SCFG node by its compatible
> > string and then the offset should be known given this issue is only on 1 SoC.
>
> Did you mean that RCPM driver just to access IPPDEXPCR1 shadowed register in SCFG
> directly without fetching it's offset info. from DT?
Yes. There's only 1 possible value of the offset because there's only
one SoC, so the driver can hardcode the offset. And I assume there's
only one SCFG node, so you can find it by its compatible string
(of_find_compatible_node).
Rob
Hi Rob,
On Monday, September 28, 2020 9:57 PM, Rob Herring wrote:
>
> On Wed, Sep 23, 2020 at 1:44 AM Ran Wang <[email protected]> wrote:
> >
> > Hi Rob,
> >
> > On Wednesday, September 23, 2020 10:33 AM, Rob Herring wrote:
> > >
> > > On Wed, Sep 16, 2020 at 04:18:27PM +0800, Ran Wang wrote:
> > > > From: Biwen Li <[email protected]>
> > > >
> > > > The 'fsl,ippdexpcr1-alt-addr' property is used to handle an errata
> > > > A-008646 on LS1021A
> > > >
> > > > Signed-off-by: Biwen Li <[email protected]>
> > > > Signed-off-by: Ran Wang <[email protected]>
> > > > ---
> > > > Documentation/devicetree/bindings/soc/fsl/rcpm.txt | 19
> > > > +++++++++++++++++++
> > > > 1 file changed, 19 insertions(+)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> > > > b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> > > > index 5a33619..1be58a3 100644
> > > > --- a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> > > > +++ b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> > > > @@ -34,6 +34,11 @@ Chassis Version Example Chips
> > > > Optional properties:
> > > > - little-endian : RCPM register block is Little Endian. Without it RCPM
> > > > will be Big Endian (default case).
> > > > + - fsl,ippdexpcr1-alt-addr : The property is related to a hardware issue
> > > > + on SoC LS1021A and only needed on SoC LS1021A.
> > > > + Must include 2 entries:
> > > > + The first entry must be a link to the SCFG device node.
> > > > + The 2nd entry must be offset of register IPPDEXPCR1 in SCFG.
> > >
> > > You don't need a DT change for this. You can find SCFG node by its
> > > compatible string and then the offset should be known given this issue is
> only on 1 SoC.
> >
> > Did you mean that RCPM driver just to access IPPDEXPCR1 shadowed
> > register in SCFG directly without fetching it's offset info. from DT?
>
> Yes. There's only 1 possible value of the offset because there's only one SoC, so
> the driver can hardcode the offset. And I assume there's only one SCFG node,
> so you can find it by its compatible string (of_find_compatible_node).
Got it, let me update this in next version, thank you.
Regards,
Ran
> Rob