Previously the variable rate audio pll output was fixed to a divider of
four. This is unfortunately incompatible with generating commonly used
I2S core clock rates like 24.576MHz from the 24MHz parent clock.
This commit adds support for arbitrary audio pll output dividers to fix
that.
Signed-off-by: Tobias Schramm <[email protected]>
---
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
index 0e36ca3bf3d5..c6cf590b235a 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
@@ -36,12 +36,9 @@ static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
0);
/*
- * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
- * the base (2x, 4x and 8x), and one variable divider (the one true
- * pll audio).
- *
- * We don't have any need for the variable divider for now, so we just
- * hardcode it to match with the clock names
+ * The Audio PLL has 4 outputs: 3 fixed factors from the base (2x, 4x and 8x),
+ * and one variable divider (the one true pll audio).
+ * The variable rate output is supported via a a separate divider below.
*/
#define SUN8I_V3S_PLL_AUDIO_REG 0x008
@@ -53,6 +50,11 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
BIT(28), /* lock */
0);
+static SUNXI_CCU_M(pll_audio_clk, "pll-audio",
+ "pll-audio-base", 0x008,
+ 16, 4, /* P from audio pll */
+ CLK_SET_RATE_PARENT);
+
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
"osc24M", 0x0010,
8, 7, /* N */
@@ -377,6 +379,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_clk, "mipi-csi", mipi_csi_parents,
static struct ccu_common *sun8i_v3s_ccu_clks[] = {
&pll_cpu_clk.common,
&pll_audio_base_clk.common,
+ &pll_audio_clk.common,
&pll_video_clk.common,
&pll_ve_clk.common,
&pll_ddr0_clk.common,
@@ -453,6 +456,7 @@ static const struct clk_hw *clk_parent_pll_audio[] = {
static struct ccu_common *sun8i_v3_ccu_clks[] = {
&pll_cpu_clk.common,
&pll_audio_base_clk.common,
+ &pll_audio_clk.common,
&pll_video_clk.common,
&pll_ve_clk.common,
&pll_ddr0_clk.common,
@@ -524,10 +528,6 @@ static struct ccu_common *sun8i_v3_ccu_clks[] = {
&mipi_csi_clk.common,
};
-/* We hardcode the divider to 4 for now */
-static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
- clk_parent_pll_audio,
- 4, 1, CLK_SET_RATE_PARENT);
static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
clk_parent_pll_audio,
2, 1, CLK_SET_RATE_PARENT);
@@ -545,7 +545,7 @@ static struct clk_hw_onecell_data sun8i_v3s_hw_clks = {
.hws = {
[CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
[CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
- [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
+ [CLK_PLL_AUDIO] = &pll_audio_clk.common.hw,
[CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
[CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
[CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
@@ -625,7 +625,7 @@ static struct clk_hw_onecell_data sun8i_v3_hw_clks = {
.hws = {
[CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
[CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
- [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
+ [CLK_PLL_AUDIO] = &pll_audio_clk.common.hw,
[CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
[CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
[CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
--
2.30.0
于 2021年2月18日 GMT+08:00 下午3:58:35, Maxime Ripard <[email protected]> 写到:
>Hi,
>
>On Fri, Feb 12, 2021 at 02:57:25PM +0100, Tobias Schramm wrote:
>> Previously the variable rate audio pll output was fixed to a divider
>of
>> four. This is unfortunately incompatible with generating commonly
>used
>> I2S core clock rates like 24.576MHz from the 24MHz parent clock.
>> This commit adds support for arbitrary audio pll output dividers to
>fix
>> that.
>>
>> Signed-off-by: Tobias Schramm <[email protected]>
>
>It's not really clear to me how that would help.
We have introducee SDM-based accurate audio PLL on several
other SoCs. Some people is quite sensitive about audio-related things.
>
>The closest frequency we can provide for 24.576MHz would be 24580645
>Hz,
>with N = 127, M = 31 and P = 4, so it would work with what we have
>already?
>
>Maxime
Hi,
On Fri, Feb 12, 2021 at 02:57:25PM +0100, Tobias Schramm wrote:
> Previously the variable rate audio pll output was fixed to a divider of
> four. This is unfortunately incompatible with generating commonly used
> I2S core clock rates like 24.576MHz from the 24MHz parent clock.
> This commit adds support for arbitrary audio pll output dividers to fix
> that.
>
> Signed-off-by: Tobias Schramm <[email protected]>
It's not really clear to me how that would help.
The closest frequency we can provide for 24.576MHz would be 24580645 Hz,
with N = 127, M = 31 and P = 4, so it would work with what we have
already?
Maxime
On Thu, Feb 18, 2021 at 4:06 PM Icenowy Zheng <[email protected]> wrote:
>
>
>
> 于 2021年2月18日 GMT+08:00 下午3:58:35, Maxime Ripard <[email protected]> 写到:
> >Hi,
> >
> >On Fri, Feb 12, 2021 at 02:57:25PM +0100, Tobias Schramm wrote:
> >> Previously the variable rate audio pll output was fixed to a divider
> >of
> >> four. This is unfortunately incompatible with generating commonly
> >used
> >> I2S core clock rates like 24.576MHz from the 24MHz parent clock.
> >> This commit adds support for arbitrary audio pll output dividers to
> >fix
> >> that.
> >>
> >> Signed-off-by: Tobias Schramm <[email protected]>
> >
> >It's not really clear to me how that would help.
>
> We have introducee SDM-based accurate audio PLL on several
> other SoCs. Some people is quite sensitive about audio-related things.
Right. What you really want is the SDM-based fractional clock support.
Just look at the other drivers.
> >
> >The closest frequency we can provide for 24.576MHz would be 24580645
> >Hz,
> >with N = 127, M = 31 and P = 4, so it would work with what we have
> >already?
Correct. And that is still slightly off. It's even worse for the 44.1khz
family.
ChenYu
> >Maxime
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Hi Maxime,
>
> It's not really clear to me how that would help.
>
> The closest frequency we can provide for 24.576MHz would be 24580645 Hz,
> with N = 127, M = 31 and P = 4, so it would work with what we have
> already?
>
As far as I'm aware the multiplier N ranges from 0 to 128 (offset of 1
from 0 to 127). Thus 24MHz * 128 / 25 / 5 = 24.576MHz. Since this
requires the postdiv to be set to 5 it is not supported yet.
Cheers,
Tobias
> Hi Maxime,
>>
>> It's not really clear to me how that would help.
>>
>> The closest frequency we can provide for 24.576MHz would be 24580645 Hz,
>> with N = 127, M = 31 and P = 4, so it would work with what we have
>> already?
>>
>
> As far as I'm aware the multiplier N ranges from 0 to 128 (offset of 1
That should have of course been "from 1 to 128".
> from 0 to 127). Thus 24MHz * 128 / 25 / 5 = 24.576MHz. Since this
> requires the postdiv to be set to 5 it is not supported yet.
>
> Cheers,
> Tobias
Hi Icenowy,
> We have introducee SDM-based accurate audio PLL on several
> other SoCs. Some people is quite sensitive about audio-related things.
>
While it is possible to support 24MHz * 128 / 25 / 5 = 24.576MHz without
delta sigma modulation, matching 22.5792MHz is indeed not possible. I
read you'd prefer me to use SDM like the other SoCs though? Shall I send
a v2 utilizing SDM?
Cheers,
Tobias
于 2021年2月18日 GMT+08:00 下午5:18:39, Tobias Schramm <[email protected]> 写到:
>Hi Icenowy,
>
> > We have introducee SDM-based accurate audio PLL on several
>> other SoCs. Some people is quite sensitive about audio-related
>things.
> >
>While it is possible to support 24MHz * 128 / 25 / 5 = 24.576MHz
>without
>delta sigma modulation, matching 22.5792MHz is indeed not possible. I
>read you'd prefer me to use SDM like the other SoCs though? Shall I
>send
>a v2 utilizing SDM?
Yes, I think so.
>
>Cheers,
>Tobias
On Thu, Feb 18, 2021 at 05:21:16PM +0800, Icenowy Zheng wrote:
>
>
> 于 2021年2月18日 GMT+08:00 下午5:18:39, Tobias Schramm <[email protected]> 写到:
> >Hi Icenowy,
> >
> > > We have introducee SDM-based accurate audio PLL on several
> >> other SoCs. Some people is quite sensitive about audio-related
> >things.
> > >
> >While it is possible to support 24MHz * 128 / 25 / 5 = 24.576MHz
> >without
> >delta sigma modulation, matching 22.5792MHz is indeed not possible. I
> >read you'd prefer me to use SDM like the other SoCs though? Shall I
> >send
> >a v2 utilizing SDM?
>
> Yes, I think so.
Yes I'd rather have consistency about how we deal with this across all SoCs
Maxime