- Added NanoPi R5C support
- Enable rk809 support for NanoPi R5 series
- Minor fixes for NanoPi R5S gmac
Tianling Shen (5):
arm64: dts: rockchip: create common dtsi for NanoPi R5 series
dt-bindings: Add doc for FriendlyARM NanoPi R5C
arm64: dts: rockchip: Add FriendlyElec NanoPi R5C
arm64: dts: rockchip: fix gmac support for NanoPi R5S
arm64: dts: rockchip: enable rk809 audio codec on the NanoPi R5 series
.../devicetree/bindings/arm/rockchip.yaml | 6 +-
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../boot/dts/rockchip/rk3568-nanopi-r5c.dts | 112 ++++
.../boot/dts/rockchip/rk3568-nanopi-r5s.dts | 582 +----------------
.../boot/dts/rockchip/rk3568-nanopi-r5s.dtsi | 611 ++++++++++++++++++
5 files changed, 731 insertions(+), 581 deletions(-)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
--
2.17.1
Add devicetree binding documentation for the FriendlyARM NanoPi R5C.
Signed-off-by: Tianling Shen <[email protected]>
---
Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index 5474cb4a13d1..d9105e609c27 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -201,9 +201,11 @@ properties:
- friendlyarm,nanopi-r4s-enterprise
- const: rockchip,rk3399
- - description: FriendlyElec NanoPi R5S board
+ - description: FriendlyElec NanoPi R5 series board
items:
- - const: friendlyarm,nanopi-r5s
+ - enum:
+ - friendlyarm,nanopi-r5c
+ - friendlyarm,nanopi-r5s
- const: rockchip,rk3568
- description: GeekBuying GeekBox
--
2.17.1
Create commit dtsi for the FriendlyElec NanoPi R5 series.
Signed-off-by: Tianling Shen <[email protected]>
---
.../boot/dts/rockchip/rk3568-nanopi-r5s.dts | 575 +----------------
.../boot/dts/rockchip/rk3568-nanopi-r5s.dtsi | 596 ++++++++++++++++++
2 files changed, 597 insertions(+), 574 deletions(-)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
index 25edc82eaa3f..e9adf5e66529 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
@@ -7,12 +7,7 @@
*/
/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/rockchip.h>
-#include <dt-bindings/soc/rockchip,vop2.h>
-#include "rk3568.dtsi"
+#include "rk3568-nanopi-r5s.dtsi"
/ {
model = "FriendlyElec NanoPi R5S";
@@ -20,23 +15,6 @@
aliases {
ethernet0 = &gmac0;
- mmc0 = &sdmmc0;
- mmc1 = &sdhci;
- };
-
- chosen: chosen {
- stdout-path = "serial2:1500000n8";
- };
-
- hdmi-con {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
};
gpio-leds {
@@ -71,130 +49,6 @@
gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
};
};
-
- vdd_usbc: vdd-usbc-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vdd_usbc";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- vcc3v3_sys: vcc3v3-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- vin-supply = <&vdd_usbc>;
- };
-
- vcc5v0_sys: vcc5v0-sys-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vdd_usbc>;
- };
-
- vcc3v3_pcie: vcc3v3-pcie-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3_pcie";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- enable-active-high;
- gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
- startup-delay-us = <200000>;
- vin-supply = <&vcc5v0_sys>;
- };
-
- vcc5v0_usb: vcc5v0-usb-regulator {
- compatible = "regulator-fixed";
- regulator-name = "vcc5v0_usb";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vdd_usbc>;
- };
-
- vcc5v0_usb_host: vcc5v0-usb-host-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_usb_host_en>;
- regulator-name = "vcc5v0_usb_host";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_usb>;
- };
-
- vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&vcc5v0_usb_otg_en>;
- regulator-name = "vcc5v0_usb_otg";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc5v0_usb>;
- };
-
- pcie30_avdd0v9: pcie30-avdd0v9-regulator {
- compatible = "regulator-fixed";
- regulator-name = "pcie30_avdd0v9";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- vin-supply = <&vcc3v3_sys>;
- };
-
- pcie30_avdd1v8: pcie30-avdd1v8-regulator {
- compatible = "regulator-fixed";
- regulator-name = "pcie30_avdd1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc3v3_sys>;
- };
-};
-
-&combphy0 {
- status = "okay";
-};
-
-&combphy1 {
- status = "okay";
-};
-
-&combphy2 {
- status = "okay";
-};
-
-&cpu0 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu1 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu2 {
- cpu-supply = <&vdd_cpu>;
-};
-
-&cpu3 {
- cpu-supply = <&vdd_cpu>;
};
&gmac0 {
@@ -219,292 +73,6 @@
status = "okay";
};
-&gpu {
- mali-supply = <&vdd_gpu>;
- status = "okay";
-};
-
-&hdmi {
- avdd-0v9-supply = <&vdda0v9_image>;
- avdd-1v8-supply = <&vcca1v8_image>;
- status = "okay";
-};
-
-&hdmi_in {
- hdmi_in_vp0: endpoint {
- remote-endpoint = <&vp0_out_hdmi>;
- };
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&hdmi_sound {
- status = "okay";
-};
-
-&i2c0 {
- status = "okay";
-
- vdd_cpu: regulator@1c {
- compatible = "tcs,tcs4525";
- reg = <0x1c>;
- fcs,suspend-voltage-selector = <1>;
- regulator-name = "vdd_cpu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1150000>;
- regulator-ramp-delay = <2300>;
- vin-supply = <&vcc5v0_sys>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- rk809: pmic@20 {
- compatible = "rockchip,rk809";
- reg = <0x20>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_int>;
- rockchip,system-power-controller;
- vcc1-supply = <&vcc3v3_sys>;
- vcc2-supply = <&vcc3v3_sys>;
- vcc3-supply = <&vcc3v3_sys>;
- vcc4-supply = <&vcc3v3_sys>;
- vcc5-supply = <&vcc3v3_sys>;
- vcc6-supply = <&vcc3v3_sys>;
- vcc7-supply = <&vcc3v3_sys>;
- vcc8-supply = <&vcc3v3_sys>;
- vcc9-supply = <&vcc3v3_sys>;
- wakeup-source;
-
- regulators {
- vdd_logic: DCDC_REG1 {
- regulator-name = "vdd_logic";
- regulator-always-on;
- regulator-boot-on;
- regulator-init-microvolt = <900000>;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdd_gpu: DCDC_REG2 {
- regulator-name = "vdd_gpu";
- regulator-always-on;
- regulator-init-microvolt = <900000>;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_ddr: DCDC_REG3 {
- regulator-name = "vcc_ddr";
- regulator-always-on;
- regulator-boot-on;
- regulator-initial-mode = <0x2>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- };
- };
-
- vdd_npu: DCDC_REG4 {
- regulator-name = "vdd_npu";
- regulator-init-microvolt = <900000>;
- regulator-initial-mode = <0x2>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1350000>;
- regulator-ramp-delay = <6001>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_1v8: DCDC_REG5 {
- regulator-name = "vcc_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda0v9_image: LDO_REG1 {
- regulator-name = "vdda0v9_image";
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <950000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda_0v9: LDO_REG2 {
- regulator-name = "vdda_0v9";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vdda0v9_pmu: LDO_REG3 {
- regulator-name = "vdda0v9_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <900000>;
- };
- };
-
- vccio_acodec: LDO_REG4 {
- regulator-name = "vccio_acodec";
- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vccio_sd: LDO_REG5 {
- regulator-name = "vccio_sd";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_pmu: LDO_REG6 {
- regulator-name = "vcc3v3_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
- };
- };
-
- vcca_1v8: LDO_REG7 {
- regulator-name = "vcca_1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcca1v8_pmu: LDO_REG8 {
- regulator-name = "vcca1v8_pmu";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <1800000>;
- };
- };
-
- vcca1v8_image: LDO_REG9 {
- regulator-name = "vcca1v8_image";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc_3v3: SWITCH_REG1 {
- regulator-name = "vcc_3v3";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
-
- vcc3v3_sd: SWITCH_REG2 {
- regulator-name = "vcc3v3_sd";
- regulator-always-on;
- regulator-boot-on;
-
- regulator-state-mem {
- regulator-off-in-suspend;
- };
- };
- };
-
- };
-};
-
-&i2c5 {
- status = "okay";
-
- hym8563: rtc@51 {
- compatible = "haoyu,hym8563";
- reg = <0x51>;
- interrupt-parent = <&gpio0>;
- interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
- #clock-cells = <0>;
- clock-output-names = "rtcic_32kout";
- pinctrl-names = "default";
- pinctrl-0 = <&hym8563_int>;
- wakeup-source;
- };
-};
-
-&i2s0_8ch {
- status = "okay";
-};
-
-&i2s1_8ch {
- rockchip,trcm-sync-tx-only;
- status = "okay";
-};
-
&mdio0 {
rgmii_phy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
@@ -568,146 +136,5 @@
rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
-
- hym8563 {
- hym8563_int: hym8563-int {
- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- pmic {
- pmic_int: pmic-int {
- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
- usb {
- vcc5v0_usb_host_en: vcc5v0-usb-host-en {
- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-};
-
-&pmu_io_domains {
- pmuio1-supply = <&vcc3v3_pmu>;
- pmuio2-supply = <&vcc3v3_pmu>;
- vccio1-supply = <&vccio_acodec>;
- vccio3-supply = <&vccio_sd>;
- vccio4-supply = <&vcc_1v8>;
- vccio5-supply = <&vcc_3v3>;
- vccio6-supply = <&vcc_1v8>;
- vccio7-supply = <&vcc_3v3>;
- status = "okay";
-};
-
-&saradc {
- vref-supply = <&vcca_1v8>;
- status = "okay";
-};
-
-&sdhci {
- bus-width = <8>;
- max-frequency = <200000000>;
- non-removable;
- pinctrl-names = "default";
- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
- status = "okay";
-};
-
-&sdmmc0 {
- max-frequency = <150000000>;
- no-sdio;
- no-mmc;
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- disable-wp;
- vmmc-supply = <&vcc3v3_sd>;
- vqmmc-supply = <&vccio_sd>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
- status = "okay";
-};
-
-&tsadc {
- rockchip,hw-tshut-mode = <1>;
- rockchip,hw-tshut-polarity = <0>;
- status = "okay";
};
-&uart2 {
- status = "okay";
-};
-
-&usb_host0_ehci {
- status = "okay";
-};
-
-&usb_host0_ohci {
- status = "okay";
-};
-
-&usb_host0_xhci {
- extcon = <&usb2phy0>;
- dr_mode = "host";
- status = "okay";
-};
-
-&usb_host1_ehci {
- status = "okay";
-};
-
-&usb_host1_ohci {
- status = "okay";
-};
-
-&usb_host1_xhci {
- status = "okay";
-};
-
-&usb2phy0 {
- status = "okay";
-};
-
-&usb2phy0_host {
- phy-supply = <&vcc5v0_usb_host>;
- status = "okay";
-};
-
-&usb2phy0_otg {
- status = "okay";
-};
-
-&usb2phy1 {
- status = "okay";
-};
-
-&usb2phy1_host {
- phy-supply = <&vcc5v0_usb_otg>;
- status = "okay";
-};
-
-&usb2phy1_otg {
- status = "okay";
-};
-
-&vop {
- assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
- assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
- status = "okay";
-};
-
-&vop_mmu {
- status = "okay";
-};
-
-&vp0 {
- vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
- reg = <ROCKCHIP_VOP2_EP_HDMI0>;
- remote-endpoint = <&hdmi_in_vp0>;
- };
-};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
new file mode 100644
index 000000000000..dd9a7907a1c5
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
@@ -0,0 +1,596 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyelec.com)
+ *
+ * Copyright (c) 2023 Tianling Shen <[email protected]>
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+ aliases {
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ hdmi-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ vdd_usbc: vdd-usbc-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_usbc";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vdd_usbc>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vdd_usbc>;
+ };
+
+ vcc3v3_pcie: vcc3v3-pcie-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <200000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb: vcc5v0-usb-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vdd_usbc>;
+ };
+
+ vcc5v0_usb_host: vcc5v0-usb-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_host_en>;
+ regulator-name = "vcc5v0_usb_host";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_otg_en>;
+ regulator-name = "vcc5v0_usb_otg";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_usb>;
+ };
+
+ pcie30_avdd0v9: pcie30-avdd0v9-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ pcie30_avdd1v8: pcie30-avdd1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+};
+
+&combphy0 {
+ status = "okay";
+};
+
+&combphy1 {
+ status = "okay";
+};
+
+&combphy2 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ avdd-0v9-supply = <&vdda0v9_image>;
+ avdd-1v8-supply = <&vcca1v8_image>;
+ status = "okay";
+};
+
+&hdmi_in {
+ hdmi_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi>;
+ };
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>;
+ rockchip,system-power-controller;
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ wakeup-source;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <950000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+
+ };
+};
+
+&i2c5 {
+ status = "okay";
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <0>;
+ clock-output-names = "rtcic_32kout";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hym8563_int>;
+ wakeup-source;
+ };
+};
+
+&i2s0_8ch {
+ status = "okay";
+};
+
+&i2s1_8ch {
+ rockchip,trcm-sync-tx-only;
+ status = "okay";
+};
+
+&pcie30phy {
+ data-lanes = <1 2>;
+ status = "okay";
+};
+
+&pinctrl {
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic-int {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb {
+ vcc5v0_usb_host_en: vcc5v0-usb-host-en {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_1v8>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_1v8>;
+ vccio7-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ max-frequency = <150000000>;
+ no-sdio;
+ no-mmc;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ extcon = <&usb2phy0>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ status = "okay";
+};
+
+&usb2phy1 {
+ status = "okay";
+};
+
+&usb2phy1_host {
+ phy-supply = <&vcc5v0_usb_otg>;
+ status = "okay";
+};
+
+&usb2phy1_otg {
+ status = "okay";
+};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi_in_vp0>;
+ };
+};
--
2.17.1
FriendlyElec NanoPi R5C is an open-sourced mini IoT gateway device.
Specification:
- Rockchip RK3568
- 1/4GB LPDDR4X RAM
- 8/32GB eMMC
- SD card slot
- M.2 Connector
- 2x USB 3.0 Port
- 2x 2500 Base-T (PCIe, r8125)
- HDMI 2.0
- MIPI DSI/CSI
- USB Type C 5V
Signed-off-by: Tianling Shen <[email protected]>
---
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../boot/dts/rockchip/rk3568-nanopi-r5c.dts | 112 ++++++++++++++++++
2 files changed, 113 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index ade66d846a20..a315a8117b0f 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -84,6 +84,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lubancat-1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat-2.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
new file mode 100644
index 000000000000..26b391910464
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyelec.com)
+ *
+ * Copyright (c) 2023 Tianling Shen <[email protected]>
+ */
+
+/dts-v1/;
+#include "rk3568-nanopi-r5s.dtsi"
+
+/ {
+ model = "FriendlyElec NanoPi R5C";
+ compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568";
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&reset_button_pin>;
+
+ button-reset {
+ debounce-interval = <50>;
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>;
+
+ led-lan {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
+ };
+
+ power_led: led-power {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_POWER;
+ linux,default-trigger = "heartbeat";
+ gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-wan {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WAN;
+ gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-wlan {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN;
+ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&pcie2x1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie20_reset_pin>;
+ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&pcie3x1 {
+ num-lanes = <1>;
+ reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ status = "okay";
+};
+
+&pcie3x2 {
+ num-lanes = <1>;
+ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ status = "okay";
+};
+
+&pinctrl {
+ gpio-leds {
+ lan_led_pin: lan-led-pin {
+ rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ power_led_pin: power-led-pin {
+ rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wan_led_pin: wan-led-pin {
+ rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wlan_led_pin: wlan-led-pin {
+ rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie {
+ pcie20_reset_pin: pcie20-reset-pin {
+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ rockchip-key {
+ reset_button_pin: reset-button-pin {
+ rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
--
2.17.1
- Changed phy-mode to rgmii.
- Fixed pull type in pinctrl for gmac0.
- Removed duplicate properties in mdio node.
These properties are defined in the gmac0 node already.
Signed-off-by: Tianling Shen <[email protected]>
---
arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
index e9adf5e66529..2a1118f15c29 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
@@ -57,7 +57,7 @@
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
phy-handle = <&rgmii_phy0>;
- phy-mode = "rgmii-id";
+ phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
@@ -79,9 +79,6 @@
reg = <1>;
pinctrl-0 = <ð_phy0_reset_pin>;
pinctrl-names = "default";
- reset-assert-us = <10000>;
- reset-deassert-us = <50000>;
- reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
};
};
@@ -115,7 +112,7 @@
&pinctrl {
gmac0 {
eth_phy0_reset_pin: eth-phy0-reset-pin {
- rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
--
2.17.1
Enable the Rockchip RK809 audio codec on the NanoPi R5 series.
Signed-off-by: Tianling Shen <[email protected]>
---
.../boot/dts/rockchip/rk3568-nanopi-r5s.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
index dd9a7907a1c5..8e1a118ae2e3 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
@@ -35,6 +35,21 @@
};
};
+ rk809-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,name = "Analog RK809";
+ simple-audio-card,mclk-fs = <256>;
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_8ch>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&rk809>;
+ };
+ };
+
vdd_usbc: vdd-usbc-regulator {
compatible = "regulator-fixed";
regulator-name = "vdd_usbc";
--
2.17.1
On Wed, Mar 15, 2023 at 9:03 AM Tianling Shen <[email protected]> wrote:
Hi Tianling,
> + rk809-sound {
There is no audio jack on my R5S, see [1] and I don't see it on R5C
either, see [2]. I don't see audio output on the pin header either.
How is it supposed to work?
> + compatible = "simple-audio-card";
> + simple-audio-card,format = "i2s";
> + simple-audio-card,name = "Analog RK809";
> + simple-audio-card,mclk-fs = <256>;
> +
> + simple-audio-card,cpu {
> + sound-dai = <&i2s1_8ch>;
> + };
> +
> + simple-audio-card,codec {
> + sound-dai = <&rk809>;
It looks like rk809 doesn't have #sound-dai-cells property and it
results in a warning:
arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi:48.27-50.5:
Warning (sound_dai_property): /rk809-sound/simple-audio-card,codec:
Missing property '#sound-dai-cells' in node /i2c@fdd40000/pmic@20 or
bad phandle (referred from sound-dai[0])
Regards,
Vasily
[1] https://wiki.friendlyelec.com/wiki/index.php/NanoPi_R5S
[2] https://wiki.friendlyelec.com/wiki/index.php/NanoPi_R5C
On Wed, Mar 15, 2023 at 9:02 AM Tianling Shen <[email protected]> wrote:
>
> - Changed phy-mode to rgmii.
>
> - Fixed pull type in pinctrl for gmac0.
>
> - Removed duplicate properties in mdio node.
> These properties are defined in the gmac0 node already.
>
> Signed-off-by: Tianling Shen <[email protected]>
> ---
> arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 7 ++-----
> 1 file changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
> index e9adf5e66529..2a1118f15c29 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
> @@ -57,7 +57,7 @@
> assigned-clock-rates = <0>, <125000000>;
> clock_in_out = "output";
> phy-handle = <&rgmii_phy0>;
> - phy-mode = "rgmii-id";
> + phy-mode = "rgmii";
> pinctrl-names = "default";
> pinctrl-0 = <&gmac0_miim
> &gmac0_tx_bus2
> @@ -79,9 +79,6 @@
> reg = <1>;
> pinctrl-0 = <ð_phy0_reset_pin>;
> pinctrl-names = "default";
> - reset-assert-us = <10000>;
> - reset-deassert-us = <50000>;
> - reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
Hmm, I don't see RK_PC4 being used anywhere else. gmac0 has RK_PC5 as
snsp,reset-gpio. So it essentially drops reset for the PHY. Is it
expected?
> };
> };
>
> @@ -115,7 +112,7 @@
> &pinctrl {
> gmac0 {
> eth_phy0_reset_pin: eth-phy0-reset-pin {
> - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
> + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
> };
> };
>
> --
> 2.17.1
>
Hi Vasily,
On Thu, Mar 16, 2023 at 8:16 AM Vasily Khoruzhick <[email protected]> wrote:
>
> On Wed, Mar 15, 2023 at 9:02 AM Tianling Shen <[email protected]> wrote:
> >
> > - Changed phy-mode to rgmii.
> >
> > - Fixed pull type in pinctrl for gmac0.
> >
> > - Removed duplicate properties in mdio node.
> > These properties are defined in the gmac0 node already.
> >
> > Signed-off-by: Tianling Shen <[email protected]>
> > ---
> > arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 7 ++-----
> > 1 file changed, 2 insertions(+), 5 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
> > index e9adf5e66529..2a1118f15c29 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
> > +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
> > @@ -57,7 +57,7 @@
> > assigned-clock-rates = <0>, <125000000>;
> > clock_in_out = "output";
> > phy-handle = <&rgmii_phy0>;
> > - phy-mode = "rgmii-id";
> > + phy-mode = "rgmii";
> > pinctrl-names = "default";
> > pinctrl-0 = <&gmac0_miim
> > &gmac0_tx_bus2
> > @@ -79,9 +79,6 @@
> > reg = <1>;
> > pinctrl-0 = <ð_phy0_reset_pin>;
> > pinctrl-names = "default";
> > - reset-assert-us = <10000>;
> > - reset-deassert-us = <50000>;
> > - reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
>
> Hmm, I don't see RK_PC4 being used anywhere else. gmac0 has RK_PC5 as
Yes, it's a typo, it should be RK_RC5.
> snsp,reset-gpio. So it essentially drops reset for the PHY. Is it
> expected?
snsp,reset-gpio defined reset already, so we don't need to set it here again.
---
snsp,reset-gpio is the legacy binding, but I still have no idea why
reset-gpios doesn't work,
the dwmac driver will fail to lookup phy:
[ 10.398514] rk_gmac-dwmac fe2a0000.ethernet eth0: no phy found
[ 10.399061] rk_gmac-dwmac fe2a0000.ethernet eth0: __stmmac_open:
Cannot attach to PHY (error: -19)
Any ideas would be appreciated.
Thanks,
Tianling.
>
> > };
> > };
> >
> > @@ -115,7 +112,7 @@
> > &pinctrl {
> > gmac0 {
> > eth_phy0_reset_pin: eth-phy0-reset-pin {
> > - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
> > + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
> > };
> > };
> >
> > --
> > 2.17.1
> >
Hi,
On Thu, Mar 16, 2023 at 7:54 AM Vasily Khoruzhick <[email protected]> wrote:
>
> On Wed, Mar 15, 2023 at 9:03 AM Tianling Shen <[email protected]> wrote:
>
> Hi Tianling,
>
> > + rk809-sound {
>
> There is no audio jack on my R5S, see [1] and I don't see it on R5C
> either, see [2]. I don't see audio output on the pin header either.
> How is it supposed to work?
I was confused by the vendor dts. I found them enabled rk809 audio
codec [1],but also disabled
the I2S1 TDM audio controller. I'm not sure what they want to do.
But from my side I agree this should not be added. And the i2s1_8ch
node in current dts
should be removed as well.
Thanks,
Tianling.
1. https://github.com/friendlyarm/kernel-rockchip/blob/2b22fccccb0c6ff18a6c952fe81e13ba4c9ba6a1/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-common.dtsi#L125-L138
2. https://github.com/friendlyarm/kernel-rockchip/blob/2b22fccccb0c6ff18a6c952fe81e13ba4c9ba6a1/arch/arm64/boot/dts/rockchip/rk3568-nanopi5-common.dtsi#L592-L600
>
> > + compatible = "simple-audio-card";
> > + simple-audio-card,format = "i2s";
> > + simple-audio-card,name = "Analog RK809";
> > + simple-audio-card,mclk-fs = <256>;
> > +
> > + simple-audio-card,cpu {
> > + sound-dai = <&i2s1_8ch>;
> > + };
> > +
> > + simple-audio-card,codec {
> > + sound-dai = <&rk809>;
>
> It looks like rk809 doesn't have #sound-dai-cells property and it
> results in a warning:
>
> arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi:48.27-50.5:
> Warning (sound_dai_property): /rk809-sound/simple-audio-card,codec:
> Missing property '#sound-dai-cells' in node /i2c@fdd40000/pmic@20 or
> bad phandle (referred from sound-dai[0])
Yeah, I did miss some properties here. There are some minor differences between
vendor bindings and upstream ones.
>
> Regards,
> Vasily
>
> [1] https://wiki.friendlyelec.com/wiki/index.php/NanoPi_R5S
> [2] https://wiki.friendlyelec.com/wiki/index.php/NanoPi_R5C
On 15/03/2023 17:02, Tianling Shen wrote:
> Add devicetree binding documentation for the FriendlyARM NanoPi R5C.
>
> Signed-off-by: Tianling Shen <[email protected]>
> ---
> Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
Hi Tianling,
On 2023-03-16 06:34, Tianling Shen wrote:
> Hi Vasily,
>
> On Thu, Mar 16, 2023 at 8:16 AM Vasily Khoruzhick <[email protected]> wrote:
>>
>> On Wed, Mar 15, 2023 at 9:02 AM Tianling Shen <[email protected]> wrote:
>>>
>>> - Changed phy-mode to rgmii.
>>>
>>> - Fixed pull type in pinctrl for gmac0.
>>>
>>> - Removed duplicate properties in mdio node.
>>> These properties are defined in the gmac0 node already.
>>>
>>> Signed-off-by: Tianling Shen <[email protected]>
>>> ---
>>> arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 7 ++-----
>>> 1 file changed, 2 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
>>> index e9adf5e66529..2a1118f15c29 100644
>>> --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
>>> +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
>>> @@ -57,7 +57,7 @@
>>> assigned-clock-rates = <0>, <125000000>;
>>> clock_in_out = "output";
>>> phy-handle = <&rgmii_phy0>;
>>> - phy-mode = "rgmii-id";
>>> + phy-mode = "rgmii";
>>> pinctrl-names = "default";
>>> pinctrl-0 = <&gmac0_miim
>>> &gmac0_tx_bus2
>>> @@ -79,9 +79,6 @@
>>> reg = <1>;
>>> pinctrl-0 = <ð_phy0_reset_pin>;
>>> pinctrl-names = "default";
>>> - reset-assert-us = <10000>;
>>> - reset-deassert-us = <50000>;
>>> - reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
>>
>> Hmm, I don't see RK_PC4 being used anywhere else. gmac0 has RK_PC5 as
>
> Yes, it's a typo, it should be RK_RC5.
>
>> snsp,reset-gpio. So it essentially drops reset for the PHY. Is it
>> expected?
>
> snsp,reset-gpio defined reset already, so we don't need to set it here again.
>
> ---
>
> snsp,reset-gpio is the legacy binding, but I still have no idea why
> reset-gpios doesn't work,
> the dwmac driver will fail to lookup phy:
>
> [ 10.398514] rk_gmac-dwmac fe2a0000.ethernet eth0: no phy found
> [ 10.399061] rk_gmac-dwmac fe2a0000.ethernet eth0: __stmmac_open:
> Cannot attach to PHY (error: -19)
>
> Any ideas would be appreciated.
Generic ethernet phy driver is not resetting the phy in the same way
that snsp,reset-gpio does, please see top two commits at [1].
I have been meaning to send that out as an RFC but I got stuck in a
u-boot rabbit hole, and I also do not know what the correct way to fix
this would be, so I played with both device tree and code changes.
Will prioritize this and send out a RFC later today.
[1] https://github.com/Kwiboo/linux-rockchip/commits/rk3568-eth-phy-reset
Regards,
Jonas
>
> Thanks,
> Tianling.
>
>>
>>> };
>>> };
>>>
>>> @@ -115,7 +112,7 @@
>>> &pinctrl {
>>> gmac0 {
>>> eth_phy0_reset_pin: eth-phy0-reset-pin {
>>> - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
>>> + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
>>> };
>>> };
>>>
>>> --
>>> 2.17.1
>>>
Hi Jonas,
On Thu, Mar 16, 2023 at 3:37 PM Jonas Karlman <[email protected]> wrote:
>
> Hi Tianling,
> On 2023-03-16 06:34, Tianling Shen wrote:
> > Hi Vasily,
> >
> > On Thu, Mar 16, 2023 at 8:16 AM Vasily Khoruzhick <[email protected]> wrote:
> >>
> >> On Wed, Mar 15, 2023 at 9:02 AM Tianling Shen <[email protected]> wrote:
> >>>
> >>> - Changed phy-mode to rgmii.
> >>>
> >>> - Fixed pull type in pinctrl for gmac0.
> >>>
> >>> - Removed duplicate properties in mdio node.
> >>> These properties are defined in the gmac0 node already.
> >>>
> >>> Signed-off-by: Tianling Shen <[email protected]>
> >>> ---
> >>> arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 7 ++-----
> >>> 1 file changed, 2 insertions(+), 5 deletions(-)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
> >>> index e9adf5e66529..2a1118f15c29 100644
> >>> --- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
> >>> +++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
> >>> @@ -57,7 +57,7 @@
> >>> assigned-clock-rates = <0>, <125000000>;
> >>> clock_in_out = "output";
> >>> phy-handle = <&rgmii_phy0>;
> >>> - phy-mode = "rgmii-id";
> >>> + phy-mode = "rgmii";
> >>> pinctrl-names = "default";
> >>> pinctrl-0 = <&gmac0_miim
> >>> &gmac0_tx_bus2
> >>> @@ -79,9 +79,6 @@
> >>> reg = <1>;
> >>> pinctrl-0 = <ð_phy0_reset_pin>;
> >>> pinctrl-names = "default";
> >>> - reset-assert-us = <10000>;
> >>> - reset-deassert-us = <50000>;
> >>> - reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
> >>
> >> Hmm, I don't see RK_PC4 being used anywhere else. gmac0 has RK_PC5 as
> >
> > Yes, it's a typo, it should be RK_RC5.
> >
> >> snsp,reset-gpio. So it essentially drops reset for the PHY. Is it
> >> expected?
> >
> > snsp,reset-gpio defined reset already, so we don't need to set it here again.
> >
> > ---
> >
> > snsp,reset-gpio is the legacy binding, but I still have no idea why
> > reset-gpios doesn't work,
> > the dwmac driver will fail to lookup phy:
> >
> > [ 10.398514] rk_gmac-dwmac fe2a0000.ethernet eth0: no phy found
> > [ 10.399061] rk_gmac-dwmac fe2a0000.ethernet eth0: __stmmac_open:
> > Cannot attach to PHY (error: -19)
> >
> > Any ideas would be appreciated.
>
> Generic ethernet phy driver is not resetting the phy in the same way
> that snsp,reset-gpio does, please see top two commits at [1].
>
> I have been meaning to send that out as an RFC but I got stuck in a
> u-boot rabbit hole, and I also do not know what the correct way to fix
> this would be, so I played with both device tree and code changes.
> Will prioritize this and send out a RFC later today.
>
> [1] https://github.com/Kwiboo/linux-rockchip/commits/rk3568-eth-phy-reset
Thanks for the hint! I will test your patches tonight.
Thanks,
Tianling.
>
> Regards,
> Jonas
>
> >
> > Thanks,
> > Tianling.
> >
> >>
> >>> };
> >>> };
> >>>
> >>> @@ -115,7 +112,7 @@
> >>> &pinctrl {
> >>> gmac0 {
> >>> eth_phy0_reset_pin: eth-phy0-reset-pin {
> >>> - rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
> >>> + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
> >>> };
> >>> };
> >>>
> >>> --
> >>> 2.17.1
> >>>
>
Hi,
On Thu, Mar 16, 2023 at 4:46 PM Tianling Shen <[email protected]> wrote:
>
> Hi Jonas,
>
> On Thu, Mar 16, 2023 at 3:37 PM Jonas Karlman <[email protected]> wrote:
> >
[...]
> >
> > Generic ethernet phy driver is not resetting the phy in the same way
> > that snsp,reset-gpio does, please see top two commits at [1].
> >
> > I have been meaning to send that out as an RFC but I got stuck in a
> > u-boot rabbit hole, and I also do not know what the correct way to fix
> > this would be, so I played with both device tree and code changes.
> > Will prioritize this and send out a RFC later today.
> >
> > [1] https://github.com/Kwiboo/linux-rockchip/commits/rk3568-eth-phy-reset
>
> Thanks for the hint! I will test your patches tonight.
I'm currently playing your patches at
https://github.com/1715173329/imoutowrt/commits/master-rockchip-mdio
I applied commit 8597fcfa0c5c792dabb44a2db7b283c56c99ec6a to NanoPi
R5S, it worked perfectly.
However, with commit c338ed260bfd87277c41aa0290f1f2aad8d629b1 + moving
reset properties into the phy node,
the driver still failed to lookup phy. I'm not sure if I missed /
misunderstood anything.
Thanks,
Tianling.
[...]