This series are based on 5.11-rc1 and SoC MT8183,
and provide 15 patch to support mediatek SOC MT8192
Changes since v2:
- fix review comment in v2
- add pm runtime for gamma and color
- move ddp path select patch to mmsys series
- remove some useless patch
Yongqiang Niu (15):
dt-bindings: mediatek: add description for postmask
dt-bindings: mediatek: add description for mt8192 display
arm64: dts: mt8192: add display node
drm/mediatek: add component OVL_2L2
drm/mediatek: add component POSTMASK
drm/mediatek: add component RDMA4
drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase
drm/mediatek: check if fb is null
drm/mediatek: Add pm runtime support for gamma
drm/mediatek: Add pm runtime support for color
drm/mediatek: fix aal size config
drm/mediatek: separate ccorr module
drm/mediatek: add matrix bits private data for ccorr
drm/mediatek: add DDP support for MT8192
drm/mediatek: add support for mediatek SOC MT8192
.../bindings/display/mediatek/mediatek,disp.txt | 3 +-
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 134 +++++++++++
drivers/gpu/drm/mediatek/Makefile | 4 +-
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 245 +++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_disp_color.c | 5 +
drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 5 +
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 34 ++-
drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 161 ++++++++++++++
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 35 +++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 98 +--------
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 52 ++++-
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +
14 files changed, 687 insertions(+), 98 deletions(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_postmask.c
--
1.8.1.1.dirty
add description for postmask
postmask is used control round corner for display frame
Signed-off-by: Yongqiang Niu <[email protected]>
---
Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
index c562cda..9d9ab65 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
@@ -37,6 +37,7 @@ Required properties (all function blocks):
"mediatek,<chip>-disp-aal" - adaptive ambient light controller
"mediatek,<chip>-disp-gamma" - gamma correction
"mediatek,<chip>-disp-merge" - merge streams from two RDMA sources
+ "mediatek,<chip>-disp-postmask" - control round corner for display frame
"mediatek,<chip>-disp-split" - split stream to two encoders
"mediatek,<chip>-disp-ufoe" - data compression engine
"mediatek,<chip>-dsi" - DSI controller, see mediatek,dsi.txt
--
1.8.1.1.dirty
enable OVL_LAYER_SMI_ID_EN for multi-layer usecase
Signed-off-by: Yongqiang Niu <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index b47c238..4934bee 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -23,6 +23,7 @@
#define DISP_REG_OVL_RST 0x0014
#define DISP_REG_OVL_ROI_SIZE 0x0020
#define DISP_REG_OVL_DATAPATH_CON 0x0024
+#define OVL_LAYER_SMI_ID_EN BIT(0)
#define OVL_BGCLR_SEL_IN BIT(2)
#define DISP_REG_OVL_ROI_BGCLR 0x0028
#define DISP_REG_OVL_SRC_CON 0x002c
@@ -61,6 +62,7 @@ struct mtk_disp_ovl_data {
unsigned int gmc_bits;
unsigned int layer_nr;
bool fmt_rgb565_is_0;
+ bool smi_id_en;
};
/**
@@ -116,7 +118,17 @@ static void mtk_ovl_disable_vblank(struct mtk_ddp_comp *comp)
static void mtk_ovl_start(struct mtk_ddp_comp *comp)
{
+ struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
+
writel_relaxed(0x1, comp->regs + DISP_REG_OVL_EN);
+
+ if(ovl->data->smi_id_en) {
+ unsigned int reg;
+
+ reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
+ reg = reg | OVL_LAYER_SMI_ID_EN;
+ writel_relaxed(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
+ }
}
static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
--
1.8.1.1.dirty
add description for mt8192 display
Signed-off-by: Yongqiang Niu <[email protected]>
Reviewed-by: Chun-Kuang Hu <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
index 9d9ab65..b47e1a0 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
@@ -44,7 +44,7 @@ Required properties (all function blocks):
"mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
"mediatek,<chip>-disp-mutex" - display mutex
"mediatek,<chip>-disp-od" - overdrive
- the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173 and mt8183.
+ the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183 and mt8192.
- reg: Physical base address and length of the function block register space
- interrupts: The interrupt signal from the function block (required, except for
merge and split function blocks).
--
1.8.1.1.dirty
add display node
Signed-off-by: Yongqiang Niu <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 134 +++++++++++++++++++++++++++++++
1 file changed, 134 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index e12e024..dcf9fdf 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -15,6 +15,11 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ ovl2-2l2 = &ovl_2l2;
+ rdma4 = &rdma4;
+ };
+
clk26m: oscillator0 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -508,5 +513,134 @@
#size-cells = <0>;
status = "disabled";
};
+
+ mmsys: syscon@14000000 {
+ compatible = "mediatek,mt8192-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ //mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
+ // <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mutex: mutex@14001000 {
+ compatible = "mediatek,mt8192-disp-mutex";
+ reg = <0 0x14001000 0 0x1000>;
+ interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
+ //clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
+ //mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
+ // <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
+ };
+
+ ovl0: ovl@14005000 {
+ compatible = "mediatek,mt8192-disp-ovl";
+ reg = <0 0x14005000 0 0x1000>;
+ interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
+ //clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ //iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+ };
+
+ ovl_2l0: ovl@14006000 {
+ compatible = "mediatek,mt8192-disp-ovl-2l";
+ reg = <0 0x14006000 0 0x1000>;
+ interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ //clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+ //iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+ };
+
+ rdma0: rdma@14007000 {
+ compatible = "mediatek,mt8192-disp-rdma";
+ reg = <0 0x14007000 0 0x1000>;
+ interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
+ //clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ //iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
+ //mediatek,larb = <&larb0>;
+ //mediatek,rdma-fifo-size = <5120>;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
+ };
+
+ color0: color@14009000 {
+ compatible = "mediatek,mt8192-disp-color",
+ "mediatek,mt8173-disp-color";
+ reg = <0 0x14009000 0 0x1000>;
+ interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ //clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
+ };
+
+ ccorr0: ccorr@1400a000 {
+ compatible = "mediatek,mt8192-disp-ccorr";
+ reg = <0 0x1400a000 0 0x1000>;
+ interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ //clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
+ };
+
+ aal0: aal@1400b000 {
+ compatible = "mediatek,mt8192-disp-aal";
+ reg = <0 0x1400b000 0 0x1000>;
+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ //clocks = <&mmsys CLK_MM_DISP_AAL0>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
+ };
+
+ gamma0: gamma@1400c000 {
+ compatible = "mediatek,mt8183-disp-gamma",
+ "mediatek,mt8192-disp-gamma";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ //clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
+ };
+
+ postmask0: postmask@1400d000 {
+ compatible = "mediatek,mt8192-disp-postmask";
+ reg = <0 0x1400d000 0 0x1000>;
+ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ //clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
+ };
+
+ dither0: dither@1400e000 {
+ compatible = "mediatek,mt8192-disp-dither",
+ "mediatek,mt8183-disp-dither";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ //clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
+ };
+
+ ovl_2l2: ovl@14014000 {
+ compatible = "mediatek,mt8192-disp-ovl-2l";
+ reg = <0 0x14014000 0 0x1000>;
+ interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ //clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
+ //iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
+ // <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
+ };
+
+ rdma4: rdma@14015000 {
+ compatible = "mediatek,mt8192-disp-rdma";
+ reg = <0 0x14015000 0 0x1000>;
+ interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
+ //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+ //clocks = <&mmsys CLK_MM_DISP_RDMA4>;
+ //iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
+ //mediatek,rdma-fifo-size = <2048>;
+ //mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
+ };
};
};
--
1.8.1.1.dirty
gamma power domain need controled in the device.
Signed-off-by: Yongqiang Niu <[email protected]>
Signed-off-by: Yidi Lin <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
index 3c1ea07..da93079 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
@@ -10,6 +10,7 @@
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk_drm_crtc.h"
@@ -156,6 +157,8 @@ static int mtk_disp_gamma_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, priv);
+ pm_runtime_enable(dev);
+
ret = component_add(dev, &mtk_disp_gamma_component_ops);
if (ret)
dev_err(dev, "Failed to add component: %d\n", ret);
@@ -165,6 +168,8 @@ static int mtk_disp_gamma_probe(struct platform_device *pdev)
static int mtk_disp_gamma_remove(struct platform_device *pdev)
{
+ pm_runtime_disable(&pdev->dev);
+
component_del(&pdev->dev, &mtk_disp_gamma_component_ops);
return 0;
--
1.8.1.1.dirty
It's possible that state->base.fb is null. Add a check before access its
format.
Fixes: b6b1bb980ec4 ( drm/mediatek: Turn off Alpha bit when plane format has no alpha)
Signed-off-by: Yongqiang Niu <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 4934bee..8e7f494 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -279,7 +279,7 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
}
con = ovl_fmt_convert(ovl, fmt);
- if (state->base.fb->format->has_alpha)
+ if (state->base.fb && state->base.fb->format->has_alpha)
con |= OVL_CON_AEN | OVL_CON_ALPHA;
if (pending->rotation & DRM_MODE_REFLECT_Y) {
--
1.8.1.1.dirty
color power domain need controled in the device.
Signed-off-by: Yongqiang Niu <[email protected]>
Signed-off-by: Yidi Lin <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_disp_color.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c b/drivers/gpu/drm/mediatek/mtk_disp_color.c
index 6048cbc..14b9dd3 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_color.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c
@@ -9,6 +9,7 @@
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk_drm_crtc.h"
@@ -132,6 +133,8 @@ static int mtk_disp_color_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, priv);
+ pm_runtime_enable(dev);
+
ret = component_add(dev, &mtk_disp_color_component_ops);
if (ret)
dev_err(dev, "Failed to add component: %d\n", ret);
@@ -141,6 +144,8 @@ static int mtk_disp_color_probe(struct platform_device *pdev)
static int mtk_disp_color_remove(struct platform_device *pdev)
{
+ pm_runtime_disable(&pdev->dev);
+
component_del(&pdev->dev, &mtk_disp_color_component_ops);
return 0;
--
1.8.1.1.dirty
the orginal setting is not correct, fix it follow hardware data sheet.
if keep this error setting, mt8173/mt8183 display ok
but mt8192 display abnormal.
Fixes: 0664d1392c26 (drm/mediatek: Add AAL engine basic function)
Signed-off-by: Yongqiang Niu <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index fc01fea..6081800 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -174,7 +174,7 @@ static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
{
- mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_AAL_SIZE);
+ mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_AAL_SIZE);
}
static void mtk_aal_start(struct mtk_ddp_comp *comp)
--
1.8.1.1.dirty
add support for mediatek SOC MT8192
Signed-off-by: Yongqiang Niu <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 6 ++++
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 20 +++++++++++++
drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 1 +
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 42 ++++++++++++++++++++++++++++
5 files changed, 75 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
index 755e75b..da3fd98 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
@@ -221,9 +221,15 @@ static int mtk_disp_ccorr_remove(struct platform_device *pdev)
.matrix_bits = CCORR_MATRIX_BITS,
};
+static const struct mtk_disp_ccorr_data mt8192_ccorr_driver_data = {
+ .matrix_bits = 13,
+};
+
static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = {
{ .compatible = "mediatek,mt8183-disp-ccorr",
.data = &mt8183_ccorr_driver_data},
+ { .compatible = "mediatek,mt8192-disp-ccorr",
+ .data = &mt8192_ccorr_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 8e7f494..4e6679e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -457,6 +457,22 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev)
.fmt_rgb565_is_0 = true,
};
+static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = {
+ .addr = DISP_REG_OVL_ADDR_MT8173,
+ .gmc_bits = 10,
+ .layer_nr = 4,
+ .fmt_rgb565_is_0 = true,
+ .smi_id_en = true,
+};
+
+static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = {
+ .addr = DISP_REG_OVL_ADDR_MT8173,
+ .gmc_bits = 10,
+ .layer_nr = 2,
+ .fmt_rgb565_is_0 = true,
+ .smi_id_en = true,
+};
+
static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-ovl",
.data = &mt2701_ovl_driver_data},
@@ -466,6 +482,10 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev)
.data = &mt8183_ovl_driver_data},
{ .compatible = "mediatek,mt8183-disp-ovl-2l",
.data = &mt8183_ovl_2l_driver_data},
+ { .compatible = "mediatek,mt8192-disp-ovl",
+ .data = &mt8192_ovl_driver_data},
+ { .compatible = "mediatek,mt8192-disp-ovl-2l",
+ .data = &mt8192_ovl_2l_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
index 736224c..3b38157 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
@@ -145,6 +145,7 @@ static int mtk_disp_postmask_remove(struct platform_device *pdev)
}
static const struct of_device_id mtk_disp_postmask_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8192-disp-postmask"},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_postmask_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index e914e3a..b160ebe 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -364,6 +364,10 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev)
.fifo_size = 5 * SZ_1K,
};
+static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = {
+ .fifo_size = 5 * SZ_1K,
+};
+
static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-rdma",
.data = &mt2701_rdma_driver_data},
@@ -371,6 +375,8 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev)
.data = &mt8173_rdma_driver_data},
{ .compatible = "mediatek,mt8183-disp-rdma",
.data = &mt8183_rdma_driver_data},
+ { .compatible = "mediatek,mt8192-disp-rdma",
+ .data = &mt8192_rdma_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 79e86f7..24ce37c 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -149,6 +149,25 @@
DDP_COMPONENT_DPI0,
};
+static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = {
+ DDP_COMPONENT_OVL0,
+ DDP_COMPONENT_OVL_2L0,
+ DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_COLOR0,
+ DDP_COMPONENT_CCORR,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_POSTMASK0,
+ DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DSI0,
+};
+
+static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = {
+ DDP_COMPONENT_OVL_2L2,
+ DDP_COMPONENT_RDMA4,
+ DDP_COMPONENT_DPI0,
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -188,6 +207,13 @@
.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
};
+static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
+ .main_path = mt8192_mtk_ddp_main,
+ .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
+ .ext_path = mt8192_mtk_ddp_ext,
+ .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
+};
+
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
@@ -406,22 +432,32 @@ static void mtk_drm_unbind(struct device *dev)
.data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt8183-disp-ovl-2l",
.data = (void *)MTK_DISP_OVL_2L },
+ { .compatible = "mediatek,mt8192-disp-ovl",
+ .data = (void *)MTK_DISP_OVL },
+ { .compatible = "mediatek,mt8192-disp-ovl-2l",
+ .data = (void *)MTK_DISP_OVL_2L },
{ .compatible = "mediatek,mt2701-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8173-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8183-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
+ { .compatible = "mediatek,mt8192-disp-rdma",
+ .data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8173-disp-wdma",
.data = (void *)MTK_DISP_WDMA },
{ .compatible = "mediatek,mt8183-disp-ccorr",
.data = (void *)MTK_DISP_CCORR },
+ { .compatible = "mediatek,mt8192-disp-ccorr",
+ .data = (void *)MTK_DISP_CCORR },
{ .compatible = "mediatek,mt2701-disp-color",
.data = (void *)MTK_DISP_COLOR },
{ .compatible = "mediatek,mt8173-disp-color",
.data = (void *)MTK_DISP_COLOR },
{ .compatible = "mediatek,mt8173-disp-aal",
.data = (void *)MTK_DISP_AAL},
+ { .compatible = "mediatek,mt8192-disp-aal",
+ .data = (void *)MTK_DISP_AAL},
{ .compatible = "mediatek,mt8173-disp-gamma",
.data = (void *)MTK_DISP_GAMMA, },
{ .compatible = "mediatek,mt8183-disp-gamma",
@@ -450,12 +486,16 @@ static void mtk_drm_unbind(struct device *dev)
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8183-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
+ { .compatible = "mediatek,mt8192-disp-mutex",
+ .data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt2701-disp-pwm",
.data = (void *)MTK_DISP_BLS },
{ .compatible = "mediatek,mt8173-disp-pwm",
.data = (void *)MTK_DISP_PWM },
{ .compatible = "mediatek,mt8173-disp-od",
.data = (void *)MTK_DISP_OD },
+ { .compatible = "mediatek,mt8192-disp-postmask",
+ .data = (void *)MTK_DISP_POSTMASK },
{ }
};
@@ -470,6 +510,8 @@ static void mtk_drm_unbind(struct device *dev)
.data = &mt8173_mmsys_driver_data},
{ .compatible = "mediatek,mt8183-mmsys",
.data = &mt8183_mmsys_driver_data},
+ { .compatible = "mediatek,mt8192-mmsys",
+ .data = &mt8192_mmsys_driver_data},
{ }
};
--
1.8.1.1.dirty
ccorr ctm matrix bits will be different in mt8192
Signed-off-by: Yongqiang Niu <[email protected]>
---
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 222 ++++++++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 92 +-----------
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
5 files changed, 231 insertions(+), 95 deletions(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index ce5ad59..a02f534 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
-mediatek-drm-y := mtk_disp_color.o \
+mediatek-drm-y := mtk_disp_ccorr.o \
+ mtk_disp_color.o \
mtk_disp_gamma.o \
mtk_disp_ovl.o \
mtk_disp_postmask.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
new file mode 100644
index 0000000..63b3ef6
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
@@ -0,0 +1,222 @@
+/*
+ * SPDX-License-Identifier:
+ *
+ * Copyright (c) 2020 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+
+#define DISP_CCORR_EN 0x0000
+#define CCORR_EN BIT(0)
+#define DISP_CCORR_CFG 0x0020
+#define CCORR_RELAY_MODE BIT(0)
+#define CCORR_ENGINE_EN BIT(1)
+#define CCORR_GAMMA_OFF BIT(2)
+#define CCORR_WGAMUT_SRC_CLIP BIT(3)
+#define DISP_CCORR_SIZE 0x0030
+#define DISP_CCORR_COEF_0 0x0080
+#define DISP_CCORR_COEF_1 0x0084
+#define DISP_CCORR_COEF_2 0x0088
+#define DISP_CCORR_COEF_3 0x008C
+#define DISP_CCORR_COEF_4 0x0090
+
+struct mtk_disp_ccorr_data {
+ u32 reserved;
+};
+
+/**
+ * struct mtk_disp_ccorr - DISP_CCORR driver structure
+ * @ddp_comp - structure containing type enum and hardware resources
+ * @crtc - associated crtc to report irq events to
+ */
+struct mtk_disp_ccorr {
+ struct mtk_ddp_comp ddp_comp;
+ const struct mtk_disp_ccorr_data *data;
+};
+
+static inline struct mtk_disp_ccorr *comp_to_ccorr(struct mtk_ddp_comp *comp)
+{
+ return container_of(comp, struct mtk_disp_ccorr, ddp_comp);
+}
+
+static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_CCORR_SIZE);
+ mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
+}
+
+static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
+{
+ writel(CCORR_EN, comp->regs + DISP_CCORR_EN);
+}
+
+static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
+{
+ writel_relaxed(0x0, comp->regs + DISP_CCORR_EN);
+}
+
+/* Converts a DRM S31.32 value to the HW S1.10 format. */
+static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
+{
+ u16 r;
+
+ /* Sign bit. */
+ r = in & BIT_ULL(63) ? BIT(11) : 0;
+
+ if ((in & GENMASK_ULL(62, 33)) > 0) {
+ /* identity value 0x100000000 -> 0x400, */
+ /* if bigger this, set it to max 0x7ff. */
+ r |= GENMASK(10, 0);
+ } else {
+ /* take the 11 most important bits. */
+ r |= (in >> 22) & GENMASK(10, 0);
+ }
+
+ return r;
+}
+
+static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
+ struct drm_crtc_state *state)
+{
+ struct drm_property_blob *blob = state->ctm;
+ struct drm_color_ctm *ctm;
+ const u64 *input;
+ uint16_t coeffs[9] = { 0 };
+ int i;
+ struct cmdq_pkt *cmdq_pkt = NULL;
+
+ if (!blob)
+ return;
+
+ ctm = (struct drm_color_ctm *)blob->data;
+ input = ctm->matrix;
+
+ for (i = 0; i < ARRAY_SIZE(coeffs); i++)
+ coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
+
+ mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
+ comp, DISP_CCORR_COEF_0);
+ mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
+ comp, DISP_CCORR_COEF_1);
+ mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
+ comp, DISP_CCORR_COEF_2);
+ mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
+ comp, DISP_CCORR_COEF_3);
+ mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
+ comp, DISP_CCORR_COEF_4);
+}
+
+static const struct mtk_ddp_comp_funcs mtk_disp_ccorr_funcs = {
+ .config = mtk_ccorr_config,
+ .start = mtk_ccorr_start,
+ .stop = mtk_ccorr_stop,
+ .ctm_set = mtk_ccorr_ctm_set,
+};
+
+static int mtk_disp_ccorr_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct mtk_disp_ccorr *priv = dev_get_drvdata(dev);
+ struct drm_device *drm_dev = data;
+ int ret;
+
+ ret = mtk_ddp_comp_register(drm_dev, &priv->ddp_comp);
+ if (ret < 0) {
+ dev_err(dev, "Failed to register component %pOF: %d\n",
+ dev->of_node, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void mtk_disp_ccorr_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct mtk_disp_ccorr *priv = dev_get_drvdata(dev);
+ struct drm_device *drm_dev = data;
+
+ mtk_ddp_comp_unregister(drm_dev, &priv->ddp_comp);
+}
+
+static const struct component_ops mtk_disp_ccorr_component_ops = {
+ .bind = mtk_disp_ccorr_bind,
+ .unbind = mtk_disp_ccorr_unbind,
+};
+
+static int mtk_disp_ccorr_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_disp_ccorr *priv;
+ int comp_id;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_CCORR);
+ if (comp_id < 0) {
+ dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
+ return comp_id;
+ }
+
+ ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id,
+ &mtk_disp_ccorr_funcs);
+ if (ret) {
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "Failed to initialize component: %d\n",
+ ret);
+
+ return ret;
+ }
+
+ priv->data = of_device_get_match_data(dev);
+
+ platform_set_drvdata(pdev, priv);
+
+ pm_runtime_enable(dev);
+
+ ret = component_add(dev, &mtk_disp_ccorr_component_ops);
+ if (ret)
+ dev_err(dev, "Failed to add component: %d\n", ret);
+
+ return ret;
+}
+
+static int mtk_disp_ccorr_remove(struct platform_device *pdev)
+{
+ pm_runtime_disable(&pdev->dev);
+
+ component_del(&pdev->dev, &mtk_disp_ccorr_component_ops);
+
+ return 0;
+}
+
+static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8183-disp-ccorr"},
+ {},
+};
+MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);
+
+struct platform_driver mtk_disp_ccorr_driver = {
+ .probe = mtk_disp_ccorr_probe,
+ .remove = mtk_disp_ccorr_remove,
+ .driver = {
+ .name = "mediatek-disp-ccorr",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_disp_ccorr_driver_dt_match,
+ },
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 6081800..bb7893d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -35,20 +35,6 @@
#define DISP_AAL_EN 0x0000
#define DISP_AAL_SIZE 0x0030
-#define DISP_CCORR_EN 0x0000
-#define CCORR_EN BIT(0)
-#define DISP_CCORR_CFG 0x0020
-#define CCORR_RELAY_MODE BIT(0)
-#define CCORR_ENGINE_EN BIT(1)
-#define CCORR_GAMMA_OFF BIT(2)
-#define CCORR_WGAMUT_SRC_CLIP BIT(3)
-#define DISP_CCORR_SIZE 0x0030
-#define DISP_CCORR_COEF_0 0x0080
-#define DISP_CCORR_COEF_1 0x0084
-#define DISP_CCORR_COEF_2 0x0088
-#define DISP_CCORR_COEF_3 0x008C
-#define DISP_CCORR_COEF_4 0x0090
-
#define DISP_DITHER_EN 0x0000
#define DITHER_EN BIT(0)
#define DISP_DITHER_CFG 0x0020
@@ -187,75 +173,6 @@ static void mtk_aal_stop(struct mtk_ddp_comp *comp)
writel_relaxed(0x0, comp->regs + DISP_AAL_EN);
}
-static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
- unsigned int h, unsigned int vrefresh,
- unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
-{
- mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE);
- mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
-}
-
-static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
-{
- writel(CCORR_EN, comp->regs + DISP_CCORR_EN);
-}
-
-static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
-{
- writel_relaxed(0x0, comp->regs + DISP_CCORR_EN);
-}
-
-/* Converts a DRM S31.32 value to the HW S1.10 format. */
-static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
-{
- u16 r;
-
- /* Sign bit. */
- r = in & BIT_ULL(63) ? BIT(11) : 0;
-
- if ((in & GENMASK_ULL(62, 33)) > 0) {
- /* identity value 0x100000000 -> 0x400, */
- /* if bigger this, set it to max 0x7ff. */
- r |= GENMASK(10, 0);
- } else {
- /* take the 11 most important bits. */
- r |= (in >> 22) & GENMASK(10, 0);
- }
-
- return r;
-}
-
-static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
- struct drm_crtc_state *state)
-{
- struct drm_property_blob *blob = state->ctm;
- struct drm_color_ctm *ctm;
- const u64 *input;
- uint16_t coeffs[9] = { 0 };
- int i;
- struct cmdq_pkt *cmdq_pkt = NULL;
-
- if (!blob)
- return;
-
- ctm = (struct drm_color_ctm *)blob->data;
- input = ctm->matrix;
-
- for (i = 0; i < ARRAY_SIZE(coeffs); i++)
- coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
-
- mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
- comp, DISP_CCORR_COEF_0);
- mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
- comp, DISP_CCORR_COEF_1);
- mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
- comp, DISP_CCORR_COEF_2);
- mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
- comp, DISP_CCORR_COEF_3);
- mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
- comp, DISP_CCORR_COEF_4);
-}
-
static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -315,13 +232,6 @@ static void mtk_dither_stop(struct mtk_ddp_comp *comp)
.stop = mtk_aal_stop,
};
-static const struct mtk_ddp_comp_funcs ddp_ccorr = {
- .config = mtk_ccorr_config,
- .start = mtk_ccorr_start,
- .stop = mtk_ccorr_stop,
- .ctm_set = mtk_ccorr_ctm_set,
-};
-
static const struct mtk_ddp_comp_funcs ddp_dither = {
.config = mtk_dither_config,
.start = mtk_dither_start,
@@ -367,7 +277,7 @@ struct mtk_ddp_comp_match {
[DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
[DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
[DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
- [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
+ [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, NULL },
[DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL },
[DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL },
[DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index bc205e9..79e86f7 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -533,11 +533,12 @@ static int mtk_drm_probe(struct platform_device *pdev)
private->comp_node[comp_id] = of_node_get(node);
/*
- * Currently only the COLOR, GAMMA, OVL, POSTMASK, RDMA, DSI, and DPI blocks have
- * separate component platform drivers and initialize their own
+ * Currently only the CCORR, COLOR, GAMMA, OVL, POSTMASK, RDMA, DSI, and DPI
+ * blocks have separate component platform drivers and initialize their own
* DDP component structure. The others are initialized here.
*/
- if (comp_type == MTK_DISP_COLOR ||
+ if (comp_type == MTK_DISP_CCORR ||
+ comp_type == MTK_DISP_COLOR ||
comp_type == MTK_DISP_GAMMA ||
comp_type == MTK_DISP_OVL ||
comp_type == MTK_DISP_OVL_2L ||
@@ -652,6 +653,7 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend,
static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_ddp_driver,
+ &mtk_disp_ccorr_driver,
&mtk_disp_color_driver,
&mtk_disp_gamma_driver,
&mtk_disp_ovl_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 8a9544b..e20a0e8 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -47,6 +47,7 @@ struct mtk_drm_private {
};
extern struct platform_driver mtk_ddp_driver;
+extern struct platform_driver mtk_disp_ccorr_driver;
extern struct platform_driver mtk_disp_color_driver;
extern struct platform_driver mtk_disp_gamma_driver;
extern struct platform_driver mtk_disp_ovl_driver;
--
1.8.1.1.dirty
Add DDP support for MT8192 SoC.
Signed-off-by: Yongqiang Niu <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 35 ++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 1308046..7aa7fc3 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -40,6 +40,18 @@
#define MT8167_MUTEX_MOD_DISP_DITHER 15
#define MT8167_MUTEX_MOD_DISP_UFOE 16
+#define MT8192_MUTEX_MOD_DISP_OVL0 0
+#define MT8192_MUTEX_MOD_DISP_OVL0_2L 1
+#define MT8192_MUTEX_MOD_DISP_RDMA0 2
+#define MT8192_MUTEX_MOD_DISP_COLOR0 4
+#define MT8192_MUTEX_MOD_DISP_CCORR0 5
+#define MT8192_MUTEX_MOD_DISP_AAL0 6
+#define MT8192_MUTEX_MOD_DISP_GAMMA0 7
+#define MT8192_MUTEX_MOD_DISP_POSTMASK0 8
+#define MT8192_MUTEX_MOD_DISP_DITHER0 9
+#define MT8192_MUTEX_MOD_DISP_OVL2_2L 16
+#define MT8192_MUTEX_MOD_DISP_RDMA4 17
+
#define MT8183_MUTEX_MOD_DISP_RDMA0 0
#define MT8183_MUTEX_MOD_DISP_RDMA1 1
#define MT8183_MUTEX_MOD_DISP_OVL0 9
@@ -215,6 +227,20 @@ struct mtk_ddp {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
+static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+ [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
+ [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
+ [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
+ [DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
+ [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
+ [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
+ [DDP_COMPONENT_OVL_2L0] = MT8192_MUTEX_MOD_DISP_OVL0_2L,
+ [DDP_COMPONENT_OVL_2L2] = MT8192_MUTEX_MOD_DISP_OVL2_2L,
+ [DDP_COMPONENT_RDMA0] = MT8192_MUTEX_MOD_DISP_RDMA0,
+ [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
+};
+
static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
[DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
@@ -275,6 +301,13 @@ struct mtk_ddp {
.no_clk = true,
};
+static const struct mtk_ddp_data mt8192_ddp_driver_data = {
+ .mutex_mod = mt8192_mutex_mod,
+ .mutex_sof = mt8183_mutex_sof,
+ .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0,
+ .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0,
+};
+
struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id)
{
struct mtk_ddp *ddp = dev_get_drvdata(dev);
@@ -497,6 +530,8 @@ static int mtk_ddp_remove(struct platform_device *pdev)
.data = &mt8173_ddp_driver_data},
{ .compatible = "mediatek,mt8183-disp-mutex",
.data = &mt8183_ddp_driver_data},
+ { .compatible = "mediatek,mt8192-disp-mutex",
+ .data = &mt8192_ddp_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, ddp_driver_dt_match);
--
1.8.1.1.dirty
This patch add component POSTMASK,
Signed-off-by: Yongqiang Niu <[email protected]>
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 160 +++++++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
6 files changed, 168 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_postmask.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 17a08e2..ce5ad59 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -3,6 +3,7 @@
mediatek-drm-y := mtk_disp_color.o \
mtk_disp_gamma.o \
mtk_disp_ovl.o \
+ mtk_disp_postmask.o \
mtk_disp_rdma.o \
mtk_drm_crtc.o \
mtk_drm_ddp.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
new file mode 100644
index 0000000..736224c
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
@@ -0,0 +1,160 @@
+/*
+ * SPDX-License-Identifier:
+ *
+ * Copyright (c) 2020 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+
+#define DISP_POSTMASK_EN 0x0000
+#define POSTMASK_EN BIT(0)
+#define DISP_POSTMASK_CFG 0x0020
+#define POSTMASK_RELAY_MODE BIT(0)
+#define DISP_POSTMASK_SIZE 0x0030
+
+struct mtk_disp_postmask_data {
+ u32 reserved;
+};
+
+/**
+ * struct mtk_disp_postmask - DISP_postmask driver structure
+ * @ddp_comp - structure containing type enum and hardware resources
+ * @crtc - associated crtc to report irq events to
+ */
+struct mtk_disp_postmask {
+ struct mtk_ddp_comp ddp_comp;
+ const struct mtk_disp_postmask_data *data;
+};
+
+static inline struct mtk_disp_postmask *comp_to_postmask(struct mtk_ddp_comp *comp)
+{
+ return container_of(comp, struct mtk_disp_postmask, ddp_comp);
+}
+
+static void mtk_postmask_config(struct mtk_ddp_comp *comp, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_POSTMASK_SIZE);
+ mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, comp, DISP_POSTMASK_CFG);
+}
+
+static void mtk_postmask_start(struct mtk_ddp_comp *comp)
+{
+ writel(POSTMASK_EN, comp->regs + DISP_POSTMASK_EN);
+}
+
+static void mtk_postmask_stop(struct mtk_ddp_comp *comp)
+{
+ writel_relaxed(0x0, comp->regs + DISP_POSTMASK_EN);
+}
+
+static const struct mtk_ddp_comp_funcs mtk_disp_postmask_funcs = {
+ .config = mtk_postmask_config,
+ .start = mtk_postmask_start,
+ .stop = mtk_postmask_stop,
+};
+
+static int mtk_disp_postmask_bind(struct device *dev, struct device *master, void *data)
+{
+ struct mtk_disp_postmask *priv = dev_get_drvdata(dev);
+ struct drm_device *drm_dev = data;
+ int ret;
+
+ ret = mtk_ddp_comp_register(drm_dev, &priv->ddp_comp);
+ if (ret < 0) {
+ dev_err(dev, "Failed to register component %pOF: %d\n",
+ dev->of_node, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void mtk_disp_postmask_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct mtk_disp_postmask *priv = dev_get_drvdata(dev);
+ struct drm_device *drm_dev = data;
+
+ mtk_ddp_comp_unregister(drm_dev, &priv->ddp_comp);
+}
+
+static const struct component_ops mtk_disp_postmask_component_ops = {
+ .bind = mtk_disp_postmask_bind,
+ .unbind = mtk_disp_postmask_unbind,
+};
+
+static int mtk_disp_postmask_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_disp_postmask *priv;
+ int comp_id;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_POSTMASK);
+ if (comp_id < 0) {
+ dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
+ return comp_id;
+ }
+
+ ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id,
+ &mtk_disp_postmask_funcs);
+ if (ret) {
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "Failed to initialize component: %d\n",
+ ret);
+
+ return ret;
+ }
+
+ priv->data = of_device_get_match_data(dev);
+
+ platform_set_drvdata(pdev, priv);
+
+ pm_runtime_enable(dev);
+
+ ret = component_add(dev, &mtk_disp_postmask_component_ops);
+ if (ret)
+ dev_err(dev, "Failed to add component: %d\n", ret);
+
+ return ret;
+}
+
+static int mtk_disp_postmask_remove(struct platform_device *pdev)
+{
+ pm_runtime_disable(&pdev->dev);
+
+ component_del(&pdev->dev, &mtk_disp_postmask_component_ops);
+
+ return 0;
+}
+
+static const struct of_device_id mtk_disp_postmask_driver_dt_match[] = {
+ {},
+};
+MODULE_DEVICE_TABLE(of, mtk_disp_postmask_driver_dt_match);
+
+struct platform_driver mtk_disp_postmask_driver = {
+ .probe = mtk_disp_postmask_probe,
+ .remove = mtk_disp_postmask_remove,
+ .driver = {
+ .name = "mediatek-disp-postmask",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_disp_postmask_driver_dt_match,
+ },
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index a715127..bc6b10a 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -354,6 +354,7 @@ static void mtk_dither_stop(struct mtk_ddp_comp *comp)
[MTK_DISP_MUTEX] = "mutex",
[MTK_DISP_OD] = "od",
[MTK_DISP_BLS] = "bls",
+ [MTK_DISP_POSTMASK] = "postmask",
};
struct mtk_ddp_comp_match {
@@ -384,6 +385,7 @@ struct mtk_ddp_comp_match {
[DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, NULL },
[DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, NULL },
[DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, NULL },
+ [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, NULL },
[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
[DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
[DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 178fae9..0b23b5c 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -29,6 +29,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_UFOE,
MTK_DSI,
MTK_DPI,
+ MTK_DISP_POSTMASK,
MTK_DISP_PWM,
MTK_DISP_MUTEX,
MTK_DISP_OD,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index b6e963e..bc205e9 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -533,7 +533,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
private->comp_node[comp_id] = of_node_get(node);
/*
- * Currently only the COLOR, GAMMA, OVL, RDMA, DSI, and DPI blocks have
+ * Currently only the COLOR, GAMMA, OVL, POSTMASK, RDMA, DSI, and DPI blocks have
* separate component platform drivers and initialize their own
* DDP component structure. The others are initialized here.
*/
@@ -541,6 +541,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type == MTK_DISP_GAMMA ||
comp_type == MTK_DISP_OVL ||
comp_type == MTK_DISP_OVL_2L ||
+ comp_type == MTK_DISP_POSTMASK ||
comp_type == MTK_DISP_RDMA ||
comp_type == MTK_DSI ||
comp_type == MTK_DPI) {
@@ -654,6 +655,7 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend,
&mtk_disp_color_driver,
&mtk_disp_gamma_driver,
&mtk_disp_ovl_driver,
+ &mtk_disp_postmask_driver,
&mtk_disp_rdma_driver,
&mtk_dpi_driver,
&mtk_drm_platform_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index bbd362b..8a9544b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -50,6 +50,7 @@ struct mtk_drm_private {
extern struct platform_driver mtk_disp_color_driver;
extern struct platform_driver mtk_disp_gamma_driver;
extern struct platform_driver mtk_disp_ovl_driver;
+extern struct platform_driver mtk_disp_postmask_driver;
extern struct platform_driver mtk_disp_rdma_driver;
extern struct platform_driver mtk_dpi_driver;
extern struct platform_driver mtk_dsi_driver;
--
1.8.1.1.dirty
matrix bits of mt8183 is 12
matrix bits of mt8192 is 13
Signed-off-by: Yongqiang Niu <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 23 ++++++++++++++++++++---
1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
index 63b3ef6..755e75b 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
@@ -30,8 +30,10 @@
#define DISP_CCORR_COEF_3 0x008C
#define DISP_CCORR_COEF_4 0x0090
+#define CCORR_MATRIX_BITS 12
+
struct mtk_disp_ccorr_data {
- u32 reserved;
+ u32 matrix_bits;
};
/**
@@ -96,6 +98,8 @@ static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
uint16_t coeffs[9] = { 0 };
int i;
struct cmdq_pkt *cmdq_pkt = NULL;
+ struct mtk_disp_ccorr *ccorr = comp_to_ccorr(comp);
+ u32 matrix_bits;
if (!blob)
return;
@@ -103,8 +107,16 @@ static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
ctm = (struct drm_color_ctm *)blob->data;
input = ctm->matrix;
- for (i = 0; i < ARRAY_SIZE(coeffs); i++)
+ if (ccorr->data)
+ matrix_bits = ccorr->data->matrix_bits;
+ else
+ matrix_bits = CCORR_MATRIX_BITS;
+
+ for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
+ if (matrix_bits > CCORR_MATRIX_BITS)
+ coeffs[i] <<= (matrix_bits - CCORR_MATRIX_BITS);
+ }
mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
comp, DISP_CCORR_COEF_0);
@@ -205,8 +217,13 @@ static int mtk_disp_ccorr_remove(struct platform_device *pdev)
return 0;
}
+static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = {
+ .matrix_bits = CCORR_MATRIX_BITS,
+};
+
static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = {
- { .compatible = "mediatek,mt8183-disp-ccorr"},
+ { .compatible = "mediatek,mt8183-disp-ccorr",
+ .data = &mt8183_ccorr_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);
--
1.8.1.1.dirty
This patch add component RDMA4
Signed-off-by: Yongqiang Niu <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index bc6b10a..fc01fea 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -392,6 +392,7 @@ struct mtk_ddp_comp_match {
[DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL },
[DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL },
[DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL },
+ [DDP_COMPONENT_RDMA4] = { MTK_DISP_RDMA, 4, NULL },
[DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
[DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
[DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
--
1.8.1.1.dirty
This patch add component OVL_2L2
Signed-off-by: Yongqiang Niu <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 81ed076..a715127 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -383,6 +383,7 @@ struct mtk_ddp_comp_match {
[DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL },
[DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, NULL },
[DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, NULL },
+ [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, NULL },
[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
[DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
[DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
--
1.8.1.1.dirty
Yongqiang Niu <[email protected]> 於 2021年1月11日 週一 下午3:44寫道：
>
> add description for postmask
> postmask is used control round corner for display frame
After changing to 'used to control',
Reviewed-by: Chun-Kuang Hu <[email protected]>
>
> Signed-off-by: Yongqiang Niu <[email protected]>
> ---
> Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> index c562cda..9d9ab65 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> @@ -37,6 +37,7 @@ Required properties (all function blocks):
> "mediatek,<chip>-disp-aal" - adaptive ambient light controller
> "mediatek,<chip>-disp-gamma" - gamma correction
> "mediatek,<chip>-disp-merge" - merge streams from two RDMA sources
> + "mediatek,<chip>-disp-postmask" - control round corner for display frame
> "mediatek,<chip>-disp-split" - split stream to two encoders
> "mediatek,<chip>-disp-ufoe" - data compression engine
> "mediatek,<chip>-dsi" - DSI controller, see mediatek,dsi.txt
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
Hi, Yongqiang:
Yongqiang Niu <[email protected]> 於 2021年1月11日 週一 下午3:44寫道：
>
> This patch add component OVL_2L2
Reviewed-by: Chun-Kuang Hu <[email protected]>
>
> Signed-off-by: Yongqiang Niu <[email protected]>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 81ed076..a715127 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -383,6 +383,7 @@ struct mtk_ddp_comp_match {
> [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL },
> [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, NULL },
> [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, NULL },
> + [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, NULL },
> [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
> [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
> [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
Hi, Yongqiang:
Yongqiang Niu <[email protected]> 於 2021年1月11日 週一 下午3:48寫道：
>
> add display node
>
> Signed-off-by: Yongqiang Niu <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 134 +++++++++++++++++++++++++++++++
> 1 file changed, 134 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index e12e024..dcf9fdf 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -15,6 +15,11 @@
> #address-cells = <2>;
> #size-cells = <2>;
>
> + aliases {
> + ovl2-2l2 = &ovl_2l2;
> + rdma4 = &rdma4;
> + };
> +
> clk26m: oscillator0 {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> @@ -508,5 +513,134 @@
> #size-cells = <0>;
> status = "disabled";
> };
> +
> + mmsys: syscon@14000000 {
> + compatible = "mediatek,mt8192-mmsys", "syscon";
> + reg = <0 0x14000000 0 0x1000>;
> + //mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
> + // <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + mutex: mutex@14001000 {
> + compatible = "mediatek,mt8192-disp-mutex";
> + reg = <0 0x14001000 0 0x1000>;
> + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> + //clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> + //mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> + // <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
> + };
> +
> + ovl0: ovl@14005000 {
> + compatible = "mediatek,mt8192-disp-ovl";
> + reg = <0 0x14005000 0 0x1000>;
> + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
> + //clocks = <&mmsys CLK_MM_DISP_OVL0>;
> + //iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>;
> + //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
I think you should not mark these property.
Regards,
Chun-Kuang.
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
> + };
> +
> + ovl_2l0: ovl@14006000 {
> + compatible = "mediatek,mt8192-disp-ovl-2l";
> + reg = <0 0x14006000 0 0x1000>;
> + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
> + //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + //clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> + //iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
> + };
> +
> + rdma0: rdma@14007000 {
> + compatible = "mediatek,mt8192-disp-rdma";
> + reg = <0 0x14007000 0 0x1000>;
> + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
> + //clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> + //iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> + //mediatek,larb = <&larb0>;
> + //mediatek,rdma-fifo-size = <5120>;
> + //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
> + };
> +
> + color0: color@14009000 {
> + compatible = "mediatek,mt8192-disp-color",
> + "mediatek,mt8173-disp-color";
> + reg = <0 0x14009000 0 0x1000>;
> + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
> + //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + //clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
> + };
> +
> + ccorr0: ccorr@1400a000 {
> + compatible = "mediatek,mt8192-disp-ccorr";
> + reg = <0 0x1400a000 0 0x1000>;
> + interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> + //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + //clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
> + };
> +
> + aal0: aal@1400b000 {
> + compatible = "mediatek,mt8192-disp-aal";
> + reg = <0 0x1400b000 0 0x1000>;
> + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
> + //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + //clocks = <&mmsys CLK_MM_DISP_AAL0>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
> + };
> +
> + gamma0: gamma@1400c000 {
> + compatible = "mediatek,mt8183-disp-gamma",
> + "mediatek,mt8192-disp-gamma";
> + reg = <0 0x1400c000 0 0x1000>;
> + interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
> + //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + //clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> + };
> +
> + postmask0: postmask@1400d000 {
> + compatible = "mediatek,mt8192-disp-postmask";
> + reg = <0 0x1400d000 0 0x1000>;
> + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
> + //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + //clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
> + };
> +
> + dither0: dither@1400e000 {
> + compatible = "mediatek,mt8192-disp-dither",
> + "mediatek,mt8183-disp-dither";
> + reg = <0 0x1400e000 0 0x1000>;
> + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
> + //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + //clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> + };
> +
> + ovl_2l2: ovl@14014000 {
> + compatible = "mediatek,mt8192-disp-ovl-2l";
> + reg = <0 0x14014000 0 0x1000>;
> + interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
> + //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + //clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
> + //iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
> + // <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
> + };
> +
> + rdma4: rdma@14015000 {
> + compatible = "mediatek,mt8192-disp-rdma";
> + reg = <0 0x14015000 0 0x1000>;
> + interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
> + //power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> + //clocks = <&mmsys CLK_MM_DISP_RDMA4>;
> + //iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
> + //mediatek,rdma-fifo-size = <2048>;
> + //mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
> + };
> };
> };
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
Hi, Yongqiang:
Yongqiang Niu <[email protected]> 於 2021年1月11日 週一 下午3:44寫道：
>
> This patch add component POSTMASK,
This patch has conflicts with the series "Decouple Mediatek DRM sub
driver" [1] which has been applied to mediatek-drm-next, so please
rebase this patch onto mediatek-drm-next.
[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=399915
Regards,
Chun-Kuang.
>
> Signed-off-by: Yongqiang Niu <[email protected]>
> ---
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 160 +++++++++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +-
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> 6 files changed, 168 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_postmask.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index 17a08e2..ce5ad59 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -3,6 +3,7 @@
> mediatek-drm-y := mtk_disp_color.o \
> mtk_disp_gamma.o \
> mtk_disp_ovl.o \
> + mtk_disp_postmask.o \
> mtk_disp_rdma.o \
> mtk_drm_crtc.o \
> mtk_drm_ddp.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
> new file mode 100644
> index 0000000..736224c
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
> @@ -0,0 +1,160 @@
> +/*
> + * SPDX-License-Identifier:
> + *
> + * Copyright (c) 2020 MediaTek Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/of_irq.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +
> +#define DISP_POSTMASK_EN 0x0000
> +#define POSTMASK_EN BIT(0)
> +#define DISP_POSTMASK_CFG 0x0020
> +#define POSTMASK_RELAY_MODE BIT(0)
> +#define DISP_POSTMASK_SIZE 0x0030
> +
> +struct mtk_disp_postmask_data {
> + u32 reserved;
> +};
> +
> +/**
> + * struct mtk_disp_postmask - DISP_postmask driver structure
> + * @ddp_comp - structure containing type enum and hardware resources
> + * @crtc - associated crtc to report irq events to
> + */
> +struct mtk_disp_postmask {
> + struct mtk_ddp_comp ddp_comp;
> + const struct mtk_disp_postmask_data *data;
> +};
> +
> +static inline struct mtk_disp_postmask *comp_to_postmask(struct mtk_ddp_comp *comp)
> +{
> + return container_of(comp, struct mtk_disp_postmask, ddp_comp);
> +}
> +
> +static void mtk_postmask_config(struct mtk_ddp_comp *comp, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_POSTMASK_SIZE);
> + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, comp, DISP_POSTMASK_CFG);
> +}
> +
> +static void mtk_postmask_start(struct mtk_ddp_comp *comp)
> +{
> + writel(POSTMASK_EN, comp->regs + DISP_POSTMASK_EN);
> +}
> +
> +static void mtk_postmask_stop(struct mtk_ddp_comp *comp)
> +{
> + writel_relaxed(0x0, comp->regs + DISP_POSTMASK_EN);
> +}
> +
> +static const struct mtk_ddp_comp_funcs mtk_disp_postmask_funcs = {
> + .config = mtk_postmask_config,
> + .start = mtk_postmask_start,
> + .stop = mtk_postmask_stop,
> +};
> +
> +static int mtk_disp_postmask_bind(struct device *dev, struct device *master, void *data)
> +{
> + struct mtk_disp_postmask *priv = dev_get_drvdata(dev);
> + struct drm_device *drm_dev = data;
> + int ret;
> +
> + ret = mtk_ddp_comp_register(drm_dev, &priv->ddp_comp);
> + if (ret < 0) {
> + dev_err(dev, "Failed to register component %pOF: %d\n",
> + dev->of_node, ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static void mtk_disp_postmask_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> + struct mtk_disp_postmask *priv = dev_get_drvdata(dev);
> + struct drm_device *drm_dev = data;
> +
> + mtk_ddp_comp_unregister(drm_dev, &priv->ddp_comp);
> +}
> +
> +static const struct component_ops mtk_disp_postmask_component_ops = {
> + .bind = mtk_disp_postmask_bind,
> + .unbind = mtk_disp_postmask_unbind,
> +};
> +
> +static int mtk_disp_postmask_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct mtk_disp_postmask *priv;
> + int comp_id;
> + int ret;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_POSTMASK);
> + if (comp_id < 0) {
> + dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
> + return comp_id;
> + }
> +
> + ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id,
> + &mtk_disp_postmask_funcs);
> + if (ret) {
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev, "Failed to initialize component: %d\n",
> + ret);
> +
> + return ret;
> + }
> +
> + priv->data = of_device_get_match_data(dev);
> +
> + platform_set_drvdata(pdev, priv);
> +
> + pm_runtime_enable(dev);
> +
> + ret = component_add(dev, &mtk_disp_postmask_component_ops);
> + if (ret)
> + dev_err(dev, "Failed to add component: %d\n", ret);
> +
> + return ret;
> +}
> +
> +static int mtk_disp_postmask_remove(struct platform_device *pdev)
> +{
> + pm_runtime_disable(&pdev->dev);
> +
> + component_del(&pdev->dev, &mtk_disp_postmask_component_ops);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id mtk_disp_postmask_driver_dt_match[] = {
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, mtk_disp_postmask_driver_dt_match);
> +
> +struct platform_driver mtk_disp_postmask_driver = {
> + .probe = mtk_disp_postmask_probe,
> + .remove = mtk_disp_postmask_remove,
> + .driver = {
> + .name = "mediatek-disp-postmask",
> + .owner = THIS_MODULE,
> + .of_match_table = mtk_disp_postmask_driver_dt_match,
> + },
> +};
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index a715127..bc6b10a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -354,6 +354,7 @@ static void mtk_dither_stop(struct mtk_ddp_comp *comp)
> [MTK_DISP_MUTEX] = "mutex",
> [MTK_DISP_OD] = "od",
> [MTK_DISP_BLS] = "bls",
> + [MTK_DISP_POSTMASK] = "postmask",
> };
>
> struct mtk_ddp_comp_match {
> @@ -384,6 +385,7 @@ struct mtk_ddp_comp_match {
> [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, NULL },
> [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, NULL },
> [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, NULL },
> + [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, NULL },
> [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
> [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
> [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 178fae9..0b23b5c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -29,6 +29,7 @@ enum mtk_ddp_comp_type {
> MTK_DISP_UFOE,
> MTK_DSI,
> MTK_DPI,
> + MTK_DISP_POSTMASK,
> MTK_DISP_PWM,
> MTK_DISP_MUTEX,
> MTK_DISP_OD,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index b6e963e..bc205e9 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -533,7 +533,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
> private->comp_node[comp_id] = of_node_get(node);
>
> /*
> - * Currently only the COLOR, GAMMA, OVL, RDMA, DSI, and DPI blocks have
> + * Currently only the COLOR, GAMMA, OVL, POSTMASK, RDMA, DSI, and DPI blocks have
> * separate component platform drivers and initialize their own
> * DDP component structure. The others are initialized here.
> */
> @@ -541,6 +541,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
> comp_type == MTK_DISP_GAMMA ||
> comp_type == MTK_DISP_OVL ||
> comp_type == MTK_DISP_OVL_2L ||
> + comp_type == MTK_DISP_POSTMASK ||
> comp_type == MTK_DISP_RDMA ||
> comp_type == MTK_DSI ||
> comp_type == MTK_DPI) {
> @@ -654,6 +655,7 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend,
> &mtk_disp_color_driver,
> &mtk_disp_gamma_driver,
> &mtk_disp_ovl_driver,
> + &mtk_disp_postmask_driver,
> &mtk_disp_rdma_driver,
> &mtk_dpi_driver,
> &mtk_drm_platform_driver,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index bbd362b..8a9544b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -50,6 +50,7 @@ struct mtk_drm_private {
> extern struct platform_driver mtk_disp_color_driver;
> extern struct platform_driver mtk_disp_gamma_driver;
> extern struct platform_driver mtk_disp_ovl_driver;
> +extern struct platform_driver mtk_disp_postmask_driver;
> extern struct platform_driver mtk_disp_rdma_driver;
> extern struct platform_driver mtk_dpi_driver;
> extern struct platform_driver mtk_dsi_driver;
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
Hi, Yongqiang:
Yongqiang Niu <[email protected]> 於 2021年1月11日 週一 下午3:44寫道：
>
> enable OVL_LAYER_SMI_ID_EN for multi-layer usecase
Could you describe more information? Without this patch, what would happen?
>
> Signed-off-by: Yongqiang Niu <[email protected]>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index b47c238..4934bee 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -23,6 +23,7 @@
> #define DISP_REG_OVL_RST 0x0014
> #define DISP_REG_OVL_ROI_SIZE 0x0020
> #define DISP_REG_OVL_DATAPATH_CON 0x0024
> +#define OVL_LAYER_SMI_ID_EN BIT(0)
> #define OVL_BGCLR_SEL_IN BIT(2)
> #define DISP_REG_OVL_ROI_BGCLR 0x0028
> #define DISP_REG_OVL_SRC_CON 0x002c
> @@ -61,6 +62,7 @@ struct mtk_disp_ovl_data {
> unsigned int gmc_bits;
> unsigned int layer_nr;
> bool fmt_rgb565_is_0;
> + bool smi_id_en;
> };
>
> /**
> @@ -116,7 +118,17 @@ static void mtk_ovl_disable_vblank(struct mtk_ddp_comp *comp)
>
> static void mtk_ovl_start(struct mtk_ddp_comp *comp)
> {
> + struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
> +
> writel_relaxed(0x1, comp->regs + DISP_REG_OVL_EN);
> +
> + if(ovl->data->smi_id_en) {
> + unsigned int reg;
> +
> + reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
> + reg = reg | OVL_LAYER_SMI_ID_EN;
> + writel_relaxed(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
I think this setting should before write 1 to DISP_REG_OVL_EN.
> + }
> }
>
> static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
Should clear DISP_REG_OVL_DATAPATH_CON when stop?
Regards,
Chun-Kuang.
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
Hi, Yongqiang:
Yongqiang Niu <[email protected]> 於 2021年1月11日 週一 下午3:48寫道：
>
> It's possible that state->base.fb is null. Add a check before access its
> format.
Applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Fixes: b6b1bb980ec4 ( drm/mediatek: Turn off Alpha bit when plane format has no alpha)
> Signed-off-by: Yongqiang Niu <[email protected]>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 4934bee..8e7f494 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -279,7 +279,7 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
> }
>
> con = ovl_fmt_convert(ovl, fmt);
> - if (state->base.fb->format->has_alpha)
> + if (state->base.fb && state->base.fb->format->has_alpha)
> con |= OVL_CON_AEN | OVL_CON_ALPHA;
>
> if (pending->rotation & DRM_MODE_REFLECT_Y) {
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
Hi, Yongqiang:
Yongqiang Niu <[email protected]> 於 2021年1月11日 週一 下午3:48寫道：
>
> add description for mt8192 display
Applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Signed-off-by: Yongqiang Niu <[email protected]>
> Reviewed-by: Chun-Kuang Hu <[email protected]>
> Acked-by: Rob Herring <[email protected]>
> ---
> Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> index 9d9ab65..b47e1a0 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> @@ -44,7 +44,7 @@ Required properties (all function blocks):
> "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
> "mediatek,<chip>-disp-mutex" - display mutex
> "mediatek,<chip>-disp-od" - overdrive
> - the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173 and mt8183.
> + the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183 and mt8192.
> - reg: Physical base address and length of the function block register space
> - interrupts: The interrupt signal from the function block (required, except for
> merge and split function blocks).
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
Hi, Yongqiang:
Yongqiang Niu <[email protected]> 於 2021年1月11日 週一 下午3:44寫道：
>
> This patch add component RDMA4
Reviewed-by: Chun-Kuang Hu <[email protected]>
>
> Signed-off-by: Yongqiang Niu <[email protected]>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index bc6b10a..fc01fea 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -392,6 +392,7 @@ struct mtk_ddp_comp_match {
> [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL },
> [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL },
> [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL },
> + [DDP_COMPONENT_RDMA4] = { MTK_DISP_RDMA, 4, NULL },
> [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
> [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
> [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
Hi, Yongqiang:
Yongqiang Niu <[email protected]> 於 2021年1月11日 週一 下午3:48寫道：
>
> gamma power domain need controled in the device.
In this series, why only gamma and color add pm runtime support? I
think all ddp component need pm runtime support. And pm runtime
support is not related to mt8192, so move these patches out of this
series.
Regards,
Chun-Kuang.
>
> Signed-off-by: Yongqiang Niu <[email protected]>
> Signed-off-by: Yidi Lin <[email protected]>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> index 3c1ea07..da93079 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> @@ -10,6 +10,7 @@
> #include <linux/of_device.h>
> #include <linux/of_irq.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> #include <linux/soc/mediatek/mtk-cmdq.h>
>
> #include "mtk_drm_crtc.h"
> @@ -156,6 +157,8 @@ static int mtk_disp_gamma_probe(struct platform_device *pdev)
>
> platform_set_drvdata(pdev, priv);
>
> + pm_runtime_enable(dev);
> +
> ret = component_add(dev, &mtk_disp_gamma_component_ops);
> if (ret)
> dev_err(dev, "Failed to add component: %d\n", ret);
> @@ -165,6 +168,8 @@ static int mtk_disp_gamma_probe(struct platform_device *pdev)
>
> static int mtk_disp_gamma_remove(struct platform_device *pdev)
> {
> + pm_runtime_disable(&pdev->dev);
> +
> component_del(&pdev->dev, &mtk_disp_gamma_component_ops);
>
> return 0;
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
Hi, Yongqiang:
Yongqiang Niu <[email protected]> 於 2021年1月11日 週一 下午3:54寫道：
>
> ccorr ctm matrix bits will be different in mt8192
This patch has conflicts with the series "Decouple Mediatek DRM sub
driver" [1] which has been applied to mediatek-drm-next, so please
rebase this patch onto mediatek-drm-next.
[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=399915
Regards,
Chun-Kuang.
>
> Signed-off-by: Yongqiang Niu <[email protected]>
> ---
> drivers/gpu/drm/mediatek/Makefile | 3 +-
> drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 222 ++++++++++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 92 +-----------
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +-
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> 5 files changed, 231 insertions(+), 95 deletions(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index ce5ad59..a02f534 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -1,6 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0
>
> -mediatek-drm-y := mtk_disp_color.o \
> +mediatek-drm-y := mtk_disp_ccorr.o \
> + mtk_disp_color.o \
> mtk_disp_gamma.o \
> mtk_disp_ovl.o \
> mtk_disp_postmask.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> new file mode 100644
> index 0000000..63b3ef6
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
> @@ -0,0 +1,222 @@
> +/*
> + * SPDX-License-Identifier:
> + *
> + * Copyright (c) 2020 MediaTek Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +
> +#define DISP_CCORR_EN 0x0000
> +#define CCORR_EN BIT(0)
> +#define DISP_CCORR_CFG 0x0020
> +#define CCORR_RELAY_MODE BIT(0)
> +#define CCORR_ENGINE_EN BIT(1)
> +#define CCORR_GAMMA_OFF BIT(2)
> +#define CCORR_WGAMUT_SRC_CLIP BIT(3)
> +#define DISP_CCORR_SIZE 0x0030
> +#define DISP_CCORR_COEF_0 0x0080
> +#define DISP_CCORR_COEF_1 0x0084
> +#define DISP_CCORR_COEF_2 0x0088
> +#define DISP_CCORR_COEF_3 0x008C
> +#define DISP_CCORR_COEF_4 0x0090
> +
> +struct mtk_disp_ccorr_data {
> + u32 reserved;
> +};
> +
> +/**
> + * struct mtk_disp_ccorr - DISP_CCORR driver structure
> + * @ddp_comp - structure containing type enum and hardware resources
> + * @crtc - associated crtc to report irq events to
> + */
> +struct mtk_disp_ccorr {
> + struct mtk_ddp_comp ddp_comp;
> + const struct mtk_disp_ccorr_data *data;
> +};
> +
> +static inline struct mtk_disp_ccorr *comp_to_ccorr(struct mtk_ddp_comp *comp)
> +{
> + return container_of(comp, struct mtk_disp_ccorr, ddp_comp);
> +}
> +
> +static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_CCORR_SIZE);
> + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
> +}
> +
> +static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
> +{
> + writel(CCORR_EN, comp->regs + DISP_CCORR_EN);
> +}
> +
> +static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
> +{
> + writel_relaxed(0x0, comp->regs + DISP_CCORR_EN);
> +}
> +
> +/* Converts a DRM S31.32 value to the HW S1.10 format. */
> +static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
> +{
> + u16 r;
> +
> + /* Sign bit. */
> + r = in & BIT_ULL(63) ? BIT(11) : 0;
> +
> + if ((in & GENMASK_ULL(62, 33)) > 0) {
> + /* identity value 0x100000000 -> 0x400, */
> + /* if bigger this, set it to max 0x7ff. */
> + r |= GENMASK(10, 0);
> + } else {
> + /* take the 11 most important bits. */
> + r |= (in >> 22) & GENMASK(10, 0);
> + }
> +
> + return r;
> +}
> +
> +static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
> + struct drm_crtc_state *state)
> +{
> + struct drm_property_blob *blob = state->ctm;
> + struct drm_color_ctm *ctm;
> + const u64 *input;
> + uint16_t coeffs[9] = { 0 };
> + int i;
> + struct cmdq_pkt *cmdq_pkt = NULL;
> +
> + if (!blob)
> + return;
> +
> + ctm = (struct drm_color_ctm *)blob->data;
> + input = ctm->matrix;
> +
> + for (i = 0; i < ARRAY_SIZE(coeffs); i++)
> + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
> +
> + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
> + comp, DISP_CCORR_COEF_0);
> + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
> + comp, DISP_CCORR_COEF_1);
> + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
> + comp, DISP_CCORR_COEF_2);
> + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
> + comp, DISP_CCORR_COEF_3);
> + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
> + comp, DISP_CCORR_COEF_4);
> +}
> +
> +static const struct mtk_ddp_comp_funcs mtk_disp_ccorr_funcs = {
> + .config = mtk_ccorr_config,
> + .start = mtk_ccorr_start,
> + .stop = mtk_ccorr_stop,
> + .ctm_set = mtk_ccorr_ctm_set,
> +};
> +
> +static int mtk_disp_ccorr_bind(struct device *dev, struct device *master,
> + void *data)
> +{
> + struct mtk_disp_ccorr *priv = dev_get_drvdata(dev);
> + struct drm_device *drm_dev = data;
> + int ret;
> +
> + ret = mtk_ddp_comp_register(drm_dev, &priv->ddp_comp);
> + if (ret < 0) {
> + dev_err(dev, "Failed to register component %pOF: %d\n",
> + dev->of_node, ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static void mtk_disp_ccorr_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> + struct mtk_disp_ccorr *priv = dev_get_drvdata(dev);
> + struct drm_device *drm_dev = data;
> +
> + mtk_ddp_comp_unregister(drm_dev, &priv->ddp_comp);
> +}
> +
> +static const struct component_ops mtk_disp_ccorr_component_ops = {
> + .bind = mtk_disp_ccorr_bind,
> + .unbind = mtk_disp_ccorr_unbind,
> +};
> +
> +static int mtk_disp_ccorr_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct mtk_disp_ccorr *priv;
> + int comp_id;
> + int ret;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_CCORR);
> + if (comp_id < 0) {
> + dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
> + return comp_id;
> + }
> +
> + ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id,
> + &mtk_disp_ccorr_funcs);
> + if (ret) {
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev, "Failed to initialize component: %d\n",
> + ret);
> +
> + return ret;
> + }
> +
> + priv->data = of_device_get_match_data(dev);
> +
> + platform_set_drvdata(pdev, priv);
> +
> + pm_runtime_enable(dev);
> +
> + ret = component_add(dev, &mtk_disp_ccorr_component_ops);
> + if (ret)
> + dev_err(dev, "Failed to add component: %d\n", ret);
> +
> + return ret;
> +}
> +
> +static int mtk_disp_ccorr_remove(struct platform_device *pdev)
> +{
> + pm_runtime_disable(&pdev->dev);
> +
> + component_del(&pdev->dev, &mtk_disp_ccorr_component_ops);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = {
> + { .compatible = "mediatek,mt8183-disp-ccorr"},
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);
> +
> +struct platform_driver mtk_disp_ccorr_driver = {
> + .probe = mtk_disp_ccorr_probe,
> + .remove = mtk_disp_ccorr_remove,
> + .driver = {
> + .name = "mediatek-disp-ccorr",
> + .owner = THIS_MODULE,
> + .of_match_table = mtk_disp_ccorr_driver_dt_match,
> + },
> +};
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 6081800..bb7893d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -35,20 +35,6 @@
> #define DISP_AAL_EN 0x0000
> #define DISP_AAL_SIZE 0x0030
>
> -#define DISP_CCORR_EN 0x0000
> -#define CCORR_EN BIT(0)
> -#define DISP_CCORR_CFG 0x0020
> -#define CCORR_RELAY_MODE BIT(0)
> -#define CCORR_ENGINE_EN BIT(1)
> -#define CCORR_GAMMA_OFF BIT(2)
> -#define CCORR_WGAMUT_SRC_CLIP BIT(3)
> -#define DISP_CCORR_SIZE 0x0030
> -#define DISP_CCORR_COEF_0 0x0080
> -#define DISP_CCORR_COEF_1 0x0084
> -#define DISP_CCORR_COEF_2 0x0088
> -#define DISP_CCORR_COEF_3 0x008C
> -#define DISP_CCORR_COEF_4 0x0090
> -
> #define DISP_DITHER_EN 0x0000
> #define DITHER_EN BIT(0)
> #define DISP_DITHER_CFG 0x0020
> @@ -187,75 +173,6 @@ static void mtk_aal_stop(struct mtk_ddp_comp *comp)
> writel_relaxed(0x0, comp->regs + DISP_AAL_EN);
> }
>
> -static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
> - unsigned int h, unsigned int vrefresh,
> - unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> -{
> - mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE);
> - mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
> -}
> -
> -static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
> -{
> - writel(CCORR_EN, comp->regs + DISP_CCORR_EN);
> -}
> -
> -static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
> -{
> - writel_relaxed(0x0, comp->regs + DISP_CCORR_EN);
> -}
> -
> -/* Converts a DRM S31.32 value to the HW S1.10 format. */
> -static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
> -{
> - u16 r;
> -
> - /* Sign bit. */
> - r = in & BIT_ULL(63) ? BIT(11) : 0;
> -
> - if ((in & GENMASK_ULL(62, 33)) > 0) {
> - /* identity value 0x100000000 -> 0x400, */
> - /* if bigger this, set it to max 0x7ff. */
> - r |= GENMASK(10, 0);
> - } else {
> - /* take the 11 most important bits. */
> - r |= (in >> 22) & GENMASK(10, 0);
> - }
> -
> - return r;
> -}
> -
> -static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
> - struct drm_crtc_state *state)
> -{
> - struct drm_property_blob *blob = state->ctm;
> - struct drm_color_ctm *ctm;
> - const u64 *input;
> - uint16_t coeffs[9] = { 0 };
> - int i;
> - struct cmdq_pkt *cmdq_pkt = NULL;
> -
> - if (!blob)
> - return;
> -
> - ctm = (struct drm_color_ctm *)blob->data;
> - input = ctm->matrix;
> -
> - for (i = 0; i < ARRAY_SIZE(coeffs); i++)
> - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
> -
> - mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
> - comp, DISP_CCORR_COEF_0);
> - mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
> - comp, DISP_CCORR_COEF_1);
> - mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
> - comp, DISP_CCORR_COEF_2);
> - mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
> - comp, DISP_CCORR_COEF_3);
> - mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
> - comp, DISP_CCORR_COEF_4);
> -}
> -
> static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> @@ -315,13 +232,6 @@ static void mtk_dither_stop(struct mtk_ddp_comp *comp)
> .stop = mtk_aal_stop,
> };
>
> -static const struct mtk_ddp_comp_funcs ddp_ccorr = {
> - .config = mtk_ccorr_config,
> - .start = mtk_ccorr_start,
> - .stop = mtk_ccorr_stop,
> - .ctm_set = mtk_ccorr_ctm_set,
> -};
> -
> static const struct mtk_ddp_comp_funcs ddp_dither = {
> .config = mtk_dither_config,
> .start = mtk_dither_start,
> @@ -367,7 +277,7 @@ struct mtk_ddp_comp_match {
> [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
> [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
> [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
> - [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
> + [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, NULL },
> [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL },
> [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL },
> [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index bc205e9..79e86f7 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -533,11 +533,12 @@ static int mtk_drm_probe(struct platform_device *pdev)
> private->comp_node[comp_id] = of_node_get(node);
>
> /*
> - * Currently only the COLOR, GAMMA, OVL, POSTMASK, RDMA, DSI, and DPI blocks have
> - * separate component platform drivers and initialize their own
> + * Currently only the CCORR, COLOR, GAMMA, OVL, POSTMASK, RDMA, DSI, and DPI
> + * blocks have separate component platform drivers and initialize their own
> * DDP component structure. The others are initialized here.
> */
> - if (comp_type == MTK_DISP_COLOR ||
> + if (comp_type == MTK_DISP_CCORR ||
> + comp_type == MTK_DISP_COLOR ||
> comp_type == MTK_DISP_GAMMA ||
> comp_type == MTK_DISP_OVL ||
> comp_type == MTK_DISP_OVL_2L ||
> @@ -652,6 +653,7 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend,
>
> static struct platform_driver * const mtk_drm_drivers[] = {
> &mtk_ddp_driver,
> + &mtk_disp_ccorr_driver,
> &mtk_disp_color_driver,
> &mtk_disp_gamma_driver,
> &mtk_disp_ovl_driver,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index 8a9544b..e20a0e8 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -47,6 +47,7 @@ struct mtk_drm_private {
> };
>
> extern struct platform_driver mtk_ddp_driver;
> +extern struct platform_driver mtk_disp_ccorr_driver;
> extern struct platform_driver mtk_disp_color_driver;
> extern struct platform_driver mtk_disp_gamma_driver;
> extern struct platform_driver mtk_disp_ovl_driver;
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
On Mon, 11 Jan 2021 15:43:37 +0800, Yongqiang Niu wrote:
> add description for postmask
> postmask is used control round corner for display frame
>
> Signed-off-by: Yongqiang Niu <[email protected]>
> ---
> Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <[email protected]>
Rob Herring <[email protected]> 於 2021年1月15日 週五 上午3:11寫道：
>
> On Mon, 11 Jan 2021 15:43:37 +0800, Yongqiang Niu wrote:
> > add description for postmask
> > postmask is used control round corner for display frame
> >
> > Signed-off-by: Yongqiang Niu <[email protected]>
> > ---
> > Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 1 +
> > 1 file changed, 1 insertion(+)
> >
>
> Acked-by: Rob Herring <[email protected]>
Applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
> _______________________________________________
> dri-devel mailing list
> [email protected]
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
Hi, Yongqiang:
Yongqiang Niu <[email protected]> 於 2021年1月11日 週一 下午3:48寫道：
>
> the orginal setting is not correct, fix it follow hardware data sheet.
> if keep this error setting, mt8173/mt8183 display ok
> but mt8192 display abnormal.
>
Applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
> Fixes: 0664d1392c26 (drm/mediatek: Add AAL engine basic function)
>
> Signed-off-by: Yongqiang Niu <[email protected]>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index fc01fea..6081800 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -174,7 +174,7 @@ static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> {
> - mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_AAL_SIZE);
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_AAL_SIZE);
> }
>
> static void mtk_aal_start(struct mtk_ddp_comp *comp)
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
On Mon, Jan 11, 2021 at 3:44 PM Yongqiang Niu
<[email protected]> wrote:
>
> This patch add component POSTMASK,
>
> Signed-off-by: Yongqiang Niu <[email protected]>
> ---
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 160 +++++++++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +-
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> 6 files changed, 168 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_postmask.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index 17a08e2..ce5ad59 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -3,6 +3,7 @@
> mediatek-drm-y := mtk_disp_color.o \
> mtk_disp_gamma.o \
> mtk_disp_ovl.o \
> + mtk_disp_postmask.o \
> mtk_disp_rdma.o \
> mtk_drm_crtc.o \
> mtk_drm_ddp.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
> new file mode 100644
> index 0000000..736224c
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
> @@ -0,0 +1,160 @@
> +/*
> + * SPDX-License-Identifier:
> + *
> + * Copyright (c) 2020 MediaTek Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/of_irq.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +
> +#define DISP_POSTMASK_EN 0x0000
> +#define POSTMASK_EN BIT(0)
> +#define DISP_POSTMASK_CFG 0x0020
> +#define POSTMASK_RELAY_MODE BIT(0)
> +#define DISP_POSTMASK_SIZE 0x0030
> +
> +struct mtk_disp_postmask_data {
> + u32 reserved;
> +};
> +
Will there be more data and config for different soc in the future? If
not, it can be put in mtk_drm_ddp_comp.c and use struct
mtk_ddp_comp_dev, like ddp_dither or ddp_aal.
> +/**
> + * struct mtk_disp_postmask - DISP_postmask driver structure
> + * @ddp_comp - structure containing type enum and hardware resources
> + * @crtc - associated crtc to report irq events to
> + */
> +struct mtk_disp_postmask {
> + struct mtk_ddp_comp ddp_comp;
> + const struct mtk_disp_postmask_data *data;
> +};
> +
> +static inline struct mtk_disp_postmask *comp_to_postmask(struct mtk_ddp_comp *comp)
> +{
> + return container_of(comp, struct mtk_disp_postmask, ddp_comp);
> +}
> +
> +static void mtk_postmask_config(struct mtk_ddp_comp *comp, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_POSTMASK_SIZE);
> + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, comp, DISP_POSTMASK_CFG);
> +}
> +
> +static void mtk_postmask_start(struct mtk_ddp_comp *comp)
> +{
> + writel(POSTMASK_EN, comp->regs + DISP_POSTMASK_EN);
> +}
> +
> +static void mtk_postmask_stop(struct mtk_ddp_comp *comp)
> +{
> + writel_relaxed(0x0, comp->regs + DISP_POSTMASK_EN);
> +}
> +
> +static const struct mtk_ddp_comp_funcs mtk_disp_postmask_funcs = {
> + .config = mtk_postmask_config,
> + .start = mtk_postmask_start,
> + .stop = mtk_postmask_stop,
> +};
> +
> +static int mtk_disp_postmask_bind(struct device *dev, struct device *master, void *data)
> +{
> + struct mtk_disp_postmask *priv = dev_get_drvdata(dev);
> + struct drm_device *drm_dev = data;
> + int ret;
> +
> + ret = mtk_ddp_comp_register(drm_dev, &priv->ddp_comp);
> + if (ret < 0) {
> + dev_err(dev, "Failed to register component %pOF: %d\n",
> + dev->of_node, ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static void mtk_disp_postmask_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> + struct mtk_disp_postmask *priv = dev_get_drvdata(dev);
> + struct drm_device *drm_dev = data;
> +
> + mtk_ddp_comp_unregister(drm_dev, &priv->ddp_comp);
> +}
> +
> +static const struct component_ops mtk_disp_postmask_component_ops = {
> + .bind = mtk_disp_postmask_bind,
> + .unbind = mtk_disp_postmask_unbind,
> +};
> +
> +static int mtk_disp_postmask_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct mtk_disp_postmask *priv;
> + int comp_id;
> + int ret;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_POSTMASK);
> + if (comp_id < 0) {
> + dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
> + return comp_id;
> + }
> +
> + ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id,
> + &mtk_disp_postmask_funcs);
> + if (ret) {
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev, "Failed to initialize component: %d\n",
> + ret);
> +
> + return ret;
> + }
> +
> + priv->data = of_device_get_match_data(dev);
> +
> + platform_set_drvdata(pdev, priv);
> +
> + pm_runtime_enable(dev);
> +
> + ret = component_add(dev, &mtk_disp_postmask_component_ops);
> + if (ret)
> + dev_err(dev, "Failed to add component: %d\n", ret);
> +
> + return ret;
> +}
> +
> +static int mtk_disp_postmask_remove(struct platform_device *pdev)
> +{
> + pm_runtime_disable(&pdev->dev);
> +
> + component_del(&pdev->dev, &mtk_disp_postmask_component_ops);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id mtk_disp_postmask_driver_dt_match[] = {
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, mtk_disp_postmask_driver_dt_match);
> +
> +struct platform_driver mtk_disp_postmask_driver = {
> + .probe = mtk_disp_postmask_probe,
> + .remove = mtk_disp_postmask_remove,
> + .driver = {
> + .name = "mediatek-disp-postmask",
> + .owner = THIS_MODULE,
> + .of_match_table = mtk_disp_postmask_driver_dt_match,
> + },
> +};
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index a715127..bc6b10a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -354,6 +354,7 @@ static void mtk_dither_stop(struct mtk_ddp_comp *comp)
> [MTK_DISP_MUTEX] = "mutex",
> [MTK_DISP_OD] = "od",
> [MTK_DISP_BLS] = "bls",
> + [MTK_DISP_POSTMASK] = "postmask",
> };
>
> struct mtk_ddp_comp_match {
> @@ -384,6 +385,7 @@ struct mtk_ddp_comp_match {
> [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, NULL },
> [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, NULL },
> [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, NULL },
> + [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, NULL },
> [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
> [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
> [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 178fae9..0b23b5c 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -29,6 +29,7 @@ enum mtk_ddp_comp_type {
> MTK_DISP_UFOE,
> MTK_DSI,
> MTK_DPI,
> + MTK_DISP_POSTMASK,
> MTK_DISP_PWM,
> MTK_DISP_MUTEX,
> MTK_DISP_OD,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index b6e963e..bc205e9 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -533,7 +533,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
> private->comp_node[comp_id] = of_node_get(node);
>
> /*
> - * Currently only the COLOR, GAMMA, OVL, RDMA, DSI, and DPI blocks have
> + * Currently only the COLOR, GAMMA, OVL, POSTMASK, RDMA, DSI, and DPI blocks have
> * separate component platform drivers and initialize their own
> * DDP component structure. The others are initialized here.
> */
> @@ -541,6 +541,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
> comp_type == MTK_DISP_GAMMA ||
> comp_type == MTK_DISP_OVL ||
> comp_type == MTK_DISP_OVL_2L ||
> + comp_type == MTK_DISP_POSTMASK ||
> comp_type == MTK_DISP_RDMA ||
> comp_type == MTK_DSI ||
> comp_type == MTK_DPI) {
> @@ -654,6 +655,7 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend,
> &mtk_disp_color_driver,
> &mtk_disp_gamma_driver,
> &mtk_disp_ovl_driver,
> + &mtk_disp_postmask_driver,
> &mtk_disp_rdma_driver,
> &mtk_dpi_driver,
> &mtk_drm_platform_driver,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index bbd362b..8a9544b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -50,6 +50,7 @@ struct mtk_drm_private {
> extern struct platform_driver mtk_disp_color_driver;
> extern struct platform_driver mtk_disp_gamma_driver;
> extern struct platform_driver mtk_disp_ovl_driver;
> +extern struct platform_driver mtk_disp_postmask_driver;
> extern struct platform_driver mtk_disp_rdma_driver;
> extern struct platform_driver mtk_dpi_driver;
> extern struct platform_driver mtk_dsi_driver;
> --
> 1.8.1.1.dirty
>
On Tue, 2021-01-12 at 07:59 +0800, Chun-Kuang Hu wrote:
> Hi, Yongqiang:
>
> Yongqiang Niu <[email protected]> 於 2021年1月11日 週一 下午3:44寫道：
> >
> > enable OVL_LAYER_SMI_ID_EN for multi-layer usecase
>
> Could you describe more information? Without this patch, what would happen?
>
without this patch, ovl will hang up when more than 1 layer enabled
> >
> > Signed-off-by: Yongqiang Niu <[email protected]>
> > ---
> > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 12 ++++++++++++
> > 1 file changed, 12 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > index b47c238..4934bee 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > @@ -23,6 +23,7 @@
> > #define DISP_REG_OVL_RST 0x0014
> > #define DISP_REG_OVL_ROI_SIZE 0x0020
> > #define DISP_REG_OVL_DATAPATH_CON 0x0024
> > +#define OVL_LAYER_SMI_ID_EN BIT(0)
> > #define OVL_BGCLR_SEL_IN BIT(2)
> > #define DISP_REG_OVL_ROI_BGCLR 0x0028
> > #define DISP_REG_OVL_SRC_CON 0x002c
> > @@ -61,6 +62,7 @@ struct mtk_disp_ovl_data {
> > unsigned int gmc_bits;
> > unsigned int layer_nr;
> > bool fmt_rgb565_is_0;
> > + bool smi_id_en;
> > };
> >
> > /**
> > @@ -116,7 +118,17 @@ static void mtk_ovl_disable_vblank(struct mtk_ddp_comp *comp)
> >
> > static void mtk_ovl_start(struct mtk_ddp_comp *comp)
> > {
> > + struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
> > +
> > writel_relaxed(0x1, comp->regs + DISP_REG_OVL_EN);
> > +
> > + if(ovl->data->smi_id_en) {
> > + unsigned int reg;
> > +
> > + reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
> > + reg = reg | OVL_LAYER_SMI_ID_EN;
> > + writel_relaxed(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
>
> I think this setting should before write 1 to DISP_REG_OVL_EN.
>
> > + }
> > }
> >
> > static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
>
> Should clear DISP_REG_OVL_DATAPATH_CON when stop?
>
> Regards,
> Chun-Kuang.
>
> > --
> > 1.8.1.1.dirty
> > _______________________________________________
> > Linux-mediatek mailing list
> > [email protected]
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek