Changes in v2:
* Rafal discovered an issue with the GIC_PPI flags being incorrect.
Since there was a dependency on that DT entry in this series, I added
a patch to correct the issue and reworked the TWD patch with the
changes.
These seemed to have been lost sometime last year. See
https://lkml.org/lkml/2016/5/11/953
I am dropping the syscon reboot from the series, as I believe that was
the sticking point, and resending the TWD and i2c patches.
Jon Mason (3):
ARM: dts: BCM5301X: Correct GIC_PPI interrupt flags
ARM: dts: bcm5301x: Add TWD WD Support to DT
ARM: dts: bcm5301x: Add I2C support to the DT
arch/arm/boot/dts/bcm5301x.dtsi | 26 ++++++++++++++++++++++----
1 file changed, 22 insertions(+), 4 deletions(-)
--
2.7.4
GIC_PPI flags were misconfigured for the timers, resulting in errors
like:
[ 0.000000] GIC: PPI11 is secure or misconfigured
Changing them to being edge triggered corrects the issue
Suggested-by: Rafał Miłecki <[email protected]>
Signed-off-by: Jon Mason <[email protected]>
Fixes: d27509f1 ("ARM: BCM5301X: add dts files for BCM4708 SoC")
---
arch/arm/boot/dts/bcm5301x.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 4fbb089..00de62d 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -66,14 +66,14 @@
timer@20200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x20200 0x100>;
- interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
clocks = <&periph_clk>;
};
local-timer@20600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x20600 0x100>;
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
clocks = <&periph_clk>;
};
--
2.7.4
From: Jon Mason <[email protected]>
Add support for the ARM TWD Watchdog to the bcm5301x device tree. The
ARM TWD timer allocated the register space for the WDT, so this patch
necessitated shrinking that. Also, the GIC masks were added for these.
Signed-off-by: Jon Mason <[email protected]>
---
arch/arm/boot/dts/bcm5301x.dtsi | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 00de62d..4e3fbce 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -70,10 +70,19 @@
clocks = <&periph_clk>;
};
- local-timer@20600 {
+ timer@20600 {
compatible = "arm,cortex-a9-twd-timer";
- reg = <0x20600 0x100>;
- interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
+ reg = <0x20600 0x20>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_EDGE_RISING)>;
+ clocks = <&periph_clk>;
+ };
+
+ watchdog@20620 {
+ compatible = "arm,cortex-a9-twd-wdt";
+ reg = <0x20620 0x20>;
+ interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_EDGE_RISING)>;
clocks = <&periph_clk>;
};
--
2.7.4
From: Jon Mason <[email protected]>
Add I2C support to the bcm5301x Device Tree. Since no driver changes
are needed to enable this hardware, only the device tree changes are
required to make this functional.
Signed-off-by: Jon Mason <[email protected]>
---
arch/arm/boot/dts/bcm5301x.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 4e3fbce..2a343f2 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -338,6 +338,15 @@
};
};
+ i2c0: i2c@18009000 {
+ compatible = "brcm,iproc-i2c";
+ reg = <0x18009000 0x50>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_NONE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ };
+
lcpll0: lcpll0@1800c100 {
#clock-cells = <1>;
compatible = "brcm,nsp-lcpll0";
--
2.7.4
On 03/02/2017 04:21 PM, Jon Mason wrote:
> From: Jon Mason <[email protected]>
>
> Add I2C support to the bcm5301x Device Tree. Since no driver changes
> are needed to enable this hardware, only the device tree changes are
> required to make this functional.
>
> Signed-off-by: Jon Mason <[email protected]>
> ---
> arch/arm/boot/dts/bcm5301x.dtsi | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
> index 4e3fbce..2a343f2 100644
> --- a/arch/arm/boot/dts/bcm5301x.dtsi
> +++ b/arch/arm/boot/dts/bcm5301x.dtsi
> @@ -338,6 +338,15 @@
> };
> };
>
> + i2c0: i2c@18009000 {
> + compatible = "brcm,iproc-i2c";
> + reg = <0x18009000 0x50>;
> + interrupts = <GIC_SPI 121 IRQ_TYPE_NONE>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-frequency = <100000>;
Should not this have a:
status = "disabled"
property by default such that boards can override this by phandle when
there are actual I2C devices available?
> + };
> +
> lcpll0: lcpll0@1800c100 {
> #clock-cells = <1>;
> compatible = "brcm,nsp-lcpll0";
>
--
Florian
On Sun, Mar 5, 2017 at 8:13 PM, Florian Fainelli <[email protected]> wrote:
>
>
> On 03/02/2017 04:21 PM, Jon Mason wrote:
>> From: Jon Mason <[email protected]>
>>
>> Add I2C support to the bcm5301x Device Tree. Since no driver changes
>> are needed to enable this hardware, only the device tree changes are
>> required to make this functional.
>>
>> Signed-off-by: Jon Mason <[email protected]>
>> ---
>> arch/arm/boot/dts/bcm5301x.dtsi | 9 +++++++++
>> 1 file changed, 9 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
>> index 4e3fbce..2a343f2 100644
>> --- a/arch/arm/boot/dts/bcm5301x.dtsi
>> +++ b/arch/arm/boot/dts/bcm5301x.dtsi
>> @@ -338,6 +338,15 @@
>> };
>> };
>>
>> + i2c0: i2c@18009000 {
>> + compatible = "brcm,iproc-i2c";
>> + reg = <0x18009000 0x50>;
>> + interrupts = <GIC_SPI 121 IRQ_TYPE_NONE>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + clock-frequency = <100000>;
>
> Should not this have a:
> status = "disabled"
>
> property by default such that boards can override this by phandle when
> there are actual I2C devices available?
Your comment appears to match the way it is being done in most device trees.
NSP implementation is identical to this. So, if I should change it
here, I should make there too.
Thanks,
Jon
>> + };
>> +
>> lcpll0: lcpll0@1800c100 {
>> #clock-cells = <1>;
>> compatible = "brcm,nsp-lcpll0";
>>
>
> --
> Florian