Signed-off-by: Rick Altherr <[email protected]>
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- Consistently write hex contstants with lowercase letters
- Drop model numbers from description as same IP is used in every generation
Changes in v2:
- Rewritten as an IIO ADC device
.../devicetree/bindings/iio/adc/aspeed_adc.txt | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt
diff --git a/Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt b/Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt
new file mode 100644
index 000000000000..674e133b7cd7
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt
@@ -0,0 +1,20 @@
+Aspeed ADC
+
+This device is a 10-bit converter for 16 voltage channels. All inputs are
+single ended.
+
+Required properties:
+- compatible: Should be "aspeed,ast2400-adc" or "aspeed,ast2500-adc"
+- reg: memory window mapping address and length
+- clocks: Input clock used to derive the sample clock. Expected to be the
+ SoC's APB clock.
+- #io-channel-cells: Must be set to <1> to indicate channels are selected
+ by index.
+
+Example:
+ adc@1e6e9000 {
+ compatible = "aspeed,ast2400-adc";
+ reg = <0x1e6e9000 0xb0>;
+ clocks = <&clk_apb>;
+ #io-channel-cells = <1>;
+ };
--
2.12.2.564.g063fe858b8-goog
Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
interrupts are supported by the hardware but are not currently implemented.
Signed-off-by: Rick Altherr <[email protected]>
---
Changes in v5:
- Return EINVAL for unimplemented read/write channel infos.
- Return EPERM for write attempts to read-only channel infos.
Changes in v4:
- Avoid copying per-model data to per-instance data
Changes in v3:
- Drop model numbers from description as same IP is used in every generation
- Remove unused macros
- Shorten macro prefix to just ASPEED_
- Remove extraneous whitespace
- Rename 2nd argument of ASPEED_CHAN() to clarify purpose
- Use existing macros in place of magic constants
- Remove unnecessary logging in failure conditions during probe
- Disable ADC hardware during remove()
- Add a NULL terminator to of_match_table
- Add per-model data to accomodate slight variations (vref, min/max sample rate)
- Added missing Kconfig depends on COMMON_CLK
Changes in v2:
- Rewritten as an IIO device
- Renamed register macros to describe the register's purpose
- Replaced awkward reading of 16-bit data registers with readw()
- Added Kconfig dependency on COMPILE_TEST
drivers/iio/adc/Kconfig | 11 ++
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/aspeed_adc.c | 294 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 306 insertions(+)
create mode 100644 drivers/iio/adc/aspeed_adc.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 2268a6fb9865..236d05f99e80 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -130,6 +130,17 @@ config AD799X
To compile this driver as a module, choose M here: the module will be
called ad799x.
+config ASPEED_ADC
+ tristate "Aspeed ADC"
+ depends on ARCH_ASPEED || COMPILE_TEST
+ depends on COMMON_CLK
+ help
+ If you say yes here you get support for the ADC included in Aspeed
+ BMC SoCs.
+
+ To compile this driver as a module, choose M here: the module will be
+ called aspeed_adc.
+
config AT91_ADC
tristate "Atmel AT91 ADC"
depends on ARCH_AT91
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index 73dbe399f894..306f10ffca74 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_AD7791) += ad7791.o
obj-$(CONFIG_AD7793) += ad7793.o
obj-$(CONFIG_AD7887) += ad7887.o
obj-$(CONFIG_AD799X) += ad799x.o
+obj-$(CONFIG_ASPEED_ADC) += aspeed_adc.o
obj-$(CONFIG_AT91_ADC) += at91_adc.o
obj-$(CONFIG_AT91_SAMA5D2_ADC) += at91-sama5d2_adc.o
obj-$(CONFIG_AXP288_ADC) += axp288_adc.o
diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c
new file mode 100644
index 000000000000..2283ed202194
--- /dev/null
+++ b/drivers/iio/adc/aspeed_adc.c
@@ -0,0 +1,294 @@
+/*
+ * Aspeed AST2400/2500 ADC
+ *
+ * Copyright (C) 2017 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ */
+
+#include <asm/io.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+#include <linux/iio/iio.h>
+#include <linux/iio/driver.h>
+
+#define ASPEED_RESOLUTION_BITS 10
+#define ASPEED_CLOCKS_PER_SAMPLE 12
+
+#define ASPEED_REG_ENGINE_CONTROL 0x00
+#define ASPEED_REG_INTERRUPT_CONTROL 0x04
+#define ASPEED_REG_VGA_DETECT_CONTROL 0x08
+#define ASPEED_REG_CLOCK_CONTROL 0x0C
+#define ASPEED_REG_MAX 0xC0
+
+#define ASPEED_OPERATION_MODE_POWER_DOWN (0x0 << 1)
+#define ASPEED_OPERATION_MODE_STANDBY (0x1 << 1)
+#define ASPEED_OPERATION_MODE_NORMAL (0x7 << 1)
+
+#define ASPEED_ENGINE_ENABLE BIT(0)
+
+struct aspeed_adc_model_data {
+ const char *model_name;
+ unsigned int min_sampling_rate; // Hz
+ unsigned int max_sampling_rate; // Hz
+ unsigned int vref_voltage; // mV
+};
+
+struct aspeed_adc_data {
+ struct device *dev;
+ void __iomem *base;
+ spinlock_t clk_lock;
+ struct clk_hw *clk_prescaler;
+ struct clk_hw *clk_scaler;
+};
+
+#define ASPEED_CHAN(_idx, _data_reg_addr) { \
+ .type = IIO_VOLTAGE, \
+ .indexed = 1, \
+ .channel = (_idx), \
+ .address = (_data_reg_addr), \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
+ BIT(IIO_CHAN_INFO_SAMP_FREQ), \
+}
+
+static const struct iio_chan_spec aspeed_adc_iio_channels[] = {
+ ASPEED_CHAN(0, 0x10),
+ ASPEED_CHAN(1, 0x12),
+ ASPEED_CHAN(2, 0x14),
+ ASPEED_CHAN(3, 0x16),
+ ASPEED_CHAN(4, 0x18),
+ ASPEED_CHAN(5, 0x1A),
+ ASPEED_CHAN(6, 0x1C),
+ ASPEED_CHAN(7, 0x1E),
+ ASPEED_CHAN(8, 0x20),
+ ASPEED_CHAN(9, 0x22),
+ ASPEED_CHAN(10, 0x24),
+ ASPEED_CHAN(11, 0x26),
+ ASPEED_CHAN(12, 0x28),
+ ASPEED_CHAN(13, 0x2A),
+ ASPEED_CHAN(14, 0x2C),
+ ASPEED_CHAN(15, 0x2E),
+};
+
+static int aspeed_adc_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val, int *val2, long mask)
+{
+ struct aspeed_adc_data *data = iio_priv(indio_dev);
+ const struct aspeed_adc_model_data *model_data =
+ of_device_get_match_data(data->dev);
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ *val = readw(data->base + chan->address);
+ return IIO_VAL_INT;
+
+ case IIO_CHAN_INFO_SCALE:
+ *val = model_data->vref_voltage;
+ *val2 = ASPEED_RESOLUTION_BITS;
+ return IIO_VAL_FRACTIONAL_LOG2;
+
+ case IIO_CHAN_INFO_SAMP_FREQ:
+ *val = clk_get_rate(data->clk_scaler->clk) /
+ ASPEED_CLOCKS_PER_SAMPLE;
+ return IIO_VAL_INT;
+
+ default:
+ return -EINVAL;
+ }
+}
+
+static int aspeed_adc_write_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int val, int val2, long mask)
+{
+ struct aspeed_adc_data *data = iio_priv(indio_dev);
+ const struct aspeed_adc_model_data *model_data =
+ of_device_get_match_data(data->dev);
+
+ switch (mask) {
+ case IIO_CHAN_INFO_SAMP_FREQ:
+ if (val < model_data->min_sampling_rate ||
+ val > model_data->max_sampling_rate)
+ return -EINVAL;
+
+ clk_set_rate(data->clk_scaler->clk,
+ val * ASPEED_CLOCKS_PER_SAMPLE);
+ return 0;
+
+ case IIO_CHAN_INFO_SCALE:
+ case IIO_CHAN_INFO_RAW:
+ /*
+ * Technically, these could be written but the only reasons
+ * for doing so seem better handled in userspace. EPERM is
+ * returned to signal this is a policy choice rather than a
+ * hardware limitation.
+ */
+ return -EPERM;
+
+ default:
+ return -EINVAL;
+ }
+}
+
+static int aspeed_adc_reg_access(struct iio_dev *indio_dev,
+ unsigned int reg, unsigned int writeval,
+ unsigned int *readval)
+{
+ struct aspeed_adc_data *data = iio_priv(indio_dev);
+
+ if (!readval || reg % 4 || reg > ASPEED_REG_MAX)
+ return -EINVAL;
+
+ *readval = readl(data->base + reg);
+ return 0;
+}
+
+static const struct iio_info aspeed_adc_iio_info = {
+ .driver_module = THIS_MODULE,
+ .read_raw = aspeed_adc_read_raw,
+ .write_raw = aspeed_adc_write_raw,
+ .debugfs_reg_access = aspeed_adc_reg_access,
+};
+
+static int aspeed_adc_probe(struct platform_device *pdev)
+{
+ struct iio_dev *indio_dev;
+ struct aspeed_adc_data *data;
+ const struct aspeed_adc_model_data *model_data;
+ struct resource *res;
+ const char *clk_parent_name;
+ int ret;
+ u32 adc_engine_control_reg_val;
+
+ indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*data));
+ if (!indio_dev)
+ return -ENOMEM;
+
+ data = iio_priv(indio_dev);
+ data->dev = &pdev->dev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ data->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(data->base))
+ return PTR_ERR(data->base);
+
+ /* Register ADC clock prescaler with source specified by device tree. */
+ spin_lock_init(&data->clk_lock);
+ clk_parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0);
+
+ data->clk_prescaler = clk_hw_register_divider(
+ &pdev->dev, "prescaler", clk_parent_name, 0,
+ data->base + ASPEED_REG_CLOCK_CONTROL,
+ 17, 15, 0, &data->clk_lock);
+ if (IS_ERR(data->clk_prescaler))
+ return PTR_ERR(data->clk_prescaler);
+
+ /*
+ * Register ADC clock scaler downstream from the prescaler. Allow rate
+ * setting to adjust the prescaler as well.
+ */
+ data->clk_scaler = clk_hw_register_divider(
+ &pdev->dev, "scaler", "prescaler",
+ CLK_SET_RATE_PARENT,
+ data->base + ASPEED_REG_CLOCK_CONTROL,
+ 0, 10, 0, &data->clk_lock);
+ if (IS_ERR(data->clk_scaler)) {
+ ret = PTR_ERR(data->clk_scaler);
+ goto scaler_error;
+ }
+
+ /* Start all channels in normal mode. */
+ clk_prepare_enable(data->clk_scaler->clk);
+ adc_engine_control_reg_val = GENMASK(31, 16) |
+ ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE;
+ writel(adc_engine_control_reg_val,
+ data->base + ASPEED_REG_ENGINE_CONTROL);
+
+ model_data = of_device_get_match_data(&pdev->dev);
+ indio_dev->name = model_data->model_name;
+ indio_dev->dev.parent = &pdev->dev;
+ indio_dev->info = &aspeed_adc_iio_info;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->channels = aspeed_adc_iio_channels;
+ indio_dev->num_channels = ARRAY_SIZE(aspeed_adc_iio_channels);
+
+ ret = iio_device_register(indio_dev);
+ if (ret)
+ goto iio_register_error;
+
+ return 0;
+
+iio_register_error:
+ writel(ASPEED_OPERATION_MODE_POWER_DOWN,
+ data->base + ASPEED_REG_ENGINE_CONTROL);
+ clk_disable_unprepare(data->clk_scaler->clk);
+ clk_hw_unregister_divider(data->clk_scaler);
+
+scaler_error:
+ clk_hw_unregister_divider(data->clk_prescaler);
+ return ret;
+}
+
+static int aspeed_adc_remove(struct platform_device *pdev)
+{
+ struct iio_dev *indio_dev = platform_get_drvdata(pdev);
+ struct aspeed_adc_data *data = iio_priv(indio_dev);
+
+ iio_device_unregister(indio_dev);
+ writel(ASPEED_OPERATION_MODE_POWER_DOWN,
+ data->base + ASPEED_REG_ENGINE_CONTROL);
+ clk_disable_unprepare(data->clk_scaler->clk);
+ clk_hw_unregister_divider(data->clk_scaler);
+ clk_hw_unregister_divider(data->clk_prescaler);
+
+ return 0;
+}
+
+static const struct aspeed_adc_model_data ast2400_model_data = {
+ .model_name = "ast2400-adc",
+ .vref_voltage = 2500, // mV
+ .min_sampling_rate = 10000,
+ .max_sampling_rate = 500000,
+};
+
+static const struct aspeed_adc_model_data ast2500_model_data = {
+ .model_name = "ast2500-adc",
+ .vref_voltage = 1800, // mV
+ .min_sampling_rate = 1,
+ .max_sampling_rate = 1000000,
+};
+
+static const struct of_device_id aspeed_adc_matches[] = {
+ { .compatible = "aspeed,ast2400-adc", .data = &ast2400_model_data },
+ { .compatible = "aspeed,ast2500-adc", .data = &ast2500_model_data },
+ {},
+};
+MODULE_DEVICE_TABLE(of, aspeed_adc_matches);
+
+static struct platform_driver aspeed_adc_driver = {
+ .probe = aspeed_adc_probe,
+ .remove = aspeed_adc_remove,
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .of_match_table = aspeed_adc_matches,
+ }
+};
+
+module_platform_driver(aspeed_adc_driver);
+
+MODULE_AUTHOR("Rick Altherr <[email protected]>");
+MODULE_DESCRIPTION("Aspeed AST2400/2500 ADC Driver");
+MODULE_LICENSE("GPL");
--
2.12.2.564.g063fe858b8-goog
On Wed, Mar 29, 2017 at 8:22 AM, Rick Altherr <[email protected]> wrote:
> Signed-off-by: Rick Altherr <[email protected]>
> ---
Acked-by: Joel Stanley <[email protected]>
>
> Changes in v5: None
> Changes in v4: None
> Changes in v3:
> - Consistently write hex contstants with lowercase letters
> - Drop model numbers from description as same IP is used in every generation
>
> Changes in v2:
> - Rewritten as an IIO ADC device
>
> .../devicetree/bindings/iio/adc/aspeed_adc.txt | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt b/Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt
> new file mode 100644
> index 000000000000..674e133b7cd7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt
> @@ -0,0 +1,20 @@
> +Aspeed ADC
> +
> +This device is a 10-bit converter for 16 voltage channels. All inputs are
> +single ended.
> +
> +Required properties:
> +- compatible: Should be "aspeed,ast2400-adc" or "aspeed,ast2500-adc"
> +- reg: memory window mapping address and length
> +- clocks: Input clock used to derive the sample clock. Expected to be the
> + SoC's APB clock.
> +- #io-channel-cells: Must be set to <1> to indicate channels are selected
> + by index.
> +
> +Example:
> + adc@1e6e9000 {
> + compatible = "aspeed,ast2400-adc";
> + reg = <0x1e6e9000 0xb0>;
> + clocks = <&clk_apb>;
> + #io-channel-cells = <1>;
> + };
> --
> 2.12.2.564.g063fe858b8-goog
>
On Wed, Mar 29, 2017 at 8:22 AM, Rick Altherr <[email protected]> wrote:
> Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
> interrupts are supported by the hardware but are not currently implemented.
>
> Signed-off-by: Rick Altherr <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
> ---
>
> Changes in v5:
> - Return EINVAL for unimplemented read/write channel infos.
> - Return EPERM for write attempts to read-only channel infos.
>
> Changes in v4:
> - Avoid copying per-model data to per-instance data
>
> Changes in v3:
> - Drop model numbers from description as same IP is used in every generation
> - Remove unused macros
> - Shorten macro prefix to just ASPEED_
> - Remove extraneous whitespace
> - Rename 2nd argument of ASPEED_CHAN() to clarify purpose
> - Use existing macros in place of magic constants
> - Remove unnecessary logging in failure conditions during probe
> - Disable ADC hardware during remove()
> - Add a NULL terminator to of_match_table
> - Add per-model data to accomodate slight variations (vref, min/max sample rate)
> - Added missing Kconfig depends on COMMON_CLK
>
> Changes in v2:
> - Rewritten as an IIO device
> - Renamed register macros to describe the register's purpose
> - Replaced awkward reading of 16-bit data registers with readw()
> - Added Kconfig dependency on COMPILE_TEST
>
> drivers/iio/adc/Kconfig | 11 ++
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/aspeed_adc.c | 294 +++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 306 insertions(+)
> create mode 100644 drivers/iio/adc/aspeed_adc.c
>
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index 2268a6fb9865..236d05f99e80 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -130,6 +130,17 @@ config AD799X
> To compile this driver as a module, choose M here: the module will be
> called ad799x.
>
> +config ASPEED_ADC
> + tristate "Aspeed ADC"
> + depends on ARCH_ASPEED || COMPILE_TEST
> + depends on COMMON_CLK
> + help
> + If you say yes here you get support for the ADC included in Aspeed
> + BMC SoCs.
> +
> + To compile this driver as a module, choose M here: the module will be
> + called aspeed_adc.
> +
> config AT91_ADC
> tristate "Atmel AT91 ADC"
> depends on ARCH_AT91
> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
> index 73dbe399f894..306f10ffca74 100644
> --- a/drivers/iio/adc/Makefile
> +++ b/drivers/iio/adc/Makefile
> @@ -14,6 +14,7 @@ obj-$(CONFIG_AD7791) += ad7791.o
> obj-$(CONFIG_AD7793) += ad7793.o
> obj-$(CONFIG_AD7887) += ad7887.o
> obj-$(CONFIG_AD799X) += ad799x.o
> +obj-$(CONFIG_ASPEED_ADC) += aspeed_adc.o
> obj-$(CONFIG_AT91_ADC) += at91_adc.o
> obj-$(CONFIG_AT91_SAMA5D2_ADC) += at91-sama5d2_adc.o
> obj-$(CONFIG_AXP288_ADC) += axp288_adc.o
> diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c
> new file mode 100644
> index 000000000000..2283ed202194
> --- /dev/null
> +++ b/drivers/iio/adc/aspeed_adc.c
> @@ -0,0 +1,294 @@
> +/*
> + * Aspeed AST2400/2500 ADC
> + *
> + * Copyright (C) 2017 Google, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + */
> +
> +#include <asm/io.h>
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/err.h>
> +#include <linux/errno.h>
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/spinlock.h>
> +#include <linux/types.h>
> +
> +#include <linux/iio/iio.h>
> +#include <linux/iio/driver.h>
> +
> +#define ASPEED_RESOLUTION_BITS 10
> +#define ASPEED_CLOCKS_PER_SAMPLE 12
> +
> +#define ASPEED_REG_ENGINE_CONTROL 0x00
> +#define ASPEED_REG_INTERRUPT_CONTROL 0x04
> +#define ASPEED_REG_VGA_DETECT_CONTROL 0x08
> +#define ASPEED_REG_CLOCK_CONTROL 0x0C
> +#define ASPEED_REG_MAX 0xC0
> +
> +#define ASPEED_OPERATION_MODE_POWER_DOWN (0x0 << 1)
> +#define ASPEED_OPERATION_MODE_STANDBY (0x1 << 1)
> +#define ASPEED_OPERATION_MODE_NORMAL (0x7 << 1)
> +
> +#define ASPEED_ENGINE_ENABLE BIT(0)
> +
> +struct aspeed_adc_model_data {
> + const char *model_name;
> + unsigned int min_sampling_rate; // Hz
> + unsigned int max_sampling_rate; // Hz
> + unsigned int vref_voltage; // mV
> +};
> +
> +struct aspeed_adc_data {
> + struct device *dev;
> + void __iomem *base;
> + spinlock_t clk_lock;
> + struct clk_hw *clk_prescaler;
> + struct clk_hw *clk_scaler;
> +};
> +
> +#define ASPEED_CHAN(_idx, _data_reg_addr) { \
> + .type = IIO_VOLTAGE, \
> + .indexed = 1, \
> + .channel = (_idx), \
> + .address = (_data_reg_addr), \
> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
> + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
> + BIT(IIO_CHAN_INFO_SAMP_FREQ), \
> +}
> +
> +static const struct iio_chan_spec aspeed_adc_iio_channels[] = {
> + ASPEED_CHAN(0, 0x10),
> + ASPEED_CHAN(1, 0x12),
> + ASPEED_CHAN(2, 0x14),
> + ASPEED_CHAN(3, 0x16),
> + ASPEED_CHAN(4, 0x18),
> + ASPEED_CHAN(5, 0x1A),
> + ASPEED_CHAN(6, 0x1C),
> + ASPEED_CHAN(7, 0x1E),
> + ASPEED_CHAN(8, 0x20),
> + ASPEED_CHAN(9, 0x22),
> + ASPEED_CHAN(10, 0x24),
> + ASPEED_CHAN(11, 0x26),
> + ASPEED_CHAN(12, 0x28),
> + ASPEED_CHAN(13, 0x2A),
> + ASPEED_CHAN(14, 0x2C),
> + ASPEED_CHAN(15, 0x2E),
> +};
> +
> +static int aspeed_adc_read_raw(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan,
> + int *val, int *val2, long mask)
> +{
> + struct aspeed_adc_data *data = iio_priv(indio_dev);
> + const struct aspeed_adc_model_data *model_data =
> + of_device_get_match_data(data->dev);
> +
> + switch (mask) {
> + case IIO_CHAN_INFO_RAW:
> + *val = readw(data->base + chan->address);
> + return IIO_VAL_INT;
> +
> + case IIO_CHAN_INFO_SCALE:
> + *val = model_data->vref_voltage;
> + *val2 = ASPEED_RESOLUTION_BITS;
> + return IIO_VAL_FRACTIONAL_LOG2;
> +
> + case IIO_CHAN_INFO_SAMP_FREQ:
> + *val = clk_get_rate(data->clk_scaler->clk) /
> + ASPEED_CLOCKS_PER_SAMPLE;
> + return IIO_VAL_INT;
> +
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static int aspeed_adc_write_raw(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan,
> + int val, int val2, long mask)
> +{
> + struct aspeed_adc_data *data = iio_priv(indio_dev);
> + const struct aspeed_adc_model_data *model_data =
> + of_device_get_match_data(data->dev);
> +
> + switch (mask) {
> + case IIO_CHAN_INFO_SAMP_FREQ:
> + if (val < model_data->min_sampling_rate ||
> + val > model_data->max_sampling_rate)
> + return -EINVAL;
> +
> + clk_set_rate(data->clk_scaler->clk,
> + val * ASPEED_CLOCKS_PER_SAMPLE);
> + return 0;
> +
> + case IIO_CHAN_INFO_SCALE:
> + case IIO_CHAN_INFO_RAW:
> + /*
> + * Technically, these could be written but the only reasons
> + * for doing so seem better handled in userspace. EPERM is
> + * returned to signal this is a policy choice rather than a
> + * hardware limitation.
> + */
> + return -EPERM;
> +
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static int aspeed_adc_reg_access(struct iio_dev *indio_dev,
> + unsigned int reg, unsigned int writeval,
> + unsigned int *readval)
> +{
> + struct aspeed_adc_data *data = iio_priv(indio_dev);
> +
> + if (!readval || reg % 4 || reg > ASPEED_REG_MAX)
> + return -EINVAL;
> +
> + *readval = readl(data->base + reg);
> + return 0;
> +}
> +
> +static const struct iio_info aspeed_adc_iio_info = {
> + .driver_module = THIS_MODULE,
> + .read_raw = aspeed_adc_read_raw,
> + .write_raw = aspeed_adc_write_raw,
> + .debugfs_reg_access = aspeed_adc_reg_access,
> +};
> +
> +static int aspeed_adc_probe(struct platform_device *pdev)
> +{
> + struct iio_dev *indio_dev;
> + struct aspeed_adc_data *data;
> + const struct aspeed_adc_model_data *model_data;
> + struct resource *res;
> + const char *clk_parent_name;
> + int ret;
> + u32 adc_engine_control_reg_val;
> +
> + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*data));
> + if (!indio_dev)
> + return -ENOMEM;
> +
> + data = iio_priv(indio_dev);
> + data->dev = &pdev->dev;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + data->base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(data->base))
> + return PTR_ERR(data->base);
> +
> + /* Register ADC clock prescaler with source specified by device tree. */
> + spin_lock_init(&data->clk_lock);
> + clk_parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0);
> +
> + data->clk_prescaler = clk_hw_register_divider(
> + &pdev->dev, "prescaler", clk_parent_name, 0,
> + data->base + ASPEED_REG_CLOCK_CONTROL,
> + 17, 15, 0, &data->clk_lock);
> + if (IS_ERR(data->clk_prescaler))
> + return PTR_ERR(data->clk_prescaler);
> +
> + /*
> + * Register ADC clock scaler downstream from the prescaler. Allow rate
> + * setting to adjust the prescaler as well.
> + */
> + data->clk_scaler = clk_hw_register_divider(
> + &pdev->dev, "scaler", "prescaler",
> + CLK_SET_RATE_PARENT,
> + data->base + ASPEED_REG_CLOCK_CONTROL,
> + 0, 10, 0, &data->clk_lock);
> + if (IS_ERR(data->clk_scaler)) {
> + ret = PTR_ERR(data->clk_scaler);
> + goto scaler_error;
> + }
> +
> + /* Start all channels in normal mode. */
> + clk_prepare_enable(data->clk_scaler->clk);
> + adc_engine_control_reg_val = GENMASK(31, 16) |
> + ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE;
> + writel(adc_engine_control_reg_val,
> + data->base + ASPEED_REG_ENGINE_CONTROL);
> +
> + model_data = of_device_get_match_data(&pdev->dev);
> + indio_dev->name = model_data->model_name;
> + indio_dev->dev.parent = &pdev->dev;
> + indio_dev->info = &aspeed_adc_iio_info;
> + indio_dev->modes = INDIO_DIRECT_MODE;
> + indio_dev->channels = aspeed_adc_iio_channels;
> + indio_dev->num_channels = ARRAY_SIZE(aspeed_adc_iio_channels);
> +
> + ret = iio_device_register(indio_dev);
> + if (ret)
> + goto iio_register_error;
> +
> + return 0;
> +
> +iio_register_error:
> + writel(ASPEED_OPERATION_MODE_POWER_DOWN,
> + data->base + ASPEED_REG_ENGINE_CONTROL);
> + clk_disable_unprepare(data->clk_scaler->clk);
> + clk_hw_unregister_divider(data->clk_scaler);
> +
> +scaler_error:
> + clk_hw_unregister_divider(data->clk_prescaler);
> + return ret;
> +}
> +
> +static int aspeed_adc_remove(struct platform_device *pdev)
> +{
> + struct iio_dev *indio_dev = platform_get_drvdata(pdev);
> + struct aspeed_adc_data *data = iio_priv(indio_dev);
> +
> + iio_device_unregister(indio_dev);
> + writel(ASPEED_OPERATION_MODE_POWER_DOWN,
> + data->base + ASPEED_REG_ENGINE_CONTROL);
> + clk_disable_unprepare(data->clk_scaler->clk);
> + clk_hw_unregister_divider(data->clk_scaler);
> + clk_hw_unregister_divider(data->clk_prescaler);
> +
> + return 0;
> +}
> +
> +static const struct aspeed_adc_model_data ast2400_model_data = {
> + .model_name = "ast2400-adc",
> + .vref_voltage = 2500, // mV
> + .min_sampling_rate = 10000,
> + .max_sampling_rate = 500000,
> +};
> +
> +static const struct aspeed_adc_model_data ast2500_model_data = {
> + .model_name = "ast2500-adc",
> + .vref_voltage = 1800, // mV
> + .min_sampling_rate = 1,
> + .max_sampling_rate = 1000000,
> +};
> +
> +static const struct of_device_id aspeed_adc_matches[] = {
> + { .compatible = "aspeed,ast2400-adc", .data = &ast2400_model_data },
> + { .compatible = "aspeed,ast2500-adc", .data = &ast2500_model_data },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, aspeed_adc_matches);
> +
> +static struct platform_driver aspeed_adc_driver = {
> + .probe = aspeed_adc_probe,
> + .remove = aspeed_adc_remove,
> + .driver = {
> + .name = KBUILD_MODNAME,
> + .of_match_table = aspeed_adc_matches,
> + }
> +};
> +
> +module_platform_driver(aspeed_adc_driver);
> +
> +MODULE_AUTHOR("Rick Altherr <[email protected]>");
> +MODULE_DESCRIPTION("Aspeed AST2400/2500 ADC Driver");
> +MODULE_LICENSE("GPL");
> --
> 2.12.2.564.g063fe858b8-goog
>
On Tue, Mar 28, 2017 at 7:33 PM, Joel Stanley <[email protected]> wrote:
> On Wed, Mar 29, 2017 at 8:22 AM, Rick Altherr <[email protected]> wrote:
>> Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
>> interrupts are supported by the hardware but are not currently implemented.
>>
>> Signed-off-by: Rick Altherr <[email protected]>
>
> Reviewed-by: Joel Stanley <[email protected]>
>
Tested-by: Xo Wang <[email protected]>
Tested on a Zaius OpenPOWER server running a AST2500 BMC alongside configs:
CONFIG_IIO=y
CONFIG_ASPEED_ADC=y
CONFIG_SENSORS_IIO_HWMON=y
as well as the appropriate device tree entries.
>> ---
>>
>> Changes in v5:
>> - Return EINVAL for unimplemented read/write channel infos.
>> - Return EPERM for write attempts to read-only channel infos.
>>
>> Changes in v4:
>> - Avoid copying per-model data to per-instance data
>>
>> Changes in v3:
>> - Drop model numbers from description as same IP is used in every generation
>> - Remove unused macros
>> - Shorten macro prefix to just ASPEED_
>> - Remove extraneous whitespace
>> - Rename 2nd argument of ASPEED_CHAN() to clarify purpose
>> - Use existing macros in place of magic constants
>> - Remove unnecessary logging in failure conditions during probe
>> - Disable ADC hardware during remove()
>> - Add a NULL terminator to of_match_table
>> - Add per-model data to accomodate slight variations (vref, min/max sample rate)
>> - Added missing Kconfig depends on COMMON_CLK
>>
>> Changes in v2:
>> - Rewritten as an IIO device
>> - Renamed register macros to describe the register's purpose
>> - Replaced awkward reading of 16-bit data registers with readw()
>> - Added Kconfig dependency on COMPILE_TEST
>>
>> drivers/iio/adc/Kconfig | 11 ++
>> drivers/iio/adc/Makefile | 1 +
>> drivers/iio/adc/aspeed_adc.c | 294 +++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 306 insertions(+)
>> create mode 100644 drivers/iio/adc/aspeed_adc.c
>>
>> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
>> index 2268a6fb9865..236d05f99e80 100644
>> --- a/drivers/iio/adc/Kconfig
>> +++ b/drivers/iio/adc/Kconfig
>> @@ -130,6 +130,17 @@ config AD799X
>> To compile this driver as a module, choose M here: the module will be
>> called ad799x.
>>
>> +config ASPEED_ADC
>> + tristate "Aspeed ADC"
>> + depends on ARCH_ASPEED || COMPILE_TEST
>> + depends on COMMON_CLK
>> + help
>> + If you say yes here you get support for the ADC included in Aspeed
>> + BMC SoCs.
>> +
>> + To compile this driver as a module, choose M here: the module will be
>> + called aspeed_adc.
>> +
>> config AT91_ADC
>> tristate "Atmel AT91 ADC"
>> depends on ARCH_AT91
>> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
>> index 73dbe399f894..306f10ffca74 100644
>> --- a/drivers/iio/adc/Makefile
>> +++ b/drivers/iio/adc/Makefile
>> @@ -14,6 +14,7 @@ obj-$(CONFIG_AD7791) += ad7791.o
>> obj-$(CONFIG_AD7793) += ad7793.o
>> obj-$(CONFIG_AD7887) += ad7887.o
>> obj-$(CONFIG_AD799X) += ad799x.o
>> +obj-$(CONFIG_ASPEED_ADC) += aspeed_adc.o
>> obj-$(CONFIG_AT91_ADC) += at91_adc.o
>> obj-$(CONFIG_AT91_SAMA5D2_ADC) += at91-sama5d2_adc.o
>> obj-$(CONFIG_AXP288_ADC) += axp288_adc.o
>> diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c
>> new file mode 100644
>> index 000000000000..2283ed202194
>> --- /dev/null
>> +++ b/drivers/iio/adc/aspeed_adc.c
>> @@ -0,0 +1,294 @@
>> +/*
>> + * Aspeed AST2400/2500 ADC
>> + *
>> + * Copyright (C) 2017 Google, Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms and conditions of the GNU General Public License,
>> + * version 2, as published by the Free Software Foundation.
>> + *
>> + */
>> +
>> +#include <asm/io.h>
>> +#include <linux/clk.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/err.h>
>> +#include <linux/errno.h>
>> +#include <linux/module.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/spinlock.h>
>> +#include <linux/types.h>
>> +
>> +#include <linux/iio/iio.h>
>> +#include <linux/iio/driver.h>
>> +
>> +#define ASPEED_RESOLUTION_BITS 10
>> +#define ASPEED_CLOCKS_PER_SAMPLE 12
>> +
>> +#define ASPEED_REG_ENGINE_CONTROL 0x00
>> +#define ASPEED_REG_INTERRUPT_CONTROL 0x04
>> +#define ASPEED_REG_VGA_DETECT_CONTROL 0x08
>> +#define ASPEED_REG_CLOCK_CONTROL 0x0C
>> +#define ASPEED_REG_MAX 0xC0
>> +
>> +#define ASPEED_OPERATION_MODE_POWER_DOWN (0x0 << 1)
>> +#define ASPEED_OPERATION_MODE_STANDBY (0x1 << 1)
>> +#define ASPEED_OPERATION_MODE_NORMAL (0x7 << 1)
>> +
>> +#define ASPEED_ENGINE_ENABLE BIT(0)
>> +
>> +struct aspeed_adc_model_data {
>> + const char *model_name;
>> + unsigned int min_sampling_rate; // Hz
>> + unsigned int max_sampling_rate; // Hz
>> + unsigned int vref_voltage; // mV
>> +};
>> +
>> +struct aspeed_adc_data {
>> + struct device *dev;
>> + void __iomem *base;
>> + spinlock_t clk_lock;
>> + struct clk_hw *clk_prescaler;
>> + struct clk_hw *clk_scaler;
>> +};
>> +
>> +#define ASPEED_CHAN(_idx, _data_reg_addr) { \
>> + .type = IIO_VOLTAGE, \
>> + .indexed = 1, \
>> + .channel = (_idx), \
>> + .address = (_data_reg_addr), \
>> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
>> + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
>> + BIT(IIO_CHAN_INFO_SAMP_FREQ), \
>> +}
>> +
>> +static const struct iio_chan_spec aspeed_adc_iio_channels[] = {
>> + ASPEED_CHAN(0, 0x10),
>> + ASPEED_CHAN(1, 0x12),
>> + ASPEED_CHAN(2, 0x14),
>> + ASPEED_CHAN(3, 0x16),
>> + ASPEED_CHAN(4, 0x18),
>> + ASPEED_CHAN(5, 0x1A),
>> + ASPEED_CHAN(6, 0x1C),
>> + ASPEED_CHAN(7, 0x1E),
>> + ASPEED_CHAN(8, 0x20),
>> + ASPEED_CHAN(9, 0x22),
>> + ASPEED_CHAN(10, 0x24),
>> + ASPEED_CHAN(11, 0x26),
>> + ASPEED_CHAN(12, 0x28),
>> + ASPEED_CHAN(13, 0x2A),
>> + ASPEED_CHAN(14, 0x2C),
>> + ASPEED_CHAN(15, 0x2E),
>> +};
>> +
>> +static int aspeed_adc_read_raw(struct iio_dev *indio_dev,
>> + struct iio_chan_spec const *chan,
>> + int *val, int *val2, long mask)
>> +{
>> + struct aspeed_adc_data *data = iio_priv(indio_dev);
>> + const struct aspeed_adc_model_data *model_data =
>> + of_device_get_match_data(data->dev);
>> +
>> + switch (mask) {
>> + case IIO_CHAN_INFO_RAW:
>> + *val = readw(data->base + chan->address);
>> + return IIO_VAL_INT;
>> +
>> + case IIO_CHAN_INFO_SCALE:
>> + *val = model_data->vref_voltage;
>> + *val2 = ASPEED_RESOLUTION_BITS;
>> + return IIO_VAL_FRACTIONAL_LOG2;
>> +
>> + case IIO_CHAN_INFO_SAMP_FREQ:
>> + *val = clk_get_rate(data->clk_scaler->clk) /
>> + ASPEED_CLOCKS_PER_SAMPLE;
>> + return IIO_VAL_INT;
>> +
>> + default:
>> + return -EINVAL;
>> + }
>> +}
>> +
>> +static int aspeed_adc_write_raw(struct iio_dev *indio_dev,
>> + struct iio_chan_spec const *chan,
>> + int val, int val2, long mask)
>> +{
>> + struct aspeed_adc_data *data = iio_priv(indio_dev);
>> + const struct aspeed_adc_model_data *model_data =
>> + of_device_get_match_data(data->dev);
>> +
>> + switch (mask) {
>> + case IIO_CHAN_INFO_SAMP_FREQ:
>> + if (val < model_data->min_sampling_rate ||
>> + val > model_data->max_sampling_rate)
>> + return -EINVAL;
>> +
>> + clk_set_rate(data->clk_scaler->clk,
>> + val * ASPEED_CLOCKS_PER_SAMPLE);
>> + return 0;
>> +
>> + case IIO_CHAN_INFO_SCALE:
>> + case IIO_CHAN_INFO_RAW:
>> + /*
>> + * Technically, these could be written but the only reasons
>> + * for doing so seem better handled in userspace. EPERM is
>> + * returned to signal this is a policy choice rather than a
>> + * hardware limitation.
>> + */
>> + return -EPERM;
>> +
>> + default:
>> + return -EINVAL;
>> + }
>> +}
>> +
>> +static int aspeed_adc_reg_access(struct iio_dev *indio_dev,
>> + unsigned int reg, unsigned int writeval,
>> + unsigned int *readval)
>> +{
>> + struct aspeed_adc_data *data = iio_priv(indio_dev);
>> +
>> + if (!readval || reg % 4 || reg > ASPEED_REG_MAX)
>> + return -EINVAL;
>> +
>> + *readval = readl(data->base + reg);
>> + return 0;
>> +}
>> +
>> +static const struct iio_info aspeed_adc_iio_info = {
>> + .driver_module = THIS_MODULE,
>> + .read_raw = aspeed_adc_read_raw,
>> + .write_raw = aspeed_adc_write_raw,
>> + .debugfs_reg_access = aspeed_adc_reg_access,
>> +};
>> +
>> +static int aspeed_adc_probe(struct platform_device *pdev)
>> +{
>> + struct iio_dev *indio_dev;
>> + struct aspeed_adc_data *data;
>> + const struct aspeed_adc_model_data *model_data;
>> + struct resource *res;
>> + const char *clk_parent_name;
>> + int ret;
>> + u32 adc_engine_control_reg_val;
>> +
>> + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*data));
>> + if (!indio_dev)
>> + return -ENOMEM;
>> +
>> + data = iio_priv(indio_dev);
>> + data->dev = &pdev->dev;
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + data->base = devm_ioremap_resource(&pdev->dev, res);
>> + if (IS_ERR(data->base))
>> + return PTR_ERR(data->base);
>> +
>> + /* Register ADC clock prescaler with source specified by device tree. */
>> + spin_lock_init(&data->clk_lock);
>> + clk_parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0);
>> +
>> + data->clk_prescaler = clk_hw_register_divider(
>> + &pdev->dev, "prescaler", clk_parent_name, 0,
>> + data->base + ASPEED_REG_CLOCK_CONTROL,
>> + 17, 15, 0, &data->clk_lock);
>> + if (IS_ERR(data->clk_prescaler))
>> + return PTR_ERR(data->clk_prescaler);
>> +
>> + /*
>> + * Register ADC clock scaler downstream from the prescaler. Allow rate
>> + * setting to adjust the prescaler as well.
>> + */
>> + data->clk_scaler = clk_hw_register_divider(
>> + &pdev->dev, "scaler", "prescaler",
>> + CLK_SET_RATE_PARENT,
>> + data->base + ASPEED_REG_CLOCK_CONTROL,
>> + 0, 10, 0, &data->clk_lock);
>> + if (IS_ERR(data->clk_scaler)) {
>> + ret = PTR_ERR(data->clk_scaler);
>> + goto scaler_error;
>> + }
>> +
>> + /* Start all channels in normal mode. */
>> + clk_prepare_enable(data->clk_scaler->clk);
>> + adc_engine_control_reg_val = GENMASK(31, 16) |
>> + ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE;
>> + writel(adc_engine_control_reg_val,
>> + data->base + ASPEED_REG_ENGINE_CONTROL);
>> +
>> + model_data = of_device_get_match_data(&pdev->dev);
>> + indio_dev->name = model_data->model_name;
>> + indio_dev->dev.parent = &pdev->dev;
>> + indio_dev->info = &aspeed_adc_iio_info;
>> + indio_dev->modes = INDIO_DIRECT_MODE;
>> + indio_dev->channels = aspeed_adc_iio_channels;
>> + indio_dev->num_channels = ARRAY_SIZE(aspeed_adc_iio_channels);
>> +
>> + ret = iio_device_register(indio_dev);
>> + if (ret)
>> + goto iio_register_error;
>> +
>> + return 0;
>> +
>> +iio_register_error:
>> + writel(ASPEED_OPERATION_MODE_POWER_DOWN,
>> + data->base + ASPEED_REG_ENGINE_CONTROL);
>> + clk_disable_unprepare(data->clk_scaler->clk);
>> + clk_hw_unregister_divider(data->clk_scaler);
>> +
>> +scaler_error:
>> + clk_hw_unregister_divider(data->clk_prescaler);
>> + return ret;
>> +}
>> +
>> +static int aspeed_adc_remove(struct platform_device *pdev)
>> +{
>> + struct iio_dev *indio_dev = platform_get_drvdata(pdev);
>> + struct aspeed_adc_data *data = iio_priv(indio_dev);
>> +
>> + iio_device_unregister(indio_dev);
>> + writel(ASPEED_OPERATION_MODE_POWER_DOWN,
>> + data->base + ASPEED_REG_ENGINE_CONTROL);
>> + clk_disable_unprepare(data->clk_scaler->clk);
>> + clk_hw_unregister_divider(data->clk_scaler);
>> + clk_hw_unregister_divider(data->clk_prescaler);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct aspeed_adc_model_data ast2400_model_data = {
>> + .model_name = "ast2400-adc",
>> + .vref_voltage = 2500, // mV
>> + .min_sampling_rate = 10000,
>> + .max_sampling_rate = 500000,
>> +};
>> +
>> +static const struct aspeed_adc_model_data ast2500_model_data = {
>> + .model_name = "ast2500-adc",
>> + .vref_voltage = 1800, // mV
>> + .min_sampling_rate = 1,
>> + .max_sampling_rate = 1000000,
>> +};
>> +
>> +static const struct of_device_id aspeed_adc_matches[] = {
>> + { .compatible = "aspeed,ast2400-adc", .data = &ast2400_model_data },
>> + { .compatible = "aspeed,ast2500-adc", .data = &ast2500_model_data },
>> + {},
>> +};
>> +MODULE_DEVICE_TABLE(of, aspeed_adc_matches);
>> +
>> +static struct platform_driver aspeed_adc_driver = {
>> + .probe = aspeed_adc_probe,
>> + .remove = aspeed_adc_remove,
>> + .driver = {
>> + .name = KBUILD_MODNAME,
>> + .of_match_table = aspeed_adc_matches,
>> + }
>> +};
>> +
>> +module_platform_driver(aspeed_adc_driver);
>> +
>> +MODULE_AUTHOR("Rick Altherr <[email protected]>");
>> +MODULE_DESCRIPTION("Aspeed AST2400/2500 ADC Driver");
>> +MODULE_LICENSE("GPL");
>> --
>> 2.12.2.564.g063fe858b8-goog
>>
On 29/03/17 03:33, Joel Stanley wrote:
> On Wed, Mar 29, 2017 at 8:22 AM, Rick Altherr <[email protected]> wrote:
>> Signed-off-by: Rick Altherr <[email protected]>
>> ---
>
> Acked-by: Joel Stanley <[email protected]>
I can't see why Rob would mind any of the changes made since he
Acked this (and having acked it I doubt he is looking at newer versions!)
so I'm going to take the view his Ack still applies.
Applied to the togreg branch of iio.git which will get pushed out first
as testing for the autobuilders to have a chance to play with it.
Thanks,
Jonathan
>
>>
>> Changes in v5: None
>> Changes in v4: None
>> Changes in v3:
>> - Consistently write hex contstants with lowercase letters
>> - Drop model numbers from description as same IP is used in every generation
>>
>> Changes in v2:
>> - Rewritten as an IIO ADC device
>>
>> .../devicetree/bindings/iio/adc/aspeed_adc.txt | 20 ++++++++++++++++++++
>> 1 file changed, 20 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt
>>
>> diff --git a/Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt b/Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt
>> new file mode 100644
>> index 000000000000..674e133b7cd7
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/iio/adc/aspeed_adc.txt
>> @@ -0,0 +1,20 @@
>> +Aspeed ADC
>> +
>> +This device is a 10-bit converter for 16 voltage channels. All inputs are
>> +single ended.
>> +
>> +Required properties:
>> +- compatible: Should be "aspeed,ast2400-adc" or "aspeed,ast2500-adc"
>> +- reg: memory window mapping address and length
>> +- clocks: Input clock used to derive the sample clock. Expected to be the
>> + SoC's APB clock.
>> +- #io-channel-cells: Must be set to <1> to indicate channels are selected
>> + by index.
>> +
>> +Example:
>> + adc@1e6e9000 {
>> + compatible = "aspeed,ast2400-adc";
>> + reg = <0x1e6e9000 0xb0>;
>> + clocks = <&clk_apb>;
>> + #io-channel-cells = <1>;
>> + };
>> --
>> 2.12.2.564.g063fe858b8-goog
>>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-iio" in
> the body of a message to [email protected]
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
On 28/03/17 22:52, Rick Altherr wrote:
> Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
> interrupts are supported by the hardware but are not currently implemented.
>
> Signed-off-by: Rick Altherr <[email protected]>
Two really trivial things inline. I'll fix them whilst applying rather than
having you do a v6 - please do sanity check I haven't messed it up though!
Applied to the togreg branch of iio.git and pushed out as testing for
the autobuilders to play with it.
Thanks,
Jonathan
> ---
>
> Changes in v5:
> - Return EINVAL for unimplemented read/write channel infos.
> - Return EPERM for write attempts to read-only channel infos.
>
> Changes in v4:
> - Avoid copying per-model data to per-instance data
>
> Changes in v3:
> - Drop model numbers from description as same IP is used in every generation
> - Remove unused macros
> - Shorten macro prefix to just ASPEED_
> - Remove extraneous whitespace
> - Rename 2nd argument of ASPEED_CHAN() to clarify purpose
> - Use existing macros in place of magic constants
> - Remove unnecessary logging in failure conditions during probe
> - Disable ADC hardware during remove()
> - Add a NULL terminator to of_match_table
> - Add per-model data to accomodate slight variations (vref, min/max sample rate)
> - Added missing Kconfig depends on COMMON_CLK
>
> Changes in v2:
> - Rewritten as an IIO device
> - Renamed register macros to describe the register's purpose
> - Replaced awkward reading of 16-bit data registers with readw()
> - Added Kconfig dependency on COMPILE_TEST
>
> drivers/iio/adc/Kconfig | 11 ++
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/aspeed_adc.c | 294 +++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 306 insertions(+)
> create mode 100644 drivers/iio/adc/aspeed_adc.c
>
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index 2268a6fb9865..236d05f99e80 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -130,6 +130,17 @@ config AD799X
> To compile this driver as a module, choose M here: the module will be
> called ad799x.
>
> +config ASPEED_ADC
> + tristate "Aspeed ADC"
> + depends on ARCH_ASPEED || COMPILE_TEST
> + depends on COMMON_CLK
> + help
> + If you say yes here you get support for the ADC included in Aspeed
> + BMC SoCs.
> +
> + To compile this driver as a module, choose M here: the module will be
> + called aspeed_adc.
> +
> config AT91_ADC
> tristate "Atmel AT91 ADC"
> depends on ARCH_AT91
> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
> index 73dbe399f894..306f10ffca74 100644
> --- a/drivers/iio/adc/Makefile
> +++ b/drivers/iio/adc/Makefile
> @@ -14,6 +14,7 @@ obj-$(CONFIG_AD7791) += ad7791.o
> obj-$(CONFIG_AD7793) += ad7793.o
> obj-$(CONFIG_AD7887) += ad7887.o
> obj-$(CONFIG_AD799X) += ad799x.o
> +obj-$(CONFIG_ASPEED_ADC) += aspeed_adc.o
> obj-$(CONFIG_AT91_ADC) += at91_adc.o
> obj-$(CONFIG_AT91_SAMA5D2_ADC) += at91-sama5d2_adc.o
> obj-$(CONFIG_AXP288_ADC) += axp288_adc.o
> diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c
> new file mode 100644
> index 000000000000..2283ed202194
> --- /dev/null
> +++ b/drivers/iio/adc/aspeed_adc.c
> @@ -0,0 +1,294 @@
> +/*
> + * Aspeed AST2400/2500 ADC
> + *
> + * Copyright (C) 2017 Google, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + */
> +
> +#include <asm/io.h>
Should be linux/io.h - if this all there is I'll fix it.
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/err.h>
> +#include <linux/errno.h>
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/spinlock.h>
> +#include <linux/types.h>
> +
> +#include <linux/iio/iio.h>
> +#include <linux/iio/driver.h>
> +
> +#define ASPEED_RESOLUTION_BITS 10
> +#define ASPEED_CLOCKS_PER_SAMPLE 12
> +
> +#define ASPEED_REG_ENGINE_CONTROL 0x00
> +#define ASPEED_REG_INTERRUPT_CONTROL 0x04
> +#define ASPEED_REG_VGA_DETECT_CONTROL 0x08
> +#define ASPEED_REG_CLOCK_CONTROL 0x0C
> +#define ASPEED_REG_MAX 0xC0
> +
> +#define ASPEED_OPERATION_MODE_POWER_DOWN (0x0 << 1)
> +#define ASPEED_OPERATION_MODE_STANDBY (0x1 << 1)
> +#define ASPEED_OPERATION_MODE_NORMAL (0x7 << 1)
> +
> +#define ASPEED_ENGINE_ENABLE BIT(0)
> +
> +struct aspeed_adc_model_data {
> + const char *model_name;
> + unsigned int min_sampling_rate; // Hz
> + unsigned int max_sampling_rate; // Hz
> + unsigned int vref_voltage; // mV
> +};
> +
> +struct aspeed_adc_data {
> + struct device *dev;
> + void __iomem *base;
> + spinlock_t clk_lock;
> + struct clk_hw *clk_prescaler;
> + struct clk_hw *clk_scaler;
> +};
> +
> +#define ASPEED_CHAN(_idx, _data_reg_addr) { \
> + .type = IIO_VOLTAGE, \
> + .indexed = 1, \
> + .channel = (_idx), \
> + .address = (_data_reg_addr), \
> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
> + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
> + BIT(IIO_CHAN_INFO_SAMP_FREQ), \
> +}
> +
> +static const struct iio_chan_spec aspeed_adc_iio_channels[] = {
> + ASPEED_CHAN(0, 0x10),
> + ASPEED_CHAN(1, 0x12),
> + ASPEED_CHAN(2, 0x14),
> + ASPEED_CHAN(3, 0x16),
> + ASPEED_CHAN(4, 0x18),
> + ASPEED_CHAN(5, 0x1A),
> + ASPEED_CHAN(6, 0x1C),
> + ASPEED_CHAN(7, 0x1E),
> + ASPEED_CHAN(8, 0x20),
> + ASPEED_CHAN(9, 0x22),
> + ASPEED_CHAN(10, 0x24),
> + ASPEED_CHAN(11, 0x26),
> + ASPEED_CHAN(12, 0x28),
> + ASPEED_CHAN(13, 0x2A),
> + ASPEED_CHAN(14, 0x2C),
> + ASPEED_CHAN(15, 0x2E),
> +};
> +
> +static int aspeed_adc_read_raw(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan,
> + int *val, int *val2, long mask)
> +{
> + struct aspeed_adc_data *data = iio_priv(indio_dev);
> + const struct aspeed_adc_model_data *model_data =
> + of_device_get_match_data(data->dev);
> +
> + switch (mask) {
> + case IIO_CHAN_INFO_RAW:
> + *val = readw(data->base + chan->address);
> + return IIO_VAL_INT;
> +
> + case IIO_CHAN_INFO_SCALE:
> + *val = model_data->vref_voltage;
> + *val2 = ASPEED_RESOLUTION_BITS;
> + return IIO_VAL_FRACTIONAL_LOG2;
> +
> + case IIO_CHAN_INFO_SAMP_FREQ:
> + *val = clk_get_rate(data->clk_scaler->clk) /
> + ASPEED_CLOCKS_PER_SAMPLE;
> + return IIO_VAL_INT;
> +
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static int aspeed_adc_write_raw(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan,
> + int val, int val2, long mask)
> +{
> + struct aspeed_adc_data *data = iio_priv(indio_dev);
> + const struct aspeed_adc_model_data *model_data =
> + of_device_get_match_data(data->dev);
> +
> + switch (mask) {
> + case IIO_CHAN_INFO_SAMP_FREQ:
> + if (val < model_data->min_sampling_rate ||
> + val > model_data->max_sampling_rate)
> + return -EINVAL;
> +
> + clk_set_rate(data->clk_scaler->clk,
> + val * ASPEED_CLOCKS_PER_SAMPLE);
> + return 0;
> +
> + case IIO_CHAN_INFO_SCALE:
> + case IIO_CHAN_INFO_RAW:
> + /*
> + * Technically, these could be written but the only reasons
> + * for doing so seem better handled in userspace. EPERM is
> + * returned to signal this is a policy choice rather than a
> + * hardware limitation.
> + */
> + return -EPERM;
> +
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static int aspeed_adc_reg_access(struct iio_dev *indio_dev,
> + unsigned int reg, unsigned int writeval,
> + unsigned int *readval)
> +{
> + struct aspeed_adc_data *data = iio_priv(indio_dev);
> +
> + if (!readval || reg % 4 || reg > ASPEED_REG_MAX)
> + return -EINVAL;
> +
> + *readval = readl(data->base + reg);
Getting really fussy, but blank line here.
> + return 0;
> +}
> +
> +static const struct iio_info aspeed_adc_iio_info = {
> + .driver_module = THIS_MODULE,
> + .read_raw = aspeed_adc_read_raw,
> + .write_raw = aspeed_adc_write_raw,
> + .debugfs_reg_access = aspeed_adc_reg_access,
> +};
> +
> +static int aspeed_adc_probe(struct platform_device *pdev)
> +{
> + struct iio_dev *indio_dev;
> + struct aspeed_adc_data *data;
> + const struct aspeed_adc_model_data *model_data;
> + struct resource *res;
> + const char *clk_parent_name;
> + int ret;
> + u32 adc_engine_control_reg_val;
> +
> + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*data));
> + if (!indio_dev)
> + return -ENOMEM;
> +
> + data = iio_priv(indio_dev);
> + data->dev = &pdev->dev;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + data->base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(data->base))
> + return PTR_ERR(data->base);
> +
> + /* Register ADC clock prescaler with source specified by device tree. */
> + spin_lock_init(&data->clk_lock);
> + clk_parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0);
> +
> + data->clk_prescaler = clk_hw_register_divider(
> + &pdev->dev, "prescaler", clk_parent_name, 0,
> + data->base + ASPEED_REG_CLOCK_CONTROL,
> + 17, 15, 0, &data->clk_lock);
> + if (IS_ERR(data->clk_prescaler))
> + return PTR_ERR(data->clk_prescaler);
> +
> + /*
> + * Register ADC clock scaler downstream from the prescaler. Allow rate
> + * setting to adjust the prescaler as well.
> + */
> + data->clk_scaler = clk_hw_register_divider(
> + &pdev->dev, "scaler", "prescaler",
> + CLK_SET_RATE_PARENT,
> + data->base + ASPEED_REG_CLOCK_CONTROL,
> + 0, 10, 0, &data->clk_lock);
> + if (IS_ERR(data->clk_scaler)) {
> + ret = PTR_ERR(data->clk_scaler);
> + goto scaler_error;
> + }
> +
> + /* Start all channels in normal mode. */
> + clk_prepare_enable(data->clk_scaler->clk);
> + adc_engine_control_reg_val = GENMASK(31, 16) |
> + ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE;
> + writel(adc_engine_control_reg_val,
> + data->base + ASPEED_REG_ENGINE_CONTROL);
> +
> + model_data = of_device_get_match_data(&pdev->dev);
> + indio_dev->name = model_data->model_name;
> + indio_dev->dev.parent = &pdev->dev;
> + indio_dev->info = &aspeed_adc_iio_info;
> + indio_dev->modes = INDIO_DIRECT_MODE;
> + indio_dev->channels = aspeed_adc_iio_channels;
> + indio_dev->num_channels = ARRAY_SIZE(aspeed_adc_iio_channels);
> +
> + ret = iio_device_register(indio_dev);
> + if (ret)
> + goto iio_register_error;
> +
> + return 0;
> +
> +iio_register_error:
> + writel(ASPEED_OPERATION_MODE_POWER_DOWN,
> + data->base + ASPEED_REG_ENGINE_CONTROL);
> + clk_disable_unprepare(data->clk_scaler->clk);
> + clk_hw_unregister_divider(data->clk_scaler);
> +
> +scaler_error:
> + clk_hw_unregister_divider(data->clk_prescaler);
> + return ret;
> +}
> +
> +static int aspeed_adc_remove(struct platform_device *pdev)
> +{
> + struct iio_dev *indio_dev = platform_get_drvdata(pdev);
> + struct aspeed_adc_data *data = iio_priv(indio_dev);
> +
> + iio_device_unregister(indio_dev);
> + writel(ASPEED_OPERATION_MODE_POWER_DOWN,
> + data->base + ASPEED_REG_ENGINE_CONTROL);
> + clk_disable_unprepare(data->clk_scaler->clk);
> + clk_hw_unregister_divider(data->clk_scaler);
> + clk_hw_unregister_divider(data->clk_prescaler);
> +
> + return 0;
> +}
> +
> +static const struct aspeed_adc_model_data ast2400_model_data = {
> + .model_name = "ast2400-adc",
> + .vref_voltage = 2500, // mV
> + .min_sampling_rate = 10000,
> + .max_sampling_rate = 500000,
> +};
> +
> +static const struct aspeed_adc_model_data ast2500_model_data = {
> + .model_name = "ast2500-adc",
> + .vref_voltage = 1800, // mV
> + .min_sampling_rate = 1,
> + .max_sampling_rate = 1000000,
> +};
> +
> +static const struct of_device_id aspeed_adc_matches[] = {
> + { .compatible = "aspeed,ast2400-adc", .data = &ast2400_model_data },
> + { .compatible = "aspeed,ast2500-adc", .data = &ast2500_model_data },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, aspeed_adc_matches);
> +
> +static struct platform_driver aspeed_adc_driver = {
> + .probe = aspeed_adc_probe,
> + .remove = aspeed_adc_remove,
> + .driver = {
> + .name = KBUILD_MODNAME,
> + .of_match_table = aspeed_adc_matches,
> + }
> +};
> +
> +module_platform_driver(aspeed_adc_driver);
> +
> +MODULE_AUTHOR("Rick Altherr <[email protected]>");
> +MODULE_DESCRIPTION("Aspeed AST2400/2500 ADC Driver");
> +MODULE_LICENSE("GPL");
>
On 31/03/17 21:57, Xo Wang wrote:
> On Tue, Mar 28, 2017 at 7:33 PM, Joel Stanley <[email protected]> wrote:
>> On Wed, Mar 29, 2017 at 8:22 AM, Rick Altherr <[email protected]> wrote:
>>> Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
>>> interrupts are supported by the hardware but are not currently implemented.
>>>
>>> Signed-off-by: Rick Altherr <[email protected]>
>>
>> Reviewed-by: Joel Stanley <[email protected]>
>>
>
> Tested-by: Xo Wang <[email protected]>
>
> Tested on a Zaius OpenPOWER server running a AST2500 BMC alongside configs:
>
> CONFIG_IIO=y
> CONFIG_ASPEED_ADC=y
> CONFIG_SENSORS_IIO_HWMON=y
>
> as well as the appropriate device tree entries.
Thanks Xo and Joel,
Testing and reviewing is sometimes a thankless task so it
is always nice when several people do these for a new driver!
Jonathan
>
>>> ---
>>>
>>> Changes in v5:
>>> - Return EINVAL for unimplemented read/write channel infos.
>>> - Return EPERM for write attempts to read-only channel infos.
>>>
>>> Changes in v4:
>>> - Avoid copying per-model data to per-instance data
>>>
>>> Changes in v3:
>>> - Drop model numbers from description as same IP is used in every generation
>>> - Remove unused macros
>>> - Shorten macro prefix to just ASPEED_
>>> - Remove extraneous whitespace
>>> - Rename 2nd argument of ASPEED_CHAN() to clarify purpose
>>> - Use existing macros in place of magic constants
>>> - Remove unnecessary logging in failure conditions during probe
>>> - Disable ADC hardware during remove()
>>> - Add a NULL terminator to of_match_table
>>> - Add per-model data to accomodate slight variations (vref, min/max sample rate)
>>> - Added missing Kconfig depends on COMMON_CLK
>>>
>>> Changes in v2:
>>> - Rewritten as an IIO device
>>> - Renamed register macros to describe the register's purpose
>>> - Replaced awkward reading of 16-bit data registers with readw()
>>> - Added Kconfig dependency on COMPILE_TEST
>>>
>>> drivers/iio/adc/Kconfig | 11 ++
>>> drivers/iio/adc/Makefile | 1 +
>>> drivers/iio/adc/aspeed_adc.c | 294 +++++++++++++++++++++++++++++++++++++++++++
>>> 3 files changed, 306 insertions(+)
>>> create mode 100644 drivers/iio/adc/aspeed_adc.c
>>>
>>> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
>>> index 2268a6fb9865..236d05f99e80 100644
>>> --- a/drivers/iio/adc/Kconfig
>>> +++ b/drivers/iio/adc/Kconfig
>>> @@ -130,6 +130,17 @@ config AD799X
>>> To compile this driver as a module, choose M here: the module will be
>>> called ad799x.
>>>
>>> +config ASPEED_ADC
>>> + tristate "Aspeed ADC"
>>> + depends on ARCH_ASPEED || COMPILE_TEST
>>> + depends on COMMON_CLK
>>> + help
>>> + If you say yes here you get support for the ADC included in Aspeed
>>> + BMC SoCs.
>>> +
>>> + To compile this driver as a module, choose M here: the module will be
>>> + called aspeed_adc.
>>> +
>>> config AT91_ADC
>>> tristate "Atmel AT91 ADC"
>>> depends on ARCH_AT91
>>> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
>>> index 73dbe399f894..306f10ffca74 100644
>>> --- a/drivers/iio/adc/Makefile
>>> +++ b/drivers/iio/adc/Makefile
>>> @@ -14,6 +14,7 @@ obj-$(CONFIG_AD7791) += ad7791.o
>>> obj-$(CONFIG_AD7793) += ad7793.o
>>> obj-$(CONFIG_AD7887) += ad7887.o
>>> obj-$(CONFIG_AD799X) += ad799x.o
>>> +obj-$(CONFIG_ASPEED_ADC) += aspeed_adc.o
>>> obj-$(CONFIG_AT91_ADC) += at91_adc.o
>>> obj-$(CONFIG_AT91_SAMA5D2_ADC) += at91-sama5d2_adc.o
>>> obj-$(CONFIG_AXP288_ADC) += axp288_adc.o
>>> diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c
>>> new file mode 100644
>>> index 000000000000..2283ed202194
>>> --- /dev/null
>>> +++ b/drivers/iio/adc/aspeed_adc.c
>>> @@ -0,0 +1,294 @@
>>> +/*
>>> + * Aspeed AST2400/2500 ADC
>>> + *
>>> + * Copyright (C) 2017 Google, Inc.
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify it
>>> + * under the terms and conditions of the GNU General Public License,
>>> + * version 2, as published by the Free Software Foundation.
>>> + *
>>> + */
>>> +
>>> +#include <asm/io.h>
>>> +#include <linux/clk.h>
>>> +#include <linux/clk-provider.h>
>>> +#include <linux/err.h>
>>> +#include <linux/errno.h>
>>> +#include <linux/module.h>
>>> +#include <linux/of_platform.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/spinlock.h>
>>> +#include <linux/types.h>
>>> +
>>> +#include <linux/iio/iio.h>
>>> +#include <linux/iio/driver.h>
>>> +
>>> +#define ASPEED_RESOLUTION_BITS 10
>>> +#define ASPEED_CLOCKS_PER_SAMPLE 12
>>> +
>>> +#define ASPEED_REG_ENGINE_CONTROL 0x00
>>> +#define ASPEED_REG_INTERRUPT_CONTROL 0x04
>>> +#define ASPEED_REG_VGA_DETECT_CONTROL 0x08
>>> +#define ASPEED_REG_CLOCK_CONTROL 0x0C
>>> +#define ASPEED_REG_MAX 0xC0
>>> +
>>> +#define ASPEED_OPERATION_MODE_POWER_DOWN (0x0 << 1)
>>> +#define ASPEED_OPERATION_MODE_STANDBY (0x1 << 1)
>>> +#define ASPEED_OPERATION_MODE_NORMAL (0x7 << 1)
>>> +
>>> +#define ASPEED_ENGINE_ENABLE BIT(0)
>>> +
>>> +struct aspeed_adc_model_data {
>>> + const char *model_name;
>>> + unsigned int min_sampling_rate; // Hz
>>> + unsigned int max_sampling_rate; // Hz
>>> + unsigned int vref_voltage; // mV
>>> +};
>>> +
>>> +struct aspeed_adc_data {
>>> + struct device *dev;
>>> + void __iomem *base;
>>> + spinlock_t clk_lock;
>>> + struct clk_hw *clk_prescaler;
>>> + struct clk_hw *clk_scaler;
>>> +};
>>> +
>>> +#define ASPEED_CHAN(_idx, _data_reg_addr) { \
>>> + .type = IIO_VOLTAGE, \
>>> + .indexed = 1, \
>>> + .channel = (_idx), \
>>> + .address = (_data_reg_addr), \
>>> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
>>> + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
>>> + BIT(IIO_CHAN_INFO_SAMP_FREQ), \
>>> +}
>>> +
>>> +static const struct iio_chan_spec aspeed_adc_iio_channels[] = {
>>> + ASPEED_CHAN(0, 0x10),
>>> + ASPEED_CHAN(1, 0x12),
>>> + ASPEED_CHAN(2, 0x14),
>>> + ASPEED_CHAN(3, 0x16),
>>> + ASPEED_CHAN(4, 0x18),
>>> + ASPEED_CHAN(5, 0x1A),
>>> + ASPEED_CHAN(6, 0x1C),
>>> + ASPEED_CHAN(7, 0x1E),
>>> + ASPEED_CHAN(8, 0x20),
>>> + ASPEED_CHAN(9, 0x22),
>>> + ASPEED_CHAN(10, 0x24),
>>> + ASPEED_CHAN(11, 0x26),
>>> + ASPEED_CHAN(12, 0x28),
>>> + ASPEED_CHAN(13, 0x2A),
>>> + ASPEED_CHAN(14, 0x2C),
>>> + ASPEED_CHAN(15, 0x2E),
>>> +};
>>> +
>>> +static int aspeed_adc_read_raw(struct iio_dev *indio_dev,
>>> + struct iio_chan_spec const *chan,
>>> + int *val, int *val2, long mask)
>>> +{
>>> + struct aspeed_adc_data *data = iio_priv(indio_dev);
>>> + const struct aspeed_adc_model_data *model_data =
>>> + of_device_get_match_data(data->dev);
>>> +
>>> + switch (mask) {
>>> + case IIO_CHAN_INFO_RAW:
>>> + *val = readw(data->base + chan->address);
>>> + return IIO_VAL_INT;
>>> +
>>> + case IIO_CHAN_INFO_SCALE:
>>> + *val = model_data->vref_voltage;
>>> + *val2 = ASPEED_RESOLUTION_BITS;
>>> + return IIO_VAL_FRACTIONAL_LOG2;
>>> +
>>> + case IIO_CHAN_INFO_SAMP_FREQ:
>>> + *val = clk_get_rate(data->clk_scaler->clk) /
>>> + ASPEED_CLOCKS_PER_SAMPLE;
>>> + return IIO_VAL_INT;
>>> +
>>> + default:
>>> + return -EINVAL;
>>> + }
>>> +}
>>> +
>>> +static int aspeed_adc_write_raw(struct iio_dev *indio_dev,
>>> + struct iio_chan_spec const *chan,
>>> + int val, int val2, long mask)
>>> +{
>>> + struct aspeed_adc_data *data = iio_priv(indio_dev);
>>> + const struct aspeed_adc_model_data *model_data =
>>> + of_device_get_match_data(data->dev);
>>> +
>>> + switch (mask) {
>>> + case IIO_CHAN_INFO_SAMP_FREQ:
>>> + if (val < model_data->min_sampling_rate ||
>>> + val > model_data->max_sampling_rate)
>>> + return -EINVAL;
>>> +
>>> + clk_set_rate(data->clk_scaler->clk,
>>> + val * ASPEED_CLOCKS_PER_SAMPLE);
>>> + return 0;
>>> +
>>> + case IIO_CHAN_INFO_SCALE:
>>> + case IIO_CHAN_INFO_RAW:
>>> + /*
>>> + * Technically, these could be written but the only reasons
>>> + * for doing so seem better handled in userspace. EPERM is
>>> + * returned to signal this is a policy choice rather than a
>>> + * hardware limitation.
>>> + */
>>> + return -EPERM;
>>> +
>>> + default:
>>> + return -EINVAL;
>>> + }
>>> +}
>>> +
>>> +static int aspeed_adc_reg_access(struct iio_dev *indio_dev,
>>> + unsigned int reg, unsigned int writeval,
>>> + unsigned int *readval)
>>> +{
>>> + struct aspeed_adc_data *data = iio_priv(indio_dev);
>>> +
>>> + if (!readval || reg % 4 || reg > ASPEED_REG_MAX)
>>> + return -EINVAL;
>>> +
>>> + *readval = readl(data->base + reg);
>>> + return 0;
>>> +}
>>> +
>>> +static const struct iio_info aspeed_adc_iio_info = {
>>> + .driver_module = THIS_MODULE,
>>> + .read_raw = aspeed_adc_read_raw,
>>> + .write_raw = aspeed_adc_write_raw,
>>> + .debugfs_reg_access = aspeed_adc_reg_access,
>>> +};
>>> +
>>> +static int aspeed_adc_probe(struct platform_device *pdev)
>>> +{
>>> + struct iio_dev *indio_dev;
>>> + struct aspeed_adc_data *data;
>>> + const struct aspeed_adc_model_data *model_data;
>>> + struct resource *res;
>>> + const char *clk_parent_name;
>>> + int ret;
>>> + u32 adc_engine_control_reg_val;
>>> +
>>> + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*data));
>>> + if (!indio_dev)
>>> + return -ENOMEM;
>>> +
>>> + data = iio_priv(indio_dev);
>>> + data->dev = &pdev->dev;
>>> +
>>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> + data->base = devm_ioremap_resource(&pdev->dev, res);
>>> + if (IS_ERR(data->base))
>>> + return PTR_ERR(data->base);
>>> +
>>> + /* Register ADC clock prescaler with source specified by device tree. */
>>> + spin_lock_init(&data->clk_lock);
>>> + clk_parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0);
>>> +
>>> + data->clk_prescaler = clk_hw_register_divider(
>>> + &pdev->dev, "prescaler", clk_parent_name, 0,
>>> + data->base + ASPEED_REG_CLOCK_CONTROL,
>>> + 17, 15, 0, &data->clk_lock);
>>> + if (IS_ERR(data->clk_prescaler))
>>> + return PTR_ERR(data->clk_prescaler);
>>> +
>>> + /*
>>> + * Register ADC clock scaler downstream from the prescaler. Allow rate
>>> + * setting to adjust the prescaler as well.
>>> + */
>>> + data->clk_scaler = clk_hw_register_divider(
>>> + &pdev->dev, "scaler", "prescaler",
>>> + CLK_SET_RATE_PARENT,
>>> + data->base + ASPEED_REG_CLOCK_CONTROL,
>>> + 0, 10, 0, &data->clk_lock);
>>> + if (IS_ERR(data->clk_scaler)) {
>>> + ret = PTR_ERR(data->clk_scaler);
>>> + goto scaler_error;
>>> + }
>>> +
>>> + /* Start all channels in normal mode. */
>>> + clk_prepare_enable(data->clk_scaler->clk);
>>> + adc_engine_control_reg_val = GENMASK(31, 16) |
>>> + ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE;
>>> + writel(adc_engine_control_reg_val,
>>> + data->base + ASPEED_REG_ENGINE_CONTROL);
>>> +
>>> + model_data = of_device_get_match_data(&pdev->dev);
>>> + indio_dev->name = model_data->model_name;
>>> + indio_dev->dev.parent = &pdev->dev;
>>> + indio_dev->info = &aspeed_adc_iio_info;
>>> + indio_dev->modes = INDIO_DIRECT_MODE;
>>> + indio_dev->channels = aspeed_adc_iio_channels;
>>> + indio_dev->num_channels = ARRAY_SIZE(aspeed_adc_iio_channels);
>>> +
>>> + ret = iio_device_register(indio_dev);
>>> + if (ret)
>>> + goto iio_register_error;
>>> +
>>> + return 0;
>>> +
>>> +iio_register_error:
>>> + writel(ASPEED_OPERATION_MODE_POWER_DOWN,
>>> + data->base + ASPEED_REG_ENGINE_CONTROL);
>>> + clk_disable_unprepare(data->clk_scaler->clk);
>>> + clk_hw_unregister_divider(data->clk_scaler);
>>> +
>>> +scaler_error:
>>> + clk_hw_unregister_divider(data->clk_prescaler);
>>> + return ret;
>>> +}
>>> +
>>> +static int aspeed_adc_remove(struct platform_device *pdev)
>>> +{
>>> + struct iio_dev *indio_dev = platform_get_drvdata(pdev);
>>> + struct aspeed_adc_data *data = iio_priv(indio_dev);
>>> +
>>> + iio_device_unregister(indio_dev);
>>> + writel(ASPEED_OPERATION_MODE_POWER_DOWN,
>>> + data->base + ASPEED_REG_ENGINE_CONTROL);
>>> + clk_disable_unprepare(data->clk_scaler->clk);
>>> + clk_hw_unregister_divider(data->clk_scaler);
>>> + clk_hw_unregister_divider(data->clk_prescaler);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static const struct aspeed_adc_model_data ast2400_model_data = {
>>> + .model_name = "ast2400-adc",
>>> + .vref_voltage = 2500, // mV
>>> + .min_sampling_rate = 10000,
>>> + .max_sampling_rate = 500000,
>>> +};
>>> +
>>> +static const struct aspeed_adc_model_data ast2500_model_data = {
>>> + .model_name = "ast2500-adc",
>>> + .vref_voltage = 1800, // mV
>>> + .min_sampling_rate = 1,
>>> + .max_sampling_rate = 1000000,
>>> +};
>>> +
>>> +static const struct of_device_id aspeed_adc_matches[] = {
>>> + { .compatible = "aspeed,ast2400-adc", .data = &ast2400_model_data },
>>> + { .compatible = "aspeed,ast2500-adc", .data = &ast2500_model_data },
>>> + {},
>>> +};
>>> +MODULE_DEVICE_TABLE(of, aspeed_adc_matches);
>>> +
>>> +static struct platform_driver aspeed_adc_driver = {
>>> + .probe = aspeed_adc_probe,
>>> + .remove = aspeed_adc_remove,
>>> + .driver = {
>>> + .name = KBUILD_MODNAME,
>>> + .of_match_table = aspeed_adc_matches,
>>> + }
>>> +};
>>> +
>>> +module_platform_driver(aspeed_adc_driver);
>>> +
>>> +MODULE_AUTHOR("Rick Altherr <[email protected]>");
>>> +MODULE_DESCRIPTION("Aspeed AST2400/2500 ADC Driver");
>>> +MODULE_LICENSE("GPL");
>>> --
>>> 2.12.2.564.g063fe858b8-goog
>>>
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>
On 04/01, Jonathan Cameron wrote:
> On 28/03/17 22:52, Rick Altherr wrote:
> > Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
> > interrupts are supported by the hardware but are not currently implemented.
> >
> > Signed-off-by: Rick Altherr <[email protected]>
> Two really trivial things inline. I'll fix them whilst applying rather than
> having you do a v6 - please do sanity check I haven't messed it up though!
>
> Applied to the togreg branch of iio.git and pushed out as testing for
> the autobuilders to play with it.
>
Oh I was too late. Blame work. Anyway, I made some comments on
v4. If they're fixed in a later patch or discussed on list that's
fine. No worries on my end.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 05/04/17 22:50, Stephen Boyd wrote:
> On 04/01, Jonathan Cameron wrote:
>> On 28/03/17 22:52, Rick Altherr wrote:
>>> Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
>>> interrupts are supported by the hardware but are not currently implemented.
>>>
>>> Signed-off-by: Rick Altherr <[email protected]>
>> Two really trivial things inline. I'll fix them whilst applying rather than
>> having you do a v6 - please do sanity check I haven't messed it up though!
>>
>> Applied to the togreg branch of iio.git and pushed out as testing for
>> the autobuilders to play with it.
>>
>
> Oh I was too late. Blame work. Anyway, I made some comments on
> v4. If they're fixed in a later patch or discussed on list that's
> fine. No worries on my end.
>
Oops. I went a bit quick on this one I guess.
Anyhow, from a quick read of your comments I'm not sure if any of
them are such that we should revert. Perhaps we Rick can prepare
a follow up patch covering them? I got a little lost so am not
sure but if there is anything effecting bindings Rick, please
get this through asap or let me know if we need to revert for now.
Even if it is a case of adding a bit of binding and following up
with the code using it a bit later.
I'd asked for input on the clock stuff then forgot all about it on
the later version. Sorry about that!
Jonathan
On 10 April 2017 17:34:33 BST, Rick Altherr <[email protected]> wrote:
>I don't believe there are any bindings changes or a need to revert.
>Stephen's suggested changes are small improvements that make the driver
>suitable for non-DT platforms (not an issue anytime soon) and help with
>a
>planned refactor of the clk_hw structure. I'll send out follow-up
>changes
>when Stephen and I have reached consensus on how to resolve the latter
>improvement.
Cool. Thanks
Jonathan
>
>On Sat, Apr 8, 2017 at 9:15 AM, Jonathan Cameron <[email protected]>
>wrote:
>
>> On 05/04/17 22:50, Stephen Boyd wrote:
>> > On 04/01, Jonathan Cameron wrote:
>> >> On 28/03/17 22:52, Rick Altherr wrote:
>> >>> Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high
>> threshold
>> >>> interrupts are supported by the hardware but are not currently
>> implemented.
>> >>>
>> >>> Signed-off-by: Rick Altherr <[email protected]>
>> >> Two really trivial things inline. I'll fix them whilst applying
>rather
>> than
>> >> having you do a v6 - please do sanity check I haven't messed it up
>> though!
>> >>
>> >> Applied to the togreg branch of iio.git and pushed out as testing
>for
>> >> the autobuilders to play with it.
>> >>
>> >
>> > Oh I was too late. Blame work. Anyway, I made some comments on
>> > v4. If they're fixed in a later patch or discussed on list that's
>> > fine. No worries on my end.
>> >
>> Oops. I went a bit quick on this one I guess.
>>
>> Anyhow, from a quick read of your comments I'm not sure if any of
>> them are such that we should revert. Perhaps we Rick can prepare
>> a follow up patch covering them? I got a little lost so am not
>> sure but if there is anything effecting bindings Rick, please
>> get this through asap or let me know if we need to revert for now.
>> Even if it is a case of adding a bit of binding and following up
>> with the code using it a bit later.
>>
>> I'd asked for input on the clock stuff then forgot all about it on
>> the later version. Sorry about that!
>>
>> Jonathan
>>
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