This adds support for driving the TPM on Socionext SynQuacer platforms
using the existing driver for a memory mapped TIS frame.
v2:
- don't use read/write_bytes() to implement read/write16/32 since that uses
the wrong address
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Ard Biesheuvel (2):
dt-bindings: tpm-tis-mmio: add compatible string for SynQuacer TPM
tpm: tis: add support for MMIO TPM on SynQuacer
Documentation/devicetree/bindings/security/tpm/tpm_tis_mmio.txt | 1 +
drivers/char/tpm/tpm_tis.c | 50 +++++++++++++++++++-
2 files changed, 49 insertions(+), 2 deletions(-)
--
2.20.1
When fitted, the SynQuacer platform exposes its SPI TPM via a MMIO
window that is backed by the SPI command sequencer in the SPI bus
controller. This arrangement has the limitation that only byte size
accesses are supported, and so we'll need to provide a separate set
of read and write accessors that take this into account.
Signed-off-by: Ard Biesheuvel <[email protected]>
---
drivers/char/tpm/tpm_tis.c | 50 +++++++++++++++++++-
1 file changed, 48 insertions(+), 2 deletions(-)
diff --git a/drivers/char/tpm/tpm_tis.c b/drivers/char/tpm/tpm_tis.c
index e7df342a317d..2466295fcfe8 100644
--- a/drivers/char/tpm/tpm_tis.c
+++ b/drivers/char/tpm/tpm_tis.c
@@ -32,6 +32,7 @@
struct tpm_info {
struct resource res;
+ const struct tpm_tis_phy_ops *ops;
/* irq > 0 means: use irq $irq;
* irq = 0 means: autoprobe for an irq;
* irq = -1 means: no irq support
@@ -186,6 +187,48 @@ static const struct tpm_tis_phy_ops tpm_tcg = {
.write32 = tpm_tcg_write32,
};
+static int tpm_tcg_read16_bw(struct tpm_tis_data *data, u32 addr, u16 *result)
+{
+ struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);
+
+ *result = (ioread8(phy->iobase + addr)) |
+ (ioread8(phy->iobase + addr + 1) << 8);
+
+ return 0;
+}
+
+static int tpm_tcg_read32_bw(struct tpm_tis_data *data, u32 addr, u32 *result)
+{
+ struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);
+
+ *result = (ioread8(phy->iobase + addr)) |
+ (ioread8(phy->iobase + addr + 1) << 8) |
+ (ioread8(phy->iobase + addr + 2) << 16) |
+ (ioread8(phy->iobase + addr + 3) << 24);
+
+ return 0;
+}
+
+static int tpm_tcg_write32_bw(struct tpm_tis_data *data, u32 addr, u32 value)
+{
+ struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);
+
+ iowrite8(value, phy->iobase + addr);
+ iowrite8(value >> 8, phy->iobase + addr + 1);
+ iowrite8(value >> 16, phy->iobase + addr + 2);
+ iowrite8(value >> 24, phy->iobase + addr + 3);
+
+ return 0;
+}
+
+static const struct tpm_tis_phy_ops tpm_tcg_bw = {
+ .read_bytes = tpm_tcg_read_bytes,
+ .write_bytes = tpm_tcg_write_bytes,
+ .read16 = tpm_tcg_read16_bw,
+ .read32 = tpm_tcg_read32_bw,
+ .write32 = tpm_tcg_write32_bw,
+};
+
static int tpm_tis_init(struct device *dev, struct tpm_info *tpm_info)
{
struct tpm_tis_tcg_phy *phy;
@@ -210,7 +253,7 @@ static int tpm_tis_init(struct device *dev, struct tpm_info *tpm_info)
if (itpm || is_itpm(ACPI_COMPANION(dev)))
phy->priv.flags |= TPM_TIS_ITPM_WORKAROUND;
- return tpm_tis_core_init(dev, &phy->priv, irq, &tpm_tcg,
+ return tpm_tis_core_init(dev, &phy->priv, irq, tpm_info->ops,
ACPI_HANDLE(dev));
}
@@ -219,7 +262,7 @@ static SIMPLE_DEV_PM_OPS(tpm_tis_pm, tpm_pm_suspend, tpm_tis_resume);
static int tpm_tis_pnp_init(struct pnp_dev *pnp_dev,
const struct pnp_device_id *pnp_id)
{
- struct tpm_info tpm_info = {};
+ struct tpm_info tpm_info = { .ops = &tpm_tcg };
struct resource *res;
res = pnp_get_resource(pnp_dev, IORESOURCE_MEM, 0);
@@ -295,6 +338,8 @@ static int tpm_tis_plat_probe(struct platform_device *pdev)
tpm_info.irq = 0;
}
+ tpm_info.ops = of_device_get_match_data(&pdev->dev) ?: &tpm_tcg;
+
return tpm_tis_init(&pdev->dev, &tpm_info);
}
@@ -311,6 +356,7 @@ static int tpm_tis_plat_remove(struct platform_device *pdev)
#ifdef CONFIG_OF
static const struct of_device_id tis_of_platform_match[] = {
{.compatible = "tcg,tpm-tis-mmio"},
+ {.compatible = "socionext,synquacer-tpm-mmio", .data = &tpm_tcg_bw},
{},
};
MODULE_DEVICE_TABLE(of, tis_of_platform_match);
--
2.20.1
Add a compatible string for the SynQuacer TPM to the binding for a
TPM exposed via a memory mapped TIS frame. The MMIO window behaves
slightly differently on this hardware, so it requires its own
identifier.
Cc: Rob Herring <[email protected]>
Signed-off-by: Ard Biesheuvel <[email protected]>
---
Documentation/devicetree/bindings/security/tpm/tpm_tis_mmio.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/security/tpm/tpm_tis_mmio.txt b/Documentation/devicetree/bindings/security/tpm/tpm_tis_mmio.txt
index 7c6304426da1..b604c8688dc8 100644
--- a/Documentation/devicetree/bindings/security/tpm/tpm_tis_mmio.txt
+++ b/Documentation/devicetree/bindings/security/tpm/tpm_tis_mmio.txt
@@ -12,6 +12,7 @@ Required properties:
- compatible: should contain a string below for the chip, followed by
"tcg,tpm-tis-mmio". Valid chip strings are:
* "atmel,at97sc3204"
+ * "socionext,synquacer-tpm-mmio"
- reg: The location of the MMIO registers, should be at least 0x5000 bytes
- interrupts: An optional interrupt indicating command completion.
--
2.20.1
On Tue, 14 Jan 2020 15:16:46 +0100, Ard Biesheuvel wrote:
> Add a compatible string for the SynQuacer TPM to the binding for a
> TPM exposed via a memory mapped TIS frame. The MMIO window behaves
> slightly differently on this hardware, so it requires its own
> identifier.
>
> Cc: Rob Herring <[email protected]>
> Signed-off-by: Ard Biesheuvel <[email protected]>
> ---
> Documentation/devicetree/bindings/security/tpm/tpm_tis_mmio.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <[email protected]>
On Thu, 23 Jan 2020 at 13:22, Jarkko Sakkinen
<[email protected]> wrote:
>
> On Tue, 2020-01-14 at 15:16 +0100, Ard Biesheuvel wrote:
> > Add a compatible string for the SynQuacer TPM to the binding for a
> > TPM exposed via a memory mapped TIS frame. The MMIO window behaves
> > slightly differently on this hardware, so it requires its own
> > identifier.
> >
> > Cc: Rob Herring <[email protected]>
> > Signed-off-by: Ard Biesheuvel <[email protected]>
> > ---
> > Documentation/devicetree/bindings/security/tpm/tpm_tis_mmio.txt | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/Documentation/devicetree/bindings/security/tpm/tpm_tis_mmio.txt b/Documentation/devicetree/bindings/security/tpm/tpm_tis_mmio.txt
> > index 7c6304426da1..b604c8688dc8 100644
> > --- a/Documentation/devicetree/bindings/security/tpm/tpm_tis_mmio.txt
> > +++ b/Documentation/devicetree/bindings/security/tpm/tpm_tis_mmio.txt
> > @@ -12,6 +12,7 @@ Required properties:
> > - compatible: should contain a string below for the chip, followed by
> > "tcg,tpm-tis-mmio". Valid chip strings are:
> > * "atmel,at97sc3204"
> > + * "socionext,synquacer-tpm-mmio"
> > - reg: The location of the MMIO registers, should be at least 0x5000 bytes
> > - interrupts: An optional interrupt indicating command completion.
> >
>
> Acked-by: Jarkko Sakkinen <[email protected]>
>
> Someone else needs to give reviewed-by as I am not expert on DT bindings.
>
Cheers Jarko.
Rob's ack should be sufficient for this to go via another tree.
However, I am still waiting to hear back from Masahisa to confirm that
the SPI command sequencer approach works 100% on this hardware, so
shall we park these patches for the time being?
Thanks,
Ard.
On Tue, 2020-01-14 at 15:16 +0100, Ard Biesheuvel wrote:
> Add a compatible string for the SynQuacer TPM to the binding for a
> TPM exposed via a memory mapped TIS frame. The MMIO window behaves
> slightly differently on this hardware, so it requires its own
> identifier.
>
> Cc: Rob Herring <[email protected]>
> Signed-off-by: Ard Biesheuvel <[email protected]>
> ---
> Documentation/devicetree/bindings/security/tpm/tpm_tis_mmio.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/security/tpm/tpm_tis_mmio.txt b/Documentation/devicetree/bindings/security/tpm/tpm_tis_mmio.txt
> index 7c6304426da1..b604c8688dc8 100644
> --- a/Documentation/devicetree/bindings/security/tpm/tpm_tis_mmio.txt
> +++ b/Documentation/devicetree/bindings/security/tpm/tpm_tis_mmio.txt
> @@ -12,6 +12,7 @@ Required properties:
> - compatible: should contain a string below for the chip, followed by
> "tcg,tpm-tis-mmio". Valid chip strings are:
> * "atmel,at97sc3204"
> + * "socionext,synquacer-tpm-mmio"
> - reg: The location of the MMIO registers, should be at least 0x5000 bytes
> - interrupts: An optional interrupt indicating command completion.
>
Acked-by: Jarkko Sakkinen <[email protected]>
Someone else needs to give reviewed-by as I am not expert on DT bindings.
/Jarkko
On Tue, 2020-01-14 at 15:16 +0100, Ard Biesheuvel wrote:
> When fitted, the SynQuacer platform exposes its SPI TPM via a MMIO
> window that is backed by the SPI command sequencer in the SPI bus
> controller. This arrangement has the limitation that only byte size
> accesses are supported, and so we'll need to provide a separate set
> of read and write accessors that take this into account.
What is SynQuacer platform?
I'm also missing a resolution why tpm_tis.c is extended to handle both
and not add tpm_tis_something.c instead. It does not follow the pattern
we have in place (e.g. look up tpm_tis_spi.c).
/Jarkko
On Thu, 23 Jan 2020 at 13:27, Jarkko Sakkinen
<[email protected]> wrote:
>
> On Tue, 2020-01-14 at 15:16 +0100, Ard Biesheuvel wrote:
> > When fitted, the SynQuacer platform exposes its SPI TPM via a MMIO
> > window that is backed by the SPI command sequencer in the SPI bus
> > controller. This arrangement has the limitation that only byte size
> > accesses are supported, and so we'll need to provide a separate set
> > of read and write accessors that take this into account.
>
> What is SynQuacer platform?
>
It is an arm64 SoC manufactured by Socionext.
> I'm also missing a resolution why tpm_tis.c is extended to handle both
> and not add tpm_tis_something.c instead. It does not follow the pattern
> we have in place (e.g. look up tpm_tis_spi.c).
>
We could easily do that instead, if preferred. It's just that it would
duplicate a bit of code.
On Thu, 2020-01-23 at 13:29 +0100, Ard Biesheuvel wrote:
> On Thu, 23 Jan 2020 at 13:27, Jarkko Sakkinen
> <[email protected]> wrote:
> > On Tue, 2020-01-14 at 15:16 +0100, Ard Biesheuvel wrote:
> > > When fitted, the SynQuacer platform exposes its SPI TPM via a MMIO
> > > window that is backed by the SPI command sequencer in the SPI bus
> > > controller. This arrangement has the limitation that only byte size
> > > accesses are supported, and so we'll need to provide a separate set
> > > of read and write accessors that take this into account.
> >
> > What is SynQuacer platform?
> >
>
> It is an arm64 SoC manufactured by Socionext.
>
> > I'm also missing a resolution why tpm_tis.c is extended to handle both
> > and not add tpm_tis_something.c instead. It does not follow the pattern
> > we have in place (e.g. look up tpm_tis_spi.c).
> >
>
> We could easily do that instead, if preferred. It's just that it would
> duplicate a bit of code.
I'm fine with that. Overally I think it is cleaner flow.
/Jarkko