2023-07-04 18:50:04

by Marco Felsch

[permalink] [raw]
Subject: [PATCH 1/3] dt-bindings: arm: fsl: fix DEBIX binding

The current imx8mp-debix-model-a.dts uses all three compatibles. Fix the
corresponding bindings by adding an own entry for it.

Signed-off-by: Marco Felsch <[email protected]>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 15d4110840654..d9e763ef932e5 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1019,8 +1019,6 @@ properties:
- dmo,imx8mp-data-modul-edm-sbc # i.MX8MP eDM SBC
- fsl,imx8mp-evk # i.MX8MP EVK Board
- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
- - polyhex,imx8mp-debix # Polyhex Debix boards
- - polyhex,imx8mp-debix-model-a # Polyhex Debix Model A Board
- toradex,verdin-imx8mp # Verdin iMX8M Plus Modules
- toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT
- toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules
@@ -1054,6 +1052,13 @@ properties:
- const: phytec,imx8mp-phycore-som # phyCORE-i.MX8MP SoM
- const: fsl,imx8mp

+ - description: Polyhex DEBIX i.MX8MP based SBCs
+ items:
+ - enum:
+ - polyhex,imx8mp-debix-model-a # Polyhex Debix Model A Board
+ - const: polyhex,imx8mp-debix # Polyhex Debix boards
+ - const: fsl,imx8mp
+
- description: Toradex Boards with Verdin iMX8M Plus Modules
items:
- enum:
--
2.39.2



2023-07-04 18:50:42

by Marco Felsch

[permalink] [raw]
Subject: [PATCH 2/3] dt-bindings: arm: Add Polyhex DEBIX SOM A based boards

Add devicetree bindings for i.MX8MP based DEBIX SOM A and SOM A I/O
baseboard:
- https://debix.io/hardware/debix-som-a.html
- https://debix.io/hardware/debix-som-a-io-board.html

Signed-off-by: Marco Felsch <[email protected]>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 8 ++++++++
1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index d9e763ef932e5..6240485ba13b2 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1059,6 +1059,14 @@ properties:
- const: polyhex,imx8mp-debix # Polyhex Debix boards
- const: fsl,imx8mp

+ - description: Polyhex DEBIX i.MX8MP SOM A based boards
+ items:
+ - enum:
+ - polyhex,imx8mp-debix-som-a-bmb-08 # Polyhex Debix SOM A on SOM A I/O board
+ - const: polyhex,imx8mp-debix-som-a # Polyhex Debix SOM A
+ - const: polyhex,imx8mp-debix # Polyhex Debix boards
+ - const: fsl,imx8mp
+
- description: Toradex Boards with Verdin iMX8M Plus Modules
items:
- enum:
--
2.39.2


2023-07-04 18:59:54

by Marco Felsch

[permalink] [raw]
Subject: [PATCH 3/3] arm64: dts: freescale: Add DEBIX SOM A and SOM A I/O Board support

Add support for the Debix SOM A + SOM A I/O board. The commit enables
only the basic features like:
- 2x UART
- 2x Network
- eMMC/µSD
- CAN
- QSPI
- USB Host / Device

Signed-off-by: Marco Felsch <[email protected]>
---

Hi,

the required patchset for the onboard usb hub is here:
https://lore.kernel.org/all/[email protected]/

arch/arm64/boot/dts/freescale/Makefile | 1 +
.../freescale/imx8mp-debix-som-a-bmb-08.dts | 476 ++++++++++++++++++
.../dts/freescale/imx8mp-debix-som-a.dtsi | 269 ++++++++++
3 files changed, 746 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index ef7d17aef58f0..ca7c9595e6ffa 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -91,6 +91,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-som-a-bmb-08.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts
new file mode 100644
index 0000000000000..1380a9d3dc8eb
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts
@@ -0,0 +1,476 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ * Copyright (C) 2023 Pengutronix, Marco Felsch <[email protected]>
+ */
+
+/dts-v1/;
+
+#include "imx8mp-debix-som-a.dtsi"
+
+/ {
+ model = "Polyhex i.MX8MPlus Debix SOM A on BMB-08";
+ compatible = "polyhex,imx8mp-debix-som-a-bmb-08", "polyhex,imx8mp-debix-som-a",
+ "polyhex,imx8mp-debix", "fsl,imx8mp";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ regulator-baseboard-vdd3v3 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "BB_VDD3V3";
+ gpio = <&expander0 10 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_baseboard_vdd5v0: regulator-baseboard-vdd5v0 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "BB_VDD5V";
+ gpio = <&expander0 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ regulator-som-vdd1v8 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "SOM_VDD1V8_SW";
+ gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ regulator-som-vdd3v3 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "SOM_VDD3V3_SW";
+ gpio = <&expander0 11 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ regulator-vbus-usb20 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "USB20_5V";
+ gpio = <&expander1 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ vin-supply = <&reg_baseboard_vdd5v0>;
+ };
+
+ regulator-vbus-usb30 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "USB30_5V";
+ gpio = <&expander1 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ vin-supply = <&reg_baseboard_vdd5v0>;
+ };
+
+ reg_vdd5v0: regulator-vdd5v0 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "VDD_5V";
+ gpio = <&expander0 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&eqos {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethphy0>;
+ snps,reset-gpio = <&gpio4 18 GPIO_ACTIVE_LOW>;
+ snps,reset-delays-us = <10 20 200000>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ qca,disable-smarteee;
+ vddio-supply = <&vddio_phy0>;
+
+ vddio_phy0: vddio-phy0-regulator {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ };
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&ethphy1>;
+ fsl,magic-packet;
+ phy-reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <10>;
+ phy-reset-post-delay = <150>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ qca,disable-smarteee;
+ vddio-supply = <&vddio_phy1>;
+
+ vddio_phy1: vddio-phy1-regulator {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ };
+ };
+};
+
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ xceiver-supply = <&reg_vdd5v0>;
+ status = "okay";
+};
+
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ xceiver-supply = <&reg_vdd5v0>;
+ status = "okay";
+};
+
+&flexspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi0>;
+ status = "okay";
+
+ flash: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <80000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
+
+&i2c4 {
+ expander0: gpio@20 {
+ compatible = "nxp,pca9535";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <0x02>;
+ };
+
+ expander1: gpio@23 {
+ compatible = "nxp,pca9535";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <0x02>;
+
+ /*
+ * Since USB1 is binded to peripheral mode we need to ensure
+ * that VBUS is turned off.
+ */
+ usb30-otg-hog {
+ gpio-hog;
+ gpios = <13 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "USB30_OTG_EN";
+ };
+ };
+
+ eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <16>;
+ };
+
+ rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rtc>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
+ #clock-cells = <0>;
+ };
+};
+
+&snvs_pwrkey {
+ status = "okay";
+};
+
+/* Debug */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usb3_0 {
+ status = "okay";
+};
+
+&usb3_1 {
+ status = "okay";
+};
+
+&usb_dwc3_0 {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+ dr_mode = "host";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ /* 2.x hub on port 1 */
+ usb_hub_2_x: hub@1 {
+ compatible = "usb5e3,610";
+ reg = <1>;
+ reset-gpios = <&expander1 9 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&reg_vdd5v0>;
+ peer-hub = <&usb_hub_3_x>;
+ };
+
+ /* 3.x hub on port 2 */
+ usb_hub_3_x: hub@2 {
+ compatible = "usb5e3,620";
+ reg = <2>;
+ reset-gpios = <&expander1 9 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&reg_vdd5v0>;
+ peer-hub = <&usb_hub_2_x>;
+ };
+};
+
+&usb3_phy0 {
+ status = "okay";
+};
+
+&usb3_phy1 {
+ status = "okay";
+};
+
+/* µSD Card */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ vmmc-supply = <&reg_usdhc2_vmmc>;
+ bus-width = <4>;
+ disable-wp;
+ no-sdio;
+ no-mmc;
+
+ assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
+ assigned-clock-rates = <400000000>;
+
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
+
+ MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x1f
+ MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19
+ >;
+ };
+
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
+ MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
+ MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
+ MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
+ MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
+ MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
+ MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
+ MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
+ MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
+ MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
+ MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
+ MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
+ MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
+ MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
+ MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1f
+ MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154
+ MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
+ MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
+ >;
+ };
+
+ pinctrl_flexspi0: flexspi0grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
+ MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
+ MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
+ MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
+ MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
+ MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_rtc: rtcgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x140
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f
+ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49
+ MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
+ MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
+ >;
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi
new file mode 100644
index 0000000000000..151a3ee0d02f7
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi
@@ -0,0 +1,269 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ * Copyright (C) 2023 Pengutronix, Marco Felsch <[email protected]>
+ */
+
+#include "imx8mp.dtsi"
+
+/ {
+ model = "Polyhex i.MX8MPlus Debix SOM A";
+ compatible = "polyhex,imx8mp-debix-som-a", "polyhex,imx8mp-debix", "fsl,imx8mp";
+};
+
+&A53_0 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_1 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_2 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_3 {
+ cpu-supply = <&buck2>;
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pmic@25 {
+ compatible = "nxp,pca9450c";
+ reg = <0x25>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 GPIO_ACTIVE_LOW>;
+
+ regulators {
+ buck1: BUCK1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck2: BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ nxp,dvs-run-voltage = <950000>;
+ nxp,dvs-standby-voltage = <850000>;
+ };
+
+ buck4: BUCK4{
+ regulator-name = "BUCK4";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5: BUCK5{
+ regulator-name = "BUCK5";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6: BUCK6 {
+ regulator-name = "BUCK6";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1: LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2: LDO2 {
+ regulator-name = "LDO2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3: LDO3 {
+ regulator-name = "LDO3";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4: LDO4 {
+ regulator-name = "LDO4";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5: LDO5 {
+ regulator-name = "LDO5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ adc@48 {
+ compatible = "ti,ads1115";
+ reg = <0x48>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@4 {
+ reg = <4>;
+ ti,gain = <1>;
+ ti,datarate = <7>;
+ };
+ channel@5 {
+ reg = <5>;
+ ti,gain = <1>;
+ ti,datarate = <7>;
+ };
+ channel@6 {
+ reg = <6>;
+ ti,gain = <1>;
+ ti,datarate = <7>;
+ };
+ channel@7 {
+ reg = <7>;
+ ti,gain = <1>;
+ ti,datarate = <7>;
+ };
+ };
+};
+
+&snvs_pwrkey {
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+
+ assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
+ assigned-clock-rates = <400000000>;
+
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
--
2.39.2


2023-07-04 20:45:12

by Fabio Estevam

[permalink] [raw]
Subject: Re: [PATCH 3/3] arm64: dts: freescale: Add DEBIX SOM A and SOM A I/O Board support

Hi Marco,

On Tue, Jul 4, 2023 at 3:41 PM Marco Felsch <[email protected]> wrote:

> +&fec {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_fec>;
> + phy-mode = "rgmii-id";
> + phy-handle = <&ethphy1>;
> + fsl,magic-packet;
> + phy-reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
> + phy-reset-duration = <10>;
> + phy-reset-post-delay = <150>;

These properties are deprecated. Please move them under the mdio node.

> + /*
> + * Since USB1 is binded to peripheral mode we need to ensure

s/binded/bound

> +/* µSD Card */
> +&usdhc2 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc2>;
> + pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
> + pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
> + vmmc-supply = <&reg_usdhc2_vmmc>;
> + bus-width = <4>;
> + disable-wp;
> + no-sdio;
> + no-mmc;
> +

No need for this blank line.

> + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
> + assigned-clock-rates = <400000000>;
> +

Ditto.

> +
> + pmic@25 {
> + compatible = "nxp,pca9450c";
> + reg = <0x25>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pmic>;
> +
> + interrupt-parent = <&gpio1>;
> + interrupts = <3 GPIO_ACTIVE_LOW>;
> +
> + regulators {
> + buck1: BUCK1 {
> + regulator-name = "BUCK1";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <2187500>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <3125>;
> + };
> +
> + buck2: BUCK2 {
> + regulator-name = "BUCK2";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <2187500>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <3125>;
> + nxp,dvs-run-voltage = <950000>;
> + nxp,dvs-standby-voltage = <850000>;
> + };
> +
> + buck4: BUCK4{

Missing space after BUCK4.

> + regulator-name = "BUCK4";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <3400000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + buck5: BUCK5{

Ditto.

> +&usdhc3 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc3>;
> + pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
> + pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
> + bus-width = <8>;
> + non-removable;
> +

No need for this blank line.


> + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
> + assigned-clock-rates = <400000000>;
> +

Ditto.

2023-07-05 06:42:49

by Krzysztof Kozlowski

[permalink] [raw]
Subject: Re: [PATCH 2/3] dt-bindings: arm: Add Polyhex DEBIX SOM A based boards

On 04/07/2023 20:41, Marco Felsch wrote:
> Add devicetree bindings for i.MX8MP based DEBIX SOM A and SOM A I/O
> baseboard:
> - https://debix.io/hardware/debix-som-a.html
> - https://debix.io/hardware/debix-som-a-io-board.html
>
> Signed-off-by: Marco Felsch <[email protected]>
> ---
> Documentation/devicetree/bindings/arm/fsl.yaml | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
> index d9e763ef932e5..6240485ba13b2 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> @@ -1059,6 +1059,14 @@ properties:
> - const: polyhex,imx8mp-debix # Polyhex Debix boards
> - const: fsl,imx8mp
>
> + - description: Polyhex DEBIX i.MX8MP SOM A based boards
> + items:
> + - enum:
> + - polyhex,imx8mp-debix-som-a-bmb-08 # Polyhex Debix SOM A on SOM A I/O board
> + - const: polyhex,imx8mp-debix-som-a # Polyhex Debix SOM A
> + - const: polyhex,imx8mp-debix # Polyhex Debix boards

A bit too generic, unless Debix boards are basically very similar. Since
your website links to "debix.io" this looks like compatible for all
vendor boards, thus way too generic.

Best regards,
Krzysztof


2023-07-05 06:49:03

by Krzysztof Kozlowski

[permalink] [raw]
Subject: Re: [PATCH 1/3] dt-bindings: arm: fsl: fix DEBIX binding

On 04/07/2023 20:41, Marco Felsch wrote:
> The current imx8mp-debix-model-a.dts uses all three compatibles. Fix the
> corresponding bindings by adding an own entry for it.
>
> Signed-off-by: Marco Felsch <[email protected]>
> ---
> Documentation/devicetree/bindings/arm/fsl.yaml | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
> index 15d4110840654..d9e763ef932e5 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> @@ -1019,8 +1019,6 @@ properties:
> - dmo,imx8mp-data-modul-edm-sbc # i.MX8MP eDM SBC
> - fsl,imx8mp-evk # i.MX8MP EVK Board
> - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
> - - polyhex,imx8mp-debix # Polyhex Debix boards
> - - polyhex,imx8mp-debix-model-a # Polyhex Debix Model A Board
> - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules
> - toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT
> - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules
> @@ -1054,6 +1052,13 @@ properties:
> - const: phytec,imx8mp-phycore-som # phyCORE-i.MX8MP SoM
> - const: fsl,imx8mp
>
> + - description: Polyhex DEBIX i.MX8MP based SBCs
> + items:
> + - enum:
> + - polyhex,imx8mp-debix-model-a # Polyhex Debix Model A Board
> + - const: polyhex,imx8mp-debix # Polyhex Debix boards

Same comments as for patch #2. I think this should be rather deprecated
- not a good pattern.

Best regards,
Krzysztof


2023-07-05 06:49:22

by Krzysztof Kozlowski

[permalink] [raw]
Subject: Re: [PATCH 3/3] arm64: dts: freescale: Add DEBIX SOM A and SOM A I/O Board support

On 04/07/2023 20:41, Marco Felsch wrote:
> Add support for the Debix SOM A + SOM A I/O board. The commit enables
> only the basic features like:
> - 2x UART
> - 2x Network
> - eMMC/µSD
> - CAN
> - QSPI

...

> +&i2c1 {
> + clock-frequency = <400000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + status = "okay";
> +
> + pmic@25 {
> + compatible = "nxp,pca9450c";
> + reg = <0x25>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pmic>;
> +
> + interrupt-parent = <&gpio1>;
> + interrupts = <3 GPIO_ACTIVE_LOW>;

Wrong flag.


Best regards,
Krzysztof


2023-07-05 09:02:05

by Marco Felsch

[permalink] [raw]
Subject: Re: [PATCH 1/3] dt-bindings: arm: fsl: fix DEBIX binding

Hi Krzysztof,

On 23-07-05, Krzysztof Kozlowski wrote:
> On 04/07/2023 20:41, Marco Felsch wrote:
> > The current imx8mp-debix-model-a.dts uses all three compatibles. Fix the
> > corresponding bindings by adding an own entry for it.
> >
> > Signed-off-by: Marco Felsch <[email protected]>
> > ---
> > Documentation/devicetree/bindings/arm/fsl.yaml | 9 +++++++--
> > 1 file changed, 7 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
> > index 15d4110840654..d9e763ef932e5 100644
> > --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> > +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> > @@ -1019,8 +1019,6 @@ properties:
> > - dmo,imx8mp-data-modul-edm-sbc # i.MX8MP eDM SBC
> > - fsl,imx8mp-evk # i.MX8MP EVK Board
> > - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
> > - - polyhex,imx8mp-debix # Polyhex Debix boards
> > - - polyhex,imx8mp-debix-model-a # Polyhex Debix Model A Board
> > - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules
> > - toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT
> > - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules
> > @@ -1054,6 +1052,13 @@ properties:
> > - const: phytec,imx8mp-phycore-som # phyCORE-i.MX8MP SoM
> > - const: fsl,imx8mp
> >
> > + - description: Polyhex DEBIX i.MX8MP based SBCs
> > + items:
> > + - enum:
> > + - polyhex,imx8mp-debix-model-a # Polyhex Debix Model A Board
> > + - const: polyhex,imx8mp-debix # Polyhex Debix boards
>
> Same comments as for patch #2. I think this should be rather deprecated
> - not a good pattern.

How can we deprecate a binding?

Regards,
Marco

2023-07-05 09:24:21

by Krzysztof Kozlowski

[permalink] [raw]
Subject: Re: [PATCH 1/3] dt-bindings: arm: fsl: fix DEBIX binding

On 05/07/2023 10:28, Marco Felsch wrote:
> Hi Krzysztof,
>
> On 23-07-05, Krzysztof Kozlowski wrote:
>> On 04/07/2023 20:41, Marco Felsch wrote:
>>> The current imx8mp-debix-model-a.dts uses all three compatibles. Fix the
>>> corresponding bindings by adding an own entry for it.
>>>
>>> Signed-off-by: Marco Felsch <[email protected]>
>>> ---
>>> Documentation/devicetree/bindings/arm/fsl.yaml | 9 +++++++--
>>> 1 file changed, 7 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
>>> index 15d4110840654..d9e763ef932e5 100644
>>> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
>>> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
>>> @@ -1019,8 +1019,6 @@ properties:
>>> - dmo,imx8mp-data-modul-edm-sbc # i.MX8MP eDM SBC
>>> - fsl,imx8mp-evk # i.MX8MP EVK Board
>>> - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
>>> - - polyhex,imx8mp-debix # Polyhex Debix boards
>>> - - polyhex,imx8mp-debix-model-a # Polyhex Debix Model A Board
>>> - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules
>>> - toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT
>>> - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules
>>> @@ -1054,6 +1052,13 @@ properties:
>>> - const: phytec,imx8mp-phycore-som # phyCORE-i.MX8MP SoM
>>> - const: fsl,imx8mp
>>>
>>> + - description: Polyhex DEBIX i.MX8MP based SBCs
>>> + items:
>>> + - enum:
>>> + - polyhex,imx8mp-debix-model-a # Polyhex Debix Model A Board
>>> + - const: polyhex,imx8mp-debix # Polyhex Debix boards
>>
>> Same comments as for patch #2. I think this should be rather deprecated
>> - not a good pattern.
>
> How can we deprecate a binding?

git grep "deprecated:" -- Documentation/devicetree/

Best regards,
Krzysztof


2023-07-05 09:35:16

by Ahmad Fatoum

[permalink] [raw]
Subject: Re: [PATCH 1/3] dt-bindings: arm: fsl: fix DEBIX binding

On 05.07.23 08:35, Krzysztof Kozlowski wrote:
> On 04/07/2023 20:41, Marco Felsch wrote:
>> The current imx8mp-debix-model-a.dts uses all three compatibles. Fix the
>> corresponding bindings by adding an own entry for it.
>>
>> Signed-off-by: Marco Felsch <[email protected]>
>> ---
>> Documentation/devicetree/bindings/arm/fsl.yaml | 9 +++++++--
>> 1 file changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
>> index 15d4110840654..d9e763ef932e5 100644
>> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
>> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
>> @@ -1019,8 +1019,6 @@ properties:
>> - dmo,imx8mp-data-modul-edm-sbc # i.MX8MP eDM SBC
>> - fsl,imx8mp-evk # i.MX8MP EVK Board
>> - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
>> - - polyhex,imx8mp-debix # Polyhex Debix boards
>> - - polyhex,imx8mp-debix-model-a # Polyhex Debix Model A Board
>> - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules
>> - toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT
>> - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules
>> @@ -1054,6 +1052,13 @@ properties:
>> - const: phytec,imx8mp-phycore-som # phyCORE-i.MX8MP SoM
>> - const: fsl,imx8mp
>>
>> + - description: Polyhex DEBIX i.MX8MP based SBCs
>> + items:
>> + - enum:
>> + - polyhex,imx8mp-debix-model-a # Polyhex Debix Model A Board
>> + - const: polyhex,imx8mp-debix # Polyhex Debix boards
>
> Same comments as for patch #2. I think this should be rather deprecated
> - not a good pattern.

The middle compatible was my suggestion, because there's also the Debix Model
B Standard and Model B SE, which is the same board, but different SoC variant:

Model A: Commercial Temperature Grade
Model B Standard: Industrial Temperature Grade
Model B SE: Industrial Temperature Grate, but i.MX8MP Lite
(No Neural/Video/Image accelerators).

As everything outside the SoC is the same, I wanted a generic board
compatible that bootloaders can match against. The SoMs should probably
not reuse it, but I think it should be kept (perhaps renamed?) for the
SBCs that don't utilize the Debix SoM.

Cheers,
Ahmad

>
> Best regards,
> Krzysztof
>
>
>

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2023-07-05 09:48:39

by Krzysztof Kozlowski

[permalink] [raw]
Subject: Re: [PATCH 1/3] dt-bindings: arm: fsl: fix DEBIX binding

On 05/07/2023 11:28, Ahmad Fatoum wrote:
>>> + items:
>>> + - enum:
>>> + - polyhex,imx8mp-debix-model-a # Polyhex Debix Model A Board
>>> + - const: polyhex,imx8mp-debix # Polyhex Debix boards
>>
>> Same comments as for patch #2. I think this should be rather deprecated
>> - not a good pattern.
>
> The middle compatible was my suggestion, because there's also the Debix Model
> B Standard and Model B SE, which is the same board, but different SoC variant:
>
> Model A: Commercial Temperature Grade
> Model B Standard: Industrial Temperature Grade
> Model B SE: Industrial Temperature Grate, but i.MX8MP Lite
> (No Neural/Video/Image accelerators).
>
> As everything outside the SoC is the same, I wanted a generic board
> compatible that bootloaders can match against. The SoMs should probably
> not reuse it, but I think it should be kept (perhaps renamed?) for the
> SBCs that don't utilize the Debix SoM.

The order of compatibles in patch two does not really look correct,
although it is accepted in some cases (e.g. Renesas). But anyway "Debix"
sounds like a vendor - they even have website - so compatible for all
boards seems too generic. This should be compatible for one specific
board. I understand that one board can have different SoMs (it is
common, just look at Toradex or Variscite), but it does not mean that
board should be unspecific.

Best regards,
Krzysztof


2023-07-14 14:54:17

by Marco Felsch

[permalink] [raw]
Subject: Re: [PATCH 3/3] arm64: dts: freescale: Add DEBIX SOM A and SOM A I/O Board support

On 23-07-05, Krzysztof Kozlowski wrote:
> On 04/07/2023 20:41, Marco Felsch wrote:
> > Add support for the Debix SOM A + SOM A I/O board. The commit enables
> > only the basic features like:
> > - 2x UART
> > - 2x Network
> > - eMMC/?SD
> > - CAN
> > - QSPI
>
> ...
>
> > +&i2c1 {
> > + clock-frequency = <400000>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_i2c1>;
> > + status = "okay";
> > +
> > + pmic@25 {
> > + compatible = "nxp,pca9450c";
> > + reg = <0x25>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_pmic>;
> > +
> > + interrupt-parent = <&gpio1>;
> > + interrupts = <3 GPIO_ACTIVE_LOW>;
>
> Wrong flag.

Sure, I will fix this. Thanks.

Regards,
Marco

2023-07-14 15:10:09

by Marco Felsch

[permalink] [raw]
Subject: Re: [PATCH 3/3] arm64: dts: freescale: Add DEBIX SOM A and SOM A I/O Board support

Hi Fabio,

On 23-07-04, Fabio Estevam wrote:
> Hi Marco,
>
> On Tue, Jul 4, 2023 at 3:41 PM Marco Felsch <[email protected]> wrote:
>
> > +&fec {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_fec>;
> > + phy-mode = "rgmii-id";
> > + phy-handle = <&ethphy1>;
> > + fsl,magic-packet;
> > + phy-reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
> > + phy-reset-duration = <10>;
> > + phy-reset-post-delay = <150>;
>
> These properties are deprecated. Please move them under the mdio node.

right

> > + /*
> > + * Since USB1 is binded to peripheral mode we need to ensure
>
> s/binded/bound

sure

> > +/* µSD Card */
> > +&usdhc2 {
> > + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > + pinctrl-0 = <&pinctrl_usdhc2>;
> > + pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
> > + pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
> > + vmmc-supply = <&reg_usdhc2_vmmc>;
> > + bus-width = <4>;
> > + disable-wp;
> > + no-sdio;
> > + no-mmc;
> > +
>
> No need for this blank line.

I added the blank lines for a better separation, but I can drop these.

> > + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
> > + assigned-clock-rates = <400000000>;
> > +
>
> Ditto.
>
> > +
> > + pmic@25 {
> > + compatible = "nxp,pca9450c";
> > + reg = <0x25>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_pmic>;
> > +
> > + interrupt-parent = <&gpio1>;
> > + interrupts = <3 GPIO_ACTIVE_LOW>;
> > +
> > + regulators {
> > + buck1: BUCK1 {
> > + regulator-name = "BUCK1";
> > + regulator-min-microvolt = <600000>;
> > + regulator-max-microvolt = <2187500>;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + regulator-ramp-delay = <3125>;
> > + };
> > +
> > + buck2: BUCK2 {
> > + regulator-name = "BUCK2";
> > + regulator-min-microvolt = <600000>;
> > + regulator-max-microvolt = <2187500>;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + regulator-ramp-delay = <3125>;
> > + nxp,dvs-run-voltage = <950000>;
> > + nxp,dvs-standby-voltage = <850000>;
> > + };
> > +
> > + buck4: BUCK4{
>
> Missing space after BUCK4.

yes.

> > + regulator-name = "BUCK4";
> > + regulator-min-microvolt = <600000>;
> > + regulator-max-microvolt = <3400000>;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + };
> > +
> > + buck5: BUCK5{
>
> Ditto.

yes.

> > +&usdhc3 {
> > + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > + pinctrl-0 = <&pinctrl_usdhc3>;
> > + pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
> > + pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
> > + bus-width = <8>;
> > + non-removable;
> > +
>
> No need for this blank line.
>
>
> > + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
> > + assigned-clock-rates = <400000000>;
> > +
>
> Ditto.

Removed these as well. Thanks for your review :)

Regards,
Marco

2023-07-14 15:35:59

by Marco Felsch

[permalink] [raw]
Subject: Re: [PATCH 1/3] dt-bindings: arm: fsl: fix DEBIX binding

On 23-07-05, Krzysztof Kozlowski wrote:
> On 05/07/2023 11:28, Ahmad Fatoum wrote:
> >>> + items:
> >>> + - enum:
> >>> + - polyhex,imx8mp-debix-model-a # Polyhex Debix Model A Board
> >>> + - const: polyhex,imx8mp-debix # Polyhex Debix boards
> >>
> >> Same comments as for patch #2. I think this should be rather deprecated
> >> - not a good pattern.
> >
> > The middle compatible was my suggestion, because there's also the Debix Model
> > B Standard and Model B SE, which is the same board, but different SoC variant:
> >
> > Model A: Commercial Temperature Grade
> > Model B Standard: Industrial Temperature Grade
> > Model B SE: Industrial Temperature Grate, but i.MX8MP Lite
> > (No Neural/Video/Image accelerators).
> >
> > As everything outside the SoC is the same, I wanted a generic board
> > compatible that bootloaders can match against. The SoMs should probably
> > not reuse it, but I think it should be kept (perhaps renamed?) for the
> > SBCs that don't utilize the Debix SoM.

The SoM may come also in a 'Standard' and 'SE' edition.

> The order of compatibles in patch two does not really look correct,
> although it is accepted in some cases (e.g. Renesas). But anyway "Debix"
> sounds like a vendor - they even have website - so compatible for all
> boards seems too generic. This should be compatible for one specific
> board. I understand that one board can have different SoMs (it is
> common, just look at Toradex or Variscite), but it does not mean that
> board should be unspecific.

I reused the "polyhex,imx8mp-debix" compatible since we already have a
user [1] and there are no differences.

I can drop it for the SoM case but for the SBC case I can't since this
would break current users [1].

Regards,
Marco

[1] https://elixir.bootlin.com/barebox/v2023.07.1/source/arch/arm/boards/polyhex-debix/board.c#L38