If FIFO depth DT property is provided, check it matches what hardware
reports and warn otherwise. Else, use hardware provided value.
Hardware exposes FIFO depth indirectly because
CQSPI_REG_SRAMPARTITION is partially read-only.
Move probe cqspi->ddata assignment prior to cqspi_of_get_pdata() call.
Signed-off-by: Théo Lebrun <[email protected]>
---
drivers/spi/spi-cadence-quadspi.c | 39 ++++++++++++++++++++++++++++++++-------
1 file changed, 32 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 9896e9fe7ffb..b499f2e5ec87 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1503,6 +1503,7 @@ static int cqspi_of_get_flash_pdata(struct platform_device *pdev,
static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
{
+ const struct cqspi_driver_platdata *ddata = cqspi->ddata;
struct device *dev = &cqspi->pdev->dev;
struct device_node *np = dev->of_node;
u32 id[2];
@@ -1510,8 +1511,8 @@ static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
- dev_err(dev, "couldn't determine fifo-depth\n");
- return -ENXIO;
+ /* Zero signals FIFO depth should be runtime detected. */
+ cqspi->fifo_depth = 0;
}
if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
@@ -1541,8 +1542,6 @@ static void cqspi_controller_init(struct cqspi_st *cqspi)
{
u32 reg;
- cqspi_controller_enable(cqspi, 0);
-
/* Configure the remap address register, no remap */
writel(0, cqspi->iobase + CQSPI_REG_REMAP);
@@ -1576,8 +1575,30 @@ static void cqspi_controller_init(struct cqspi_st *cqspi)
reg |= CQSPI_REG_CONFIG_DMA_MASK;
writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
}
+}
- cqspi_controller_enable(cqspi, 1);
+static void cqspi_controller_detect_fifo_depth(struct cqspi_st *cqspi)
+{
+ const struct cqspi_driver_platdata *ddata = cqspi->ddata;
+ struct device *dev = &cqspi->pdev->dev;
+ u32 reg, fifo_depth;
+
+ /*
+ * Bits N-1:0 are writable while bits 31:N are read as zero, with 2^N
+ * the FIFO depth.
+ */
+ writel(U32_MAX, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
+ reg = readl(cqspi->iobase + CQSPI_REG_SRAMPARTITION);
+ fifo_depth = reg + 1;
+
+ /* FIFO depth of zero means no value from devicetree was provided. */
+ if (cqspi->fifo_depth == 0) {
+ cqspi->fifo_depth = fifo_depth;
+ dev_dbg(dev, "using FIFO depth of %u\n", fifo_depth);
+ } else if (fifo_depth != cqspi->fifo_depth) {
+ dev_warn(dev, "detected FIFO depth (%u) different from config (%u)\n",
+ fifo_depth, cqspi->fifo_depth);
+ }
}
static int cqspi_request_mmap_dma(struct cqspi_st *cqspi)
@@ -1730,6 +1751,7 @@ static int cqspi_probe(struct platform_device *pdev)
cqspi->pdev = pdev;
cqspi->host = host;
cqspi->is_jh7110 = false;
+ cqspi->ddata = ddata = of_device_get_match_data(dev);
platform_set_drvdata(pdev, cqspi);
/* Obtain configuration from OF. */
@@ -1821,8 +1843,6 @@ static int cqspi_probe(struct platform_device *pdev)
/* write completion is supported by default */
cqspi->wr_completion = true;
- ddata = of_device_get_match_data(dev);
- cqspi->ddata = ddata;
if (ddata) {
if (ddata->quirks & CQSPI_NEEDS_WR_DELAY)
cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC,
@@ -1864,7 +1884,10 @@ static int cqspi_probe(struct platform_device *pdev)
}
cqspi_wait_idle(cqspi);
+ cqspi_controller_enable(cqspi, 0);
+ cqspi_controller_detect_fifo_depth(cqspi);
cqspi_controller_init(cqspi);
+ cqspi_controller_enable(cqspi, 1);
cqspi->current_cs = -1;
cqspi->sclk = 0;
@@ -1947,7 +1970,9 @@ static int cqspi_runtime_resume(struct device *dev)
clk_prepare_enable(cqspi->clk);
cqspi_wait_idle(cqspi);
+ cqspi_controller_enable(cqspi, 0);
cqspi_controller_init(cqspi);
+ cqspi_controller_enable(cqspi, 1);
cqspi->current_cs = -1;
cqspi->sclk = 0;
--
2.44.0
On Wed, Apr 10, 2024 at 11:29:07AM +0200, Théo Lebrun wrote:
> If FIFO depth DT property is provided, check it matches what hardware
> reports and warn otherwise. Else, use hardware provided value.
>
> Hardware exposes FIFO depth indirectly because
> CQSPI_REG_SRAMPARTITION is partially read-only.
This breaks an allmodconfig build:
/build/stage/linux/drivers/spi/spi-cadence-quadspi.c: In function ‘cqspi_of_get_
pdata’:
/build/stage/linux/drivers/spi/spi-cadence-quadspi.c:1506:45: error: unused vari
able ‘ddata’ [-Werror=unused-variable]
1506 | const struct cqspi_driver_platdata *ddata = cqspi->ddata;
| ^~~~~
/build/stage/linux/drivers/spi/spi-cadence-quadspi.c: In function ‘cqspi_control
ler_detect_fifo_depth’:
/build/stage/linux/drivers/spi/spi-cadence-quadspi.c:1582:45: error: unused vari
able ‘ddata’ [-Werror=unused-variable]
1582 | const struct cqspi_driver_platdata *ddata = cqspi->ddata;
| ^~~~~
cc1: all warnings being treated as errors
Hello,
On Wed Apr 10, 2024 at 10:03 PM CEST, Mark Brown wrote:
> On Wed, Apr 10, 2024 at 11:29:07AM +0200, Théo Lebrun wrote:
>
> > If FIFO depth DT property is provided, check it matches what hardware
> > reports and warn otherwise. Else, use hardware provided value.
> >
> > Hardware exposes FIFO depth indirectly because
> > CQSPI_REG_SRAMPARTITION is partially read-only.
>
> This breaks an allmodconfig build:
>
> /build/stage/linux/drivers/spi/spi-cadence-quadspi.c: In function ‘cqspi_of_get_
> pdata’:
> /build/stage/linux/drivers/spi/spi-cadence-quadspi.c:1506:45: error: unused vari
> able ‘ddata’ [-Werror=unused-variable]
> 1506 | const struct cqspi_driver_platdata *ddata = cqspi->ddata;
> | ^~~~~
> /build/stage/linux/drivers/spi/spi-cadence-quadspi.c: In function ‘cqspi_control
> ler_detect_fifo_depth’:
> /build/stage/linux/drivers/spi/spi-cadence-quadspi.c:1582:45: error: unused vari
> able ‘ddata’ [-Werror=unused-variable]
> 1582 | const struct cqspi_driver_platdata *ddata = cqspi->ddata;
> | ^~~~~
> cc1: all warnings being treated as errors
I really should fix my kernel compiler warnings. Sorry about that.
Will fix next revision.
Regards,
--
Théo Lebrun, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com