From: Peng Fan <[email protected]>
V5:
Drop patch v4 11, 12 which could added together with wlan support.
V4:
Use mmc-pwrseq in patch 12
V3:
Drop patch V2 3/15
Add A-b R-b
Sort order in patch 9
Update commit log in patch 10
Drop #address-cells, #size-cells in patch 11
Use off-on-delay-us in patch 12
Update patch 13 according to patch 12 change
V2:
https://lore.kernel.org/all/[email protected]/
Address Marco's comments
Update commit log for patch [3,5,9,14]/15
Order iomuxc in patch 4/15
Update flexspi node name in patch 6/15
Increase i2c speed in patch 7/15
V1:
https://lore.kernel.org/all/[email protected]/
This patchset includes several dts update for i.MX8M/N/P-EVK, with
only one dtsi patch to add mlmix power domain for i.MX8MP.
i.MX8MP-EVK: Enable PWM, uart1/3, I2C2
correct pcie pad
Fix pmic buck/ldo voltage
off-on-delay-us for SD
i.MX8MN-EVK: Enable UART1, SDHC1, I2C recovery IOMUXC
Update vdd_soc dvs voltage
i.MX8MM-EVK: add vcc supply for pca6416
use off-on-delay-us for SD
A few patches are directly cherry-picked from NXP downstream which
already includes R-b tag
Adrian Alonso (1):
arm64: dts: imx8mm-evk: add vcc supply for pca6416
Clark Wang (1):
ARM64: dts: imx8mp-evk: add pwm support
Haibo Chen (1):
arm64: dts: imx8m[m,q]-evk: change to use off-on-delay-us in regulator
Han Xu (1):
arm64: dts: imx8mp-evk: enable fspi nor on imx8mp evk
Peng Fan (8):
arm64: dts: imx8mp: add mlmix power domain
arm64: dts: imx8mp-evk: correct pcie pad settings
arm64: dts: imx8mp-evk: enable uart1/3 ports
arm64: dts: imx8mp-evk: enable I2C2 node
arm64: dts: imx8mn-evk: update vdd_soc dvs voltage
arm64: dts: imx8mn-evk: set off-on-delay-us in regulator
arm64: dts: imx8mn-evk: add i2c gpio recovery settings
arm64: dts: imx8mn-evk: enable uart1
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 2 +
arch/arm64/boot/dts/freescale/imx8mn-evk.dts | 4 +-
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 43 ++++++-
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 117 +++++++++++++++++-
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 8 ++
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 1 +
6 files changed, 168 insertions(+), 7 deletions(-)
--
2.37.1
From: Peng Fan <[email protected]>
Add mlmix power domain
Signed-off-by: Peng Fan <[email protected]>
Acked-by: Marco Felsch <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 7be02cd100cf..08704d2d9fdf 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -631,6 +631,14 @@ pgc_vpu_vc8000e: power-domain@22 {
reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
};
+
+ pgc_mlmix: power-domain@24 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_MLMIX>;
+ clocks = <&clk IMX8MP_CLK_ML_AXI>,
+ <&clk IMX8MP_CLK_ML_AHB>,
+ <&clk IMX8MP_CLK_NPU_ROOT>;
+ };
};
};
};
--
2.37.1
From: Peng Fan <[email protected]>
Enable uart1 for BT usage
Configure the clock to source from IMX8MN_SYS_PLL1_80M, because the uart
could only support max 1.5M buadrate if using OSC_24M as clock source.
Signed-off-by: Peng Fan <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
index 1971f095e4c2..12dc5d398a03 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
@@ -247,6 +247,15 @@ &spdif1 {
status = "okay";
};
+&uart1 { /* BT */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ assigned-clocks = <&clk IMX8MN_CLK_UART1>;
+ assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
&uart2 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
@@ -440,6 +449,15 @@ MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
>;
};
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
+ MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
+ >;
+ };
+
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
--
2.37.1
From: Clark Wang <[email protected]>
Enable pwm1/2/4 support.
Enable pwm1 on pin GPIO1_IO01 for DSI_BL_PWM
pwm2 on pin GPIO1_IO11 for LVDS_BL_PWM
pwm4 on pin SAI5_RXFS for J21-32
Acked-by: Fugang Duan <[email protected]>
Signed-off-by: Clark Wang <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Marco Felsch <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 36 ++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index b4c1ef2559f2..e323e6f4b7e5 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -390,6 +390,24 @@ &pcie {
status = "okay";
};
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+ status = "okay";
+};
+
&snvs_pwrkey {
status = "okay";
};
@@ -567,6 +585,24 @@ MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */
>;
};
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x116
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116
+ >;
+ };
+
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
--
2.37.1
From: Han Xu <[email protected]>
enable fspi nor on imx8mp evk dts
Reviewed-by: Frank Li <[email protected]>
Signed-off-by: Han Xu <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Marco Felsch <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 25 ++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 29472502d547..4164f69a89a6 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -85,6 +85,20 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
};
};
+&flexspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <80000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
&A53_0 {
cpu-supply = <®_arm>;
};
@@ -551,6 +565,17 @@ MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */
>;
};
+ pinctrl_flexspi0: flexspi0grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
+ MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
+ MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
+ MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
+ MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
+ MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
+ >;
+ };
+
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140
--
2.37.1
From: Peng Fan <[email protected]>
Per schematic, BUCK1 is for VDD_SOC&DRAM&PU_0V9. The nxp,dvs-run-voltage
and nxp,dvs-standby-voltage need set for BUCK1, not BUCK2.
BUCK2 is for A53, which is handled by DVFS, so no need dvs property.
Signed-off-by: Peng Fan <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mn-evk.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
index 4eb467df5ba7..a5a7d74ec1d5 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
@@ -47,6 +47,8 @@ buck1: BUCK1{
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
+ nxp,dvs-run-voltage = <950000>;
+ nxp,dvs-standby-voltage = <750000>;
};
buck2: BUCK2 {
@@ -56,8 +58,6 @@ buck2: BUCK2 {
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
- nxp,dvs-run-voltage = <950000>;
- nxp,dvs-standby-voltage = <850000>;
};
buck4: BUCK4{
--
2.37.1
From: Peng Fan <[email protected]>
Enable uart1/3 ports for evk board.
Configure the clock to source from IMX8MP_SYS_PLL1_80M, because the uart
could only support max 1.5M buadrate if using OSC_24M as clock source.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Marco Felsch <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 36 ++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index e323e6f4b7e5..29472502d547 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -412,6 +412,15 @@ &snvs_pwrkey {
status = "okay";
};
+&uart1 { /* BT */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ assigned-clocks = <&clk IMX8MP_CLK_UART1>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
&uart2 {
/* console */
pinctrl-names = "default";
@@ -434,6 +443,15 @@ &usb_dwc3_1 {
status = "okay";
};
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ assigned-clocks = <&clk IMX8MP_CLK_UART3>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
&usdhc2 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
assigned-clock-rates = <400000000>;
@@ -609,6 +627,15 @@ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
>;
};
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
+ MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
+ MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
+ MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
+ >;
+ };
+
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
@@ -622,6 +649,15 @@ MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10
>;
};
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
+ MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
+ MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140
+ MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
+ >;
+ };
+
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
--
2.37.1
From: Haibo Chen <[email protected]>
Some SD Card controller and power circuitry has increased capacitance,
so the usual toggling of regulator to power the card off and on
is insufficient.
According to SD spec, for sd card power reset operation, the sd card
supply voltage needs to be lower than 0.5v and keep over 1ms, otherwise,
next time power back the sd card supply voltage to 3.3v, sd card can't
support SD3.0 mode again.
This patch add the off-on-delay-us, make sure the sd power reset behavior
is align with the specification. Without this patch, when do quick system
suspend/resume test, some sd card can't work at SD3.0 mode after system
resume back.
Signed-off-by: Haibo Chen <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 1 +
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
index 7d6317d95b13..f881494996a1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
@@ -56,6 +56,7 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ off-on-delay-us = <20000>;
enable-active-high;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 82387b9cb800..07d9fb2aacf8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -46,6 +46,7 @@ reg_usdhc2_vmmc: regulator-vsd-3v3 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ off-on-delay-us = <20000>;
enable-active-high;
};
--
2.37.1
From: Peng Fan <[email protected]>
Add I2C gpio recovery iomuxc settings
Signed-off-by: Peng Fan <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 24 +++++++++++++++++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
index 2b4395854283..1971f095e4c2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
@@ -160,8 +160,11 @@ &i2c1 {
&i2c2 {
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
status = "okay";
ptn5110: tcpc@50 {
@@ -196,8 +199,11 @@ typec1_con: connector {
&i2c3 {
clock-frequency = <400000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
status = "okay";
pca6416: gpio@20 {
@@ -370,6 +376,13 @@ MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
+ pinctrl_i2c2_gpio: i2c2grp-gpio {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3
+ MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3
+ >;
+ };
+
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
@@ -377,6 +390,13 @@ MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
+ pinctrl_i2c3_gpio: i2c3grp-gpio {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3
+ MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3
+ >;
+ };
+
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
--
2.37.1
From: Peng Fan <[email protected]>
Enable I2C node for i.MX8MP-EVK
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Marco Felsch <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 4164f69a89a6..878d4a752090 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -331,6 +331,13 @@ LDO5 {
};
};
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
@@ -589,6 +596,13 @@ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
>;
};
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
+ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
+ >;
+ };
+
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
--
2.37.1
From: Adrian Alonso <[email protected]>
pca6146 requires vcc-supply to work on i.MX8MM-EVK board.
Reviewed-by: Shengjiu Wang <[email protected]>
Signed-off-by: Adrian Alonso <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
index f881494996a1..e7984205de3e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
@@ -344,6 +344,7 @@ pca6416: gpio@20 {
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
+ vcc-supply = <&buck4_reg>;
};
};
--
2.37.1
On 22-11-15, Peng Fan (OSS) wrote:
> From: Adrian Alonso <[email protected]>
>
> pca6146 requires vcc-supply to work on i.MX8MM-EVK board.
>
> Reviewed-by: Shengjiu Wang <[email protected]>
> Signed-off-by: Adrian Alonso <[email protected]>
> Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Marco Felsch <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> index f881494996a1..e7984205de3e 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> @@ -344,6 +344,7 @@ pca6416: gpio@20 {
> reg = <0x20>;
> gpio-controller;
> #gpio-cells = <2>;
> + vcc-supply = <&buck4_reg>;
> };
> };
>
> --
> 2.37.1
>
>
>
From: Peng Fan <[email protected]>
Some SD Card controller and power circuitry has increased capacitance,
so the usual toggling of regulator to power the card off and on
is insufficient.
According to SD spec, for sd card power reset operation, the sd card
supply voltage needs to be lower than 0.5v and keep over 1ms, otherwise,
next time power back the sd card supply voltage to 3.3v, sd card can't
support SD3.0 mode again.
This patch add the off-on-delay-us, make sure the sd power reset behavior
is align with the specification. Without this patch, when do quick system
suspend/resume test, some sd card can't work at SD3.0 mode after system
resume back.
Signed-off-by: Peng Fan <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
index 261c36540079..2b4395854283 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
@@ -36,6 +36,7 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ off-on-delay-us = <12000>;
enable-active-high;
};
--
2.37.1
From: Peng Fan <[email protected]>
According to RM bit layout, BIT3 and BIT0 are reserved.
8 7 6 5 4 3 2 1 0
PE HYS PUE ODE FSEL X DSE X
Although function is not broken, we should not set reserved bit.
Fixes: d50650500064 ("arm64: dts: imx8mp-evk: Add PCIe support")
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Marco Felsch <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 9f1469db554d..b4c1ef2559f2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -544,14 +544,14 @@ MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2
pinctrl_pcie0: pcie0grp {
fsl,pins = <
- MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x61 /* open drain, pull up */
- MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41
+ MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60 /* open drain, pull up */
+ MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x40
>;
};
pinctrl_pcie0_reg: pcie0reggrp {
fsl,pins = <
- MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41
+ MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40
>;
};
--
2.37.1
On 22-11-15, Peng Fan (OSS) wrote:
> From: Haibo Chen <[email protected]>
>
> Some SD Card controller and power circuitry has increased capacitance,
> so the usual toggling of regulator to power the card off and on
> is insufficient.
>
> According to SD spec, for sd card power reset operation, the sd card
> supply voltage needs to be lower than 0.5v and keep over 1ms, otherwise,
> next time power back the sd card supply voltage to 3.3v, sd card can't
> support SD3.0 mode again.
>
> This patch add the off-on-delay-us, make sure the sd power reset behavior
> is align with the specification. Without this patch, when do quick system
> suspend/resume test, some sd card can't work at SD3.0 mode after system
> resume back.
>
> Signed-off-by: Haibo Chen <[email protected]>
> Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Marco Felsch <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 1 +
> arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> index 7d6317d95b13..f881494996a1 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> @@ -56,6 +56,7 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
> regulator-min-microvolt = <3300000>;
> regulator-max-microvolt = <3300000>;
> gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> + off-on-delay-us = <20000>;
> enable-active-high;
> };
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> index 82387b9cb800..07d9fb2aacf8 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> @@ -46,6 +46,7 @@ reg_usdhc2_vmmc: regulator-vsd-3v3 {
> regulator-min-microvolt = <3300000>;
> regulator-max-microvolt = <3300000>;
> gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> + off-on-delay-us = <20000>;
> enable-active-high;
> };
>
> --
> 2.37.1
>
>
>
Hi Peng,
On 22-11-15, Peng Fan (OSS) wrote:
> From: Peng Fan <[email protected]>
>
> Per schematic, BUCK1 is for VDD_SOC&DRAM&PU_0V9. The nxp,dvs-run-voltage
> and nxp,dvs-standby-voltage need set for BUCK1, not BUCK2.
> BUCK2 is for A53, which is handled by DVFS, so no need dvs property.
>
> Signed-off-by: Peng Fan <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8mn-evk.dts | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
> index 4eb467df5ba7..a5a7d74ec1d5 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
> @@ -47,6 +47,8 @@ buck1: BUCK1{
> regulator-boot-on;
> regulator-always-on;
> regulator-ramp-delay = <3125>;
> + nxp,dvs-run-voltage = <950000>;
One last question on this. According the schematic the max should be
0.88/0.945V and you are going to set it to 0.950V.
According the driver the nxp,dvs-run-voltage is just the same as the
normal regulator voltage. So I would suggest to just use the
nxp,dvs-standby-voltage property to enable the DVS feature since the run
voltage is already handled by the
regulator-min-microvolt/regulator-max-microvolt. So it would be just:
> + nxp,dvs-standby-voltage = <750000>;
Regards,
Marco
> };
>
> buck2: BUCK2 {
> @@ -56,8 +58,6 @@ buck2: BUCK2 {
> regulator-boot-on;
> regulator-always-on;
> regulator-ramp-delay = <3125>;
> - nxp,dvs-run-voltage = <950000>;
> - nxp,dvs-standby-voltage = <850000>;
> };
>
> buck4: BUCK4{
> --
> 2.37.1
>
>
>
On 22-11-15, Peng Fan (OSS) wrote:
> From: Peng Fan <[email protected]>
>
> Enable uart1 for BT usage
> Configure the clock to source from IMX8MN_SYS_PLL1_80M, because the uart
> could only support max 1.5M buadrate if using OSC_24M as clock source.
>
> Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Marco Felsch <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> index 1971f095e4c2..12dc5d398a03 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> @@ -247,6 +247,15 @@ &spdif1 {
> status = "okay";
> };
>
> +&uart1 { /* BT */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + assigned-clocks = <&clk IMX8MN_CLK_UART1>;
> + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
> + fsl,uart-has-rtscts;
> + status = "okay";
> +};
> +
> &uart2 { /* console */
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_uart2>;
> @@ -440,6 +449,15 @@ MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
> >;
> };
>
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
> + MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
> + MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
> + MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
> + >;
> + };
> +
> pinctrl_uart2: uart2grp {
> fsl,pins = <
> MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
> --
> 2.37.1
>
>
>
On 22-11-15, Peng Fan (OSS) wrote:
> From: Peng Fan <[email protected]>
>
> Add I2C gpio recovery iomuxc settings
>
> Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Marco Felsch <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 24 +++++++++++++++++--
> 1 file changed, 22 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> index 2b4395854283..1971f095e4c2 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> @@ -160,8 +160,11 @@ &i2c1 {
>
> &i2c2 {
> clock-frequency = <400000>;
> - pinctrl-names = "default";
> + pinctrl-names = "default", "gpio";
> pinctrl-0 = <&pinctrl_i2c2>;
> + pinctrl-1 = <&pinctrl_i2c2_gpio>;
> + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
> + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
> status = "okay";
>
> ptn5110: tcpc@50 {
> @@ -196,8 +199,11 @@ typec1_con: connector {
>
> &i2c3 {
> clock-frequency = <400000>;
> - pinctrl-names = "default";
> + pinctrl-names = "default", "gpio";
> pinctrl-0 = <&pinctrl_i2c3>;
> + pinctrl-1 = <&pinctrl_i2c3_gpio>;
> + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
> + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
> status = "okay";
>
> pca6416: gpio@20 {
> @@ -370,6 +376,13 @@ MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
> >;
> };
>
> + pinctrl_i2c2_gpio: i2c2grp-gpio {
> + fsl,pins = <
> + MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3
> + MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3
> + >;
> + };
> +
> pinctrl_i2c3: i2c3grp {
> fsl,pins = <
> MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
> @@ -377,6 +390,13 @@ MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
> >;
> };
>
> + pinctrl_i2c3_gpio: i2c3grp-gpio {
> + fsl,pins = <
> + MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3
> + MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3
> + >;
> + };
> +
> pinctrl_pmic: pmicirqgrp {
> fsl,pins = <
> MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
> --
> 2.37.1
>
>
>
On 22-11-15, Peng Fan (OSS) wrote:
> From: Peng Fan <[email protected]>
>
> Some SD Card controller and power circuitry has increased capacitance,
> so the usual toggling of regulator to power the card off and on
> is insufficient.
>
> According to SD spec, for sd card power reset operation, the sd card
> supply voltage needs to be lower than 0.5v and keep over 1ms, otherwise,
> next time power back the sd card supply voltage to 3.3v, sd card can't
> support SD3.0 mode again.
>
> This patch add the off-on-delay-us, make sure the sd power reset behavior
> is align with the specification. Without this patch, when do quick system
> suspend/resume test, some sd card can't work at SD3.0 mode after system
> resume back.
>
> Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Marco Felsch <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> index 261c36540079..2b4395854283 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> @@ -36,6 +36,7 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
> regulator-min-microvolt = <3300000>;
> regulator-max-microvolt = <3300000>;
> gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> + off-on-delay-us = <12000>;
> enable-active-high;
> };
>
> --
> 2.37.1
>
>
>
> Subject: Re: [PATCH V5 07/12] arm64: dts: imx8mn-evk: update vdd_soc dvs
> voltage
>
> Hi Peng,
>
> On 22-11-15, Peng Fan (OSS) wrote:
> > From: Peng Fan <[email protected]>
> >
> > Per schematic, BUCK1 is for VDD_SOC&DRAM&PU_0V9. The
> > nxp,dvs-run-voltage and nxp,dvs-standby-voltage need set for BUCK1, not
> BUCK2.
> > BUCK2 is for A53, which is handled by DVFS, so no need dvs property.
> >
> > Signed-off-by: Peng Fan <[email protected]>
> > ---
> > arch/arm64/boot/dts/freescale/imx8mn-evk.dts | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
> > b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
> > index 4eb467df5ba7..a5a7d74ec1d5 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
> > @@ -47,6 +47,8 @@ buck1: BUCK1{
> > regulator-boot-on;
> > regulator-always-on;
> > regulator-ramp-delay = <3125>;
> > + nxp,dvs-run-voltage = <950000>;
>
> One last question on this. According the schematic the max should be
> 0.88/0.945V and you are going to set it to 0.950V.
No, my schematic shows the TYP voltage is 0.85/0.95V.
>
> According the driver the nxp,dvs-run-voltage is just the same as the normal
> regulator voltage. So I would suggest to just use the nxp,dvs-standby-
> voltage property to enable the DVS feature since the run voltage is already
> handled by the regulator-min-microvolt/regulator-max-microvolt. So it
> would be just:
It should be fine to not set nxp,dvs-run-voltage, because bootloader already
set that.
Thanks,
Peng.
>
> > + nxp,dvs-standby-voltage = <750000>;
>
> Regards,
> Marco
>
> > };
> >
> > buck2: BUCK2 {
> > @@ -56,8 +58,6 @@ buck2: BUCK2 {
> > regulator-boot-on;
> > regulator-always-on;
> > regulator-ramp-delay = <3125>;
> > - nxp,dvs-run-voltage = <950000>;
> > - nxp,dvs-standby-voltage = <850000>;
> > };
> >
> > buck4: BUCK4{
> > --
> > 2.37.1
> >
> >
> >
On 22-11-16, Peng Fan wrote:
> > Subject: Re: [PATCH V5 07/12] arm64: dts: imx8mn-evk: update vdd_soc dvs
> > voltage
> >
> > Hi Peng,
> >
> > On 22-11-15, Peng Fan (OSS) wrote:
> > > From: Peng Fan <[email protected]>
> > >
> > > Per schematic, BUCK1 is for VDD_SOC&DRAM&PU_0V9. The
> > > nxp,dvs-run-voltage and nxp,dvs-standby-voltage need set for BUCK1, not
> > BUCK2.
> > > BUCK2 is for A53, which is handled by DVFS, so no need dvs property.
> > >
> > > Signed-off-by: Peng Fan <[email protected]>
> > > ---
> > > arch/arm64/boot/dts/freescale/imx8mn-evk.dts | 4 ++--
> > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
> > > b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
> > > index 4eb467df5ba7..a5a7d74ec1d5 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
> > > @@ -47,6 +47,8 @@ buck1: BUCK1{
> > > regulator-boot-on;
> > > regulator-always-on;
> > > regulator-ramp-delay = <3125>;
> > > + nxp,dvs-run-voltage = <950000>;
> >
> > One last question on this. According the schematic the max should be
> > 0.88/0.945V and you are going to set it to 0.950V.
>
> No, my schematic shows the TYP voltage is 0.85/0.95V.
I have the Rev.A2 i.MX8MNano DDR4 SoM schematic and TYP is listed as
0.8/0.9V. Is this different for different ram configurations? Sorry for
asking but the i.MX8MNano LPDDR4 schematic is not available.
> > According the driver the nxp,dvs-run-voltage is just the same as the normal
> > regulator voltage. So I would suggest to just use the nxp,dvs-standby-
> > voltage property to enable the DVS feature since the run voltage is already
> > handled by the regulator-min-microvolt/regulator-max-microvolt. So it
> > would be just:
> It should be fine to not set nxp,dvs-run-voltage, because bootloader already
> set that.
Okay, so leave the voltage as it is right now and just add the
nxp,dvs-standby-voltage seems fine :)
Regards,
Marco
>
> Thanks,
> Peng.
> >
> > > + nxp,dvs-standby-voltage = <750000>;
> >
> > Regards,
> > Marco
> >
> > > };
> > >
> > > buck2: BUCK2 {
> > > @@ -56,8 +58,6 @@ buck2: BUCK2 {
> > > regulator-boot-on;
> > > regulator-always-on;
> > > regulator-ramp-delay = <3125>;
> > > - nxp,dvs-run-voltage = <950000>;
> > > - nxp,dvs-standby-voltage = <850000>;
> > > };
> > >
> > > buck4: BUCK4{
> > > --
> > > 2.37.1
> > >
> > >
> > >
>
> Subject: Re: [PATCH V5 07/12] arm64: dts: imx8mn-evk: update vdd_soc dvs
> voltage
>
> On 22-11-16, Peng Fan wrote:
> > > Subject: Re: [PATCH V5 07/12] arm64: dts: imx8mn-evk: update vdd_soc
> > > dvs voltage
> > >
> > > Hi Peng,
> > >
> > > On 22-11-15, Peng Fan (OSS) wrote:
> > > > From: Peng Fan <[email protected]>
> > > >
> > > > Per schematic, BUCK1 is for VDD_SOC&DRAM&PU_0V9. The
> > > > nxp,dvs-run-voltage and nxp,dvs-standby-voltage need set for
> > > > BUCK1, not
> > > BUCK2.
> > > > BUCK2 is for A53, which is handled by DVFS, so no need dvs property.
> > > >
> > > > Signed-off-by: Peng Fan <[email protected]>
> > > > ---
> > > > arch/arm64/boot/dts/freescale/imx8mn-evk.dts | 4 ++--
> > > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
> > > > b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
> > > > index 4eb467df5ba7..a5a7d74ec1d5 100644
> > > > --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
> > > > +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
> > > > @@ -47,6 +47,8 @@ buck1: BUCK1{
> > > > regulator-boot-on;
> > > > regulator-always-on;
> > > > regulator-ramp-delay = <3125>;
> > > > + nxp,dvs-run-voltage = <950000>;
> > >
> > > One last question on this. According the schematic the max should be
> > > 0.88/0.945V and you are going to set it to 0.950V.
> >
> > No, my schematic shows the TYP voltage is 0.85/0.95V.
>
> I have the Rev.A2 i.MX8MNano DDR4 SoM schematic and TYP is listed as
> 0.8/0.9V. Is this different for different ram configurations?
[Peng Fan]
It maybe DDR4 board support 2400MTS, LPDDR4 board support 3200MTS,
but I am not sure.
Regards,
Peng.
Sorry for asking
> but the i.MX8MNano LPDDR4 schematic is not available.
>
> > > According the driver the nxp,dvs-run-voltage is just the same as the
> > > normal regulator voltage. So I would suggest to just use the
> > > nxp,dvs-standby- voltage property to enable the DVS feature since
> > > the run voltage is already handled by the
> > > regulator-min-microvolt/regulator-max-microvolt. So it would be just:
> > It should be fine to not set nxp,dvs-run-voltage, because bootloader
> > already set that.
>
> Okay, so leave the voltage as it is right now and just add the nxp,dvs-
> standby-voltage seems fine :)
>
> Regards,
> Marco
>
> >
> > Thanks,
> > Peng.
> > >
> > > > + nxp,dvs-standby-voltage = <750000>;
> > >
> > > Regards,
> > > Marco
> > >
> > > > };
> > > >
> > > > buck2: BUCK2 {
> > > > @@ -56,8 +58,6 @@ buck2: BUCK2 {
> > > > regulator-boot-on;
> > > > regulator-always-on;
> > > > regulator-ramp-delay = <3125>;
> > > > - nxp,dvs-run-voltage = <950000>;
> > > > - nxp,dvs-standby-voltage = <850000>;
> > > > };
> > > >
> > > > buck4: BUCK4{
> > > > --
> > > > 2.37.1
> > > >
> > > >
> > > >
> >