Huashan Pi board is an embedded development platform based on the
CV1812H chip. Add minimal device tree files for this board.
Currently, it can boot to a basic shell.
NOTE: this series is based on the Jisheng's Milk-V Duo patch.
Link: https://en.sophgo.com/product/introduce/huashan.html
Link: https://en.sophgo.com/product/introduce/cv181xH.html
Link: https://lore.kernel.org/linux-riscv/[email protected]/
Changed from v3:
1. merge the patch 4 and 5 of v2 to preserve bisectability.
Changed from v2:
1. use dt override to save code.
2. code cleanup.
Changed from v1:
1. split the patch into several patch and refactor them.
Inochi Amaoto (7):
dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic
dt-bindings: timer: Add SOPHGO CV1812H clint
dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles
riscv: dts: sophgo: Separate compatible specific for CV1800B soc
riscv: dts: sophgo: cv18xx: Add gpio devices
riscv: dts: sophgo: add initial CV1812H SoC device tree
riscv: dts: sophgo: add Huashan Pi board device tree
.../sifive,plic-1.0.0.yaml | 1 +
.../devicetree/bindings/riscv/sophgo.yaml | 4 +
.../bindings/timer/sifive,clint.yaml | 1 +
arch/riscv/boot/dts/sophgo/Makefile | 1 +
arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 119 +----------
.../boot/dts/sophgo/cv1812h-huashan-pi.dts | 48 +++++
arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 24 +++
arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 193 ++++++++++++++++++
8 files changed, 279 insertions(+), 112 deletions(-)
create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi
create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx.dtsi
--
2.42.0
Add compatible string for SOPHGO CV1812H plic.
Signed-off-by: Inochi Amaoto <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Jisheng Zhang <[email protected]>
---
.../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 0c07e8dda445..709b2211276b 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -66,6 +66,7 @@ properties:
- enum:
- allwinner,sun20i-d1-plic
- sophgo,cv1800b-plic
+ - sophgo,cv1812h-plic
- sophgo,sg2042-plic
- thead,th1520-plic
- const: thead,c900-plic
--
2.42.0
Add compatible string for the SOPHGO CV1812H clint.
Signed-off-by: Inochi Amaoto <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Jisheng Zhang <[email protected]>
---
Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index e8be6c470364..4b6c20fc8194 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -38,6 +38,7 @@ properties:
- enum:
- allwinner,sun20i-d1-clint
- sophgo,cv1800b-clint
+ - sophgo,cv1812h-clint
- thead,th1520-clint
- const: thead,c900-clint
- items:
--
2.42.0
Document the compatible strings for the SOPHGO Huashan Pi board which
uses the SOPHGO CV1812H SoC.
Signed-off-by: Inochi Amaoto <[email protected]>
Link: https://en.sophgo.com/product/introduce/huashan.html
Link: https://en.sophgo.com/product/introduce/cv181xH.html
Acked-by: Chen Wang <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Jisheng Zhang <[email protected]>
---
Documentation/devicetree/bindings/riscv/sophgo.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml
index 86748c5390be..9bc813dad098 100644
--- a/Documentation/devicetree/bindings/riscv/sophgo.yaml
+++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml
@@ -22,6 +22,10 @@ properties:
- enum:
- milkv,duo
- const: sophgo,cv1800b
+ - items:
+ - enum:
+ - sophgo,huashan-pi
+ - const: sophgo,cv1812h
- items:
- enum:
- milkv,pioneer
--
2.42.0
Add initial device tree for the CV1812H RISC-V SoC by SOPHGO.
Signed-off-by: Inochi Amaoto <[email protected]>
---
arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi
diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
new file mode 100644
index 000000000000..3e7a942f5c1a
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Inochi Amaoto <[email protected]>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "cv18xx.dtsi"
+
+/ {
+ compatible = "sophgo,cv1812h";
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>;
+ };
+};
+
+&plic {
+ compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
+};
+
+&clint {
+ compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
+};
--
2.42.0
Add initial device tree files for the Huashan Pi board.
Note: The boot of CV1812H chip needs a rtos firmware for coprocessor to
function properly. To make the soc happy, reserved the last 2M memory
for the rtos firmware.
Signed-off-by: Inochi Amaoto <[email protected]>
Link: https://en.sophgo.com/product/introduce/huashan.html
Link: https://en.sophgo.com/product/introduce/cv181xH.html
Link: https://github.com/milkv-duo/duo-buildroot-sdk/blob/develop/build/boards/cv181x/cv1812h_wevb_0007a_emmc_huashan/memmap.py#L15
Reviewed-by: Jisheng Zhang <[email protected]>
---
arch/riscv/boot/dts/sophgo/Makefile | 1 +
.../boot/dts/sophgo/cv1812h-huashan-pi.dts | 48 +++++++++++++++++++
2 files changed, 49 insertions(+)
create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile
index 3fb65512c631..57ad82a61ea6 100644
--- a/arch/riscv/boot/dts/sophgo/Makefile
+++ b/arch/riscv/boot/dts/sophgo/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
+dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
diff --git a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
new file mode 100644
index 000000000000..aa361f3a86bb
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Inochi Amaoto <[email protected]>
+ */
+
+/dts-v1/;
+
+#include "cv1812h.dtsi"
+
+/ {
+ model = "Huashan Pi";
+ compatible = "sophgo,huashan-pi", "sophgo,cv1812h";
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ coprocessor_rtos: region@8fe00000 {
+ reg = <0x8fe00000 0x200000>;
+ no-map;
+ };
+ };
+};
+
+&osc {
+ clock-frequency = <25000000>;
+};
+
+&uart0 {
+ status = "okay";
+};
--
2.42.0
Add common GPIO devices for the CV180x and CV181x soc.
Signed-off-by: Inochi Amaoto <[email protected]>
Reviewed-by: Jisheng Zhang <[email protected]>
---
arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 73 ++++++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
index 55d4bc84faa0..d415cc758def 100644
--- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2023 Jisheng Zhang <[email protected]>
+ * Copyright (C) 2023 Inochi Amaoto <[email protected]>
*/
#include <dt-bindings/interrupt-controller/irq.h>
@@ -53,6 +54,78 @@ soc {
dma-noncoherent;
ranges;
+ gpio0: gpio@3020000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x3020000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpio1: gpio@3021000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x3021000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ portb: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpio2: gpio@3022000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x3022000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ portc: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ gpio3: gpio@3023000 {
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x3023000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ portd: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <32>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
uart0: serial@4140000 {
compatible = "snps,dw-apb-uart";
reg = <0x04140000 0x100>;
--
2.42.0
As CV180x and CV181x have the identical layouts, it is OK to use the
cv1800b basic device tree for the whole series.
For CV1800B soc specific compatible, just move them out of the common
file.
Signed-off-by: Inochi Amaoto <[email protected]>
---
arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 119 ++---------------------
arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 120 ++++++++++++++++++++++++
2 files changed, 127 insertions(+), 112 deletions(-)
create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx.dtsi
diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
index df40e87ee063..165e9e320a8c 100644
--- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
@@ -3,121 +3,16 @@
* Copyright (C) 2023 Jisheng Zhang <[email protected]>
*/
-#include <dt-bindings/interrupt-controller/irq.h>
+#include "cv18xx.dtsi"
/ {
compatible = "sophgo,cv1800b";
- #address-cells = <1>;
- #size-cells = <1>;
-
- cpus: cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- timebase-frequency = <25000000>;
-
- cpu0: cpu@0 {
- compatible = "thead,c906", "riscv";
- device_type = "cpu";
- reg = <0>;
- d-cache-block-size = <64>;
- d-cache-sets = <512>;
- d-cache-size = <65536>;
- i-cache-block-size = <64>;
- i-cache-sets = <128>;
- i-cache-size = <32768>;
- mmu-type = "riscv,sv39";
- riscv,isa = "rv64imafdc";
- riscv,isa-base = "rv64i";
- riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
- "zifencei", "zihpm";
-
- cpu0_intc: interrupt-controller {
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- };
- };
- };
-
- osc: oscillator {
- compatible = "fixed-clock";
- clock-output-names = "osc_25m";
- #clock-cells = <0>;
- };
-
- soc {
- compatible = "simple-bus";
- interrupt-parent = <&plic>;
- #address-cells = <1>;
- #size-cells = <1>;
- dma-noncoherent;
- ranges;
-
- uart0: serial@4140000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x04140000 0x100>;
- interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- uart1: serial@4150000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x04150000 0x100>;
- interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- uart2: serial@4160000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x04160000 0x100>;
- interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- uart3: serial@4170000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x04170000 0x100>;
- interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- uart4: serial@41c0000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x041c0000 0x100>;
- interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
+};
- plic: interrupt-controller@70000000 {
- compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
- reg = <0x70000000 0x4000000>;
- interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- riscv,ndev = <101>;
- };
+&plic {
+ compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
+};
- clint: timer@74000000 {
- compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
- reg = <0x74000000 0x10000>;
- interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
- };
- };
+&clint {
+ compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
};
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
new file mode 100644
index 000000000000..55d4bc84faa0
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Jisheng Zhang <[email protected]>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <25000000>;
+
+ cpu0: cpu@0 {
+ compatible = "thead,c906", "riscv";
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <512>;
+ d-cache-size = <65536>;
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ mmu-type = "riscv,sv39";
+ riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+ };
+ };
+
+ osc: oscillator {
+ compatible = "fixed-clock";
+ clock-output-names = "osc_25m";
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&plic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ dma-noncoherent;
+ ranges;
+
+ uart0: serial@4140000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x04140000 0x100>;
+ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart1: serial@4150000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x04150000 0x100>;
+ interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart2: serial@4160000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x04160000 0x100>;
+ interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart3: serial@4170000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x04170000 0x100>;
+ interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart4: serial@41c0000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x041c0000 0x100>;
+ interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ plic: interrupt-controller@70000000 {
+ reg = <0x70000000 0x4000000>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ riscv,ndev = <101>;
+ };
+
+ clint: timer@74000000 {
+ reg = <0x74000000 0x10000>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
+ };
+ };
+};
--
2.42.0
On 2023/10/19 7:18, Inochi Amaoto wrote:
> Add initial device tree files for the Huashan Pi board.
>
> Note: The boot of CV1812H chip needs a rtos firmware for coprocessor to
> function properly. To make the soc happy, reserved the last 2M memory
> for the rtos firmware.
>
> Signed-off-by: Inochi Amaoto <[email protected]>
> Link: https://en.sophgo.com/product/introduce/huashan.html
> Link: https://en.sophgo.com/product/introduce/cv181xH.html
> Link: https://github.com/milkv-duo/duo-buildroot-sdk/blob/develop/build/boards/cv181x/cv1812h_wevb_0007a_emmc_huashan/memmap.py#L15
> Reviewed-by: Jisheng Zhang <[email protected]>
LGTM.
Acked-by: Chen Wang <[email protected]>
> ---
> arch/riscv/boot/dts/sophgo/Makefile | 1 +
> .../boot/dts/sophgo/cv1812h-huashan-pi.dts | 48 +++++++++++++++++++
> 2 files changed, 49 insertions(+)
> create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
>
> diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile
> index 3fb65512c631..57ad82a61ea6 100644
> --- a/arch/riscv/boot/dts/sophgo/Makefile
> +++ b/arch/riscv/boot/dts/sophgo/Makefile
> @@ -1,3 +1,4 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
> +dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
> dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb
> diff --git a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
> new file mode 100644
> index 000000000000..aa361f3a86bb
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
> @@ -0,0 +1,48 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2023 Inochi Amaoto <[email protected]>
> + */
> +
> +/dts-v1/;
> +
> +#include "cv1812h.dtsi"
> +
> +/ {
> + model = "Huashan Pi";
> + compatible = "sophgo,huashan-pi", "sophgo,cv1812h";
> +
> + aliases {
> + gpio0 = &gpio0;
> + gpio1 = &gpio1;
> + gpio2 = &gpio2;
> + gpio3 = &gpio3;
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + serial3 = &uart3;
> + serial4 = &uart4;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + reserved-memory {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + coprocessor_rtos: region@8fe00000 {
> + reg = <0x8fe00000 0x200000>;
> + no-map;
> + };
> + };
> +};
> +
> +&osc {
> + clock-frequency = <25000000>;
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> --
> 2.42.0
>
On 2023/10/19 7:18, Inochi Amaoto wrote:
> Add initial device tree for the CV1812H RISC-V SoC by SOPHGO.
>
> Signed-off-by: Inochi Amaoto <[email protected]>
LGTM.
Acked-by: Chen Wang <[email protected]>
> ---
> arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
> create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi
>
> diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> new file mode 100644
> index 000000000000..3e7a942f5c1a
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> @@ -0,0 +1,24 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2023 Inochi Amaoto <[email protected]>
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include "cv18xx.dtsi"
> +
> +/ {
> + compatible = "sophgo,cv1812h";
> +
> + memory@80000000 {
> + device_type = "memory";
> + reg = <0x80000000 0x10000000>;
> + };
> +};
> +
> +&plic {
> + compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
> +};
> +
> +&clint {
> + compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
> +};
> --
> 2.42.0
>
On 2023/10/19 7:18, Inochi Amaoto wrote:
> Add common GPIO devices for the CV180x and CV181x soc.
>
> Signed-off-by: Inochi Amaoto <[email protected]>
> Reviewed-by: Jisheng Zhang <[email protected]>
LGTM.
Acked-by: Chen Wang <[email protected]>
> ---
> arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 73 ++++++++++++++++++++++++++
> 1 file changed, 73 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> index 55d4bc84faa0..d415cc758def 100644
> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> @@ -1,6 +1,7 @@
> // SPDX-License-Identifier: (GPL-2.0 OR MIT)
> /*
> * Copyright (C) 2023 Jisheng Zhang <[email protected]>
> + * Copyright (C) 2023 Inochi Amaoto <[email protected]>
> */
>
> #include <dt-bindings/interrupt-controller/irq.h>
> @@ -53,6 +54,78 @@ soc {
> dma-noncoherent;
> ranges;
>
> + gpio0: gpio@3020000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0x3020000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + porta: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + gpio1: gpio@3021000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0x3021000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + portb: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + gpio2: gpio@3022000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0x3022000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + portc: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + gpio3: gpio@3023000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0x3023000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + portd: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> uart0: serial@4140000 {
> compatible = "snps,dw-apb-uart";
> reg = <0x04140000 0x100>;
> --
> 2.42.0
>
On 2023/10/19 7:18, Inochi Amaoto wrote:
> As CV180x and CV181x have the identical layouts, it is OK to use the
> cv1800b basic device tree for the whole series.
> For CV1800B soc specific compatible, just move them out of the common
> file.
>
> Signed-off-by: Inochi Amaoto <[email protected]>
Thanks, it looks good now.
Acked-by: Chen Wang <[email protected]>
> ---
> arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 119 ++---------------------
> arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 120 ++++++++++++++++++++++++
> 2 files changed, 127 insertions(+), 112 deletions(-)
> create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx.dtsi
>
> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> index df40e87ee063..165e9e320a8c 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> @@ -3,121 +3,16 @@
> * Copyright (C) 2023 Jisheng Zhang <[email protected]>
> */
>
> -#include <dt-bindings/interrupt-controller/irq.h>
> +#include "cv18xx.dtsi"
>
> / {
> compatible = "sophgo,cv1800b";
> - #address-cells = <1>;
> - #size-cells = <1>;
> -
> - cpus: cpus {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - timebase-frequency = <25000000>;
> -
> - cpu0: cpu@0 {
> - compatible = "thead,c906", "riscv";
> - device_type = "cpu";
> - reg = <0>;
> - d-cache-block-size = <64>;
> - d-cache-sets = <512>;
> - d-cache-size = <65536>;
> - i-cache-block-size = <64>;
> - i-cache-sets = <128>;
> - i-cache-size = <32768>;
> - mmu-type = "riscv,sv39";
> - riscv,isa = "rv64imafdc";
> - riscv,isa-base = "rv64i";
> - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> - "zifencei", "zihpm";
> -
> - cpu0_intc: interrupt-controller {
> - compatible = "riscv,cpu-intc";
> - interrupt-controller;
> - #address-cells = <0>;
> - #interrupt-cells = <1>;
> - };
> - };
> - };
> -
> - osc: oscillator {
> - compatible = "fixed-clock";
> - clock-output-names = "osc_25m";
> - #clock-cells = <0>;
> - };
> -
> - soc {
> - compatible = "simple-bus";
> - interrupt-parent = <&plic>;
> - #address-cells = <1>;
> - #size-cells = <1>;
> - dma-noncoherent;
> - ranges;
> -
> - uart0: serial@4140000 {
> - compatible = "snps,dw-apb-uart";
> - reg = <0x04140000 0x100>;
> - interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&osc>;
> - reg-shift = <2>;
> - reg-io-width = <4>;
> - status = "disabled";
> - };
> -
> - uart1: serial@4150000 {
> - compatible = "snps,dw-apb-uart";
> - reg = <0x04150000 0x100>;
> - interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&osc>;
> - reg-shift = <2>;
> - reg-io-width = <4>;
> - status = "disabled";
> - };
> -
> - uart2: serial@4160000 {
> - compatible = "snps,dw-apb-uart";
> - reg = <0x04160000 0x100>;
> - interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&osc>;
> - reg-shift = <2>;
> - reg-io-width = <4>;
> - status = "disabled";
> - };
> -
> - uart3: serial@4170000 {
> - compatible = "snps,dw-apb-uart";
> - reg = <0x04170000 0x100>;
> - interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&osc>;
> - reg-shift = <2>;
> - reg-io-width = <4>;
> - status = "disabled";
> - };
> -
> - uart4: serial@41c0000 {
> - compatible = "snps,dw-apb-uart";
> - reg = <0x041c0000 0x100>;
> - interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&osc>;
> - reg-shift = <2>;
> - reg-io-width = <4>;
> - status = "disabled";
> - };
> +};
>
> - plic: interrupt-controller@70000000 {
> - compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
> - reg = <0x70000000 0x4000000>;
> - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> - interrupt-controller;
> - #address-cells = <0>;
> - #interrupt-cells = <2>;
> - riscv,ndev = <101>;
> - };
> +&plic {
> + compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
> +};
>
> - clint: timer@74000000 {
> - compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
> - reg = <0x74000000 0x10000>;
> - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> - };
> - };
> +&clint {
> + compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
> };
> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> new file mode 100644
> index 000000000000..55d4bc84faa0
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> @@ -0,0 +1,120 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2023 Jisheng Zhang <[email protected]>
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpus: cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <25000000>;
> +
> + cpu0: cpu@0 {
> + compatible = "thead,c906", "riscv";
> + device_type = "cpu";
> + reg = <0>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <512>;
> + d-cache-size = <65536>;
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + mmu-type = "riscv,sv39";
> + riscv,isa = "rv64imafdc";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> + "zifencei", "zihpm";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + };
> + };
> + };
> +
> + osc: oscillator {
> + compatible = "fixed-clock";
> + clock-output-names = "osc_25m";
> + #clock-cells = <0>;
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + interrupt-parent = <&plic>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + dma-noncoherent;
> + ranges;
> +
> + uart0: serial@4140000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x04140000 0x100>;
> + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart1: serial@4150000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x04150000 0x100>;
> + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart2: serial@4160000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x04160000 0x100>;
> + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart3: serial@4170000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x04170000 0x100>;
> + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart4: serial@41c0000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x041c0000 0x100>;
> + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + plic: interrupt-controller@70000000 {
> + reg = <0x70000000 0x4000000>;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + riscv,ndev = <101>;
> + };
> +
> + clint: timer@74000000 {
> + reg = <0x74000000 0x10000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
> + };
> + };
> +};
> --
> 2.42.0
>
Hey,
On Thu, Oct 19, 2023 at 07:18:00AM +0800, Inochi Amaoto wrote:
> Huashan Pi board is an embedded development platform based on the
> CV1812H chip. Add minimal device tree files for this board.
> Currently, it can boot to a basic shell.
Just pointing out that this series is too late for v6.7, so you probably
won't hear anything from me until v6.7-rc1 has been tagged.
Cheers,
Conor.
>
> NOTE: this series is based on the Jisheng's Milk-V Duo patch.
>
> Link: https://en.sophgo.com/product/introduce/huashan.html
> Link: https://en.sophgo.com/product/introduce/cv181xH.html
> Link: https://lore.kernel.org/linux-riscv/[email protected]/
>
> Changed from v3:
> 1. merge the patch 4 and 5 of v2 to preserve bisectability.
>
> Changed from v2:
> 1. use dt override to save code.
> 2. code cleanup.
>
> Changed from v1:
> 1. split the patch into several patch and refactor them.
>
> Inochi Amaoto (7):
> dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic
> dt-bindings: timer: Add SOPHGO CV1812H clint
> dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles
> riscv: dts: sophgo: Separate compatible specific for CV1800B soc
> riscv: dts: sophgo: cv18xx: Add gpio devices
> riscv: dts: sophgo: add initial CV1812H SoC device tree
> riscv: dts: sophgo: add Huashan Pi board device tree
>
> .../sifive,plic-1.0.0.yaml | 1 +
> .../devicetree/bindings/riscv/sophgo.yaml | 4 +
> .../bindings/timer/sifive,clint.yaml | 1 +
> arch/riscv/boot/dts/sophgo/Makefile | 1 +
> arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 119 +----------
> .../boot/dts/sophgo/cv1812h-huashan-pi.dts | 48 +++++
> arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 24 +++
> arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 193 ++++++++++++++++++
> 8 files changed, 279 insertions(+), 112 deletions(-)
> create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
> create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h.dtsi
> create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx.dtsi
>
> --
> 2.42.0
>
From: Conor Dooley <[email protected]>
On Thu, 19 Oct 2023 07:18:00 +0800, Inochi Amaoto wrote:
> Huashan Pi board is an embedded development platform based on the
> CV1812H chip. Add minimal device tree files for this board.
> Currently, it can boot to a basic shell.
>
> NOTE: this series is based on the Jisheng's Milk-V Duo patch.
>
> Link: https://en.sophgo.com/product/introduce/huashan.html
> Link: https://en.sophgo.com/product/introduce/cv181xH.html
> Link: https://lore.kernel.org/linux-riscv/[email protected]/
>
> [...]
Applied to riscv-dt-for-next, thanks! LMK if something looks not as
expected.
[1/7] dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic
https://git.kernel.org/conor/c/21a34e63afcc
[2/7] dt-bindings: timer: Add SOPHGO CV1812H clint
https://git.kernel.org/conor/c/06ea2a1968a9
[3/7] dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles
https://git.kernel.org/conor/c/d7b92027834e
[4/7] riscv: dts: sophgo: Separate compatible specific for CV1800B soc
https://git.kernel.org/conor/c/5b5dce3951b2
[5/7] riscv: dts: sophgo: cv18xx: Add gpio devices
https://git.kernel.org/conor/c/dd791b45c866
[6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree
https://git.kernel.org/conor/c/681ec684a741
[7/7] riscv: dts: sophgo: add Huashan Pi board device tree
https://git.kernel.org/conor/c/2c36b0cfb408
Thanks,
Conor.
>
>On Thu, 19 Oct 2023 07:18:00 +0800, Inochi Amaoto wrote:
>> Huashan Pi board is an embedded development platform based on the
>> CV1812H chip. Add minimal device tree files for this board.
>> Currently, it can boot to a basic shell.
>>
>> NOTE: this series is based on the Jisheng's Milk-V Duo patch.
>>
>> Link: https://en.sophgo.com/product/introduce/huashan.html
>> Link: https://en.sophgo.com/product/introduce/cv181xH.html
>> Link: https://lore.kernel.org/linux-riscv/[email protected]/
>>
>> [...]
>
>Applied to riscv-dt-for-next, thanks! LMK if something looks not as
>expected.
>
>[1/7] dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic
> https://git.kernel.org/conor/c/21a34e63afcc
>[2/7] dt-bindings: timer: Add SOPHGO CV1812H clint
> https://git.kernel.org/conor/c/06ea2a1968a9
>[3/7] dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles
> https://git.kernel.org/conor/c/d7b92027834e
>[4/7] riscv: dts: sophgo: Separate compatible specific for CV1800B soc
> https://git.kernel.org/conor/c/5b5dce3951b2
>[5/7] riscv: dts: sophgo: cv18xx: Add gpio devices
> https://git.kernel.org/conor/c/dd791b45c866
>[6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree
> https://git.kernel.org/conor/c/681ec684a741
>[7/7] riscv: dts: sophgo: add Huashan Pi board device tree
> https://git.kernel.org/conor/c/2c36b0cfb408
>
>Thanks,
>Conor.
>
Hi Conor,
Thanks for the confirmation. But I suggest to revert these patches.
Several days ago, Sophgo informed me that CV1810 series will be
renamed. And the Huashan Pi will switch to the chip with new name.
To avoid unnecessary conflict, please drop these patch and I will
prepare a new patch once the renamed chip is launched.
Sorry for this inconvenience.
On Fri, Dec 01, 2023 at 07:21:29AM +0800, Inochi Amaoto wrote:
> >
> >On Thu, 19 Oct 2023 07:18:00 +0800, Inochi Amaoto wrote:
> >> Huashan Pi board is an embedded development platform based on the
> >> CV1812H chip. Add minimal device tree files for this board.
> >> Currently, it can boot to a basic shell.
> >>
> >> NOTE: this series is based on the Jisheng's Milk-V Duo patch.
> >>
> >> Link: https://en.sophgo.com/product/introduce/huashan.html
> >> Link: https://en.sophgo.com/product/introduce/cv181xH.html
> >> Link: https://lore.kernel.org/linux-riscv/[email protected]/
> >>
> >> [...]
> >
> >Applied to riscv-dt-for-next, thanks! LMK if something looks not as
> >expected.
> >
> >[1/7] dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic
> > https://git.kernel.org/conor/c/21a34e63afcc
> >[2/7] dt-bindings: timer: Add SOPHGO CV1812H clint
> > https://git.kernel.org/conor/c/06ea2a1968a9
> >[3/7] dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles
> > https://git.kernel.org/conor/c/d7b92027834e
> >[4/7] riscv: dts: sophgo: Separate compatible specific for CV1800B soc
> > https://git.kernel.org/conor/c/5b5dce3951b2
> >[5/7] riscv: dts: sophgo: cv18xx: Add gpio devices
> > https://git.kernel.org/conor/c/dd791b45c866
> >[6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree
> > https://git.kernel.org/conor/c/681ec684a741
> >[7/7] riscv: dts: sophgo: add Huashan Pi board device tree
> > https://git.kernel.org/conor/c/2c36b0cfb408
> >
> >Thanks,
> >Conor.
> >
>
> Hi Conor,
>
> Thanks for the confirmation. But I suggest to revert these patches.
> Several days ago, Sophgo informed me that CV1810 series will be
> renamed. And the Huashan Pi will switch to the chip with new name.
> To avoid unnecessary conflict, please drop these patch and I will
> prepare a new patch once the renamed chip is launched.
This is a board that exists, that you (and possibly others) have, right?
>
>On Fri, Dec 01, 2023 at 07:21:29AM +0800, Inochi Amaoto wrote:
>>>
>>> On Thu, 19 Oct 2023 07:18:00 +0800, Inochi Amaoto wrote:
>>>> Huashan Pi board is an embedded development platform based on the
>>>> CV1812H chip. Add minimal device tree files for this board.
>>>> Currently, it can boot to a basic shell.
>>>>
>>>> NOTE: this series is based on the Jisheng's Milk-V Duo patch.
>>>>
>>>> Link: https://en.sophgo.com/product/introduce/huashan.html
>>>> Link: https://en.sophgo.com/product/introduce/cv181xH.html
>>>> Link: https://lore.kernel.org/linux-riscv/[email protected]/
>>>>
>>>> [...]
>>>
>>> Applied to riscv-dt-for-next, thanks! LMK if something looks not as
>>> expected.
>>>
>>> [1/7] dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic
>>> https://git.kernel.org/conor/c/21a34e63afcc
>>> [2/7] dt-bindings: timer: Add SOPHGO CV1812H clint
>>> https://git.kernel.org/conor/c/06ea2a1968a9
>>> [3/7] dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles
>>> https://git.kernel.org/conor/c/d7b92027834e
>>> [4/7] riscv: dts: sophgo: Separate compatible specific for CV1800B soc
>>> https://git.kernel.org/conor/c/5b5dce3951b2
>>> [5/7] riscv: dts: sophgo: cv18xx: Add gpio devices
>>> https://git.kernel.org/conor/c/dd791b45c866
>>> [6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree
>>> https://git.kernel.org/conor/c/681ec684a741
>>> [7/7] riscv: dts: sophgo: add Huashan Pi board device tree
>>> https://git.kernel.org/conor/c/2c36b0cfb408
>>>
>>> Thanks,
>>> Conor.
>>>
>>
>> Hi Conor,
>>
>> Thanks for the confirmation. But I suggest to revert these patches.
>> Several days ago, Sophgo informed me that CV1810 series will be
>> renamed. And the Huashan Pi will switch to the chip with new name.
>> To avoid unnecessary conflict, please drop these patch and I will
>> prepare a new patch once the renamed chip is launched.
>
>This is a board that exists, that you (and possibly others) have, right?
>
Yes, of course.
On Fri, Dec 01, 2023 at 09:02:59AM +0800, Inochi Amaoto wrote:
> >
> >On Fri, Dec 01, 2023 at 07:21:29AM +0800, Inochi Amaoto wrote:
> >>>
> >>> On Thu, 19 Oct 2023 07:18:00 +0800, Inochi Amaoto wrote:
> >>>> Huashan Pi board is an embedded development platform based on the
> >>>> CV1812H chip. Add minimal device tree files for this board.
> >>>> Currently, it can boot to a basic shell.
> >>>>
> >>>> NOTE: this series is based on the Jisheng's Milk-V Duo patch.
> >>>>
> >>>> Link: https://en.sophgo.com/product/introduce/huashan.html
> >>>> Link: https://en.sophgo.com/product/introduce/cv181xH.html
> >>>> Link: https://lore.kernel.org/linux-riscv/[email protected]/
> >>>>
> >>>> [...]
> >>>
> >>> Applied to riscv-dt-for-next, thanks! LMK if something looks not as
> >>> expected.
> >>>
> >>> [1/7] dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic
> >>> https://git.kernel.org/conor/c/21a34e63afcc
> >>> [2/7] dt-bindings: timer: Add SOPHGO CV1812H clint
> >>> https://git.kernel.org/conor/c/06ea2a1968a9
> >>> [3/7] dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles
> >>> https://git.kernel.org/conor/c/d7b92027834e
> >>> [4/7] riscv: dts: sophgo: Separate compatible specific for CV1800B soc
> >>> https://git.kernel.org/conor/c/5b5dce3951b2
> >>> [5/7] riscv: dts: sophgo: cv18xx: Add gpio devices
> >>> https://git.kernel.org/conor/c/dd791b45c866
> >>> [6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree
> >>> https://git.kernel.org/conor/c/681ec684a741
> >>> [7/7] riscv: dts: sophgo: add Huashan Pi board device tree
> >>> https://git.kernel.org/conor/c/2c36b0cfb408
> >> Thanks for the confirmation. But I suggest to revert these patches.
> >> Several days ago, Sophgo informed me that CV1810 series will be
> >> renamed. And the Huashan Pi will switch to the chip with new name.
> >> To avoid unnecessary conflict, please drop these patch and I will
> >> prepare a new patch once the renamed chip is launched.
> >
> >This is a board that exists, that you (and possibly others) have, right?
> >
>
> Yes, of course.
I dunno then. It sounds from your message that this is purely a rebrand
of the SoCs, so since people already have these boards, I'd rather not.
We should be able to support both since it's just a naming change,
right?
>
>On Fri, Dec 01, 2023 at 09:02:59AM +0800, Inochi Amaoto wrote:
>>>
>>> On Fri, Dec 01, 2023 at 07:21:29AM +0800, Inochi Amaoto wrote:
>>>>>
>>>>> On Thu, 19 Oct 2023 07:18:00 +0800, Inochi Amaoto wrote:
>>>>>> Huashan Pi board is an embedded development platform based on the
>>>>>> CV1812H chip. Add minimal device tree files for this board.
>>>>>> Currently, it can boot to a basic shell.
>>>>>>
>>>>>> NOTE: this series is based on the Jisheng's Milk-V Duo patch.
>>>>>>
>>>>>> Link: https://en.sophgo.com/product/introduce/huashan.html
>>>>>> Link: https://en.sophgo.com/product/introduce/cv181xH.html
>>>>>> Link: https://lore.kernel.org/linux-riscv/[email protected]/
>>>>>>
>>>>>> [...]
>>>>>
>>>>> Applied to riscv-dt-for-next, thanks! LMK if something looks not as
>>>>> expected.
>>>>>
>>>>> [1/7] dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic
>>>>> https://git.kernel.org/conor/c/21a34e63afcc
>>>>> [2/7] dt-bindings: timer: Add SOPHGO CV1812H clint
>>>>> https://git.kernel.org/conor/c/06ea2a1968a9
>>>>> [3/7] dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles
>>>>> https://git.kernel.org/conor/c/d7b92027834e
>>>>> [4/7] riscv: dts: sophgo: Separate compatible specific for CV1800B soc
>>>>> https://git.kernel.org/conor/c/5b5dce3951b2
>>>>> [5/7] riscv: dts: sophgo: cv18xx: Add gpio devices
>>>>> https://git.kernel.org/conor/c/dd791b45c866
>>>>> [6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree
>>>>> https://git.kernel.org/conor/c/681ec684a741
>>>>> [7/7] riscv: dts: sophgo: add Huashan Pi board device tree
>>>>> https://git.kernel.org/conor/c/2c36b0cfb408
>
>>>> Thanks for the confirmation. But I suggest to revert these patches.
>>>> Several days ago, Sophgo informed me that CV1810 series will be
>>>> renamed. And the Huashan Pi will switch to the chip with new name.
>>>> To avoid unnecessary conflict, please drop these patch and I will
>>>> prepare a new patch once the renamed chip is launched.
>>>
>>> This is a board that exists, that you (and possibly others) have, right?
>>>
>>
>> Yes, of course.
>
>I dunno then. It sounds from your message that this is purely a rebrand
>of the SoCs,
IIRC, it is.
FYI, Chen and Chao. Maybe you know something more.
>so since people already have these boards, I'd rather not.
>We should be able to support both since it's just a naming change,
>right?
I agree with this. If the above is true, we can just reuse the exists code
with a different compatible name, right?
On Fri, Dec 01, 2023 at 04:31:38PM +0800, Inochi Amaoto wrote:
> >
> >On Fri, Dec 01, 2023 at 09:02:59AM +0800, Inochi Amaoto wrote:
> >>>
> >>> On Fri, Dec 01, 2023 at 07:21:29AM +0800, Inochi Amaoto wrote:
> >>>>>
> >>>>> On Thu, 19 Oct 2023 07:18:00 +0800, Inochi Amaoto wrote:
> >>>>>> Huashan Pi board is an embedded development platform based on the
> >>>>>> CV1812H chip. Add minimal device tree files for this board.
> >>>>>> Currently, it can boot to a basic shell.
> >>>>>>
> >>>>>> NOTE: this series is based on the Jisheng's Milk-V Duo patch.
> >>>>>>
> >>>>>> Link: https://en.sophgo.com/product/introduce/huashan.html
> >>>>>> Link: https://en.sophgo.com/product/introduce/cv181xH.html
> >>>>>> Link: https://lore.kernel.org/linux-riscv/[email protected]/
> >>>>>>
> >>>>>> [...]
> >>>>>
> >>>>> Applied to riscv-dt-for-next, thanks! LMK if something looks not as
> >>>>> expected.
> >>>>>
> >>>>> [1/7] dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic
> >>>>> https://git.kernel.org/conor/c/21a34e63afcc
> >>>>> [2/7] dt-bindings: timer: Add SOPHGO CV1812H clint
> >>>>> https://git.kernel.org/conor/c/06ea2a1968a9
> >>>>> [3/7] dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles
> >>>>> https://git.kernel.org/conor/c/d7b92027834e
> >>>>> [4/7] riscv: dts: sophgo: Separate compatible specific for CV1800B soc
> >>>>> https://git.kernel.org/conor/c/5b5dce3951b2
> >>>>> [5/7] riscv: dts: sophgo: cv18xx: Add gpio devices
> >>>>> https://git.kernel.org/conor/c/dd791b45c866
> >>>>> [6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree
> >>>>> https://git.kernel.org/conor/c/681ec684a741
> >>>>> [7/7] riscv: dts: sophgo: add Huashan Pi board device tree
> >>>>> https://git.kernel.org/conor/c/2c36b0cfb408
> >
> >>>> Thanks for the confirmation. But I suggest to revert these patches.
> >>>> Several days ago, Sophgo informed me that CV1810 series will be
> >>>> renamed. And the Huashan Pi will switch to the chip with new name.
> >>>> To avoid unnecessary conflict, please drop these patch and I will
> >>>> prepare a new patch once the renamed chip is launched.
> >>>
> >>> This is a board that exists, that you (and possibly others) have, right?
> >>>
> >>
> >> Yes, of course.
> >
> >I dunno then. It sounds from your message that this is purely a rebrand
> >of the SoCs,
>
> IIRC, it is.
> FYI, Chen and Chao. Maybe you know something more.
>
> >so since people already have these boards, I'd rather not.
> >We should be able to support both since it's just a naming change,
> >right?
>
> I agree with this. If the above is true, we can just reuse the exists code
> with a different compatible name, right?
I think so? I'm not sure what the precedent really is for pure
rebrandings of an SoC.
I say for now, assume we can do that, and we can discuss it with Rob and
Krzysztof when the time comes if there is no difference between the SoCs
and boards.
Cheers,
Conor.
>
>On Fri, Dec 01, 2023 at 04:31:38PM +0800, Inochi Amaoto wrote:
>>>
>>> On Fri, Dec 01, 2023 at 09:02:59AM +0800, Inochi Amaoto wrote:
>>>>>
>>>>> On Fri, Dec 01, 2023 at 07:21:29AM +0800, Inochi Amaoto wrote:
>>>>>>>
>>>>>>> On Thu, 19 Oct 2023 07:18:00 +0800, Inochi Amaoto wrote:
>>>>>>>> Huashan Pi board is an embedded development platform based on the
>>>>>>>> CV1812H chip. Add minimal device tree files for this board.
>>>>>>>> Currently, it can boot to a basic shell.
>>>>>>>>
>>>>>>>> NOTE: this series is based on the Jisheng's Milk-V Duo patch.
>>>>>>>>
>>>>>>>> Link: https://en.sophgo.com/product/introduce/huashan.html
>>>>>>>> Link: https://en.sophgo.com/product/introduce/cv181xH.html
>>>>>>>> Link: https://lore.kernel.org/linux-riscv/[email protected]/
>>>>>>>>
>>>>>>>> [...]
>>>>>>>
>>>>>>> Applied to riscv-dt-for-next, thanks! LMK if something looks not as
>>>>>>> expected.
>>>>>>>
>>>>>>> [1/7] dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic
>>>>>>> https://git.kernel.org/conor/c/21a34e63afcc
>>>>>>> [2/7] dt-bindings: timer: Add SOPHGO CV1812H clint
>>>>>>> https://git.kernel.org/conor/c/06ea2a1968a9
>>>>>>> [3/7] dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles
>>>>>>> https://git.kernel.org/conor/c/d7b92027834e
>>>>>>> [4/7] riscv: dts: sophgo: Separate compatible specific for CV1800B soc
>>>>>>> https://git.kernel.org/conor/c/5b5dce3951b2
>>>>>>> [5/7] riscv: dts: sophgo: cv18xx: Add gpio devices
>>>>>>> https://git.kernel.org/conor/c/dd791b45c866
>>>>>>> [6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree
>>>>>>> https://git.kernel.org/conor/c/681ec684a741
>>>>>>> [7/7] riscv: dts: sophgo: add Huashan Pi board device tree
>>>>>>> https://git.kernel.org/conor/c/2c36b0cfb408
>>>
>>>>>> Thanks for the confirmation. But I suggest to revert these patches.
>>>>>> Several days ago, Sophgo informed me that CV1810 series will be
>>>>>> renamed. And the Huashan Pi will switch to the chip with new name.
>>>>>> To avoid unnecessary conflict, please drop these patch and I will
>>>>>> prepare a new patch once the renamed chip is launched.
>>>>>
>>>>> This is a board that exists, that you (and possibly others) have, right?
>>>>>
>>>>
>>>> Yes, of course.
>>>
>>> I dunno then. It sounds from your message that this is purely a rebrand
>>> of the SoCs,
>>
>> IIRC, it is.
>> FYI, Chen and Chao. Maybe you know something more.
>>
>>> so since people already have these boards, I'd rather not.
>>> We should be able to support both since it's just a naming change,
>>> right?
>>
>> I agree with this. If the above is true, we can just reuse the exists code
>> with a different compatible name, right?
>
>I think so? I'm not sure what the precedent really is for pure
>rebrandings of an SoC.
>I say for now, assume we can do that, and we can discuss it with Rob and
>Krzysztof when the time comes if there is no difference between the SoCs
>and boards.
>
OK, now let's reserve these code and discuss when the board with
those SoCs come. Thanks for your explanation.
>Cheers,
>Conor.
>
>
On 2023/12/2 0:21, Conor Dooley wrote:
> On Fri, Dec 01, 2023 at 04:31:38PM +0800, Inochi Amaoto wrote:
>>> On Fri, Dec 01, 2023 at 09:02:59AM +0800, Inochi Amaoto wrote:
>>>>> On Fri, Dec 01, 2023 at 07:21:29AM +0800, Inochi Amaoto wrote:
>>>>>>> On Thu, 19 Oct 2023 07:18:00 +0800, Inochi Amaoto wrote:
>>>>>>>> Huashan Pi board is an embedded development platform based on the
>>>>>>>> CV1812H chip. Add minimal device tree files for this board.
>>>>>>>> Currently, it can boot to a basic shell.
>>>>>>>>
>>>>>>>> NOTE: this series is based on the Jisheng's Milk-V Duo patch.
>>>>>>>>
>>>>>>>> Link: https://en.sophgo.com/product/introduce/huashan.html
>>>>>>>> Link: https://en.sophgo.com/product/introduce/cv181xH.html
>>>>>>>> Link: https://lore.kernel.org/linux-riscv/[email protected]/
>>>>>>>>
>>>>>>>> [...]
>>>>>>> Applied to riscv-dt-for-next, thanks! LMK if something looks not as
>>>>>>> expected.
>>>>>>>
>>>>>>> [1/7] dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic
>>>>>>> https://git.kernel.org/conor/c/21a34e63afcc
>>>>>>> [2/7] dt-bindings: timer: Add SOPHGO CV1812H clint
>>>>>>> https://git.kernel.org/conor/c/06ea2a1968a9
>>>>>>> [3/7] dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles
>>>>>>> https://git.kernel.org/conor/c/d7b92027834e
>>>>>>> [4/7] riscv: dts: sophgo: Separate compatible specific for CV1800B soc
>>>>>>> https://git.kernel.org/conor/c/5b5dce3951b2
>>>>>>> [5/7] riscv: dts: sophgo: cv18xx: Add gpio devices
>>>>>>> https://git.kernel.org/conor/c/dd791b45c866
>>>>>>> [6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree
>>>>>>> https://git.kernel.org/conor/c/681ec684a741
>>>>>>> [7/7] riscv: dts: sophgo: add Huashan Pi board device tree
>>>>>>> https://git.kernel.org/conor/c/2c36b0cfb408
>>>>>> Thanks for the confirmation. But I suggest to revert these patches.
>>>>>> Several days ago, Sophgo informed me that CV1810 series will be
>>>>>> renamed. And the Huashan Pi will switch to the chip with new name.
>>>>>> To avoid unnecessary conflict, please drop these patch and I will
>>>>>> prepare a new patch once the renamed chip is launched.
>>>>> This is a board that exists, that you (and possibly others) have, right?
>>>>>
>>>> Yes, of course.
>>> I dunno then. It sounds from your message that this is purely a rebrand
>>> of the SoCs,
>> IIRC, it is.
>> FYI, Chen and Chao. Maybe you know something more.
>>
>>> so since people already have these boards, I'd rather not.
>>> We should be able to support both since it's just a naming change,
>>> right?
>> I agree with this. If the above is true, we can just reuse the exists code
>> with a different compatible name, right?
> I think so? I'm not sure what the precedent really is for pure
> rebrandings of an SoC.
> I say for now, assume we can do that, and we can discuss it with Rob and
> Krzysztof when the time comes if there is no difference between the SoCs
> and boards.
>
> Cheers,
> Conor.
As far as I know, sophgo's SoC product names all start with "sg", while
products starting with "cv" come from CVITEK (another chip company).
CVITEK was acquired by sophgo a year ago, so now many SOC product names
that originally started with "cv" are being repackaged and changed to
start with "sg".
For the cv1800b adopted by Duo, Sophgo has made it clear that it will
not change its codename.
But I heard that for other products, such as the cv1812h used by
Huashanpi, sophgo may change their names in the future, but sophgo has
not officially confirmed it yet. Looks like sophgo themselves are still
in the process of digesting cv's products, ;)
Since we have just started to support cv1812h and have not done much
work yet, I suggest not to merge this patch into the mainline, and wait
until there is clear news before doing this to avoid introducing
unnecessary modifications later.
Thanks,
Chen
On Sat, Dec 02, 2023 at 09:11:38AM +0800, Chen Wang wrote:
> As far as I know, sophgo's SoC product names all start with "sg", while
> products starting with "cv" come from CVITEK (another chip company). CVITEK
> was acquired by sophgo a year ago, so now many SOC product names that
> originally started with "cv" are being repackaged and changed to start with
> "sg".
>
> For the cv1800b adopted by Duo, Sophgo has made it clear that it will not
> change its codename.
>
> But I heard that for other products, such as the cv1812h used by Huashanpi,
> sophgo may change their names in the future, but sophgo has not officially
> confirmed it yet. Looks like sophgo themselves are still in the process of
> digesting cv's products, ;)
>
> Since we have just started to support cv1812h and have not done much work
> yet, I suggest not to merge this patch into the mainline, and wait until
> there is clear news before doing this to avoid introducing unnecessary
> modifications later.
If there are people who have the boards, I'd be inclined to make the
mainline kernel usable for them. Doing some renames or adding
compatibles down the road, if the SoC is actually rebranded, is not a big
deal. I'll leave it up to you guys as to what to do - it's only -rc4
today, so there's no impending doom.
Cheers,
Conor.
>On 2023/12/2 0:21, Conor Dooley wrote:
>> On Fri, Dec 01, 2023 at 04:31:38PM +0800, Inochi Amaoto wrote:
>>>> On Fri, Dec 01, 2023 at 09:02:59AM +0800, Inochi Amaoto wrote:
>>>>>> On Fri, Dec 01, 2023 at 07:21:29AM +0800, Inochi Amaoto wrote:
>>>>>>>> On Thu, 19 Oct 2023 07:18:00 +0800, Inochi Amaoto wrote:
>>>>>>>>> Huashan Pi board is an embedded development platform based on the
>>>>>>>>> CV1812H chip. Add minimal device tree files for this board.
>>>>>>>>> Currently, it can boot to a basic shell.
>>>>>>>>>
>>>>>>>>> NOTE: this series is based on the Jisheng's Milk-V Duo patch.
>>>>>>>>>
>>>>>>>>> Link: https://en.sophgo.com/product/introduce/huashan.html
>>>>>>>>> Link: https://en.sophgo.com/product/introduce/cv181xH.html
>>>>>>>>> Link: https://lore.kernel.org/linux-riscv/[email protected]/
>>>>>>>>>
>>>>>>>>> [...]
>>>>>>>> Applied to riscv-dt-for-next, thanks! LMK if something looks not as
>>>>>>>> expected.
>>>>>>>>
>>>>>>>> [1/7] dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic
>>>>>>>> https://git.kernel.org/conor/c/21a34e63afcc
>>>>>>>> [2/7] dt-bindings: timer: Add SOPHGO CV1812H clint
>>>>>>>> https://git.kernel.org/conor/c/06ea2a1968a9
>>>>>>>> [3/7] dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles
>>>>>>>> https://git.kernel.org/conor/c/d7b92027834e
>>>>>>>> [4/7] riscv: dts: sophgo: Separate compatible specific for CV1800B soc
>>>>>>>> https://git.kernel.org/conor/c/5b5dce3951b2
>>>>>>>> [5/7] riscv: dts: sophgo: cv18xx: Add gpio devices
>>>>>>>> https://git.kernel.org/conor/c/dd791b45c866
>>>>>>>> [6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree
>>>>>>>> https://git.kernel.org/conor/c/681ec684a741
>>>>>>>> [7/7] riscv: dts: sophgo: add Huashan Pi board device tree
>>>>>>>> https://git.kernel.org/conor/c/2c36b0cfb408
>>>>>>> Thanks for the confirmation. But I suggest to revert these patches.
>>>>>>> Several days ago, Sophgo informed me that CV1810 series will be
>>>>>>> renamed. And the Huashan Pi will switch to the chip with new name.
>>>>>>> To avoid unnecessary conflict, please drop these patch and I will
>>>>>>> prepare a new patch once the renamed chip is launched.
>>>>>> This is a board that exists, that you (and possibly others) have, right?
>>>>>>
>>>>> Yes, of course.
>>>> I dunno then. It sounds from your message that this is purely a rebrand
>>>> of the SoCs,
>>> IIRC, it is.
>>> FYI, Chen and Chao. Maybe you know something more.
>>>
>>>> so since people already have these boards, I'd rather not.
>>>> We should be able to support both since it's just a naming change,
>>>> right?
>>> I agree with this. If the above is true, we can just reuse the exists code
>>> with a different compatible name, right?
>> I think so? I'm not sure what the precedent really is for pure
>> rebrandings of an SoC.
>> I say for now, assume we can do that, and we can discuss it with Rob and
>> Krzysztof when the time comes if there is no difference between the SoCs
>> and boards.
>>
>> Cheers,
>> Conor.
>
>As far as I know, sophgo's SoC product names all start with "sg", while products starting with "cv" come from CVITEK (another chip company). CVITEK was acquired by sophgo a year ago, so now many SOC product names that originally started with "cv" are being repackaged and changed to start with "sg".
>
>For the cv1800b adopted by Duo, Sophgo has made it clear that it will not change its codename.
>
>But I heard that for other products, such as the cv1812h used by Huashanpi, sophgo may change their names in the future, but sophgo has not officially confirmed it yet. Looks like sophgo themselves are still in the process of digesting cv's products, ;)
>
>Since we have just started to support cv1812h and have not done much work yet, I suggest not to merge this patch into the mainline, and wait until there is clear news before doing this to avoid introducing unnecessary modifications later.
>
Hi Chen,
There is a update for you. The cv1812h does not have the A53 core as the
sg200x does. Maybe we should treat cv1812h as a trim of sg200x, not just
a reband.
According to this information, I suggest to preserve these code for
cv1812h, it can make upstream the new soc eaiser. Also, adding a new
compatible is not too hard, and it is necessary if we have new soc.
Otherwise, the one with Huashan Pi now may be confused because it have
a old version.
>Thanks,
>
>Chen
>
On 2023/12/4 7:32, Inochi Amaoto wrote:
>> On 2023/12/2 0:21, Conor Dooley wrote:
>>> On Fri, Dec 01, 2023 at 04:31:38PM +0800, Inochi Amaoto wrote:
>>>>> On Fri, Dec 01, 2023 at 09:02:59AM +0800, Inochi Amaoto wrote:
>>>>>>> On Fri, Dec 01, 2023 at 07:21:29AM +0800, Inochi Amaoto wrote:
>>>>>>>>> On Thu, 19 Oct 2023 07:18:00 +0800, Inochi Amaoto wrote:
>>>>>>>>>> Huashan Pi board is an embedded development platform based on the
>>>>>>>>>> CV1812H chip. Add minimal device tree files for this board.
>>>>>>>>>> Currently, it can boot to a basic shell.
>>>>>>>>>>
>>>>>>>>>> NOTE: this series is based on the Jisheng's Milk-V Duo patch.
>>>>>>>>>>
>>>>>>>>>> Link: https://en.sophgo.com/product/introduce/huashan.html
>>>>>>>>>> Link: https://en.sophgo.com/product/introduce/cv181xH.html
>>>>>>>>>> Link: https://lore.kernel.org/linux-riscv/[email protected]/
>>>>>>>>>>
>>>>>>>>>> [...]
>>>>>>>>> Applied to riscv-dt-for-next, thanks! LMK if something looks not as
>>>>>>>>> expected.
>>>>>>>>>
>>>>>>>>> [1/7] dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic
>>>>>>>>> https://git.kernel.org/conor/c/21a34e63afcc
>>>>>>>>> [2/7] dt-bindings: timer: Add SOPHGO CV1812H clint
>>>>>>>>> https://git.kernel.org/conor/c/06ea2a1968a9
>>>>>>>>> [3/7] dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles
>>>>>>>>> https://git.kernel.org/conor/c/d7b92027834e
>>>>>>>>> [4/7] riscv: dts: sophgo: Separate compatible specific for CV1800B soc
>>>>>>>>> https://git.kernel.org/conor/c/5b5dce3951b2
>>>>>>>>> [5/7] riscv: dts: sophgo: cv18xx: Add gpio devices
>>>>>>>>> https://git.kernel.org/conor/c/dd791b45c866
>>>>>>>>> [6/7] riscv: dts: sophgo: add initial CV1812H SoC device tree
>>>>>>>>> https://git.kernel.org/conor/c/681ec684a741
>>>>>>>>> [7/7] riscv: dts: sophgo: add Huashan Pi board device tree
>>>>>>>>> https://git.kernel.org/conor/c/2c36b0cfb408
>>>>>>>> Thanks for the confirmation. But I suggest to revert these patches.
>>>>>>>> Several days ago, Sophgo informed me that CV1810 series will be
>>>>>>>> renamed. And the Huashan Pi will switch to the chip with new name.
>>>>>>>> To avoid unnecessary conflict, please drop these patch and I will
>>>>>>>> prepare a new patch once the renamed chip is launched.
>>>>>>> This is a board that exists, that you (and possibly others) have, right?
>>>>>>>
>>>>>> Yes, of course.
>>>>> I dunno then. It sounds from your message that this is purely a rebrand
>>>>> of the SoCs,
>>>> IIRC, it is.
>>>> FYI, Chen and Chao. Maybe you know something more.
>>>>
>>>>> so since people already have these boards, I'd rather not.
>>>>> We should be able to support both since it's just a naming change,
>>>>> right?
>>>> I agree with this. If the above is true, we can just reuse the exists code
>>>> with a different compatible name, right?
>>> I think so? I'm not sure what the precedent really is for pure
>>> rebrandings of an SoC.
>>> I say for now, assume we can do that, and we can discuss it with Rob and
>>> Krzysztof when the time comes if there is no difference between the SoCs
>>> and boards.
>>>
>>> Cheers,
>>> Conor.
>> As far as I know, sophgo's SoC product names all start with "sg", while products starting with "cv" come from CVITEK (another chip company). CVITEK was acquired by sophgo a year ago, so now many SOC product names that originally started with "cv" are being repackaged and changed to start with "sg".
>>
>> For the cv1800b adopted by Duo, Sophgo has made it clear that it will not change its codename.
>>
>> But I heard that for other products, such as the cv1812h used by Huashanpi, sophgo may change their names in the future, but sophgo has not officially confirmed it yet. Looks like sophgo themselves are still in the process of digesting cv's products, ;)
>>
>> Since we have just started to support cv1812h and have not done much work yet, I suggest not to merge this patch into the mainline, and wait until there is clear news before doing this to avoid introducing unnecessary modifications later.
>>
> Hi Chen,
>
> There is a update for you. The cv1812h does not have the A53 core as the
> sg200x does. Maybe we should treat cv1812h as a trim of sg200x, not just
> a reband.
>
> According to this information, I suggest to preserve these code for
> cv1812h, it can make upstream the new soc eaiser. Also, adding a new
> compatible is not too hard, and it is necessary if we have new soc.
> Otherwise, the one with Huashan Pi now may be confused because it have
> a old version.
Thanks Inochi for your info, let's just preserve these code for huashan
pi now and keep watching on what's going on then.
Regards,
Chen
>
>> Thanks,
>>
>> Chen
>>
On Mon, Dec 04, 2023 at 05:15:36PM +0800, Chen Wang wrote:
>
> On 2023/12/4 7:32, Inochi Amaoto wrote:
> > > On 2023/12/2 0:21, Conor Dooley wrote:
> > > As far as I know, sophgo's SoC product names all start with "sg", while products starting with "cv" come from CVITEK (another chip company). CVITEK was acquired by sophgo a year ago, so now many SOC product names that originally started with "cv" are being repackaged and changed to start with "sg".
> > >
> > > For the cv1800b adopted by Duo, Sophgo has made it clear that it will not change its codename.
> > >
> > > But I heard that for other products, such as the cv1812h used by Huashanpi, sophgo may change their names in the future, but sophgo has not officially confirmed it yet. Looks like sophgo themselves are still in the process of digesting cv's products, ;)
> > >
> > > Since we have just started to support cv1812h and have not done much work yet, I suggest not to merge this patch into the mainline, and wait until there is clear news before doing this to avoid introducing unnecessary modifications later.
> > >
> > Hi Chen,
> >
> > There is a update for you. The cv1812h does not have the A53 core as the
> > sg200x does. Maybe we should treat cv1812h as a trim of sg200x, not just
> > a reband.
> >
> > According to this information, I suggest to preserve these code for
> > cv1812h, it can make upstream the new soc eaiser. Also, adding a new
> > compatible is not too hard, and it is necessary if we have new soc.
> > Otherwise, the one with Huashan Pi now may be confused because it have
> > a old version.
>
> Thanks Inochi for your info, let's just preserve these code for huashan pi
> now and keep watching on what's going on then.
Could you explain on what you mean by "preserve"? I'm a little unsure.
On 2023/12/4 17:32, Conor Dooley wrote:
> On Mon, Dec 04, 2023 at 05:15:36PM +0800, Chen Wang wrote:
>> On 2023/12/4 7:32, Inochi Amaoto wrote:
>>>> On 2023/12/2 0:21, Conor Dooley wrote:
>>>> As far as I know, sophgo's SoC product names all start with "sg", while products starting with "cv" come from CVITEK (another chip company). CVITEK was acquired by sophgo a year ago, so now many SOC product names that originally started with "cv" are being repackaged and changed to start with "sg".
>>>>
>>>> For the cv1800b adopted by Duo, Sophgo has made it clear that it will not change its codename.
>>>>
>>>> But I heard that for other products, such as the cv1812h used by Huashanpi, sophgo may change their names in the future, but sophgo has not officially confirmed it yet. Looks like sophgo themselves are still in the process of digesting cv's products, ;)
>>>>
>>>> Since we have just started to support cv1812h and have not done much work yet, I suggest not to merge this patch into the mainline, and wait until there is clear news before doing this to avoid introducing unnecessary modifications later.
>>>>
>>> Hi Chen,
>>>
>>> There is a update for you. The cv1812h does not have the A53 core as the
>>> sg200x does. Maybe we should treat cv1812h as a trim of sg200x, not just
>>> a reband.
>>>
>>> According to this information, I suggest to preserve these code for
>>> cv1812h, it can make upstream the new soc eaiser. Also, adding a new
>>> compatible is not too hard, and it is necessary if we have new soc.
>>> Otherwise, the one with Huashan Pi now may be confused because it have
>>> a old version.
>> Thanks Inochi for your info, let's just preserve these code for huashan pi
>> now and keep watching on what's going on then.
> Could you explain on what you mean by "preserve"? I'm a little unsure.
hi, Conor,
I meant keeping your changes on riscv-dt-for-next and continue
submitting this patch ([PATCH v4 0/7] Add Huashan Pi board support) to
upstream.
Sorry for my poor english, hope I have explained it well. :$
Thanks,
Chen
> > > Thanks Inochi for your info, let's just preserve these code for huashan pi
> > > now and keep watching on what's going on then.
> > Could you explain on what you mean by "preserve"? I'm a little unsure.
>
> I meant keeping your changes on riscv-dt-for-next and continue submitting
> this patch ([PATCH v4 0/7] Add Huashan Pi board support) to upstream.
>
> Sorry for my poor english, hope I have explained it well. :$
I thought that was what you meant, but I just wanted to make sure :)
Thanks for explaining it again,
Conor.