As Piyush is leaving AMD, he handed over ahci-ceva, ZynqMP Mode Pin GPIO
controller, Zynq UltraScale+ MPSoC and Versal reset, Xilinx SuperSpeed
DWC3 USB SoC controller, Microchip USB5744 4-port Hub Controller and
Xilinx udc controller maintainership duties to Mubin and Radhey.
Signed-off-by: Radhey Shyam Pandey <[email protected]>
---
Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml | 3 ++-
.../devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml | 3 ++-
Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml | 3 ++-
Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml | 3 ++-
Documentation/devicetree/bindings/usb/microchip,usb5744.yaml | 3 ++-
Documentation/devicetree/bindings/usb/xlnx,usb2.yaml | 3 ++-
6 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
index b29ce598f9aa..9952e0ef7767 100644
--- a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
+++ b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
@@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ceva AHCI SATA Controller
maintainers:
- - Piyush Mehta <[email protected]>
+ - Mubin Sayyed <[email protected]>
+ - Radhey Shyam Pandey <[email protected]>
description: |
The Ceva SATA controller mostly conforms to the AHCI interface with some
diff --git a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
index b1fd632718d4..bb93baa88879 100644
--- a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
+++ b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
@@ -12,7 +12,8 @@ description:
PS_MODE). Every pin can be configured as input/output.
maintainers:
- - Piyush Mehta <[email protected]>
+ - Mubin Sayyed <[email protected]>
+ - Radhey Shyam Pandey <[email protected]>
properties:
compatible:
diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
index 49db66801429..1f1b42dde94d 100644
--- a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
+++ b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
@@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Zynq UltraScale+ MPSoC and Versal reset
maintainers:
- - Piyush Mehta <[email protected]>
+ - Mubin Sayyed <[email protected]>
+ - Radhey Shyam Pandey <[email protected]>
description: |
The Zynq UltraScale+ MPSoC and Versal has several different resets.
diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
index bb373eb025a5..00f87a558c7d 100644
--- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
+++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
@@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx SuperSpeed DWC3 USB SoC controller
maintainers:
- - Piyush Mehta <[email protected]>
+ - Mubin Sayyed <[email protected]>
+ - Radhey Shyam Pandey <[email protected]>
properties:
compatible:
diff --git a/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml b/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml
index 6d4cfd943f58..445183d9d6db 100644
--- a/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml
+++ b/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml
@@ -16,8 +16,9 @@ description:
USB 2.0 traffic.
maintainers:
- - Piyush Mehta <[email protected]>
- Michal Simek <[email protected]>
+ - Mubin Sayyed <[email protected]>
+ - Radhey Shyam Pandey <[email protected]>
properties:
compatible:
diff --git a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml
index 868dffe314bc..a7f75fe36665 100644
--- a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml
+++ b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml
@@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx udc controller
maintainers:
- - Piyush Mehta <[email protected]>
+ - Mubin Sayyed <[email protected]>
+ - Radhey Shyam Pandey <[email protected]>
properties:
compatible:
--
2.34.1
On Fri, Jan 19, 2024 at 05:06:21PM +0530, Radhey Shyam Pandey wrote:
> As Piyush is leaving AMD, he handed over ahci-ceva, ZynqMP Mode Pin GPIO
> controller, Zynq UltraScale+ MPSoC and Versal reset, Xilinx SuperSpeed
> DWC3 USB SoC controller, Microchip USB5744 4-port Hub Controller and
> Xilinx udc controller maintainership duties to Mubin and Radhey.
>
> Signed-off-by: Radhey Shyam Pandey <[email protected]>
Needs an ack by Piyush.
On Fri, Jan 19, 2024 at 12:36 PM Radhey Shyam Pandey
<[email protected]> wrote:
>
> As Piyush is leaving AMD, he handed over ahci-ceva, ZynqMP Mode Pin GPIO
> controller, Zynq UltraScale+ MPSoC and Versal reset, Xilinx SuperSpeed
> DWC3 USB SoC controller, Microchip USB5744 4-port Hub Controller and
> Xilinx udc controller maintainership duties to Mubin and Radhey.
>
> Signed-off-by: Radhey Shyam Pandey <[email protected]>
> ---
[snip]
> diff --git a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
> index b1fd632718d4..bb93baa88879 100644
> --- a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
> +++ b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
> @@ -12,7 +12,8 @@ description:
> PS_MODE). Every pin can be configured as input/output.
>
> maintainers:
> - - Piyush Mehta <[email protected]>
> + - Mubin Sayyed <[email protected]>
> + - Radhey Shyam Pandey <[email protected]>
>
> properties:
> compatible:
For GPIO:
Acked-by: Bartosz Golaszewski <[email protected]>
[snip]
> -----Original Message-----
> From: Radhey Shyam Pandey <[email protected]>
> Sent: Friday, January 19, 2024 5:06 PM
> To: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; Simek, Michal
> <[email protected]>; [email protected];
> [email protected]; Mehta, Piyush <[email protected]>;
> Sayyed, Mubin <[email protected]>; Pandey, Radhey Shyam
> <[email protected]>
> Cc: [email protected]; [email protected]; linux-
> [email protected]; [email protected]; linux-arm-
> [email protected]; [email protected]; git (AMD-Xilinx)
> <[email protected]>
> Subject: [PATCH] dt-bindings: xilinx: replace Piyush Mehta maintainership
>
> As Piyush is leaving AMD, he handed over ahci-ceva, ZynqMP Mode Pin GPIO
> controller, Zynq UltraScale+ MPSoC and Versal reset, Xilinx SuperSpeed
> DWC3 USB SoC controller, Microchip USB5744 4-port Hub Controller and Xilinx
> udc controller maintainership duties to Mubin and Radhey.
>
> Signed-off-by: Radhey Shyam Pandey <[email protected]>
Acked-by: Piyush Mehta <[email protected]>
> ---
> Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml | 3 ++-
> .../devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml | 3 ++-
> Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml | 3 ++-
> Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml | 3 ++-
> Documentation/devicetree/bindings/usb/microchip,usb5744.yaml | 3 ++-
> Documentation/devicetree/bindings/usb/xlnx,usb2.yaml | 3 ++-
> 6 files changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
> b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
> index b29ce598f9aa..9952e0ef7767 100644
> --- a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
> +++ b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
> @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Ceva AHCI SATA Controller
>
> maintainers:
> - - Piyush Mehta <[email protected]>
> + - Mubin Sayyed <[email protected]>
> + - Radhey Shyam Pandey <[email protected]>
>
> description: |
> The Ceva SATA controller mostly conforms to the AHCI interface with some
> diff --git a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-
> modepin.yaml b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-
> modepin.yaml
> index b1fd632718d4..bb93baa88879 100644
> --- a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-
> modepin.yaml
> +++ b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-
> modepin.ya
> +++ ml
> @@ -12,7 +12,8 @@ description:
> PS_MODE). Every pin can be configured as input/output.
>
> maintainers:
> - - Piyush Mehta <[email protected]>
> + - Mubin Sayyed <[email protected]>
> + - Radhey Shyam Pandey <[email protected]>
>
> properties:
> compatible:
> diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
> b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
> index 49db66801429..1f1b42dde94d 100644
> --- a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
> +++ b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
> @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Zynq UltraScale+ MPSoC and Versal reset
>
> maintainers:
> - - Piyush Mehta <[email protected]>
> + - Mubin Sayyed <[email protected]>
> + - Radhey Shyam Pandey <[email protected]>
>
> description: |
> The Zynq UltraScale+ MPSoC and Versal has several different resets.
> diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
> b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
> index bb373eb025a5..00f87a558c7d 100644
> --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
> +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
> @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Xilinx SuperSpeed DWC3 USB SoC controller
>
> maintainers:
> - - Piyush Mehta <[email protected]>
> + - Mubin Sayyed <[email protected]>
> + - Radhey Shyam Pandey <[email protected]>
>
> properties:
> compatible:
> diff --git a/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml
> b/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml
> index 6d4cfd943f58..445183d9d6db 100644
> --- a/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml
> +++ b/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml
> @@ -16,8 +16,9 @@ description:
> USB 2.0 traffic.
>
> maintainers:
> - - Piyush Mehta <[email protected]>
> - Michal Simek <[email protected]>
> + - Mubin Sayyed <[email protected]>
> + - Radhey Shyam Pandey <[email protected]>
>
> properties:
> compatible:
> diff --git a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml
> b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml
> index 868dffe314bc..a7f75fe36665 100644
> --- a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml
> +++ b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml
> @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Xilinx udc controller
>
> maintainers:
> - - Piyush Mehta <[email protected]>
> + - Mubin Sayyed <[email protected]>
> + - Radhey Shyam Pandey <[email protected]>
>
> properties:
> compatible:
> --
> 2.34.1
On 19/01/2024 12:36, Radhey Shyam Pandey wrote:
> As Piyush is leaving AMD, he handed over ahci-ceva, ZynqMP Mode Pin GPIO
> controller, Zynq UltraScale+ MPSoC and Versal reset, Xilinx SuperSpeed
> DWC3 USB SoC controller, Microchip USB5744 4-port Hub Controller and
> Xilinx udc controller maintainership duties to Mubin and Radhey.
>
> Signed-off-by: Radhey Shyam Pandey <[email protected]>
> ---
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 1/19/24 12:36, Radhey Shyam Pandey wrote:
> As Piyush is leaving AMD, he handed over ahci-ceva, ZynqMP Mode Pin GPIO
> controller, Zynq UltraScale+ MPSoC and Versal reset, Xilinx SuperSpeed
> DWC3 USB SoC controller, Microchip USB5744 4-port Hub Controller and
> Xilinx udc controller maintainership duties to Mubin and Radhey.
>
> Signed-off-by: Radhey Shyam Pandey <[email protected]>
> ---
> Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml | 3 ++-
> .../devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml | 3 ++-
> Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml | 3 ++-
> Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml | 3 ++-
> Documentation/devicetree/bindings/usb/microchip,usb5744.yaml | 3 ++-
> Documentation/devicetree/bindings/usb/xlnx,usb2.yaml | 3 ++-
> 6 files changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
> index b29ce598f9aa..9952e0ef7767 100644
> --- a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
> +++ b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
> @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Ceva AHCI SATA Controller
>
> maintainers:
> - - Piyush Mehta <[email protected]>
> + - Mubin Sayyed <[email protected]>
> + - Radhey Shyam Pandey <[email protected]>
>
> description: |
> The Ceva SATA controller mostly conforms to the AHCI interface with some
> diff --git a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
> index b1fd632718d4..bb93baa88879 100644
> --- a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
> +++ b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
> @@ -12,7 +12,8 @@ description:
> PS_MODE). Every pin can be configured as input/output.
>
> maintainers:
> - - Piyush Mehta <[email protected]>
> + - Mubin Sayyed <[email protected]>
> + - Radhey Shyam Pandey <[email protected]>
>
> properties:
> compatible:
> diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
> index 49db66801429..1f1b42dde94d 100644
> --- a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
> +++ b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
> @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Zynq UltraScale+ MPSoC and Versal reset
>
> maintainers:
> - - Piyush Mehta <[email protected]>
> + - Mubin Sayyed <[email protected]>
> + - Radhey Shyam Pandey <[email protected]>
>
> description: |
> The Zynq UltraScale+ MPSoC and Versal has several different resets.
> diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
> index bb373eb025a5..00f87a558c7d 100644
> --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
> +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
> @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Xilinx SuperSpeed DWC3 USB SoC controller
>
> maintainers:
> - - Piyush Mehta <[email protected]>
> + - Mubin Sayyed <[email protected]>
> + - Radhey Shyam Pandey <[email protected]>
>
> properties:
> compatible:
> diff --git a/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml b/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml
> index 6d4cfd943f58..445183d9d6db 100644
> --- a/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml
> +++ b/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml
> @@ -16,8 +16,9 @@ description:
> USB 2.0 traffic.
>
> maintainers:
> - - Piyush Mehta <[email protected]>
> - Michal Simek <[email protected]>
> + - Mubin Sayyed <[email protected]>
> + - Radhey Shyam Pandey <[email protected]>
>
> properties:
> compatible:
> diff --git a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml
> index 868dffe314bc..a7f75fe36665 100644
> --- a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml
> +++ b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml
> @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Xilinx udc controller
>
> maintainers:
> - - Piyush Mehta <[email protected]>
> + - Mubin Sayyed <[email protected]>
> + - Radhey Shyam Pandey <[email protected]>
>
> properties:
> compatible:
Acked-by: Michal Simek <[email protected]>
Thanks,
Michal
On Fri, Jan 19, 2024 at 05:06:21PM +0530, Radhey Shyam Pandey wrote:
> As Piyush is leaving AMD, he handed over ahci-ceva, ZynqMP Mode Pin GPIO
> controller, Zynq UltraScale+ MPSoC and Versal reset, Xilinx SuperSpeed
> DWC3 USB SoC controller, Microchip USB5744 4-port Hub Controller and
> Xilinx udc controller maintainership duties to Mubin and Radhey.
>
> Signed-off-by: Radhey Shyam Pandey <[email protected]>
> ---
> Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml | 3 ++-
> .../devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml | 3 ++-
> Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml | 3 ++-
> Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml | 3 ++-
> Documentation/devicetree/bindings/usb/microchip,usb5744.yaml | 3 ++-
> Documentation/devicetree/bindings/usb/xlnx,usb2.yaml | 3 ++-
> 6 files changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
> index b29ce598f9aa..9952e0ef7767 100644
> --- a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
> +++ b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
> @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Ceva AHCI SATA Controller
>
> maintainers:
> - - Piyush Mehta <[email protected]>
> + - Mubin Sayyed <[email protected]>
> + - Radhey Shyam Pandey <[email protected]>
>
> description: |
> The Ceva SATA controller mostly conforms to the AHCI interface with some
For ata:
Acked-by: Niklas Cassel <[email protected]>
On 1/19/24 20:36, Radhey Shyam Pandey wrote:
> As Piyush is leaving AMD, he handed over ahci-ceva, ZynqMP Mode Pin GPIO
> controller, Zynq UltraScale+ MPSoC and Versal reset, Xilinx SuperSpeed
> DWC3 USB SoC controller, Microchip USB5744 4-port Hub Controller and
> Xilinx udc controller maintainership duties to Mubin and Radhey.
>
> Signed-off-by: Radhey Shyam Pandey <[email protected]>
Acked-by from Mubin is missing.
> ---
> Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml | 3 ++-
> .../devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml | 3 ++-
> Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml | 3 ++-
> Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml | 3 ++-
> Documentation/devicetree/bindings/usb/microchip,usb5744.yaml | 3 ++-
> Documentation/devicetree/bindings/usb/xlnx,usb2.yaml | 3 ++-
> 6 files changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
> index b29ce598f9aa..9952e0ef7767 100644
> --- a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
> +++ b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
> @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Ceva AHCI SATA Controller
>
> maintainers:
> - - Piyush Mehta <[email protected]>
> + - Mubin Sayyed <[email protected]>
> + - Radhey Shyam Pandey <[email protected]>
>
> description: |
> The Ceva SATA controller mostly conforms to the AHCI interface with some
> diff --git a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
> index b1fd632718d4..bb93baa88879 100644
> --- a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
> +++ b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
> @@ -12,7 +12,8 @@ description:
> PS_MODE). Every pin can be configured as input/output.
>
> maintainers:
> - - Piyush Mehta <[email protected]>
> + - Mubin Sayyed <[email protected]>
> + - Radhey Shyam Pandey <[email protected]>
>
> properties:
> compatible:
> diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
> index 49db66801429..1f1b42dde94d 100644
> --- a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
> +++ b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
> @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Zynq UltraScale+ MPSoC and Versal reset
>
> maintainers:
> - - Piyush Mehta <[email protected]>
> + - Mubin Sayyed <[email protected]>
> + - Radhey Shyam Pandey <[email protected]>
>
> description: |
> The Zynq UltraScale+ MPSoC and Versal has several different resets.
> diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
> index bb373eb025a5..00f87a558c7d 100644
> --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
> +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
> @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Xilinx SuperSpeed DWC3 USB SoC controller
>
> maintainers:
> - - Piyush Mehta <[email protected]>
> + - Mubin Sayyed <[email protected]>
> + - Radhey Shyam Pandey <[email protected]>
>
> properties:
> compatible:
> diff --git a/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml b/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml
> index 6d4cfd943f58..445183d9d6db 100644
> --- a/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml
> +++ b/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml
> @@ -16,8 +16,9 @@ description:
> USB 2.0 traffic.
>
> maintainers:
> - - Piyush Mehta <[email protected]>
> - Michal Simek <[email protected]>
> + - Mubin Sayyed <[email protected]>
> + - Radhey Shyam Pandey <[email protected]>
>
> properties:
> compatible:
> diff --git a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml
> index 868dffe314bc..a7f75fe36665 100644
> --- a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml
> +++ b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml
> @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Xilinx udc controller
>
> maintainers:
> - - Piyush Mehta <[email protected]>
> + - Mubin Sayyed <[email protected]>
> + - Radhey Shyam Pandey <[email protected]>
>
> properties:
> compatible:
--
Damien Le Moal
Western Digital Research
> -----Original Message-----
> From: Radhey Shyam Pandey <[email protected]>
> Sent: Friday, January 19, 2024 5:06 PM
> To: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; Simek, Michal
> <[email protected]>; [email protected];
> [email protected]; Mehta, Piyush <[email protected]>;
> Sayyed, Mubin <[email protected]>; Pandey, Radhey Shyam
> <[email protected]>
> Cc: [email protected]; [email protected]; linux-
> [email protected]; [email protected]; linux-arm-
> [email protected]; [email protected]; git (AMD-Xilinx)
> <[email protected]>
> Subject: [PATCH] dt-bindings: xilinx: replace Piyush Mehta maintainership
>
> As Piyush is leaving AMD, he handed over ahci-ceva, ZynqMP Mode Pin GPIO
> controller, Zynq UltraScale+ MPSoC and Versal reset, Xilinx SuperSpeed
> DWC3 USB SoC controller, Microchip USB5744 4-port Hub Controller and Xilinx
> udc controller maintainership duties to Mubin and Radhey.
>
> Signed-off-by: Radhey Shyam Pandey <[email protected]>
Acked-by: Mubin Sayyed <[email protected]>
Thanks,
Mubin
> ---
> Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml | 3 ++-
> .../devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml | 3 ++-
> Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml | 3 ++-
> Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml | 3 ++-
> Documentation/devicetree/bindings/usb/microchip,usb5744.yaml | 3 ++-
> Documentation/devicetree/bindings/usb/xlnx,usb2.yaml | 3 ++-
> 6 files changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
> b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
> index b29ce598f9aa..9952e0ef7767 100644
> --- a/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
> +++ b/Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
> @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Ceva AHCI SATA Controller
>
> maintainers:
> - - Piyush Mehta <[email protected]>
> + - Mubin Sayyed <[email protected]>
> + - Radhey Shyam Pandey <[email protected]>
>
> description: |
> The Ceva SATA controller mostly conforms to the AHCI interface with some
> diff --git a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-
> modepin.yaml b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-
> modepin.yaml
> index b1fd632718d4..bb93baa88879 100644
> --- a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-
> modepin.yaml
> +++ b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-
> modepin.ya
> +++ ml
> @@ -12,7 +12,8 @@ description:
> PS_MODE). Every pin can be configured as input/output.
>
> maintainers:
> - - Piyush Mehta <[email protected]>
> + - Mubin Sayyed <[email protected]>
> + - Radhey Shyam Pandey <[email protected]>
>
> properties:
> compatible:
> diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
> b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
> index 49db66801429..1f1b42dde94d 100644
> --- a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
> +++ b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
> @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Zynq UltraScale+ MPSoC and Versal reset
>
> maintainers:
> - - Piyush Mehta <[email protected]>
> + - Mubin Sayyed <[email protected]>
> + - Radhey Shyam Pandey <[email protected]>
>
> description: |
> The Zynq UltraScale+ MPSoC and Versal has several different resets.
> diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
> b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
> index bb373eb025a5..00f87a558c7d 100644
> --- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
> +++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
> @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Xilinx SuperSpeed DWC3 USB SoC controller
>
> maintainers:
> - - Piyush Mehta <[email protected]>
> + - Mubin Sayyed <[email protected]>
> + - Radhey Shyam Pandey <[email protected]>
>
> properties:
> compatible:
> diff --git a/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml
> b/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml
> index 6d4cfd943f58..445183d9d6db 100644
> --- a/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml
> +++ b/Documentation/devicetree/bindings/usb/microchip,usb5744.yaml
> @@ -16,8 +16,9 @@ description:
> USB 2.0 traffic.
>
> maintainers:
> - - Piyush Mehta <[email protected]>
> - Michal Simek <[email protected]>
> + - Mubin Sayyed <[email protected]>
> + - Radhey Shyam Pandey <[email protected]>
>
> properties:
> compatible:
> diff --git a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml
> b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml
> index 868dffe314bc..a7f75fe36665 100644
> --- a/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml
> +++ b/Documentation/devicetree/bindings/usb/xlnx,usb2.yaml
> @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Xilinx udc controller
>
> maintainers:
> - - Piyush Mehta <[email protected]>
> + - Mubin Sayyed <[email protected]>
> + - Radhey Shyam Pandey <[email protected]>
>
> properties:
> compatible:
> --
> 2.34.1
On Fri, 19 Jan 2024 17:06:21 +0530, Radhey Shyam Pandey wrote:
> As Piyush is leaving AMD, he handed over ahci-ceva, ZynqMP Mode Pin GPIO
> controller, Zynq UltraScale+ MPSoC and Versal reset, Xilinx SuperSpeed
> DWC3 USB SoC controller, Microchip USB5744 4-port Hub Controller and
> Xilinx udc controller maintainership duties to Mubin and Radhey.
>
> Signed-off-by: Radhey Shyam Pandey <[email protected]>
> ---
> Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml | 3 ++-
> .../devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml | 3 ++-
> Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml | 3 ++-
> Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml | 3 ++-
> Documentation/devicetree/bindings/usb/microchip,usb5744.yaml | 3 ++-
> Documentation/devicetree/bindings/usb/xlnx,usb2.yaml | 3 ++-
> 6 files changed, 12 insertions(+), 6 deletions(-)
>
Applied, thanks!