2023-06-06 17:09:31

by George Stark

Subject: [PATCH v3] meson saradc: fix clock divider mask length

According to datasheets of supported meson SOCs length of ADC_CLK_DIV
field is 6 bits long. Although all supported SOCs have the register
with that field documented later SOCs use external clock rather than
ADC internal clock so this patch affects only meson8 family (S8* SOCs)

Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs")
Signed-off-by: George Stark <[email protected]>
---
Changelog:

v1 -> v2:
* Update commit message
v2 -> v3:
* Update commit message
---
drivers/iio/adc/meson_saradc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
index 85b6826cc10c..b93ff42b8c19 100644
--- a/drivers/iio/adc/meson_saradc.c
+++ b/drivers/iio/adc/meson_saradc.c
@@ -72,7 +72,7 @@
#define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
#define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
#define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
- #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
+ #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 6
#define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
#define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)

--
2.38.4

2023-06-06 19:20:13

by Martin Blumenstingl

Subject: Re: [PATCH v3] meson saradc: fix clock divider mask length

Thank you George!

On Tue, Jun 6, 2023 at 6:54 PM George Stark <[email protected]> wrote:
>
> According to datasheets of supported meson SOCs length of ADC_CLK_DIV
> field is 6 bits long. Although all supported SOCs have the register
> with that field documented later SOCs use external clock rather than
> ADC internal clock so this patch affects only meson8 family (S8* SOCs)
>
> Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs")
> Signed-off-by: George Stark <[email protected]>
Reviewed-by: Martin Blumenstingl <[email protected]>

2023-06-06 23:20:41

by Andy Shevchenko

Subject: Re: [PATCH v3] meson saradc: fix clock divider mask length

Tue, Jun 06, 2023 at 07:53:57PM +0300, George Stark kirjoitti:
> According to datasheets of supported meson SOCs length of ADC_CLK_DIV

the datasheets

> field is 6 bits long. Although all supported SOCs have the register

6-bit

> with that field documented later SOCs use external clock rather than
> ADC internal clock so this patch affects only meson8 family (S8* SOCs)

s/SOC/SoC/g, and mind the grammar period at the end.

I believe Jonathan can fix when applying this, no need to resend unless
he asks for it.

FWIW,
Reviewed-by: Andy Shevchenko <[email protected]>

> Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs")
> Signed-off-by: George Stark <[email protected]>
> ---
> Changelog:
>
> v1 -> v2:
> * Update commit message
> v2 -> v3:
> * Update commit message
> ---
> drivers/iio/adc/meson_saradc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
> index 85b6826cc10c..b93ff42b8c19 100644
> --- a/drivers/iio/adc/meson_saradc.c
> +++ b/drivers/iio/adc/meson_saradc.c
> @@ -72,7 +72,7 @@
> #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
> #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
> #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
> - #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
> + #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 6
> #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
> #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
>
> --
> 2.38.4
>

--
With Best Regards,
Andy Shevchenko

2023-06-10 19:03:30

by Jonathan Cameron

Subject: Re: [PATCH v3] meson saradc: fix clock divider mask length

On Wed, 7 Jun 2023 01:52:26 +0300
[email protected] wrote:

> Tue, Jun 06, 2023 at 07:53:57PM +0300, George Stark kirjoitti:
> > According to datasheets of supported meson SOCs length of ADC_CLK_DIV
>
> the datasheets
>
> > field is 6 bits long. Although all supported SOCs have the register
>
> 6-bit
>
> > with that field documented later SOCs use external clock rather than
> > ADC internal clock so this patch affects only meson8 family (S8* SOCs)
>
> s/SOC/SoC/g, and mind the grammar period at the end.
>
> I believe Jonathan can fix when applying this, no need to resend unless
> he asks for it.
>
Indeed - done and applied to the fixes-togreg branch of iio.git + marked it
for stable inclusion.

Thanks,

Jonathan

> FWIW,
> Reviewed-by: Andy Shevchenko <[email protected]>
>
> > Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs")
> > Signed-off-by: George Stark <[email protected]>
> > ---
> > Changelog:
> >
> > v1 -> v2:
> > * Update commit message
> > v2 -> v3:
> > * Update commit message
> > ---
> > drivers/iio/adc/meson_saradc.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
> > index 85b6826cc10c..b93ff42b8c19 100644
> > --- a/drivers/iio/adc/meson_saradc.c
> > +++ b/drivers/iio/adc/meson_saradc.c
> > @@ -72,7 +72,7 @@
> > #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
> > #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
> > #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
> > - #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
> > + #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 6
> > #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
> > #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
> >
> > --
> > 2.38.4
> >
>