2024-04-18 03:44:21

by yunhui cui

Subject: [PATCH v4 1/3] riscv: cacheinfo: remove the useless input parameter (node) of ci_leaf_init()

ci_leaf_init() is a declared static function. The implementation of the
function body and the caller do not use the parameter (struct device_node
*node) input parameter, so remove it.

Fixes: 6a24915145c9 ("Revert "riscv: Set more data to cacheinfo"")
Signed-off-by: Yunhui Cui <[email protected]>
Reviewed-by: Jeremy Linton <[email protected]>
Reviewed-by: Sudeep Holla <[email protected]>
---
arch/riscv/kernel/cacheinfo.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
index 09e9b88110d1..30a6878287ad 100644
--- a/arch/riscv/kernel/cacheinfo.c
+++ b/arch/riscv/kernel/cacheinfo.c
@@ -64,7 +64,6 @@ uintptr_t get_cache_geometry(u32 level, enum cache_type type)
}

static void ci_leaf_init(struct cacheinfo *this_leaf,
- struct device_node *node,
enum cache_type type, unsigned int level)
{
this_leaf->level = level;
@@ -80,11 +79,11 @@ int populate_cache_leaves(unsigned int cpu)
int levels = 1, level = 1;

if (of_property_read_bool(np, "cache-size"))
- ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level);
+ ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
if (of_property_read_bool(np, "i-cache-size"))
- ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level);
+ ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
if (of_property_read_bool(np, "d-cache-size"))
- ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level);
+ ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);

prev = np;
while ((np = of_find_next_cache_node(np))) {
@@ -97,11 +96,11 @@ int populate_cache_leaves(unsigned int cpu)
if (level <= levels)
break;
if (of_property_read_bool(np, "cache-size"))
- ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level);
+ ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
if (of_property_read_bool(np, "i-cache-size"))
- ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level);
+ ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
if (of_property_read_bool(np, "d-cache-size"))
- ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level);
+ ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
levels = level;
}
of_node_put(np);
--
2.20.1

2024-04-18 03:44:30

by yunhui cui

Subject: [PATCH v4 2/3] riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT

Before cacheinfo can be built correctly, we need to initialize level
and type. Since RSIC-V currently does not have a register group that
describes cache-related attributes like ARM64, we cannot obtain them
directly, so now we obtain cache leaves from the ACPI PPTT table
(acpi_get_cache_info()) and set the cache type through split_levels.

Suggested-by: Jeremy Linton <[email protected]>
Suggested-by: Sudeep Holla <[email protected]>
Signed-off-by: Yunhui Cui <[email protected]>
---
arch/riscv/kernel/cacheinfo.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)

diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
index 30a6878287ad..e47a1e6bd3fe 100644
--- a/arch/riscv/kernel/cacheinfo.c
+++ b/arch/riscv/kernel/cacheinfo.c
@@ -6,6 +6,7 @@
#include <linux/cpu.h>
#include <linux/of.h>
#include <asm/cacheinfo.h>
+#include <linux/acpi.h>

static struct riscv_cacheinfo_ops *rv_cache_ops;

@@ -78,6 +79,27 @@ int populate_cache_leaves(unsigned int cpu)
struct device_node *prev = NULL;
int levels = 1, level = 1;

+ if (!acpi_disabled) {
+ int ret, fw_levels, split_levels;
+
+ ret = acpi_get_cache_info(cpu, &fw_levels, &split_levels);
+ if (ret)
+ return ret;
+
+ BUG_ON((split_levels > fw_levels) ||
+ (split_levels + fw_levels > this_cpu_ci->num_leaves));
+
+ for (; level <= this_cpu_ci->num_levels; level++) {
+ if (level <= split_levels) {
+ ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
+ ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
+ } else {
+ ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
+ }
+ }
+ return 0;
+ }
+
if (of_property_read_bool(np, "cache-size"))
ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
if (of_property_read_bool(np, "i-cache-size"))
--
2.20.1

2024-04-18 03:44:43

by yunhui cui

Subject: [PATCH v4 3/3] RISC-V: Select ACPI PPTT drivers

After adding ACPI support to populate_cache_leaves(), RISC-V can build
cacheinfo through the ACPI PPTT table, thus enabling the ACPI_PPTT
configuration.

Signed-off-by: Yunhui Cui <[email protected]>
Reviewed-by: Jeremy Linton <[email protected]>
Reviewed-by: Sudeep Holla <[email protected]>
---
arch/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 6d64888134ba..5d73fcaf9136 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -14,6 +14,7 @@ config RISCV
def_bool y
select ACPI_GENERIC_GSI if ACPI
select ACPI_REDUCED_HARDWARE_ONLY if ACPI
+ select ACPI_PPTT if ACPI
select ARCH_DMA_DEFAULT_COHERENT
select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
--
2.20.1

2024-04-18 08:42:13

by Sudeep Holla

Subject: Re: [PATCH v4 2/3] riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT

On Thu, Apr 18, 2024 at 11:43:29AM +0800, Yunhui Cui wrote:
> Before cacheinfo can be built correctly, we need to initialize level
> and type. Since RSIC-V currently does not have a register group that
> describes cache-related attributes like ARM64, we cannot obtain them
> directly, so now we obtain cache leaves from the ACPI PPTT table
> (acpi_get_cache_info()) and set the cache type through split_levels.
>
> Suggested-by: Jeremy Linton <[email protected]>
> Suggested-by: Sudeep Holla <[email protected]>
> Signed-off-by: Yunhui Cui <[email protected]>
> ---
> arch/riscv/kernel/cacheinfo.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
> index 30a6878287ad..e47a1e6bd3fe 100644
> --- a/arch/riscv/kernel/cacheinfo.c
> +++ b/arch/riscv/kernel/cacheinfo.c
> @@ -6,6 +6,7 @@
> #include <linux/cpu.h>
> #include <linux/of.h>
> #include <asm/cacheinfo.h>
> +#include <linux/acpi.h>
>
> static struct riscv_cacheinfo_ops *rv_cache_ops;
>
> @@ -78,6 +79,27 @@ int populate_cache_leaves(unsigned int cpu)
> struct device_node *prev = NULL;
> int levels = 1, level = 1;
>
> + if (!acpi_disabled) {
> + int ret, fw_levels, split_levels;
> +
> + ret = acpi_get_cache_info(cpu, &fw_levels, &split_levels);
> + if (ret)
> + return ret;
> +
> + BUG_ON((split_levels > fw_levels) ||
> + (split_levels + fw_levels > this_cpu_ci->num_leaves));
> +
> + for (; level <= this_cpu_ci->num_levels; level++) {
> + if (level <= split_levels) {
> + ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
> + ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
> + } else {
> + ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
> + }
> + }
> + return 0;
> + }
> +

Much better, so my review still stands ????

Reviewed-by: Sudeep Holla <[email protected]>

> if (of_property_read_bool(np, "cache-size"))
> ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
> if (of_property_read_bool(np, "i-cache-size"))
> --
> 2.20.1
>

--
Regards,
Sudeep

2024-04-19 06:28:02

by yunhui cui

Subject: Re: [External] Re: [PATCH v4 2/3] riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT

Hi palmer,

On Thu, Apr 18, 2024 at 4:42 PM Sudeep Holla <[email protected]> wrote:
>
> On Thu, Apr 18, 2024 at 11:43:29AM +0800, Yunhui Cui wrote:
> > Before cacheinfo can be built correctly, we need to initialize level
> > and type. Since RSIC-V currently does not have a register group that
> > describes cache-related attributes like ARM64, we cannot obtain them
> > directly, so now we obtain cache leaves from the ACPI PPTT table
> > (acpi_get_cache_info()) and set the cache type through split_levels.
> >
> > Suggested-by: Jeremy Linton <[email protected]>
> > Suggested-by: Sudeep Holla <[email protected]>
> > Signed-off-by: Yunhui Cui <[email protected]>
> > ---
> > arch/riscv/kernel/cacheinfo.c | 22 ++++++++++++++++++++++
> > 1 file changed, 22 insertions(+)
> >
> > diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
> > index 30a6878287ad..e47a1e6bd3fe 100644
> > --- a/arch/riscv/kernel/cacheinfo.c
> > +++ b/arch/riscv/kernel/cacheinfo.c
> > @@ -6,6 +6,7 @@
> > #include <linux/cpu.h>
> > #include <linux/of.h>
> > #include <asm/cacheinfo.h>
> > +#include <linux/acpi.h>
> >
> > static struct riscv_cacheinfo_ops *rv_cache_ops;
> >
> > @@ -78,6 +79,27 @@ int populate_cache_leaves(unsigned int cpu)
> > struct device_node *prev = NULL;
> > int levels = 1, level = 1;
> >
> > + if (!acpi_disabled) {
> > + int ret, fw_levels, split_levels;
> > +
> > + ret = acpi_get_cache_info(cpu, &fw_levels, &split_levels);
> > + if (ret)
> > + return ret;
> > +
> > + BUG_ON((split_levels > fw_levels) ||
> > + (split_levels + fw_levels > this_cpu_ci->num_leaves));
> > +
> > + for (; level <= this_cpu_ci->num_levels; level++) {
> > + if (level <= split_levels) {
> > + ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
> > + ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
> > + } else {
> > + ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
> > + }
> > + }
> > + return 0;
> > + }
> > +
>
> Much better, so my review still stands ????
>
> Reviewed-by: Sudeep Holla <[email protected]>
>
> > if (of_property_read_bool(np, "cache-size"))
> > ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
> > if (of_property_read_bool(np, "i-cache-size"))
> > --
> > 2.20.1
> >
>
> --
> Regards,
> Sudeep

Do you have any comments about this patch series?

Thanks,
Yunhui

2024-04-19 15:29:00

by Jeremy Linton

Subject: Re: [PATCH v4 2/3] riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT

Hi,

On 4/17/24 22:43, Yunhui Cui wrote:
> Before cacheinfo can be built correctly, we need to initialize level
> and type. Since RSIC-V currently does not have a register group that
> describes cache-related attributes like ARM64, we cannot obtain them
> directly, so now we obtain cache leaves from the ACPI PPTT table
> (acpi_get_cache_info()) and set the cache type through split_levels.
>
> Suggested-by: Jeremy Linton <[email protected]>
> Suggested-by: Sudeep Holla <[email protected]>
> Signed-off-by: Yunhui Cui <[email protected]>
> ---
> arch/riscv/kernel/cacheinfo.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
> index 30a6878287ad..e47a1e6bd3fe 100644
> --- a/arch/riscv/kernel/cacheinfo.c
> +++ b/arch/riscv/kernel/cacheinfo.c
> @@ -6,6 +6,7 @@
> #include <linux/cpu.h>
> #include <linux/of.h>
> #include <asm/cacheinfo.h>
> +#include <linux/acpi.h>
>
> static struct riscv_cacheinfo_ops *rv_cache_ops;
>
> @@ -78,6 +79,27 @@ int populate_cache_leaves(unsigned int cpu)
> struct device_node *prev = NULL;
> int levels = 1, level = 1;
>
> + if (!acpi_disabled) {
> + int ret, fw_levels, split_levels;
> +
> + ret = acpi_get_cache_info(cpu, &fw_levels, &split_levels);
> + if (ret)
> + return ret;
> +
> + BUG_ON((split_levels > fw_levels) ||
> + (split_levels + fw_levels > this_cpu_ci->num_leaves));
> +
> + for (; level <= this_cpu_ci->num_levels; level++) {
> + if (level <= split_levels) {
> + ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
> + ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
> + } else {
> + ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
> + }
> + }
> + return 0;
> + }
> +
> if (of_property_read_bool(np, "cache-size"))
> ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
> if (of_property_read_bool(np, "i-cache-size"))

Yes, looks good.

Reviewed-by: Jeremy Linton <[email protected]>



Thanks,

2024-04-23 11:09:06

by yunhui cui

Subject: Re: [External] Re: [PATCH v4 2/3] riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT

Hi Palmer,

On Fri, Apr 19, 2024 at 11:29 PM Jeremy Linton <[email protected]> wrote:
>
> Hi,
>
> On 4/17/24 22:43, Yunhui Cui wrote:
> > Before cacheinfo can be built correctly, we need to initialize level
> > and type. Since RSIC-V currently does not have a register group that
> > describes cache-related attributes like ARM64, we cannot obtain them
> > directly, so now we obtain cache leaves from the ACPI PPTT table
> > (acpi_get_cache_info()) and set the cache type through split_levels.
> >
> > Suggested-by: Jeremy Linton <[email protected]>
> > Suggested-by: Sudeep Holla <[email protected]>
> > Signed-off-by: Yunhui Cui <[email protected]>
> > ---
> > arch/riscv/kernel/cacheinfo.c | 22 ++++++++++++++++++++++
> > 1 file changed, 22 insertions(+)
> >
> > diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
> > index 30a6878287ad..e47a1e6bd3fe 100644
> > --- a/arch/riscv/kernel/cacheinfo.c
> > +++ b/arch/riscv/kernel/cacheinfo.c
> > @@ -6,6 +6,7 @@
> > #include <linux/cpu.h>
> > #include <linux/of.h>
> > #include <asm/cacheinfo.h>
> > +#include <linux/acpi.h>
> >
> > static struct riscv_cacheinfo_ops *rv_cache_ops;
> >
> > @@ -78,6 +79,27 @@ int populate_cache_leaves(unsigned int cpu)
> > struct device_node *prev = NULL;
> > int levels = 1, level = 1;
> >
> > + if (!acpi_disabled) {
> > + int ret, fw_levels, split_levels;
> > +
> > + ret = acpi_get_cache_info(cpu, &fw_levels, &split_levels);
> > + if (ret)
> > + return ret;
> > +
> > + BUG_ON((split_levels > fw_levels) ||
> > + (split_levels + fw_levels > this_cpu_ci->num_leaves));
> > +
> > + for (; level <= this_cpu_ci->num_levels; level++) {
> > + if (level <= split_levels) {
> > + ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
> > + ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
> > + } else {
> > + ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
> > + }
> > + }
> > + return 0;
> > + }
> > +
> > if (of_property_read_bool(np, "cache-size"))
> > ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
> > if (of_property_read_bool(np, "i-cache-size"))
>
> Yes, looks good.
>
> Reviewed-by: Jeremy Linton <[email protected]>
>
>
>
> Thanks,

Could you help review this patchset? Thanks.

Thanks,
Yunhui

2024-04-30 03:16:54

by yunhui cui

Subject: Re: [External] Re: [PATCH v4 2/3] riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT

Hi Palmer,

Gentle ping...

On Tue, Apr 23, 2024 at 7:03 PM yunhui cui <[email protected]> wrote:
>
> Hi Palmer,
>
> On Fri, Apr 19, 2024 at 11:29 PM Jeremy Linton <jeremy.linton@armcom> wrote:
> >
> > Hi,
> >
> > On 4/17/24 22:43, Yunhui Cui wrote:
> > > Before cacheinfo can be built correctly, we need to initialize level
> > > and type. Since RSIC-V currently does not have a register group that
> > > describes cache-related attributes like ARM64, we cannot obtain them
> > > directly, so now we obtain cache leaves from the ACPI PPTT table
> > > (acpi_get_cache_info()) and set the cache type through split_levels.
> > >
> > > Suggested-by: Jeremy Linton <[email protected]>
> > > Suggested-by: Sudeep Holla <[email protected]>
> > > Signed-off-by: Yunhui Cui <[email protected]>
> > > ---
> > > arch/riscv/kernel/cacheinfo.c | 22 ++++++++++++++++++++++
> > > 1 file changed, 22 insertions(+)
> > >
> > > diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
> > > index 30a6878287ad..e47a1e6bd3fe 100644
> > > --- a/arch/riscv/kernel/cacheinfo.c
> > > +++ b/arch/riscv/kernel/cacheinfo.c
> > > @@ -6,6 +6,7 @@
> > > #include <linux/cpu.h>
> > > #include <linux/of.h>
> > > #include <asm/cacheinfo.h>
> > > +#include <linux/acpi.h>
> > >
> > > static struct riscv_cacheinfo_ops *rv_cache_ops;
> > >
> > > @@ -78,6 +79,27 @@ int populate_cache_leaves(unsigned int cpu)
> > > struct device_node *prev = NULL;
> > > int levels = 1, level = 1;
> > >
> > > + if (!acpi_disabled) {
> > > + int ret, fw_levels, split_levels;
> > > +
> > > + ret = acpi_get_cache_info(cpu, &fw_levels, &split_levels);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + BUG_ON((split_levels > fw_levels) ||
> > > + (split_levels + fw_levels > this_cpu_ci->num_leaves));
> > > +
> > > + for (; level <= this_cpu_ci->num_levels; level++) {
> > > + if (level <= split_levels) {
> > > + ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
> > > + ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
> > > + } else {
> > > + ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
> > > + }
> > > + }
> > > + return 0;
> > > + }
> > > +
> > > if (of_property_read_bool(np, "cache-size"))
> > > ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
> > > if (of_property_read_bool(np, "i-cache-size"))
> >
> > Yes, looks good.
> >
> > Reviewed-by: Jeremy Linton <[email protected]>
> >
> >
> >
> > Thanks,
>
> Could you help review this patchset? Thanks.
>
> Thanks,
> Yunhui

Thanks,
Yunhui

2024-05-02 16:28:33

by Conor Dooley

Subject: Re: [PATCH v4 1/3] riscv: cacheinfo: remove the useless input parameter (node) of ci_leaf_init()

On Thu, Apr 18, 2024 at 11:43:28AM +0800, Yunhui Cui wrote:
> ci_leaf_init() is a declared static function. The implementation of the
> function body and the caller do not use the parameter (struct device_node
> *node) input parameter, so remove it.
>
> Fixes: 6a24915145c9 ("Revert "riscv: Set more data to cacheinfo"")
> Signed-off-by: Yunhui Cui <[email protected]>
> Reviewed-by: Jeremy Linton <[email protected]>
> Reviewed-by: Sudeep Holla <[email protected]>

Reviewed-by: Conor Dooley <[email protected]>

By the way, please use cover letters for multi patch patchsets. I don't
enjoy marking previous versions "superceded" by hand in patchwork.

Thanks,
Conor.

Attachments:

2024-05-02 16:37:38

by Conor Dooley

Subject: Re: [PATCH v4 2/3] riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT

On Thu, Apr 18, 2024 at 11:43:29AM +0800, Yunhui Cui wrote:
> Before cacheinfo can be built correctly, we need to initialize level
> and type. Since RSIC-V currently does not have a register group that
> describes cache-related attributes like ARM64, we cannot obtain them
> directly, so now we obtain cache leaves from the ACPI PPTT table
> (acpi_get_cache_info()) and set the cache type through split_levels.
>
> Suggested-by: Jeremy Linton <[email protected]>
> Suggested-by: Sudeep Holla <[email protected]>
: Signed-off-by: Yunhui Cui <[email protected]>

I'm not an ACPI head, so whether or not the table is valid on RISC-V or
w/e I do not know, but the code here looks sane to me, so
Reviewed-by: Conor Dooley <[email protected]>

Cheers,
Conor.

Attachments:

2024-05-08 11:19:26

by yunhui cui

Subject: Re: [External] Re: [PATCH v4 2/3] riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT

Hi Palmer,

Gentle ping...

On Fri, May 3, 2024 at 12:37 AM Conor Dooley <[email protected]> wrote:
>
> On Thu, Apr 18, 2024 at 11:43:29AM +0800, Yunhui Cui wrote:
> > Before cacheinfo can be built correctly, we need to initialize level
> > and type. Since RSIC-V currently does not have a register group that
> > describes cache-related attributes like ARM64, we cannot obtain them
> > directly, so now we obtain cache leaves from the ACPI PPTT table
> > (acpi_get_cache_info()) and set the cache type through split_levels.
> >
> > Suggested-by: Jeremy Linton <[email protected]>
> > Suggested-by: Sudeep Holla <[email protected]>
> : Signed-off-by: Yunhui Cui <[email protected]>
>
> I'm not an ACPI head, so whether or not the table is valid on RISC-V or
> w/e I do not know, but the code here looks sane to me, so

> Reviewed-by: Conor Dooley <[email protected]>
>
> Cheers,
> Conor.

Thanks,
Yunhui

2024-05-08 15:06:29

by Palmer Dabbelt

Subject: Re: [External] Re: [PATCH v4 2/3] riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT

On Wed, 08 May 2024 04:19:01 PDT (-0700), [email protected] wrote:
> Hi Palmer,
>
> Gentle ping...

+Sunil, as he's the ACPI/RISC-V maintainer and I generally wait for his
review on this stuff.

>
> On Fri, May 3, 2024 at 12:37 AM Conor Dooley <[email protected]> wrote:
>>
>> On Thu, Apr 18, 2024 at 11:43:29AM +0800, Yunhui Cui wrote:
>> > Before cacheinfo can be built correctly, we need to initialize level
>> > and type. Since RSIC-V currently does not have a register group that
>> > describes cache-related attributes like ARM64, we cannot obtain them
>> > directly, so now we obtain cache leaves from the ACPI PPTT table
>> > (acpi_get_cache_info()) and set the cache type through split_levels.
>> >
>> > Suggested-by: Jeremy Linton <[email protected]>
>> > Suggested-by: Sudeep Holla <[email protected]>
>> : Signed-off-by: Yunhui Cui <[email protected]>
>>
>> I'm not an ACPI head, so whether or not the table is valid on RISC-V or
>> w/e I do not know, but the code here looks sane to me, so
>
>> Reviewed-by: Conor Dooley <[email protected]>
>>
>> Cheers,
>> Conor.
>
> Thanks,
> Yunhui

2024-05-09 04:09:51

by Sunil V L

Subject: Re: [PATCH v4 2/3] riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT

On Thu, Apr 18, 2024 at 11:43:29AM +0800, Yunhui Cui wrote:
> Before cacheinfo can be built correctly, we need to initialize level
> and type. Since RSIC-V currently does not have a register group that

NIT: Typo RISC-V

> describes cache-related attributes like ARM64, we cannot obtain them
> directly, so now we obtain cache leaves from the ACPI PPTT table
> (acpi_get_cache_info()) and set the cache type through split_levels.
>
> Suggested-by: Jeremy Linton <[email protected]>
> Suggested-by: Sudeep Holla <[email protected]>
> Signed-off-by: Yunhui Cui <[email protected]>
> ---
> arch/riscv/kernel/cacheinfo.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
> index 30a6878287ad..e47a1e6bd3fe 100644
> --- a/arch/riscv/kernel/cacheinfo.c
> +++ b/arch/riscv/kernel/cacheinfo.c
> @@ -6,6 +6,7 @@
> #include <linux/cpu.h>
> #include <linux/of.h>
> #include <asm/cacheinfo.h>
> +#include <linux/acpi.h>
>
Can this be added in the order? Like, include acpi.h prior to cpu.h?

> static struct riscv_cacheinfo_ops *rv_cache_ops;
>
> @@ -78,6 +79,27 @@ int populate_cache_leaves(unsigned int cpu)
> struct device_node *prev = NULL;
> int levels = 1, level = 1;
>
> + if (!acpi_disabled) {
> + int ret, fw_levels, split_levels;
> +
> + ret = acpi_get_cache_info(cpu, &fw_levels, &split_levels);
> + if (ret)
> + return ret;
> +
> + BUG_ON((split_levels > fw_levels) ||
> + (split_levels + fw_levels > this_cpu_ci->num_leaves));
> +
> + for (; level <= this_cpu_ci->num_levels; level++) {
> + if (level <= split_levels) {
> + ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
> + ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
> + } else {
> + ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
> + }
> + }
> + return 0;
> + }
> +
Other than above nits, it looks good to me. Thanks for the patch!

Reviewed-by: Sunil V L <[email protected]>

2024-05-09 06:33:34

by yunhui cui

Subject: Re: [External] Re: [PATCH v4 2/3] riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT

Hi Sunil,

On Thu, May 9, 2024 at 12:09 PM Sunil V L <[email protected]> wrote:
>
> On Thu, Apr 18, 2024 at 11:43:29AM +0800, Yunhui Cui wrote:
> > Before cacheinfo can be built correctly, we need to initialize level
> > and type. Since RSIC-V currently does not have a register group that
>
> NIT: Typo RISC-V
Okay, I'll update it in v5.

>
> > describes cache-related attributes like ARM64, we cannot obtain them
> > directly, so now we obtain cache leaves from the ACPI PPTT table
> > (acpi_get_cache_info()) and set the cache type through split_levels.
> >
> > Suggested-by: Jeremy Linton <[email protected]>
> > Suggested-by: Sudeep Holla <[email protected]>
> > Signed-off-by: Yunhui Cui <[email protected]>
> > ---
> > arch/riscv/kernel/cacheinfo.c | 22 ++++++++++++++++++++++
> > 1 file changed, 22 insertions(+)
> >
> > diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
> > index 30a6878287ad..e47a1e6bd3fe 100644
> > --- a/arch/riscv/kernel/cacheinfo.c
> > +++ b/arch/riscv/kernel/cacheinfo.c
> > @@ -6,6 +6,7 @@
> > #include <linux/cpu.h>
> > #include <linux/of.h>
> > #include <asm/cacheinfo.h>
> > +#include <linux/acpi.h>
> >
> Can this be added in the order? Like, include acpi.h prior to cpu.h?
Okay, I'll update it in v5.

>
> > static struct riscv_cacheinfo_ops *rv_cache_ops;
> >
> > @@ -78,6 +79,27 @@ int populate_cache_leaves(unsigned int cpu)
> > struct device_node *prev = NULL;
> > int levels = 1, level = 1;
> >
> > + if (!acpi_disabled) {
> > + int ret, fw_levels, split_levels;
> > +
> > + ret = acpi_get_cache_info(cpu, &fw_levels, &split_levels);
> > + if (ret)
> > + return ret;
> > +
> > + BUG_ON((split_levels > fw_levels) ||
> > + (split_levels + fw_levels > this_cpu_ci->num_leaves));
> > +
> > + for (; level <= this_cpu_ci->num_levels; level++) {
> > + if (level <= split_levels) {
> > + ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
> > + ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
> > + } else {
> > + ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level);
> > + }
> > + }
> > + return 0;
> > + }
> > +
> Other than above nits, it looks good to me. Thanks for the patch!
>
> Reviewed-by: Sunil V L <[email protected]>


Thanks,
Yunhui