On Wed, Nov 15, 2023 at 11:25:14AM +0800, Luo Jie wrote:
> The PHY & PCS clocks need to be enabled and the reset
> sequence needs to be completed to make qca8084 PHY
> probeable by MDIO bus.
Is all this guaranteed to be the same between different boards? Can
the board be wired differently and need a different configuration?
Andrew
On 11/15/23 17:20, Andrew Lunn wrote:
> On Wed, Nov 15, 2023 at 11:25:14AM +0800, Luo Jie wrote:
>> The PHY & PCS clocks need to be enabled and the reset
>> sequence needs to be completed to make qca8084 PHY
>> probeable by MDIO bus.
>
> Is all this guaranteed to be the same between different boards?
No, this looks like a total subsystem overreach, these should be
taken care of from within clk framework and consumed with the clk
APIs.
Konrad
On Wed, Nov 15, 2023 at 6:01 PM Konrad Dybcio <[email protected]> wrote:
>
>
>
> On 11/15/23 17:20, Andrew Lunn wrote:
> > On Wed, Nov 15, 2023 at 11:25:14AM +0800, Luo Jie wrote:
> >> The PHY & PCS clocks need to be enabled and the reset
> >> sequence needs to be completed to make qca8084 PHY
> >> probeable by MDIO bus.
> >
> > Is all this guaranteed to be the same between different boards?
> No, this looks like a total subsystem overreach, these should be
> taken care of from within clk framework and consumed with the clk
> APIs.
>
> Konrad
There are patches for QCA8084 clocks:
https://patchwork.kernel.org/project/linux-arm-msm/cover/[email protected]/
I guess all of the clocking should be done there, it isn't really a MDIO issue.
Regards,
Robert
--
Robert Marko
Staff Embedded Linux Engineer
Sartura Ltd.
Lendavska ulica 16a
10000 Zagreb, Croatia
Email: [email protected]
Web: http://www.sartura.hr
On 11/16/2023 1:01 AM, Konrad Dybcio wrote:
>
>
> On 11/15/23 17:20, Andrew Lunn wrote:
>> On Wed, Nov 15, 2023 at 11:25:14AM +0800, Luo Jie wrote:
>>> The PHY & PCS clocks need to be enabled and the reset
>>> sequence needs to be completed to make qca8084 PHY
>>> probeable by MDIO bus.
>>
>> Is all this guaranteed to be the same between different boards?
> No, this looks like a total subsystem overreach, these should be
> taken care of from within clk framework and consumed with the clk
> APIs.
>
> Konrad
Hi Konrad,
As Robert shared the link of the clock provider driver, which is
registered as MDIO device and not available until to the qca8084
initializations completed done here, so i need to do raw read/write
the clock registers in this patch.
On 11/16/2023 1:03 AM, Robert Marko wrote:
> On Wed, Nov 15, 2023 at 6:01 PM Konrad Dybcio <[email protected]> wrote:
>>
>>
>>
>> On 11/15/23 17:20, Andrew Lunn wrote:
>>> On Wed, Nov 15, 2023 at 11:25:14AM +0800, Luo Jie wrote:
>>>> The PHY & PCS clocks need to be enabled and the reset
>>>> sequence needs to be completed to make qca8084 PHY
>>>> probeable by MDIO bus.
>>>
>>> Is all this guaranteed to be the same between different boards?
>> No, this looks like a total subsystem overreach, these should be
>> taken care of from within clk framework and consumed with the clk
>> APIs.
>>
>> Konrad
>
> There are patches for QCA8084 clocks:
> https://patchwork.kernel.org/project/linux-arm-msm/cover/[email protected]/
>
> I guess all of the clocking should be done there, it isn't really a MDIO issue.
>
> Regards,
> Robert
>
Thanks Robert for the link of this patch.
Yes, the clock driver of qca8084 is probed as the MDIO device, the
configuration sequence here to lighten the qca8084 PHY need to
be completed before the clock APIs available to call.
On 11/16/2023 12:20 AM, Andrew Lunn wrote:
> On Wed, Nov 15, 2023 at 11:25:14AM +0800, Luo Jie wrote:
>> The PHY & PCS clocks need to be enabled and the reset
>> sequence needs to be completed to make qca8084 PHY
>> probeable by MDIO bus.
>
> Is all this guaranteed to be the same between different boards? Can
> the board be wired differently and need a different configuration?
>
> Andrew
Hi Andrew,
This configuration sequence is specified to the qca8084 chip,
not related with the platform(such as ipq5332).
All these configured registers are located in qca8084 chip, we need
to complete these configurations to make MDIO bus being able to
scan the qca8084 PHY(PHY registers can be accessed).
> Yes, the clock driver of qca8084 is probed as the MDIO device, the
> configuration sequence here to lighten the qca8084 PHY need to
> be completed before the clock APIs available to call.
Please cleanly separate clock from MDIO. The MDIO driver should only
use the common clock framework API calls. If the clock driver is not
loaded yet, trying to get a clock should return -EPROBE_DEFER. The
MDIO driver should return that from its probe function. The driver
core will then try to probe the MDIO driver later, by which time the
clock driver should of loaded.
Andrew
On Thu, Nov 16, 2023 at 06:47:08PM +0800, Jie Luo wrote:
>
>
> On 11/16/2023 12:20 AM, Andrew Lunn wrote:
> > On Wed, Nov 15, 2023 at 11:25:14AM +0800, Luo Jie wrote:
> > > The PHY & PCS clocks need to be enabled and the reset
> > > sequence needs to be completed to make qca8084 PHY
> > > probeable by MDIO bus.
> >
> > Is all this guaranteed to be the same between different boards? Can
> > the board be wired differently and need a different configuration?
> >
> > Andrew
>
> Hi Andrew,
> This configuration sequence is specified to the qca8084 chip,
> not related with the platform(such as ipq5332).
>
> All these configured registers are located in qca8084 chip, we need
> to complete these configurations to make MDIO bus being able to
> scan the qca8084 PHY(PHY registers can be accessed).
So nothing here has anything to do with the actual PHYs on the bus?
The only clock exposed here is MDC, and that runs at the standard
2.5MHz? All the clock tree configuration is completely internal to the
SOC?
What we don't want is some hard coded configuration which only works
for one specific reference design.
Andrew
On 11/17/2023 1:08 AM, Andrew Lunn wrote:
>> Yes, the clock driver of qca8084 is probed as the MDIO device, the
>> configuration sequence here to lighten the qca8084 PHY need to
>> be completed before the clock APIs available to call.
>
> Please cleanly separate clock from MDIO. The MDIO driver should only
> use the common clock framework API calls. If the clock driver is not
> loaded yet, trying to get a clock should return -EPROBE_DEFER. The
> MDIO driver should return that from its probe function. The driver
> core will then try to probe the MDIO driver later, by which time the
> clock driver should of loaded.
>
> Andrew
>
Ok, will update the patches to take this solution using the clock
consume APIs. Thanks Andrew for the suggestion.
On 11/17/2023 1:12 AM, Andrew Lunn wrote:
> On Thu, Nov 16, 2023 at 06:47:08PM +0800, Jie Luo wrote:
>>
>>
>> On 11/16/2023 12:20 AM, Andrew Lunn wrote:
>>> On Wed, Nov 15, 2023 at 11:25:14AM +0800, Luo Jie wrote:
>>>> The PHY & PCS clocks need to be enabled and the reset
>>>> sequence needs to be completed to make qca8084 PHY
>>>> probeable by MDIO bus.
>>>
>>> Is all this guaranteed to be the same between different boards? Can
>>> the board be wired differently and need a different configuration?
>>>
>>> Andrew
>>
>> Hi Andrew,
>> This configuration sequence is specified to the qca8084 chip,
>> not related with the platform(such as ipq5332).
>>
>> All these configured registers are located in qca8084 chip, we need
>> to complete these configurations to make MDIO bus being able to
>> scan the qca8084 PHY(PHY registers can be accessed).
>
> So nothing here has anything to do with the actual PHYs on the bus?
> The only clock exposed here is MDC, and that runs at the standard
> 2.5MHz? All the clock tree configuration is completely internal to the
> SOC?
>
> What we don't want is some hard coded configuration which only works
> for one specific reference design.
>
> Andrew
These configured registers are related with PHYs, which is located in
the qca8084 PHY chip, qca8084 PHY chip includes the GCC register that
is not from the SOC(ipq5332), is a internal part of qca8084 PHY.
qca8084 PHY works on 6.25MHZ and other clock rates below 6.25MHZ.
will move these clock configurations using the clock APIs into the PHY
probe function in the next patch set, since it is the internal configs
of qca8084 PHY.