This patch series introduces full support for the Amlogic A1 USB controller
in OTG mode (peripheral and host modes switching).
Previously, Amlogic's patch series [1] was applied to the upstream tree,
but it only had USB host mode support.
Furthermore, the device tree patchset [2] wasn't merged due to a missing
clk driver.
Patchset [2] has been completely reworked:
- changed register base offsets to proper values
- introduced dwc2 in peripheral mode
- OTG mode support
- the SoB of Amlogic authors still remain
Testing:
- USB OTG role switching between gadget and host - OK
- Peripheral mode - OK (tested with adb shell/push/pop)
- Host mode - OK (tested only USB enumeration and detection)
Changes v3 since v2 at [4]:
- if reset_control_reset() fails during phy_exit() callback
execution, do not disable clkin, instead, return an error
immediately
- provide proper 'phy-names' for the dwc2 device tree node as
'usb2-phy' instead of 'usb2_phy' (replace underscore with dash)
Changes v2 since v1 at [3]:
- as Martin suggested in v1, this commit completely removes
the 'otg_switch_supported' parameter from dwc3_meson_g12a_drvdata;
this parameter is no longer necessary as all IP versions now
support OTG switching
- this commit moves the USB PHY clkin enable/disable calls to
the PHY init/exit routines
Links:
[1] https://lore.kernel.org/all/[email protected]/
[2] https://lore.kernel.org/all/[email protected]/
[3] https://lore.kernel.org/all/[email protected]/
[4] https://lore.kernel.org/all/[email protected]/
Dmitry Rokosov (5):
phy: amlogic: enable/disable clkin during Amlogic USB PHY init/exit
usb: dwc2: support dwc2 IP for Amlogic A1 SoC family
dt-bindings: usb: dwc2: add support for Amlogic A1 SoC USB peripheral
usb: dwc3-meson-g12a: support OTG switch for all IP versions
arm64: dts: meson: a1: support USB controller in OTG mode
.../devicetree/bindings/usb/dwc2.yaml | 1 +
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 59 +++++++++++++++++++
drivers/phy/amlogic/phy-meson-g12a-usb2.c | 15 ++++-
drivers/usb/dwc2/params.c | 21 +++++++
drivers/usb/dwc3/dwc3-meson-g12a.c | 16 +----
5 files changed, 97 insertions(+), 15 deletions(-)
--
2.36.0
Amlogic A1 SoC family has USB2.0 controller based on dwc2 and dwc3
heads. It supports otg/host/peripheral modes.
Signed-off-by: Yue Wang <[email protected]>
Signed-off-by: Hanjie Lin <[email protected]>
Signed-off-by: Dmitry Rokosov <[email protected]>
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 59 +++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index ae7d39cff07a..5588ee602161 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -8,6 +8,8 @@
#include <dt-bindings/gpio/meson-a1-gpio.h>
#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
#include <dt-bindings/clock/amlogic,a1-clkc.h>
+#include <dt-bindings/power/meson-a1-power.h>
+#include <dt-bindings/reset/amlogic,meson-a1-reset.h>
/ {
compatible = "amlogic,a1";
@@ -169,6 +171,17 @@ gpio_intc: interrupt-controller@0440 {
amlogic,channel-interrupts =
<49 50 51 52 53 54 55 56>;
};
+
+ usb2_phy1: phy@4000 {
+ compatible = "amlogic,a1-usb2-phy";
+ clocks = <&clkc CLKID_USB_PHY_IN>;
+ clock-names = "xtal";
+ reg = <0x0 0x4000 0x0 0x60>;
+ resets = <&reset RESET_USBPHY>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ power-domains = <&pwrc PWRC_USB_ID>;
+ };
};
gic: interrupt-controller@ff901000 {
@@ -192,6 +205,52 @@ spifc: spi@fd000400 {
#size-cells = <0>;
status = "disabled";
};
+
+ usb: usb@fe004400 {
+ status = "disabled";
+ compatible = "amlogic,meson-a1-usb-ctrl";
+ reg = <0x0 0xfe004400 0x0 0xa0>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&clkc CLKID_USB_CTRL>,
+ <&clkc CLKID_USB_BUS>,
+ <&clkc CLKID_USB_CTRL_IN>;
+ clock-names = "usb_ctrl", "usb_bus", "xtal_usb_ctrl";
+ resets = <&reset RESET_USBCTRL>;
+ reset-name = "usb_ctrl";
+
+ dr_mode = "otg";
+
+ phys = <&usb2_phy1>;
+ phy-names = "usb2-phy1";
+
+ dwc2: usb@ff500000 {
+ compatible = "amlogic,meson-a1-usb", "snps,dwc2";
+ reg = <0x0 0xff500000 0x0 0x40000>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb2_phy1>;
+ phy-names = "usb2-phy";
+ clocks = <&clkc CLKID_USB_PHY>;
+ clock-names = "otg";
+ dr_mode = "peripheral";
+ g-rx-fifo-size = <192>;
+ g-np-tx-fifo-size = <128>;
+ g-tx-fifo-size = <128 128 16 16 16>;
+ };
+
+ dwc3: usb@ff400000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xff400000 0x0 0x100000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,dis_u2_susphy_quirk;
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,parkmode-disable-ss-quirk;
+ };
+ };
};
timer {
--
2.36.0
On Wed, Apr 26, 2023 at 12:29 PM Dmitry Rokosov
<[email protected]> wrote:
>
> Amlogic A1 SoC family has USB2.0 controller based on dwc2 and dwc3
> heads. It supports otg/host/peripheral modes.
>
> Signed-off-by: Yue Wang <[email protected]>
> Signed-off-by: Hanjie Lin <[email protected]>
> Signed-off-by: Dmitry Rokosov <[email protected]>
Reviewed-by: Martin Blumenstingl <[email protected]>
Hi,
On 26/04/2023 12:29, Dmitry Rokosov wrote:
> Amlogic A1 SoC family has USB2.0 controller based on dwc2 and dwc3
> heads. It supports otg/host/peripheral modes.
>
> Signed-off-by: Yue Wang <[email protected]>
> Signed-off-by: Hanjie Lin <[email protected]>
> Signed-off-by: Dmitry Rokosov <[email protected]>
> ---
> arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 59 +++++++++++++++++++++++
> 1 file changed, 59 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> index ae7d39cff07a..5588ee602161 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> @@ -8,6 +8,8 @@
> #include <dt-bindings/gpio/meson-a1-gpio.h>
> #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
> #include <dt-bindings/clock/amlogic,a1-clkc.h>
> +#include <dt-bindings/power/meson-a1-power.h>
> +#include <dt-bindings/reset/amlogic,meson-a1-reset.h>
>
> / {
> compatible = "amlogic,a1";
> @@ -169,6 +171,17 @@ gpio_intc: interrupt-controller@0440 {
> amlogic,channel-interrupts =
> <49 50 51 52 53 54 55 56>;
> };
> +
> + usb2_phy1: phy@4000 {
> + compatible = "amlogic,a1-usb2-phy";
> + clocks = <&clkc CLKID_USB_PHY_IN>;
> + clock-names = "xtal";
> + reg = <0x0 0x4000 0x0 0x60>;
> + resets = <&reset RESET_USBPHY>;
> + reset-names = "phy";
> + #phy-cells = <0>;
> + power-domains = <&pwrc PWRC_USB_ID>;
> + };
> };
>
> gic: interrupt-controller@ff901000 {
> @@ -192,6 +205,52 @@ spifc: spi@fd000400 {
> #size-cells = <0>;
> status = "disabled";
> };
> +
> + usb: usb@fe004400 {
> + status = "disabled";
> + compatible = "amlogic,meson-a1-usb-ctrl";
> + reg = <0x0 0xfe004400 0x0 0xa0>;
> + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + clocks = <&clkc CLKID_USB_CTRL>,
> + <&clkc CLKID_USB_BUS>,
> + <&clkc CLKID_USB_CTRL_IN>;
> + clock-names = "usb_ctrl", "usb_bus", "xtal_usb_ctrl";
> + resets = <&reset RESET_USBCTRL>;
> + reset-name = "usb_ctrl";
> +
> + dr_mode = "otg";
> +
> + phys = <&usb2_phy1>;
> + phy-names = "usb2-phy1";
> +
> + dwc2: usb@ff500000 {
> + compatible = "amlogic,meson-a1-usb", "snps,dwc2";
> + reg = <0x0 0xff500000 0x0 0x40000>;
> + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&usb2_phy1>;
> + phy-names = "usb2-phy";
> + clocks = <&clkc CLKID_USB_PHY>;
> + clock-names = "otg";
> + dr_mode = "peripheral";
> + g-rx-fifo-size = <192>;
> + g-np-tx-fifo-size = <128>;
> + g-tx-fifo-size = <128 128 16 16 16>;
> + };
> +
> + dwc3: usb@ff400000 {
> + compatible = "snps,dwc3";
> + reg = <0x0 0xff400000 0x0 0x100000>;
> + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> + dr_mode = "host";
> + snps,dis_u2_susphy_quirk;
> + snps,quirk-frame-length-adjustment = <0x20>;
> + snps,parkmode-disable-ss-quirk;
> + };
> + };
> };
>
> timer {
This patcj is fine, but depends on clock bindings & dt, so now Vinod took the PHY
patch, please resend this wiyhout patches 1 & 5, then resend the DT patch later when
the clock bindings is merged.
Thanks,
Neil
Hello Neil,
I apologize for the delayed response, as I did not have access to my laptop
for a few days.
On Tue, May 09, 2023 at 09:44:33AM +0200, [email protected] wrote:
> Hi,
>
> On 26/04/2023 12:29, Dmitry Rokosov wrote:
> > Amlogic A1 SoC family has USB2.0 controller based on dwc2 and dwc3
> > heads. It supports otg/host/peripheral modes.
> >
> > Signed-off-by: Yue Wang <[email protected]>
> > Signed-off-by: Hanjie Lin <[email protected]>
> > Signed-off-by: Dmitry Rokosov <[email protected]>
> > ---
> > arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 59 +++++++++++++++++++++++
> > 1 file changed, 59 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> > index ae7d39cff07a..5588ee602161 100644
> > --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> > +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
> > @@ -8,6 +8,8 @@
> > #include <dt-bindings/gpio/meson-a1-gpio.h>
> > #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
> > #include <dt-bindings/clock/amlogic,a1-clkc.h>
> > +#include <dt-bindings/power/meson-a1-power.h>
> > +#include <dt-bindings/reset/amlogic,meson-a1-reset.h>
> > / {
> > compatible = "amlogic,a1";
> > @@ -169,6 +171,17 @@ gpio_intc: interrupt-controller@0440 {
> > amlogic,channel-interrupts =
> > <49 50 51 52 53 54 55 56>;
> > };
> > +
> > + usb2_phy1: phy@4000 {
> > + compatible = "amlogic,a1-usb2-phy";
> > + clocks = <&clkc CLKID_USB_PHY_IN>;
> > + clock-names = "xtal";
> > + reg = <0x0 0x4000 0x0 0x60>;
> > + resets = <&reset RESET_USBPHY>;
> > + reset-names = "phy";
> > + #phy-cells = <0>;
> > + power-domains = <&pwrc PWRC_USB_ID>;
> > + };
> > };
> > gic: interrupt-controller@ff901000 {
> > @@ -192,6 +205,52 @@ spifc: spi@fd000400 {
> > #size-cells = <0>;
> > status = "disabled";
> > };
> > +
> > + usb: usb@fe004400 {
> > + status = "disabled";
> > + compatible = "amlogic,meson-a1-usb-ctrl";
> > + reg = <0x0 0xfe004400 0x0 0xa0>;
> > + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + clocks = <&clkc CLKID_USB_CTRL>,
> > + <&clkc CLKID_USB_BUS>,
> > + <&clkc CLKID_USB_CTRL_IN>;
> > + clock-names = "usb_ctrl", "usb_bus", "xtal_usb_ctrl";
> > + resets = <&reset RESET_USBCTRL>;
> > + reset-name = "usb_ctrl";
> > +
> > + dr_mode = "otg";
> > +
> > + phys = <&usb2_phy1>;
> > + phy-names = "usb2-phy1";
> > +
> > + dwc2: usb@ff500000 {
> > + compatible = "amlogic,meson-a1-usb", "snps,dwc2";
> > + reg = <0x0 0xff500000 0x0 0x40000>;
> > + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> > + phys = <&usb2_phy1>;
> > + phy-names = "usb2-phy";
> > + clocks = <&clkc CLKID_USB_PHY>;
> > + clock-names = "otg";
> > + dr_mode = "peripheral";
> > + g-rx-fifo-size = <192>;
> > + g-np-tx-fifo-size = <128>;
> > + g-tx-fifo-size = <128 128 16 16 16>;
> > + };
> > +
> > + dwc3: usb@ff400000 {
> > + compatible = "snps,dwc3";
> > + reg = <0x0 0xff400000 0x0 0x100000>;
> > + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> > + dr_mode = "host";
> > + snps,dis_u2_susphy_quirk;
> > + snps,quirk-frame-length-adjustment = <0x20>;
> > + snps,parkmode-disable-ss-quirk;
> > + };
> > + };
> > };
> > timer {
>
> This patcj is fine, but depends on clock bindings & dt, so now Vinod took the PHY
> patch, please resend this wiyhout patches 1 & 5, then resend the DT patch later when
> the clock bindings is merged.
>
> Thanks,
> Neil
Sure, not a problem. I will resend the 3 patchsets in different series.
--
Thank you,
Dmitry