Hi,
This series aims to add Freescale i.MX8qxp pixel link MSI bus support
by using the existing simple-pm-bus driver. A power domain and two input
clocks need to be enabled before the MSI bus accesses it's child devices,
which matches what a simple power-managed bus is(See simple-pm-bus.yaml).
Patch 1 enables/disables functional clock(s) as a bulk in the
simple-pm-bus driver when the simple-pm-bus is being power managed,
since the MSI bus takes the two input clocks as functional clocks.
Patch 2 adds dt-bindings for the MSI bus.
v3->v4:
* Drop patch 1 in v3, because simple-bus/simple-mfd devices probed by the
simple-pm-bus driver should not be child nodes of simple-pm-bus at all,
as simple-bus/simple-mfd's child devices PM operations cannot be propagated
to simple-pm-bus. Those simple-bus/simple-mfd devices needs dedicated drivers.
* Drop unnecessary 'bus == NULL' check from simple_pm_bus_runtime_{suspend,resume}.
for patch 1 in v4. (Geert)
* Add Geert's R-b tag on patch 1 in v4.
* Add child nodes in the example MSI bus node of the MSI bus dt-binding. (Krzysztof)
* Resend v4 to imply this series is based on v6.0-rc1 so that there are not any
dependencies for the MSI bus dt-binding. (Rob)
v2->v3:
* Add a pattern property to allow child nodes in the MSI bus dt-binding. (Rob)
v1->v2:
Address Krzysztof's comments on patch 3:
* Add a select to explicitly select the MSI bus dt-binding.
* List 'simple-pm-bus' explicitly as one item of compatible strings.
* Require compatible and reg properties.
* Put reg property just after compatible property in example.
Liu Ying (2):
drivers: bus: simple-pm-bus: Use clocks
dt-bindings: bus: Add Freescale i.MX8qxp pixel link MSI bus binding
.../bus/fsl,imx8qxp-pixel-link-msi-bus.yaml | 232 ++++++++++++++++++
drivers/bus/simple-pm-bus.c | 48 ++++
2 files changed, 280 insertions(+)
create mode 100644 Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml
--
2.37.1
Freescale i.MX8qxp pixel link MSI bus is a simple memory-mapped bus.
It is used to access peripherals in i.MX8qm/qxp imaging, LVDS, MIPI
DSI and HDMI TX subsystems, like I2C controller, PWM controller,
MIPI DSI controller and Control and Status Registers (CSR) module.
Reference simple-pm-bus bindings and add Freescale i.MX8qxp pixel
link MSI bus specific bindings.
Signed-off-by: Liu Ying <[email protected]>
---
v3->v4:
* Add child nodes in the example MSI bus node of the MSI bus dt-binding. (Krzysztof)
* Resend v4 to imply this patch is based on v6.0-rc1 so that there are not any
dependencies. (Rob)
v2->v3:
* Add a pattern property to allow child nodes. (Rob)
v1->v2:
Address Krzysztof's comments:
* Add a select to explicitly select the MSI bus dt-binding.
* List 'simple-pm-bus' explicitly as one item of compatible strings.
* Require compatible and reg properties.
* Put reg property just after compatible property in example.
.../bus/fsl,imx8qxp-pixel-link-msi-bus.yaml | 232 ++++++++++++++++++
1 file changed, 232 insertions(+)
create mode 100644 Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml
diff --git a/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml b/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml
new file mode 100644
index 000000000000..b568d0ce438d
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml
@@ -0,0 +1,232 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus
+
+maintainers:
+ - Liu Ying <[email protected]>
+
+description: |
+ i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os
+ sitting together with the PHYs. It is not the same as the MSI bus coming
+ from i.MX8 System Controller Unit (SCU) which is used to control power,
+ clock and reset through the i.MX8 Distributed Slave System Controller (DSC).
+
+ i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
+ that is, MSI clock and AHB clock, need to be enabled so that peripherals
+ connected to the bus can be accessed. Also, the bus is part of a power
+ domain. The power domain needs to be enabled before the peripherals can
+ be accessed.
+
+ Peripherals in i.MX8qm/qxp imaging, LVDS, MIPI DSI and HDMI TX subsystems,
+ like I2C controller, PWM controller, MIPI DSI controller and Control and
+ Status Registers (CSR) module, are accessed through the bus.
+
+ The i.MX System Controller Firmware (SCFW) owns and uses the i.MX8qm/qxp
+ pixel link MSI bus controller and does not allow SCFW user to control it.
+ So, the controller's registers cannot be accessed by SCFW user. Hence,
+ the interrupts generated by the controller don't make any sense from SCFW
+ user's point of view.
+
+allOf:
+ - $ref: simple-pm-bus.yaml#
+
+# We need a select here so we don't match all nodes with 'simple-pm-bus'.
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8qxp-display-pixel-link-msi-bus
+ - fsl,imx8qm-display-pixel-link-msi-bus
+ required:
+ - compatible
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - fsl,imx8qxp-display-pixel-link-msi-bus
+ - fsl,imx8qm-display-pixel-link-msi-bus
+ - const: simple-pm-bus
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: master gated clock from system
+ - description: AHB clock
+
+ clock-names:
+ items:
+ - const: msi
+ - const: ahb
+
+patternProperties:
+ "^.*@[0-9a-f]+$":
+ description: Devices attached to the bus
+ type: object
+ properties:
+ reg:
+ maxItems: 1
+
+ required:
+ - reg
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - power-domains
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8-lpcg.h>
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ bus@56200000 {
+ compatible = "fsl,imx8qxp-display-pixel-link-msi-bus", "simple-pm-bus";
+ reg = <0x56200000 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&dc0_irqsteer>;
+ interrupts = <320>;
+ ranges;
+ clocks = <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>,
+ <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "msi", "ahb";
+ power-domains = <&pd IMX_SC_R_DC_0>;
+
+ syscon@56221000 {
+ compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd";
+ reg = <0x56221000 0x1000>;
+ clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "ipg";
+
+ pxl2dpi {
+ compatible = "fsl,imx8qxp-pxl2dpi";
+ fsl,sc-resource = <IMX_SC_R_MIPI_0>;
+ power-domains = <&pd IMX_SC_R_MIPI_0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>;
+ };
+
+ mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
+ };
+
+ mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
+ };
+ };
+ };
+ };
+
+ ldb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx8qxp-ldb";
+ clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
+ <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
+ clock-names = "pixel", "bypass";
+ power-domains = <&pd IMX_SC_R_LVDS_0>;
+
+ channel@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ phys = <&mipi_lvds_0_phy>;
+ phy-names = "lvds_phy";
+
+ port@0 {
+ reg = <0>;
+
+ mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {
+ remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ /* ... */
+ };
+ };
+
+ channel@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ phys = <&mipi_lvds_0_phy>;
+ phy-names = "lvds_phy";
+
+ port@0 {
+ reg = <0>;
+
+ mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {
+ remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ /* ... */
+ };
+ };
+ };
+ };
+
+ clock-controller@56223004 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x56223004 0x4>;
+ #clock-cells = <1>;
+ clocks = <&mipi_lvds_0_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_4>;
+ clock-output-names = "mipi_lvds_0_di_mipi_lvds_regs_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_MIPI_0>;
+ };
+
+ phy@56228300 {
+ compatible = "fsl,imx8qxp-mipi-dphy";
+ reg = <0x56228300 0x100>;
+ clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
+ clock-names = "phy_ref";
+ #phy-cells = <0>;
+ fsl,syscon = <&mipi_lvds_0_csr>;
+ power-domains = <&pd IMX_SC_R_MIPI_0>;
+ };
+ };
--
2.37.1
On Mon, 22 Aug 2022 14:03:23 +0800, Liu Ying wrote:
> Freescale i.MX8qxp pixel link MSI bus is a simple memory-mapped bus.
> It is used to access peripherals in i.MX8qm/qxp imaging, LVDS, MIPI
> DSI and HDMI TX subsystems, like I2C controller, PWM controller,
> MIPI DSI controller and Control and Status Registers (CSR) module.
>
> Reference simple-pm-bus bindings and add Freescale i.MX8qxp pixel
> link MSI bus specific bindings.
>
> Signed-off-by: Liu Ying <[email protected]>
> ---
> v3->v4:
> * Add child nodes in the example MSI bus node of the MSI bus dt-binding. (Krzysztof)
> * Resend v4 to imply this patch is based on v6.0-rc1 so that there are not any
> dependencies. (Rob)
>
> v2->v3:
> * Add a pattern property to allow child nodes. (Rob)
>
> v1->v2:
> Address Krzysztof's comments:
> * Add a select to explicitly select the MSI bus dt-binding.
> * List 'simple-pm-bus' explicitly as one item of compatible strings.
> * Require compatible and reg properties.
> * Put reg property just after compatible property in example.
>
> .../bus/fsl,imx8qxp-pixel-link-msi-bus.yaml | 232 ++++++++++++++++++
> 1 file changed, 232 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml
>
Reviewed-by: Rob Herring <[email protected]>
Hi,
On Mon, 2022-08-22 at 14:03 +0800, Liu Ying wrote:
> Hi,
>
> This series aims to add Freescale i.MX8qxp pixel link MSI bus support
> by using the existing simple-pm-bus driver. A power domain and two
> input
> clocks need to be enabled before the MSI bus accesses it's child
> devices,
> which matches what a simple power-managed bus is(See simple-pm-
> bus.yaml).
>
> Patch 1 enables/disables functional clock(s) as a bulk in the
> simple-pm-bus driver when the simple-pm-bus is being power managed,
> since the MSI bus takes the two input clocks as functional clocks.
>
> Patch 2 adds dt-bindings for the MSI bus.
>
> v3->v4:
> * Drop patch 1 in v3, because simple-bus/simple-mfd devices probed by
> the
> simple-pm-bus driver should not be child nodes of simple-pm-bus at
> all,
> as simple-bus/simple-mfd's child devices PM operations cannot be
> propagated
> to simple-pm-bus. Those simple-bus/simple-mfd devices needs
> dedicated drivers.
> * Drop unnecessary 'bus == NULL' check from
> simple_pm_bus_runtime_{suspend,resume}.
> for patch 1 in v4. (Geert)
> * Add Geert's R-b tag on patch 1 in v4.
> * Add child nodes in the example MSI bus node of the MSI bus dt-
> binding. (Krzysztof)
> * Resend v4 to imply this series is based on v6.0-rc1 so that there
> are not any
> dependencies for the MSI bus dt-binding. (Rob)
>
> v2->v3:
> * Add a pattern property to allow child nodes in the MSI bus dt-
> binding. (Rob)
>
> v1->v2:
> Address Krzysztof's comments on patch 3:
> * Add a select to explicitly select the MSI bus dt-binding.
> * List 'simple-pm-bus' explicitly as one item of compatible strings.
> * Require compatible and reg properties.
> * Put reg property just after compatible property in example.
>
>
> Liu Ying (2):
> drivers: bus: simple-pm-bus: Use clocks
> dt-bindings: bus: Add Freescale i.MX8qxp pixel link MSI bus binding
>
> .../bus/fsl,imx8qxp-pixel-link-msi-bus.yaml | 232
> ++++++++++++++++++
> drivers/bus/simple-pm-bus.c | 48 ++++
> 2 files changed, 280 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-
> bus.yaml
>
I don't see any more comments on this patch series. Can it be picked
up please?
Regards,
Liu Ying
On Thu, Oct 06, 2022 at 11:18:06AM +0800, Liu Ying wrote:
> Hi,
>
> On Mon, 2022-08-22 at 14:03 +0800, Liu Ying wrote:
> > Hi,
> >
> > This series aims to add Freescale i.MX8qxp pixel link MSI bus support
> > by using the existing simple-pm-bus driver. A power domain and two
> > input
> > clocks need to be enabled before the MSI bus accesses it's child
> > devices,
> > which matches what a simple power-managed bus is(See simple-pm-
> > bus.yaml).
> >
> > Patch 1 enables/disables functional clock(s) as a bulk in the
> > simple-pm-bus driver when the simple-pm-bus is being power managed,
> > since the MSI bus takes the two input clocks as functional clocks.
> >
> > Patch 2 adds dt-bindings for the MSI bus.
> >
> > v3->v4:
> > * Drop patch 1 in v3, because simple-bus/simple-mfd devices probed by
> > the
> > simple-pm-bus driver should not be child nodes of simple-pm-bus at
> > all,
> > as simple-bus/simple-mfd's child devices PM operations cannot be
> > propagated
> > to simple-pm-bus. Those simple-bus/simple-mfd devices needs
> > dedicated drivers.
> > * Drop unnecessary 'bus == NULL' check from
> > simple_pm_bus_runtime_{suspend,resume}.
> > for patch 1 in v4. (Geert)
> > * Add Geert's R-b tag on patch 1 in v4.
> > * Add child nodes in the example MSI bus node of the MSI bus dt-
> > binding. (Krzysztof)
> > * Resend v4 to imply this series is based on v6.0-rc1 so that there
> > are not any
> > dependencies for the MSI bus dt-binding. (Rob)
> >
> > v2->v3:
> > * Add a pattern property to allow child nodes in the MSI bus dt-
> > binding. (Rob)
> >
> > v1->v2:
> > Address Krzysztof's comments on patch 3:
> > * Add a select to explicitly select the MSI bus dt-binding.
> > * List 'simple-pm-bus' explicitly as one item of compatible strings.
> > * Require compatible and reg properties.
> > * Put reg property just after compatible property in example.
> >
> >
> > Liu Ying (2):
> > drivers: bus: simple-pm-bus: Use clocks
> > dt-bindings: bus: Add Freescale i.MX8qxp pixel link MSI bus binding
> >
> > .../bus/fsl,imx8qxp-pixel-link-msi-bus.yaml | 232
> > ++++++++++++++++++
> > drivers/bus/simple-pm-bus.c | 48 ++++
> > 2 files changed, 280 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-
> > bus.yaml
> >
>
> I don't see any more comments on this patch series. Can it be picked
> up please?
It is the middle of the merge window, we can not add any new code to any
tree until after -rc1 is out. Please resend it at that time if you wish
us to review it again.
thanks,
greg k-h